1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include "i915_drv.h"
9 #include "i915_irq.h"
10 #include "intel_backlight_regs.h"
11 #include "intel_cdclk.h"
12 #include "intel_combo_phy.h"
13 #include "intel_de.h"
14 #include "intel_display_power.h"
15 #include "intel_display_power_map.h"
16 #include "intel_display_power_well.h"
17 #include "intel_display_types.h"
18 #include "intel_dmc.h"
19 #include "intel_mchbar_regs.h"
20 #include "intel_pch_refclk.h"
21 #include "intel_pcode.h"
22 #include "intel_snps_phy.h"
23 #include "skl_watermark.h"
24 #include "vlv_sideband.h"
25
26 #define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
27 for_each_power_well(__dev_priv, __power_well) \
28 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
29
30 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
31 for_each_power_well_reverse(__dev_priv, __power_well) \
32 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
33
34 const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)35 intel_display_power_domain_str(enum intel_display_power_domain domain)
36 {
37 switch (domain) {
38 case POWER_DOMAIN_DISPLAY_CORE:
39 return "DISPLAY_CORE";
40 case POWER_DOMAIN_PIPE_A:
41 return "PIPE_A";
42 case POWER_DOMAIN_PIPE_B:
43 return "PIPE_B";
44 case POWER_DOMAIN_PIPE_C:
45 return "PIPE_C";
46 case POWER_DOMAIN_PIPE_D:
47 return "PIPE_D";
48 case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
49 return "PIPE_PANEL_FITTER_A";
50 case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
51 return "PIPE_PANEL_FITTER_B";
52 case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
53 return "PIPE_PANEL_FITTER_C";
54 case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
55 return "PIPE_PANEL_FITTER_D";
56 case POWER_DOMAIN_TRANSCODER_A:
57 return "TRANSCODER_A";
58 case POWER_DOMAIN_TRANSCODER_B:
59 return "TRANSCODER_B";
60 case POWER_DOMAIN_TRANSCODER_C:
61 return "TRANSCODER_C";
62 case POWER_DOMAIN_TRANSCODER_D:
63 return "TRANSCODER_D";
64 case POWER_DOMAIN_TRANSCODER_EDP:
65 return "TRANSCODER_EDP";
66 case POWER_DOMAIN_TRANSCODER_DSI_A:
67 return "TRANSCODER_DSI_A";
68 case POWER_DOMAIN_TRANSCODER_DSI_C:
69 return "TRANSCODER_DSI_C";
70 case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
71 return "TRANSCODER_VDSC_PW2";
72 case POWER_DOMAIN_PORT_DDI_LANES_A:
73 return "PORT_DDI_LANES_A";
74 case POWER_DOMAIN_PORT_DDI_LANES_B:
75 return "PORT_DDI_LANES_B";
76 case POWER_DOMAIN_PORT_DDI_LANES_C:
77 return "PORT_DDI_LANES_C";
78 case POWER_DOMAIN_PORT_DDI_LANES_D:
79 return "PORT_DDI_LANES_D";
80 case POWER_DOMAIN_PORT_DDI_LANES_E:
81 return "PORT_DDI_LANES_E";
82 case POWER_DOMAIN_PORT_DDI_LANES_F:
83 return "PORT_DDI_LANES_F";
84 case POWER_DOMAIN_PORT_DDI_LANES_TC1:
85 return "PORT_DDI_LANES_TC1";
86 case POWER_DOMAIN_PORT_DDI_LANES_TC2:
87 return "PORT_DDI_LANES_TC2";
88 case POWER_DOMAIN_PORT_DDI_LANES_TC3:
89 return "PORT_DDI_LANES_TC3";
90 case POWER_DOMAIN_PORT_DDI_LANES_TC4:
91 return "PORT_DDI_LANES_TC4";
92 case POWER_DOMAIN_PORT_DDI_LANES_TC5:
93 return "PORT_DDI_LANES_TC5";
94 case POWER_DOMAIN_PORT_DDI_LANES_TC6:
95 return "PORT_DDI_LANES_TC6";
96 case POWER_DOMAIN_PORT_DDI_IO_A:
97 return "PORT_DDI_IO_A";
98 case POWER_DOMAIN_PORT_DDI_IO_B:
99 return "PORT_DDI_IO_B";
100 case POWER_DOMAIN_PORT_DDI_IO_C:
101 return "PORT_DDI_IO_C";
102 case POWER_DOMAIN_PORT_DDI_IO_D:
103 return "PORT_DDI_IO_D";
104 case POWER_DOMAIN_PORT_DDI_IO_E:
105 return "PORT_DDI_IO_E";
106 case POWER_DOMAIN_PORT_DDI_IO_F:
107 return "PORT_DDI_IO_F";
108 case POWER_DOMAIN_PORT_DDI_IO_TC1:
109 return "PORT_DDI_IO_TC1";
110 case POWER_DOMAIN_PORT_DDI_IO_TC2:
111 return "PORT_DDI_IO_TC2";
112 case POWER_DOMAIN_PORT_DDI_IO_TC3:
113 return "PORT_DDI_IO_TC3";
114 case POWER_DOMAIN_PORT_DDI_IO_TC4:
115 return "PORT_DDI_IO_TC4";
116 case POWER_DOMAIN_PORT_DDI_IO_TC5:
117 return "PORT_DDI_IO_TC5";
118 case POWER_DOMAIN_PORT_DDI_IO_TC6:
119 return "PORT_DDI_IO_TC6";
120 case POWER_DOMAIN_PORT_DSI:
121 return "PORT_DSI";
122 case POWER_DOMAIN_PORT_CRT:
123 return "PORT_CRT";
124 case POWER_DOMAIN_PORT_OTHER:
125 return "PORT_OTHER";
126 case POWER_DOMAIN_VGA:
127 return "VGA";
128 case POWER_DOMAIN_AUDIO_MMIO:
129 return "AUDIO_MMIO";
130 case POWER_DOMAIN_AUDIO_PLAYBACK:
131 return "AUDIO_PLAYBACK";
132 case POWER_DOMAIN_AUX_A:
133 return "AUX_A";
134 case POWER_DOMAIN_AUX_B:
135 return "AUX_B";
136 case POWER_DOMAIN_AUX_C:
137 return "AUX_C";
138 case POWER_DOMAIN_AUX_D:
139 return "AUX_D";
140 case POWER_DOMAIN_AUX_E:
141 return "AUX_E";
142 case POWER_DOMAIN_AUX_F:
143 return "AUX_F";
144 case POWER_DOMAIN_AUX_USBC1:
145 return "AUX_USBC1";
146 case POWER_DOMAIN_AUX_USBC2:
147 return "AUX_USBC2";
148 case POWER_DOMAIN_AUX_USBC3:
149 return "AUX_USBC3";
150 case POWER_DOMAIN_AUX_USBC4:
151 return "AUX_USBC4";
152 case POWER_DOMAIN_AUX_USBC5:
153 return "AUX_USBC5";
154 case POWER_DOMAIN_AUX_USBC6:
155 return "AUX_USBC6";
156 case POWER_DOMAIN_AUX_IO_A:
157 return "AUX_IO_A";
158 case POWER_DOMAIN_AUX_TBT1:
159 return "AUX_TBT1";
160 case POWER_DOMAIN_AUX_TBT2:
161 return "AUX_TBT2";
162 case POWER_DOMAIN_AUX_TBT3:
163 return "AUX_TBT3";
164 case POWER_DOMAIN_AUX_TBT4:
165 return "AUX_TBT4";
166 case POWER_DOMAIN_AUX_TBT5:
167 return "AUX_TBT5";
168 case POWER_DOMAIN_AUX_TBT6:
169 return "AUX_TBT6";
170 case POWER_DOMAIN_GMBUS:
171 return "GMBUS";
172 case POWER_DOMAIN_INIT:
173 return "INIT";
174 case POWER_DOMAIN_MODESET:
175 return "MODESET";
176 case POWER_DOMAIN_GT_IRQ:
177 return "GT_IRQ";
178 case POWER_DOMAIN_DC_OFF:
179 return "DC_OFF";
180 case POWER_DOMAIN_TC_COLD_OFF:
181 return "TC_COLD_OFF";
182 default:
183 MISSING_CASE(domain);
184 return "?";
185 }
186 }
187
188 /**
189 * __intel_display_power_is_enabled - unlocked check for a power domain
190 * @dev_priv: i915 device instance
191 * @domain: power domain to check
192 *
193 * This is the unlocked version of intel_display_power_is_enabled() and should
194 * only be used from error capture and recovery code where deadlocks are
195 * possible.
196 *
197 * Returns:
198 * True when the power domain is enabled, false otherwise.
199 */
__intel_display_power_is_enabled(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)200 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
201 enum intel_display_power_domain domain)
202 {
203 struct i915_power_well *power_well;
204 bool is_enabled;
205
206 if (dev_priv->runtime_pm.suspended)
207 return false;
208
209 is_enabled = true;
210
211 for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
212 if (intel_power_well_is_always_on(power_well))
213 continue;
214
215 if (!intel_power_well_is_enabled_cached(power_well)) {
216 is_enabled = false;
217 break;
218 }
219 }
220
221 return is_enabled;
222 }
223
224 /**
225 * intel_display_power_is_enabled - check for a power domain
226 * @dev_priv: i915 device instance
227 * @domain: power domain to check
228 *
229 * This function can be used to check the hw power domain state. It is mostly
230 * used in hardware state readout functions. Everywhere else code should rely
231 * upon explicit power domain reference counting to ensure that the hardware
232 * block is powered up before accessing it.
233 *
234 * Callers must hold the relevant modesetting locks to ensure that concurrent
235 * threads can't disable the power well while the caller tries to read a few
236 * registers.
237 *
238 * Returns:
239 * True when the power domain is enabled, false otherwise.
240 */
intel_display_power_is_enabled(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)241 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
242 enum intel_display_power_domain domain)
243 {
244 struct i915_power_domains *power_domains;
245 bool ret;
246
247 power_domains = &dev_priv->display.power.domains;
248
249 mutex_lock(&power_domains->lock);
250 ret = __intel_display_power_is_enabled(dev_priv, domain);
251 mutex_unlock(&power_domains->lock);
252
253 return ret;
254 }
255
256 static u32
sanitize_target_dc_state(struct drm_i915_private * dev_priv,u32 target_dc_state)257 sanitize_target_dc_state(struct drm_i915_private *dev_priv,
258 u32 target_dc_state)
259 {
260 static const u32 states[] = {
261 DC_STATE_EN_UPTO_DC6,
262 DC_STATE_EN_UPTO_DC5,
263 DC_STATE_EN_DC3CO,
264 DC_STATE_DISABLE,
265 };
266 int i;
267
268 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
269 if (target_dc_state != states[i])
270 continue;
271
272 if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
273 break;
274
275 target_dc_state = states[i + 1];
276 }
277
278 return target_dc_state;
279 }
280
281 /**
282 * intel_display_power_set_target_dc_state - Set target dc state.
283 * @dev_priv: i915 device
284 * @state: state which needs to be set as target_dc_state.
285 *
286 * This function set the "DC off" power well target_dc_state,
287 * based upon this target_dc_stste, "DC off" power well will
288 * enable desired DC state.
289 */
intel_display_power_set_target_dc_state(struct drm_i915_private * dev_priv,u32 state)290 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
291 u32 state)
292 {
293 struct i915_power_well *power_well;
294 bool dc_off_enabled;
295 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
296
297 mutex_lock(&power_domains->lock);
298 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
299
300 if (drm_WARN_ON(&dev_priv->drm, !power_well))
301 goto unlock;
302
303 state = sanitize_target_dc_state(dev_priv, state);
304
305 if (state == dev_priv->display.dmc.target_dc_state)
306 goto unlock;
307
308 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
309 /*
310 * If DC off power well is disabled, need to enable and disable the
311 * DC off power well to effect target DC state.
312 */
313 if (!dc_off_enabled)
314 intel_power_well_enable(dev_priv, power_well);
315
316 dev_priv->display.dmc.target_dc_state = state;
317
318 if (!dc_off_enabled)
319 intel_power_well_disable(dev_priv, power_well);
320
321 unlock:
322 mutex_unlock(&power_domains->lock);
323 }
324
325 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
326
__async_put_domains_mask(struct i915_power_domains * power_domains,struct intel_power_domain_mask * mask)327 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
328 struct intel_power_domain_mask *mask)
329 {
330 bitmap_or(mask->bits,
331 power_domains->async_put_domains[0].bits,
332 power_domains->async_put_domains[1].bits,
333 POWER_DOMAIN_NUM);
334 }
335
336 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
337
338 static bool
assert_async_put_domain_masks_disjoint(struct i915_power_domains * power_domains)339 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
340 {
341 struct drm_i915_private *i915 = container_of(power_domains,
342 struct drm_i915_private,
343 display.power.domains);
344
345 return !drm_WARN_ON(&i915->drm,
346 bitmap_intersects(power_domains->async_put_domains[0].bits,
347 power_domains->async_put_domains[1].bits,
348 POWER_DOMAIN_NUM));
349 }
350
351 static bool
__async_put_domains_state_ok(struct i915_power_domains * power_domains)352 __async_put_domains_state_ok(struct i915_power_domains *power_domains)
353 {
354 struct drm_i915_private *i915 = container_of(power_domains,
355 struct drm_i915_private,
356 display.power.domains);
357 struct intel_power_domain_mask async_put_mask;
358 enum intel_display_power_domain domain;
359 bool err = false;
360
361 err |= !assert_async_put_domain_masks_disjoint(power_domains);
362 __async_put_domains_mask(power_domains, &async_put_mask);
363 err |= drm_WARN_ON(&i915->drm,
364 !!power_domains->async_put_wakeref !=
365 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
366
367 for_each_power_domain(domain, &async_put_mask)
368 err |= drm_WARN_ON(&i915->drm,
369 power_domains->domain_use_count[domain] != 1);
370
371 return !err;
372 }
373
print_power_domains(struct i915_power_domains * power_domains,const char * prefix,struct intel_power_domain_mask * mask)374 static void print_power_domains(struct i915_power_domains *power_domains,
375 const char *prefix, struct intel_power_domain_mask *mask)
376 {
377 struct drm_i915_private *i915 = container_of(power_domains,
378 struct drm_i915_private,
379 display.power.domains);
380 enum intel_display_power_domain domain;
381
382 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
383 for_each_power_domain(domain, mask)
384 drm_dbg(&i915->drm, "%s use_count %d\n",
385 intel_display_power_domain_str(domain),
386 power_domains->domain_use_count[domain]);
387 }
388
389 static void
print_async_put_domains_state(struct i915_power_domains * power_domains)390 print_async_put_domains_state(struct i915_power_domains *power_domains)
391 {
392 struct drm_i915_private *i915 = container_of(power_domains,
393 struct drm_i915_private,
394 display.power.domains);
395
396 drm_dbg(&i915->drm, "async_put_wakeref %u\n",
397 power_domains->async_put_wakeref);
398
399 print_power_domains(power_domains, "async_put_domains[0]",
400 &power_domains->async_put_domains[0]);
401 print_power_domains(power_domains, "async_put_domains[1]",
402 &power_domains->async_put_domains[1]);
403 }
404
405 static void
verify_async_put_domains_state(struct i915_power_domains * power_domains)406 verify_async_put_domains_state(struct i915_power_domains *power_domains)
407 {
408 if (!__async_put_domains_state_ok(power_domains))
409 print_async_put_domains_state(power_domains);
410 }
411
412 #else
413
414 static void
assert_async_put_domain_masks_disjoint(struct i915_power_domains * power_domains)415 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
416 {
417 }
418
419 static void
verify_async_put_domains_state(struct i915_power_domains * power_domains)420 verify_async_put_domains_state(struct i915_power_domains *power_domains)
421 {
422 }
423
424 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
425
async_put_domains_mask(struct i915_power_domains * power_domains,struct intel_power_domain_mask * mask)426 static void async_put_domains_mask(struct i915_power_domains *power_domains,
427 struct intel_power_domain_mask *mask)
428
429 {
430 assert_async_put_domain_masks_disjoint(power_domains);
431
432 __async_put_domains_mask(power_domains, mask);
433 }
434
435 static void
async_put_domains_clear_domain(struct i915_power_domains * power_domains,enum intel_display_power_domain domain)436 async_put_domains_clear_domain(struct i915_power_domains *power_domains,
437 enum intel_display_power_domain domain)
438 {
439 assert_async_put_domain_masks_disjoint(power_domains);
440
441 clear_bit(domain, power_domains->async_put_domains[0].bits);
442 clear_bit(domain, power_domains->async_put_domains[1].bits);
443 }
444
445 static bool
intel_display_power_grab_async_put_ref(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)446 intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
447 enum intel_display_power_domain domain)
448 {
449 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
450 struct intel_power_domain_mask async_put_mask;
451 bool ret = false;
452
453 async_put_domains_mask(power_domains, &async_put_mask);
454 if (!test_bit(domain, async_put_mask.bits))
455 goto out_verify;
456
457 async_put_domains_clear_domain(power_domains, domain);
458
459 ret = true;
460
461 async_put_domains_mask(power_domains, &async_put_mask);
462 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
463 goto out_verify;
464
465 cancel_delayed_work(&power_domains->async_put_work);
466 intel_runtime_pm_put_raw(&dev_priv->runtime_pm,
467 fetch_and_zero(&power_domains->async_put_wakeref));
468 out_verify:
469 verify_async_put_domains_state(power_domains);
470
471 return ret;
472 }
473
474 static void
__intel_display_power_get_domain(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)475 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
476 enum intel_display_power_domain domain)
477 {
478 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
479 struct i915_power_well *power_well;
480
481 if (intel_display_power_grab_async_put_ref(dev_priv, domain))
482 return;
483
484 for_each_power_domain_well(dev_priv, power_well, domain)
485 intel_power_well_get(dev_priv, power_well);
486
487 power_domains->domain_use_count[domain]++;
488 }
489
490 /**
491 * intel_display_power_get - grab a power domain reference
492 * @dev_priv: i915 device instance
493 * @domain: power domain to reference
494 *
495 * This function grabs a power domain reference for @domain and ensures that the
496 * power domain and all its parents are powered up. Therefore users should only
497 * grab a reference to the innermost power domain they need.
498 *
499 * Any power domain reference obtained by this function must have a symmetric
500 * call to intel_display_power_put() to release the reference again.
501 */
intel_display_power_get(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)502 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
503 enum intel_display_power_domain domain)
504 {
505 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
506 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
507
508 mutex_lock(&power_domains->lock);
509 __intel_display_power_get_domain(dev_priv, domain);
510 mutex_unlock(&power_domains->lock);
511
512 return wakeref;
513 }
514
515 /**
516 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
517 * @dev_priv: i915 device instance
518 * @domain: power domain to reference
519 *
520 * This function grabs a power domain reference for @domain and ensures that the
521 * power domain and all its parents are powered up. Therefore users should only
522 * grab a reference to the innermost power domain they need.
523 *
524 * Any power domain reference obtained by this function must have a symmetric
525 * call to intel_display_power_put() to release the reference again.
526 */
527 intel_wakeref_t
intel_display_power_get_if_enabled(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)528 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
529 enum intel_display_power_domain domain)
530 {
531 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
532 intel_wakeref_t wakeref;
533 bool is_enabled;
534
535 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
536 if (!wakeref)
537 return false;
538
539 mutex_lock(&power_domains->lock);
540
541 if (__intel_display_power_is_enabled(dev_priv, domain)) {
542 __intel_display_power_get_domain(dev_priv, domain);
543 is_enabled = true;
544 } else {
545 is_enabled = false;
546 }
547
548 mutex_unlock(&power_domains->lock);
549
550 if (!is_enabled) {
551 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
552 wakeref = 0;
553 }
554
555 return wakeref;
556 }
557
558 static void
__intel_display_power_put_domain(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)559 __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
560 enum intel_display_power_domain domain)
561 {
562 struct i915_power_domains *power_domains;
563 struct i915_power_well *power_well;
564 const char *name = intel_display_power_domain_str(domain);
565 struct intel_power_domain_mask async_put_mask;
566
567 power_domains = &dev_priv->display.power.domains;
568
569 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
570 "Use count on domain %s is already zero\n",
571 name);
572 async_put_domains_mask(power_domains, &async_put_mask);
573 drm_WARN(&dev_priv->drm,
574 test_bit(domain, async_put_mask.bits),
575 "Async disabling of domain %s is pending\n",
576 name);
577
578 power_domains->domain_use_count[domain]--;
579
580 for_each_power_domain_well_reverse(dev_priv, power_well, domain)
581 intel_power_well_put(dev_priv, power_well);
582 }
583
__intel_display_power_put(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)584 static void __intel_display_power_put(struct drm_i915_private *dev_priv,
585 enum intel_display_power_domain domain)
586 {
587 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
588
589 mutex_lock(&power_domains->lock);
590 __intel_display_power_put_domain(dev_priv, domain);
591 mutex_unlock(&power_domains->lock);
592 }
593
594 static void
queue_async_put_domains_work(struct i915_power_domains * power_domains,intel_wakeref_t wakeref)595 queue_async_put_domains_work(struct i915_power_domains *power_domains,
596 intel_wakeref_t wakeref)
597 {
598 struct drm_i915_private *i915 = container_of(power_domains,
599 struct drm_i915_private,
600 display.power.domains);
601 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
602 power_domains->async_put_wakeref = wakeref;
603 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
604 &power_domains->async_put_work,
605 msecs_to_jiffies(100)));
606 }
607
608 static void
release_async_put_domains(struct i915_power_domains * power_domains,struct intel_power_domain_mask * mask)609 release_async_put_domains(struct i915_power_domains *power_domains,
610 struct intel_power_domain_mask *mask)
611 {
612 struct drm_i915_private *dev_priv =
613 container_of(power_domains, struct drm_i915_private,
614 display.power.domains);
615 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
616 enum intel_display_power_domain domain;
617 intel_wakeref_t wakeref;
618
619 /*
620 * The caller must hold already raw wakeref, upgrade that to a proper
621 * wakeref to make the state checker happy about the HW access during
622 * power well disabling.
623 */
624 assert_rpm_raw_wakeref_held(rpm);
625 wakeref = intel_runtime_pm_get(rpm);
626
627 for_each_power_domain(domain, mask) {
628 /* Clear before put, so put's sanity check is happy. */
629 async_put_domains_clear_domain(power_domains, domain);
630 __intel_display_power_put_domain(dev_priv, domain);
631 }
632
633 intel_runtime_pm_put(rpm, wakeref);
634 }
635
636 static void
intel_display_power_put_async_work(struct work_struct * work)637 intel_display_power_put_async_work(struct work_struct *work)
638 {
639 struct drm_i915_private *dev_priv =
640 container_of(work, struct drm_i915_private,
641 display.power.domains.async_put_work.work);
642 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
643 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
644 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
645 intel_wakeref_t old_work_wakeref = 0;
646
647 mutex_lock(&power_domains->lock);
648
649 /*
650 * Bail out if all the domain refs pending to be released were grabbed
651 * by subsequent gets or a flush_work.
652 */
653 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
654 if (!old_work_wakeref)
655 goto out_verify;
656
657 release_async_put_domains(power_domains,
658 &power_domains->async_put_domains[0]);
659
660 /* Requeue the work if more domains were async put meanwhile. */
661 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
662 bitmap_copy(power_domains->async_put_domains[0].bits,
663 power_domains->async_put_domains[1].bits,
664 POWER_DOMAIN_NUM);
665 bitmap_zero(power_domains->async_put_domains[1].bits,
666 POWER_DOMAIN_NUM);
667 queue_async_put_domains_work(power_domains,
668 fetch_and_zero(&new_work_wakeref));
669 } else {
670 /*
671 * Cancel the work that got queued after this one got dequeued,
672 * since here we released the corresponding async-put reference.
673 */
674 cancel_delayed_work(&power_domains->async_put_work);
675 }
676
677 out_verify:
678 verify_async_put_domains_state(power_domains);
679
680 mutex_unlock(&power_domains->lock);
681
682 if (old_work_wakeref)
683 intel_runtime_pm_put_raw(rpm, old_work_wakeref);
684 if (new_work_wakeref)
685 intel_runtime_pm_put_raw(rpm, new_work_wakeref);
686 }
687
688 /**
689 * intel_display_power_put_async - release a power domain reference asynchronously
690 * @i915: i915 device instance
691 * @domain: power domain to reference
692 * @wakeref: wakeref acquired for the reference that is being released
693 *
694 * This function drops the power domain reference obtained by
695 * intel_display_power_get*() and schedules a work to power down the
696 * corresponding hardware block if this is the last reference.
697 */
__intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)698 void __intel_display_power_put_async(struct drm_i915_private *i915,
699 enum intel_display_power_domain domain,
700 intel_wakeref_t wakeref)
701 {
702 struct i915_power_domains *power_domains = &i915->display.power.domains;
703 struct intel_runtime_pm *rpm = &i915->runtime_pm;
704 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
705
706 mutex_lock(&power_domains->lock);
707
708 if (power_domains->domain_use_count[domain] > 1) {
709 __intel_display_power_put_domain(i915, domain);
710
711 goto out_verify;
712 }
713
714 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1);
715
716 /* Let a pending work requeue itself or queue a new one. */
717 if (power_domains->async_put_wakeref) {
718 set_bit(domain, power_domains->async_put_domains[1].bits);
719 } else {
720 set_bit(domain, power_domains->async_put_domains[0].bits);
721 queue_async_put_domains_work(power_domains,
722 fetch_and_zero(&work_wakeref));
723 }
724
725 out_verify:
726 verify_async_put_domains_state(power_domains);
727
728 mutex_unlock(&power_domains->lock);
729
730 if (work_wakeref)
731 intel_runtime_pm_put_raw(rpm, work_wakeref);
732
733 intel_runtime_pm_put(rpm, wakeref);
734 }
735
736 /**
737 * intel_display_power_flush_work - flushes the async display power disabling work
738 * @i915: i915 device instance
739 *
740 * Flushes any pending work that was scheduled by a preceding
741 * intel_display_power_put_async() call, completing the disabling of the
742 * corresponding power domains.
743 *
744 * Note that the work handler function may still be running after this
745 * function returns; to ensure that the work handler isn't running use
746 * intel_display_power_flush_work_sync() instead.
747 */
intel_display_power_flush_work(struct drm_i915_private * i915)748 void intel_display_power_flush_work(struct drm_i915_private *i915)
749 {
750 struct i915_power_domains *power_domains = &i915->display.power.domains;
751 struct intel_power_domain_mask async_put_mask;
752 intel_wakeref_t work_wakeref;
753
754 mutex_lock(&power_domains->lock);
755
756 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
757 if (!work_wakeref)
758 goto out_verify;
759
760 async_put_domains_mask(power_domains, &async_put_mask);
761 release_async_put_domains(power_domains, &async_put_mask);
762 cancel_delayed_work(&power_domains->async_put_work);
763
764 out_verify:
765 verify_async_put_domains_state(power_domains);
766
767 mutex_unlock(&power_domains->lock);
768
769 if (work_wakeref)
770 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref);
771 }
772
773 /**
774 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
775 * @i915: i915 device instance
776 *
777 * Like intel_display_power_flush_work(), but also ensure that the work
778 * handler function is not running any more when this function returns.
779 */
780 static void
intel_display_power_flush_work_sync(struct drm_i915_private * i915)781 intel_display_power_flush_work_sync(struct drm_i915_private *i915)
782 {
783 struct i915_power_domains *power_domains = &i915->display.power.domains;
784
785 intel_display_power_flush_work(i915);
786 cancel_delayed_work_sync(&power_domains->async_put_work);
787
788 verify_async_put_domains_state(power_domains);
789
790 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
791 }
792
793 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
794 /**
795 * intel_display_power_put - release a power domain reference
796 * @dev_priv: i915 device instance
797 * @domain: power domain to reference
798 * @wakeref: wakeref acquired for the reference that is being released
799 *
800 * This function drops the power domain reference obtained by
801 * intel_display_power_get() and might power down the corresponding hardware
802 * block right away if this is the last reference.
803 */
intel_display_power_put(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain,intel_wakeref_t wakeref)804 void intel_display_power_put(struct drm_i915_private *dev_priv,
805 enum intel_display_power_domain domain,
806 intel_wakeref_t wakeref)
807 {
808 __intel_display_power_put(dev_priv, domain);
809 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
810 }
811 #else
812 /**
813 * intel_display_power_put_unchecked - release an unchecked power domain reference
814 * @dev_priv: i915 device instance
815 * @domain: power domain to reference
816 *
817 * This function drops the power domain reference obtained by
818 * intel_display_power_get() and might power down the corresponding hardware
819 * block right away if this is the last reference.
820 *
821 * This function is only for the power domain code's internal use to suppress wakeref
822 * tracking when the correspondig debug kconfig option is disabled, should not
823 * be used otherwise.
824 */
intel_display_power_put_unchecked(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)825 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
826 enum intel_display_power_domain domain)
827 {
828 __intel_display_power_put(dev_priv, domain);
829 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
830 }
831 #endif
832
833 void
intel_display_power_get_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set,enum intel_display_power_domain domain)834 intel_display_power_get_in_set(struct drm_i915_private *i915,
835 struct intel_display_power_domain_set *power_domain_set,
836 enum intel_display_power_domain domain)
837 {
838 intel_wakeref_t __maybe_unused wf;
839
840 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
841
842 wf = intel_display_power_get(i915, domain);
843 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
844 power_domain_set->wakerefs[domain] = wf;
845 #endif
846 set_bit(domain, power_domain_set->mask.bits);
847 }
848
849 bool
intel_display_power_get_in_set_if_enabled(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set,enum intel_display_power_domain domain)850 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
851 struct intel_display_power_domain_set *power_domain_set,
852 enum intel_display_power_domain domain)
853 {
854 intel_wakeref_t wf;
855
856 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
857
858 wf = intel_display_power_get_if_enabled(i915, domain);
859 if (!wf)
860 return false;
861
862 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
863 power_domain_set->wakerefs[domain] = wf;
864 #endif
865 set_bit(domain, power_domain_set->mask.bits);
866
867 return true;
868 }
869
870 void
intel_display_power_put_mask_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set,struct intel_power_domain_mask * mask)871 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
872 struct intel_display_power_domain_set *power_domain_set,
873 struct intel_power_domain_mask *mask)
874 {
875 enum intel_display_power_domain domain;
876
877 drm_WARN_ON(&i915->drm,
878 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
879
880 for_each_power_domain(domain, mask) {
881 intel_wakeref_t __maybe_unused wf = -1;
882
883 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
884 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
885 #endif
886 intel_display_power_put(i915, domain, wf);
887 clear_bit(domain, power_domain_set->mask.bits);
888 }
889 }
890
891 static int
sanitize_disable_power_well_option(const struct drm_i915_private * dev_priv,int disable_power_well)892 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
893 int disable_power_well)
894 {
895 if (disable_power_well >= 0)
896 return !!disable_power_well;
897
898 return 1;
899 }
900
get_allowed_dc_mask(const struct drm_i915_private * dev_priv,int enable_dc)901 static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
902 int enable_dc)
903 {
904 u32 mask;
905 int requested_dc;
906 int max_dc;
907
908 if (!HAS_DISPLAY(dev_priv))
909 return 0;
910
911 if (IS_DG2(dev_priv))
912 max_dc = 1;
913 else if (IS_DG1(dev_priv))
914 max_dc = 3;
915 else if (DISPLAY_VER(dev_priv) >= 12)
916 max_dc = 4;
917 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
918 max_dc = 1;
919 else if (DISPLAY_VER(dev_priv) >= 9)
920 max_dc = 2;
921 else
922 max_dc = 0;
923
924 /*
925 * DC9 has a separate HW flow from the rest of the DC states,
926 * not depending on the DMC firmware. It's needed by system
927 * suspend/resume, so allow it unconditionally.
928 */
929 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
930 DISPLAY_VER(dev_priv) >= 11 ?
931 DC_STATE_EN_DC9 : 0;
932
933 if (!dev_priv->params.disable_power_well)
934 max_dc = 0;
935
936 if (enable_dc >= 0 && enable_dc <= max_dc) {
937 requested_dc = enable_dc;
938 } else if (enable_dc == -1) {
939 requested_dc = max_dc;
940 } else if (enable_dc > max_dc && enable_dc <= 4) {
941 drm_dbg_kms(&dev_priv->drm,
942 "Adjusting requested max DC state (%d->%d)\n",
943 enable_dc, max_dc);
944 requested_dc = max_dc;
945 } else {
946 drm_err(&dev_priv->drm,
947 "Unexpected value for enable_dc (%d)\n", enable_dc);
948 requested_dc = max_dc;
949 }
950
951 switch (requested_dc) {
952 case 4:
953 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
954 break;
955 case 3:
956 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
957 break;
958 case 2:
959 mask |= DC_STATE_EN_UPTO_DC6;
960 break;
961 case 1:
962 mask |= DC_STATE_EN_UPTO_DC5;
963 break;
964 }
965
966 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask);
967
968 return mask;
969 }
970
971 /**
972 * intel_power_domains_init - initializes the power domain structures
973 * @dev_priv: i915 device instance
974 *
975 * Initializes the power domain structures for @dev_priv depending upon the
976 * supported platform.
977 */
intel_power_domains_init(struct drm_i915_private * dev_priv)978 int intel_power_domains_init(struct drm_i915_private *dev_priv)
979 {
980 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
981
982 dev_priv->params.disable_power_well =
983 sanitize_disable_power_well_option(dev_priv,
984 dev_priv->params.disable_power_well);
985 dev_priv->display.dmc.allowed_dc_mask =
986 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
987
988 dev_priv->display.dmc.target_dc_state =
989 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
990
991 mutex_init(&power_domains->lock);
992
993 INIT_DELAYED_WORK(&power_domains->async_put_work,
994 intel_display_power_put_async_work);
995
996 return intel_display_power_map_init(power_domains);
997 }
998
999 /**
1000 * intel_power_domains_cleanup - clean up power domains resources
1001 * @dev_priv: i915 device instance
1002 *
1003 * Release any resources acquired by intel_power_domains_init()
1004 */
intel_power_domains_cleanup(struct drm_i915_private * dev_priv)1005 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
1006 {
1007 intel_display_power_map_cleanup(&dev_priv->display.power.domains);
1008 }
1009
intel_power_domains_sync_hw(struct drm_i915_private * dev_priv)1010 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
1011 {
1012 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1013 struct i915_power_well *power_well;
1014
1015 mutex_lock(&power_domains->lock);
1016 for_each_power_well(dev_priv, power_well)
1017 intel_power_well_sync_hw(dev_priv, power_well);
1018 mutex_unlock(&power_domains->lock);
1019 }
1020
gen9_dbuf_slice_set(struct drm_i915_private * dev_priv,enum dbuf_slice slice,bool enable)1021 static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
1022 enum dbuf_slice slice, bool enable)
1023 {
1024 i915_reg_t reg = DBUF_CTL_S(slice);
1025 bool state;
1026
1027 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
1028 enable ? DBUF_POWER_REQUEST : 0);
1029 intel_de_posting_read(dev_priv, reg);
1030 udelay(10);
1031
1032 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
1033 drm_WARN(&dev_priv->drm, enable != state,
1034 "DBuf slice %d power %s timeout!\n",
1035 slice, str_enable_disable(enable));
1036 }
1037
gen9_dbuf_slices_update(struct drm_i915_private * dev_priv,u8 req_slices)1038 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
1039 u8 req_slices)
1040 {
1041 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1042 u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
1043 enum dbuf_slice slice;
1044
1045 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
1046 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
1047 req_slices, slice_mask);
1048
1049 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
1050 req_slices);
1051
1052 /*
1053 * Might be running this in parallel to gen9_dc_off_power_well_enable
1054 * being called from intel_dp_detect for instance,
1055 * which causes assertion triggered by race condition,
1056 * as gen9_assert_dbuf_enabled might preempt this when registers
1057 * were already updated, while dev_priv was not.
1058 */
1059 mutex_lock(&power_domains->lock);
1060
1061 for_each_dbuf_slice(dev_priv, slice)
1062 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
1063
1064 dev_priv->display.dbuf.enabled_slices = req_slices;
1065
1066 mutex_unlock(&power_domains->lock);
1067 }
1068
gen9_dbuf_enable(struct drm_i915_private * dev_priv)1069 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
1070 {
1071 dev_priv->display.dbuf.enabled_slices =
1072 intel_enabled_dbuf_slices_mask(dev_priv);
1073
1074 /*
1075 * Just power up at least 1 slice, we will
1076 * figure out later which slices we have and what we need.
1077 */
1078 gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
1079 dev_priv->display.dbuf.enabled_slices);
1080 }
1081
gen9_dbuf_disable(struct drm_i915_private * dev_priv)1082 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
1083 {
1084 gen9_dbuf_slices_update(dev_priv, 0);
1085 }
1086
gen12_dbuf_slices_config(struct drm_i915_private * dev_priv)1087 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
1088 {
1089 enum dbuf_slice slice;
1090
1091 if (IS_ALDERLAKE_P(dev_priv))
1092 return;
1093
1094 for_each_dbuf_slice(dev_priv, slice)
1095 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
1096 DBUF_TRACKER_STATE_SERVICE_MASK,
1097 DBUF_TRACKER_STATE_SERVICE(8));
1098 }
1099
icl_mbus_init(struct drm_i915_private * dev_priv)1100 static void icl_mbus_init(struct drm_i915_private *dev_priv)
1101 {
1102 unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
1103 u32 mask, val, i;
1104
1105 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
1106 return;
1107
1108 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
1109 MBUS_ABOX_BT_CREDIT_POOL2_MASK |
1110 MBUS_ABOX_B_CREDIT_MASK |
1111 MBUS_ABOX_BW_CREDIT_MASK;
1112 val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
1113 MBUS_ABOX_BT_CREDIT_POOL2(16) |
1114 MBUS_ABOX_B_CREDIT(1) |
1115 MBUS_ABOX_BW_CREDIT(1);
1116
1117 /*
1118 * gen12 platforms that use abox1 and abox2 for pixel data reads still
1119 * expect us to program the abox_ctl0 register as well, even though
1120 * we don't have to program other instance-0 registers like BW_BUDDY.
1121 */
1122 if (DISPLAY_VER(dev_priv) == 12)
1123 abox_regs |= BIT(0);
1124
1125 for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
1126 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
1127 }
1128
hsw_assert_cdclk(struct drm_i915_private * dev_priv)1129 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
1130 {
1131 u32 val = intel_de_read(dev_priv, LCPLL_CTL);
1132
1133 /*
1134 * The LCPLL register should be turned on by the BIOS. For now
1135 * let's just check its state and print errors in case
1136 * something is wrong. Don't even try to turn it on.
1137 */
1138
1139 if (val & LCPLL_CD_SOURCE_FCLK)
1140 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n");
1141
1142 if (val & LCPLL_PLL_DISABLE)
1143 drm_err(&dev_priv->drm, "LCPLL is disabled\n");
1144
1145 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
1146 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n");
1147 }
1148
assert_can_disable_lcpll(struct drm_i915_private * dev_priv)1149 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
1150 {
1151 struct drm_device *dev = &dev_priv->drm;
1152 struct intel_crtc *crtc;
1153
1154 for_each_intel_crtc(dev, crtc)
1155 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
1156 pipe_name(crtc->pipe));
1157
1158 I915_STATE_WARN(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2),
1159 "Display power well on\n");
1160 I915_STATE_WARN(intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE,
1161 "SPLL enabled\n");
1162 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1163 "WRPLL1 enabled\n");
1164 I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1165 "WRPLL2 enabled\n");
1166 I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON,
1167 "Panel power on\n");
1168 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1169 "CPU PWM1 enabled\n");
1170 if (IS_HASWELL(dev_priv))
1171 I915_STATE_WARN(intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1172 "CPU PWM2 enabled\n");
1173 I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1174 "PCH PWM1 enabled\n");
1175 I915_STATE_WARN(intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
1176 "Utility pin enabled\n");
1177 I915_STATE_WARN(intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1178 "PCH GTC enabled\n");
1179
1180 /*
1181 * In theory we can still leave IRQs enabled, as long as only the HPD
1182 * interrupts remain enabled. We used to check for that, but since it's
1183 * gen-specific and since we only disable LCPLL after we fully disable
1184 * the interrupts, the check below should be enough.
1185 */
1186 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
1187 }
1188
hsw_read_dcomp(struct drm_i915_private * dev_priv)1189 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
1190 {
1191 if (IS_HASWELL(dev_priv))
1192 return intel_de_read(dev_priv, D_COMP_HSW);
1193 else
1194 return intel_de_read(dev_priv, D_COMP_BDW);
1195 }
1196
hsw_write_dcomp(struct drm_i915_private * dev_priv,u32 val)1197 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
1198 {
1199 if (IS_HASWELL(dev_priv)) {
1200 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
1201 drm_dbg_kms(&dev_priv->drm,
1202 "Failed to write to D_COMP\n");
1203 } else {
1204 intel_de_write(dev_priv, D_COMP_BDW, val);
1205 intel_de_posting_read(dev_priv, D_COMP_BDW);
1206 }
1207 }
1208
1209 /*
1210 * This function implements pieces of two sequences from BSpec:
1211 * - Sequence for display software to disable LCPLL
1212 * - Sequence for display software to allow package C8+
1213 * The steps implemented here are just the steps that actually touch the LCPLL
1214 * register. Callers should take care of disabling all the display engine
1215 * functions, doing the mode unset, fixing interrupts, etc.
1216 */
hsw_disable_lcpll(struct drm_i915_private * dev_priv,bool switch_to_fclk,bool allow_power_down)1217 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
1218 bool switch_to_fclk, bool allow_power_down)
1219 {
1220 u32 val;
1221
1222 assert_can_disable_lcpll(dev_priv);
1223
1224 val = intel_de_read(dev_priv, LCPLL_CTL);
1225
1226 if (switch_to_fclk) {
1227 val |= LCPLL_CD_SOURCE_FCLK;
1228 intel_de_write(dev_priv, LCPLL_CTL, val);
1229
1230 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
1231 LCPLL_CD_SOURCE_FCLK_DONE, 1))
1232 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
1233
1234 val = intel_de_read(dev_priv, LCPLL_CTL);
1235 }
1236
1237 val |= LCPLL_PLL_DISABLE;
1238 intel_de_write(dev_priv, LCPLL_CTL, val);
1239 intel_de_posting_read(dev_priv, LCPLL_CTL);
1240
1241 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
1242 drm_err(&dev_priv->drm, "LCPLL still locked\n");
1243
1244 val = hsw_read_dcomp(dev_priv);
1245 val |= D_COMP_COMP_DISABLE;
1246 hsw_write_dcomp(dev_priv, val);
1247 ndelay(100);
1248
1249 if (wait_for((hsw_read_dcomp(dev_priv) &
1250 D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
1251 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n");
1252
1253 if (allow_power_down) {
1254 val = intel_de_read(dev_priv, LCPLL_CTL);
1255 val |= LCPLL_POWER_DOWN_ALLOW;
1256 intel_de_write(dev_priv, LCPLL_CTL, val);
1257 intel_de_posting_read(dev_priv, LCPLL_CTL);
1258 }
1259 }
1260
1261 /*
1262 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
1263 * source.
1264 */
hsw_restore_lcpll(struct drm_i915_private * dev_priv)1265 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
1266 {
1267 u32 val;
1268
1269 val = intel_de_read(dev_priv, LCPLL_CTL);
1270
1271 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
1272 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
1273 return;
1274
1275 /*
1276 * Make sure we're not on PC8 state before disabling PC8, otherwise
1277 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
1278 */
1279 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1280
1281 if (val & LCPLL_POWER_DOWN_ALLOW) {
1282 val &= ~LCPLL_POWER_DOWN_ALLOW;
1283 intel_de_write(dev_priv, LCPLL_CTL, val);
1284 intel_de_posting_read(dev_priv, LCPLL_CTL);
1285 }
1286
1287 val = hsw_read_dcomp(dev_priv);
1288 val |= D_COMP_COMP_FORCE;
1289 val &= ~D_COMP_COMP_DISABLE;
1290 hsw_write_dcomp(dev_priv, val);
1291
1292 val = intel_de_read(dev_priv, LCPLL_CTL);
1293 val &= ~LCPLL_PLL_DISABLE;
1294 intel_de_write(dev_priv, LCPLL_CTL, val);
1295
1296 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
1297 drm_err(&dev_priv->drm, "LCPLL not locked yet\n");
1298
1299 if (val & LCPLL_CD_SOURCE_FCLK) {
1300 val = intel_de_read(dev_priv, LCPLL_CTL);
1301 val &= ~LCPLL_CD_SOURCE_FCLK;
1302 intel_de_write(dev_priv, LCPLL_CTL, val);
1303
1304 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
1305 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
1306 drm_err(&dev_priv->drm,
1307 "Switching back to LCPLL failed\n");
1308 }
1309
1310 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1311
1312 intel_update_cdclk(dev_priv);
1313 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1314 }
1315
1316 /*
1317 * Package states C8 and deeper are really deep PC states that can only be
1318 * reached when all the devices on the system allow it, so even if the graphics
1319 * device allows PC8+, it doesn't mean the system will actually get to these
1320 * states. Our driver only allows PC8+ when going into runtime PM.
1321 *
1322 * The requirements for PC8+ are that all the outputs are disabled, the power
1323 * well is disabled and most interrupts are disabled, and these are also
1324 * requirements for runtime PM. When these conditions are met, we manually do
1325 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
1326 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
1327 * hang the machine.
1328 *
1329 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1330 * the state of some registers, so when we come back from PC8+ we need to
1331 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1332 * need to take care of the registers kept by RC6. Notice that this happens even
1333 * if we don't put the device in PCI D3 state (which is what currently happens
1334 * because of the runtime PM support).
1335 *
1336 * For more, read "Display Sequences for Package C8" on the hardware
1337 * documentation.
1338 */
hsw_enable_pc8(struct drm_i915_private * dev_priv)1339 static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
1340 {
1341 u32 val;
1342
1343 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n");
1344
1345 if (HAS_PCH_LPT_LP(dev_priv)) {
1346 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
1347 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
1348 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
1349 }
1350
1351 lpt_disable_clkout_dp(dev_priv);
1352 hsw_disable_lcpll(dev_priv, true, true);
1353 }
1354
hsw_disable_pc8(struct drm_i915_private * dev_priv)1355 static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
1356 {
1357 u32 val;
1358
1359 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
1360
1361 hsw_restore_lcpll(dev_priv);
1362 intel_init_pch_refclk(dev_priv);
1363
1364 if (HAS_PCH_LPT_LP(dev_priv)) {
1365 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
1366 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
1367 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
1368 }
1369 }
1370
intel_pch_reset_handshake(struct drm_i915_private * dev_priv,bool enable)1371 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
1372 bool enable)
1373 {
1374 i915_reg_t reg;
1375 u32 reset_bits, val;
1376
1377 if (IS_IVYBRIDGE(dev_priv)) {
1378 reg = GEN7_MSG_CTL;
1379 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
1380 } else {
1381 reg = HSW_NDE_RSTWRN_OPT;
1382 reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
1383 }
1384
1385 if (DISPLAY_VER(dev_priv) >= 14)
1386 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN;
1387
1388 val = intel_de_read(dev_priv, reg);
1389
1390 if (enable)
1391 val |= reset_bits;
1392 else
1393 val &= ~reset_bits;
1394
1395 intel_de_write(dev_priv, reg, val);
1396 }
1397
skl_display_core_init(struct drm_i915_private * dev_priv,bool resume)1398 static void skl_display_core_init(struct drm_i915_private *dev_priv,
1399 bool resume)
1400 {
1401 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1402 struct i915_power_well *well;
1403
1404 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1405
1406 /* enable PCH reset handshake */
1407 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1408
1409 if (!HAS_DISPLAY(dev_priv))
1410 return;
1411
1412 /* enable PG1 and Misc I/O */
1413 mutex_lock(&power_domains->lock);
1414
1415 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1416 intel_power_well_enable(dev_priv, well);
1417
1418 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1419 intel_power_well_enable(dev_priv, well);
1420
1421 mutex_unlock(&power_domains->lock);
1422
1423 intel_cdclk_init_hw(dev_priv);
1424
1425 gen9_dbuf_enable(dev_priv);
1426
1427 if (resume)
1428 intel_dmc_load_program(dev_priv);
1429 }
1430
skl_display_core_uninit(struct drm_i915_private * dev_priv)1431 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
1432 {
1433 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1434 struct i915_power_well *well;
1435
1436 if (!HAS_DISPLAY(dev_priv))
1437 return;
1438
1439 gen9_disable_dc_states(dev_priv);
1440 /* TODO: disable DMC program */
1441
1442 gen9_dbuf_disable(dev_priv);
1443
1444 intel_cdclk_uninit_hw(dev_priv);
1445
1446 /* The spec doesn't call for removing the reset handshake flag */
1447 /* disable PG1 and Misc I/O */
1448
1449 mutex_lock(&power_domains->lock);
1450
1451 /*
1452 * BSpec says to keep the MISC IO power well enabled here, only
1453 * remove our request for power well 1.
1454 * Note that even though the driver's request is removed power well 1
1455 * may stay enabled after this due to DMC's own request on it.
1456 */
1457 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1458 intel_power_well_disable(dev_priv, well);
1459
1460 mutex_unlock(&power_domains->lock);
1461
1462 usleep_range(10, 30); /* 10 us delay per Bspec */
1463 }
1464
bxt_display_core_init(struct drm_i915_private * dev_priv,bool resume)1465 static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
1466 {
1467 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1468 struct i915_power_well *well;
1469
1470 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1471
1472 /*
1473 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
1474 * or else the reset will hang because there is no PCH to respond.
1475 * Move the handshake programming to initialization sequence.
1476 * Previously was left up to BIOS.
1477 */
1478 intel_pch_reset_handshake(dev_priv, false);
1479
1480 if (!HAS_DISPLAY(dev_priv))
1481 return;
1482
1483 /* Enable PG1 */
1484 mutex_lock(&power_domains->lock);
1485
1486 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1487 intel_power_well_enable(dev_priv, well);
1488
1489 mutex_unlock(&power_domains->lock);
1490
1491 intel_cdclk_init_hw(dev_priv);
1492
1493 gen9_dbuf_enable(dev_priv);
1494
1495 if (resume)
1496 intel_dmc_load_program(dev_priv);
1497 }
1498
bxt_display_core_uninit(struct drm_i915_private * dev_priv)1499 static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
1500 {
1501 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1502 struct i915_power_well *well;
1503
1504 if (!HAS_DISPLAY(dev_priv))
1505 return;
1506
1507 gen9_disable_dc_states(dev_priv);
1508 /* TODO: disable DMC program */
1509
1510 gen9_dbuf_disable(dev_priv);
1511
1512 intel_cdclk_uninit_hw(dev_priv);
1513
1514 /* The spec doesn't call for removing the reset handshake flag */
1515
1516 /*
1517 * Disable PW1 (PG1).
1518 * Note that even though the driver's request is removed power well 1
1519 * may stay enabled after this due to DMC's own request on it.
1520 */
1521 mutex_lock(&power_domains->lock);
1522
1523 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1524 intel_power_well_disable(dev_priv, well);
1525
1526 mutex_unlock(&power_domains->lock);
1527
1528 usleep_range(10, 30); /* 10 us delay per Bspec */
1529 }
1530
1531 struct buddy_page_mask {
1532 u32 page_mask;
1533 u8 type;
1534 u8 num_channels;
1535 };
1536
1537 static const struct buddy_page_mask tgl_buddy_page_masks[] = {
1538 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
1539 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF },
1540 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
1541 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
1542 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
1543 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E },
1544 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
1545 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
1546 {}
1547 };
1548
1549 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
1550 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
1551 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 },
1552 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 },
1553 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
1554 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
1555 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 },
1556 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 },
1557 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
1558 {}
1559 };
1560
tgl_bw_buddy_init(struct drm_i915_private * dev_priv)1561 static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
1562 {
1563 enum intel_dram_type type = dev_priv->dram_info.type;
1564 u8 num_channels = dev_priv->dram_info.num_channels;
1565 const struct buddy_page_mask *table;
1566 unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
1567 int config, i;
1568
1569 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */
1570 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv))
1571 return;
1572
1573 if (IS_ALDERLAKE_S(dev_priv) ||
1574 IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
1575 IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
1576 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
1577 /* Wa_1409767108:tgl,dg1,adl-s */
1578 table = wa_1409767108_buddy_page_masks;
1579 else
1580 table = tgl_buddy_page_masks;
1581
1582 for (config = 0; table[config].page_mask != 0; config++)
1583 if (table[config].num_channels == num_channels &&
1584 table[config].type == type)
1585 break;
1586
1587 if (table[config].page_mask == 0) {
1588 drm_dbg(&dev_priv->drm,
1589 "Unknown memory configuration; disabling address buddy logic.\n");
1590 for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
1591 intel_de_write(dev_priv, BW_BUDDY_CTL(i),
1592 BW_BUDDY_DISABLE);
1593 } else {
1594 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
1595 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
1596 table[config].page_mask);
1597
1598 /* Wa_22010178259:tgl,dg1,rkl,adl-s */
1599 if (DISPLAY_VER(dev_priv) == 12)
1600 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
1601 BW_BUDDY_TLB_REQ_TIMER_MASK,
1602 BW_BUDDY_TLB_REQ_TIMER(0x8));
1603 }
1604 }
1605 }
1606
icl_display_core_init(struct drm_i915_private * dev_priv,bool resume)1607 static void icl_display_core_init(struct drm_i915_private *dev_priv,
1608 bool resume)
1609 {
1610 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1611 struct i915_power_well *well;
1612 u32 val;
1613
1614 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1615
1616 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
1617 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
1618 INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
1619 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
1620 PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
1621
1622 /* 1. Enable PCH reset handshake. */
1623 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1624
1625 if (!HAS_DISPLAY(dev_priv))
1626 return;
1627
1628 /* 2. Initialize all combo phys */
1629 intel_combo_phy_init(dev_priv);
1630
1631 /*
1632 * 3. Enable Power Well 1 (PG1).
1633 * The AUX IO power wells will be enabled on demand.
1634 */
1635 mutex_lock(&power_domains->lock);
1636 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1637 intel_power_well_enable(dev_priv, well);
1638 mutex_unlock(&power_domains->lock);
1639
1640 /* 4. Enable CDCLK. */
1641 intel_cdclk_init_hw(dev_priv);
1642
1643 if (DISPLAY_VER(dev_priv) >= 12)
1644 gen12_dbuf_slices_config(dev_priv);
1645
1646 /* 5. Enable DBUF. */
1647 gen9_dbuf_enable(dev_priv);
1648
1649 /* 6. Setup MBUS. */
1650 icl_mbus_init(dev_priv);
1651
1652 /* 7. Program arbiter BW_BUDDY registers */
1653 if (DISPLAY_VER(dev_priv) >= 12)
1654 tgl_bw_buddy_init(dev_priv);
1655
1656 /* 8. Ensure PHYs have completed calibration and adaptation */
1657 if (IS_DG2(dev_priv))
1658 intel_snps_phy_wait_for_calibration(dev_priv);
1659
1660 if (resume)
1661 intel_dmc_load_program(dev_priv);
1662
1663 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
1664 if (DISPLAY_VER(dev_priv) >= 12) {
1665 val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
1666 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
1667 intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
1668 }
1669
1670 /* Wa_14011503030:xelpd */
1671 if (DISPLAY_VER(dev_priv) >= 13)
1672 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1673 }
1674
icl_display_core_uninit(struct drm_i915_private * dev_priv)1675 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
1676 {
1677 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1678 struct i915_power_well *well;
1679
1680 if (!HAS_DISPLAY(dev_priv))
1681 return;
1682
1683 gen9_disable_dc_states(dev_priv);
1684 intel_dmc_disable_program(dev_priv);
1685
1686 /* 1. Disable all display engine functions -> aready done */
1687
1688 /* 2. Disable DBUF */
1689 gen9_dbuf_disable(dev_priv);
1690
1691 /* 3. Disable CD clock */
1692 intel_cdclk_uninit_hw(dev_priv);
1693
1694 /*
1695 * 4. Disable Power Well 1 (PG1).
1696 * The AUX IO power wells are toggled on demand, so they are already
1697 * disabled at this point.
1698 */
1699 mutex_lock(&power_domains->lock);
1700 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1701 intel_power_well_disable(dev_priv, well);
1702 mutex_unlock(&power_domains->lock);
1703
1704 /* 5. */
1705 intel_combo_phy_uninit(dev_priv);
1706 }
1707
chv_phy_control_init(struct drm_i915_private * dev_priv)1708 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1709 {
1710 struct i915_power_well *cmn_bc =
1711 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1712 struct i915_power_well *cmn_d =
1713 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1714
1715 /*
1716 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1717 * workaround never ever read DISPLAY_PHY_CONTROL, and
1718 * instead maintain a shadow copy ourselves. Use the actual
1719 * power well state and lane status to reconstruct the
1720 * expected initial value.
1721 */
1722 dev_priv->display.power.chv_phy_control =
1723 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1724 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1725 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1726 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1727 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1728
1729 /*
1730 * If all lanes are disabled we leave the override disabled
1731 * with all power down bits cleared to match the state we
1732 * would use after disabling the port. Otherwise enable the
1733 * override and set the lane powerdown bits accding to the
1734 * current lane status.
1735 */
1736 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1737 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
1738 unsigned int mask;
1739
1740 mask = status & DPLL_PORTB_READY_MASK;
1741 if (mask == 0xf)
1742 mask = 0x0;
1743 else
1744 dev_priv->display.power.chv_phy_control |=
1745 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1746
1747 dev_priv->display.power.chv_phy_control |=
1748 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1749
1750 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1751 if (mask == 0xf)
1752 mask = 0x0;
1753 else
1754 dev_priv->display.power.chv_phy_control |=
1755 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1756
1757 dev_priv->display.power.chv_phy_control |=
1758 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1759
1760 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1761
1762 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
1763 } else {
1764 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
1765 }
1766
1767 if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1768 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
1769 unsigned int mask;
1770
1771 mask = status & DPLL_PORTD_READY_MASK;
1772
1773 if (mask == 0xf)
1774 mask = 0x0;
1775 else
1776 dev_priv->display.power.chv_phy_control |=
1777 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1778
1779 dev_priv->display.power.chv_phy_control |=
1780 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1781
1782 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1783
1784 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
1785 } else {
1786 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
1787 }
1788
1789 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
1790 dev_priv->display.power.chv_phy_control);
1791
1792 /* Defer application of initial phy_control to enabling the powerwell */
1793 }
1794
vlv_cmnlane_wa(struct drm_i915_private * dev_priv)1795 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1796 {
1797 struct i915_power_well *cmn =
1798 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1799 struct i915_power_well *disp2d =
1800 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
1801
1802 /* If the display might be already active skip this */
1803 if (intel_power_well_is_enabled(dev_priv, cmn) &&
1804 intel_power_well_is_enabled(dev_priv, disp2d) &&
1805 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
1806 return;
1807
1808 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
1809
1810 /* cmnlane needs DPLL registers */
1811 intel_power_well_enable(dev_priv, disp2d);
1812
1813 /*
1814 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1815 * Need to assert and de-assert PHY SB reset by gating the
1816 * common lane power, then un-gating it.
1817 * Simply ungating isn't enough to reset the PHY enough to get
1818 * ports and lanes running.
1819 */
1820 intel_power_well_disable(dev_priv, cmn);
1821 }
1822
vlv_punit_is_power_gated(struct drm_i915_private * dev_priv,u32 reg0)1823 static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
1824 {
1825 bool ret;
1826
1827 vlv_punit_get(dev_priv);
1828 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
1829 vlv_punit_put(dev_priv);
1830
1831 return ret;
1832 }
1833
assert_ved_power_gated(struct drm_i915_private * dev_priv)1834 static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
1835 {
1836 drm_WARN(&dev_priv->drm,
1837 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
1838 "VED not power gated\n");
1839 }
1840
assert_isp_power_gated(struct drm_i915_private * dev_priv)1841 static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
1842 {
1843 static const struct pci_device_id isp_ids[] = {
1844 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
1845 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
1846 {}
1847 };
1848
1849 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) &&
1850 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
1851 "ISP not power gated\n");
1852 }
1853
1854 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1855
1856 /**
1857 * intel_power_domains_init_hw - initialize hardware power domain state
1858 * @i915: i915 device instance
1859 * @resume: Called from resume code paths or not
1860 *
1861 * This function initializes the hardware power domain state and enables all
1862 * power wells belonging to the INIT power domain. Power wells in other
1863 * domains (and not in the INIT domain) are referenced or disabled by
1864 * intel_modeset_readout_hw_state(). After that the reference count of each
1865 * power well must match its HW enabled state, see
1866 * intel_power_domains_verify_state().
1867 *
1868 * It will return with power domains disabled (to be enabled later by
1869 * intel_power_domains_enable()) and must be paired with
1870 * intel_power_domains_driver_remove().
1871 */
intel_power_domains_init_hw(struct drm_i915_private * i915,bool resume)1872 void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
1873 {
1874 struct i915_power_domains *power_domains = &i915->display.power.domains;
1875
1876 power_domains->initializing = true;
1877
1878 if (DISPLAY_VER(i915) >= 11) {
1879 icl_display_core_init(i915, resume);
1880 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1881 bxt_display_core_init(i915, resume);
1882 } else if (DISPLAY_VER(i915) == 9) {
1883 skl_display_core_init(i915, resume);
1884 } else if (IS_CHERRYVIEW(i915)) {
1885 mutex_lock(&power_domains->lock);
1886 chv_phy_control_init(i915);
1887 mutex_unlock(&power_domains->lock);
1888 assert_isp_power_gated(i915);
1889 } else if (IS_VALLEYVIEW(i915)) {
1890 mutex_lock(&power_domains->lock);
1891 vlv_cmnlane_wa(i915);
1892 mutex_unlock(&power_domains->lock);
1893 assert_ved_power_gated(i915);
1894 assert_isp_power_gated(i915);
1895 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
1896 hsw_assert_cdclk(i915);
1897 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1898 } else if (IS_IVYBRIDGE(i915)) {
1899 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1900 }
1901
1902 /*
1903 * Keep all power wells enabled for any dependent HW access during
1904 * initialization and to make sure we keep BIOS enabled display HW
1905 * resources powered until display HW readout is complete. We drop
1906 * this reference in intel_power_domains_enable().
1907 */
1908 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
1909 power_domains->init_wakeref =
1910 intel_display_power_get(i915, POWER_DOMAIN_INIT);
1911
1912 /* Disable power support if the user asked so. */
1913 if (!i915->params.disable_power_well) {
1914 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
1915 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
1916 POWER_DOMAIN_INIT);
1917 }
1918 intel_power_domains_sync_hw(i915);
1919
1920 power_domains->initializing = false;
1921 }
1922
1923 /**
1924 * intel_power_domains_driver_remove - deinitialize hw power domain state
1925 * @i915: i915 device instance
1926 *
1927 * De-initializes the display power domain HW state. It also ensures that the
1928 * device stays powered up so that the driver can be reloaded.
1929 *
1930 * It must be called with power domains already disabled (after a call to
1931 * intel_power_domains_disable()) and must be paired with
1932 * intel_power_domains_init_hw().
1933 */
intel_power_domains_driver_remove(struct drm_i915_private * i915)1934 void intel_power_domains_driver_remove(struct drm_i915_private *i915)
1935 {
1936 intel_wakeref_t wakeref __maybe_unused =
1937 fetch_and_zero(&i915->display.power.domains.init_wakeref);
1938
1939 /* Remove the refcount we took to keep power well support disabled. */
1940 if (!i915->params.disable_power_well)
1941 intel_display_power_put(i915, POWER_DOMAIN_INIT,
1942 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
1943
1944 intel_display_power_flush_work_sync(i915);
1945
1946 intel_power_domains_verify_state(i915);
1947
1948 /* Keep the power well enabled, but cancel its rpm wakeref. */
1949 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1950 }
1951
1952 /**
1953 * intel_power_domains_sanitize_state - sanitize power domains state
1954 * @i915: i915 device instance
1955 *
1956 * Sanitize the power domains state during driver loading and system resume.
1957 * The function will disable all display power wells that BIOS has enabled
1958 * without a user for it (any user for a power well has taken a reference
1959 * on it by the time this function is called, after the state of all the
1960 * pipe, encoder, etc. HW resources have been sanitized).
1961 */
intel_power_domains_sanitize_state(struct drm_i915_private * i915)1962 void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
1963 {
1964 struct i915_power_domains *power_domains = &i915->display.power.domains;
1965 struct i915_power_well *power_well;
1966
1967 mutex_lock(&power_domains->lock);
1968
1969 for_each_power_well_reverse(i915, power_well) {
1970 if (power_well->desc->always_on || power_well->count ||
1971 !intel_power_well_is_enabled(i915, power_well))
1972 continue;
1973
1974 drm_dbg_kms(&i915->drm,
1975 "BIOS left unused %s power well enabled, disabling it\n",
1976 intel_power_well_name(power_well));
1977 intel_power_well_disable(i915, power_well);
1978 }
1979
1980 mutex_unlock(&power_domains->lock);
1981 }
1982
1983 /**
1984 * intel_power_domains_enable - enable toggling of display power wells
1985 * @i915: i915 device instance
1986 *
1987 * Enable the ondemand enabling/disabling of the display power wells. Note that
1988 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
1989 * only at specific points of the display modeset sequence, thus they are not
1990 * affected by the intel_power_domains_enable()/disable() calls. The purpose
1991 * of these function is to keep the rest of power wells enabled until the end
1992 * of display HW readout (which will acquire the power references reflecting
1993 * the current HW state).
1994 */
intel_power_domains_enable(struct drm_i915_private * i915)1995 void intel_power_domains_enable(struct drm_i915_private *i915)
1996 {
1997 intel_wakeref_t wakeref __maybe_unused =
1998 fetch_and_zero(&i915->display.power.domains.init_wakeref);
1999
2000 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2001 intel_power_domains_verify_state(i915);
2002 }
2003
2004 /**
2005 * intel_power_domains_disable - disable toggling of display power wells
2006 * @i915: i915 device instance
2007 *
2008 * Disable the ondemand enabling/disabling of the display power wells. See
2009 * intel_power_domains_enable() for which power wells this call controls.
2010 */
intel_power_domains_disable(struct drm_i915_private * i915)2011 void intel_power_domains_disable(struct drm_i915_private *i915)
2012 {
2013 struct i915_power_domains *power_domains = &i915->display.power.domains;
2014
2015 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2016 power_domains->init_wakeref =
2017 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2018
2019 intel_power_domains_verify_state(i915);
2020 }
2021
2022 /**
2023 * intel_power_domains_suspend - suspend power domain state
2024 * @i915: i915 device instance
2025 * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
2026 *
2027 * This function prepares the hardware power domain state before entering
2028 * system suspend.
2029 *
2030 * It must be called with power domains already disabled (after a call to
2031 * intel_power_domains_disable()) and paired with intel_power_domains_resume().
2032 */
intel_power_domains_suspend(struct drm_i915_private * i915,enum i915_drm_suspend_mode suspend_mode)2033 void intel_power_domains_suspend(struct drm_i915_private *i915,
2034 enum i915_drm_suspend_mode suspend_mode)
2035 {
2036 struct i915_power_domains *power_domains = &i915->display.power.domains;
2037 intel_wakeref_t wakeref __maybe_unused =
2038 fetch_and_zero(&power_domains->init_wakeref);
2039
2040 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2041
2042 /*
2043 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
2044 * support don't manually deinit the power domains. This also means the
2045 * DMC firmware will stay active, it will power down any HW
2046 * resources as required and also enable deeper system power states
2047 * that would be blocked if the firmware was inactive.
2048 */
2049 if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
2050 suspend_mode == I915_DRM_SUSPEND_IDLE &&
2051 intel_dmc_has_payload(i915)) {
2052 intel_display_power_flush_work(i915);
2053 intel_power_domains_verify_state(i915);
2054 return;
2055 }
2056
2057 /*
2058 * Even if power well support was disabled we still want to disable
2059 * power wells if power domains must be deinitialized for suspend.
2060 */
2061 if (!i915->params.disable_power_well)
2062 intel_display_power_put(i915, POWER_DOMAIN_INIT,
2063 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
2064
2065 intel_display_power_flush_work(i915);
2066 intel_power_domains_verify_state(i915);
2067
2068 if (DISPLAY_VER(i915) >= 11)
2069 icl_display_core_uninit(i915);
2070 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
2071 bxt_display_core_uninit(i915);
2072 else if (DISPLAY_VER(i915) == 9)
2073 skl_display_core_uninit(i915);
2074
2075 power_domains->display_core_suspended = true;
2076 }
2077
2078 /**
2079 * intel_power_domains_resume - resume power domain state
2080 * @i915: i915 device instance
2081 *
2082 * This function resume the hardware power domain state during system resume.
2083 *
2084 * It will return with power domain support disabled (to be enabled later by
2085 * intel_power_domains_enable()) and must be paired with
2086 * intel_power_domains_suspend().
2087 */
intel_power_domains_resume(struct drm_i915_private * i915)2088 void intel_power_domains_resume(struct drm_i915_private *i915)
2089 {
2090 struct i915_power_domains *power_domains = &i915->display.power.domains;
2091
2092 if (power_domains->display_core_suspended) {
2093 intel_power_domains_init_hw(i915, true);
2094 power_domains->display_core_suspended = false;
2095 } else {
2096 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2097 power_domains->init_wakeref =
2098 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2099 }
2100
2101 intel_power_domains_verify_state(i915);
2102 }
2103
2104 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2105
intel_power_domains_dump_info(struct drm_i915_private * i915)2106 static void intel_power_domains_dump_info(struct drm_i915_private *i915)
2107 {
2108 struct i915_power_domains *power_domains = &i915->display.power.domains;
2109 struct i915_power_well *power_well;
2110
2111 for_each_power_well(i915, power_well) {
2112 enum intel_display_power_domain domain;
2113
2114 drm_dbg(&i915->drm, "%-25s %d\n",
2115 intel_power_well_name(power_well), intel_power_well_refcount(power_well));
2116
2117 for_each_power_domain(domain, intel_power_well_domains(power_well))
2118 drm_dbg(&i915->drm, " %-23s %d\n",
2119 intel_display_power_domain_str(domain),
2120 power_domains->domain_use_count[domain]);
2121 }
2122 }
2123
2124 /**
2125 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
2126 * @i915: i915 device instance
2127 *
2128 * Verify if the reference count of each power well matches its HW enabled
2129 * state and the total refcount of the domains it belongs to. This must be
2130 * called after modeset HW state sanitization, which is responsible for
2131 * acquiring reference counts for any power wells in use and disabling the
2132 * ones left on by BIOS but not required by any active output.
2133 */
intel_power_domains_verify_state(struct drm_i915_private * i915)2134 static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2135 {
2136 struct i915_power_domains *power_domains = &i915->display.power.domains;
2137 struct i915_power_well *power_well;
2138 bool dump_domain_info;
2139
2140 mutex_lock(&power_domains->lock);
2141
2142 verify_async_put_domains_state(power_domains);
2143
2144 dump_domain_info = false;
2145 for_each_power_well(i915, power_well) {
2146 enum intel_display_power_domain domain;
2147 int domains_count;
2148 bool enabled;
2149
2150 enabled = intel_power_well_is_enabled(i915, power_well);
2151 if ((intel_power_well_refcount(power_well) ||
2152 intel_power_well_is_always_on(power_well)) !=
2153 enabled)
2154 drm_err(&i915->drm,
2155 "power well %s state mismatch (refcount %d/enabled %d)",
2156 intel_power_well_name(power_well),
2157 intel_power_well_refcount(power_well), enabled);
2158
2159 domains_count = 0;
2160 for_each_power_domain(domain, intel_power_well_domains(power_well))
2161 domains_count += power_domains->domain_use_count[domain];
2162
2163 if (intel_power_well_refcount(power_well) != domains_count) {
2164 drm_err(&i915->drm,
2165 "power well %s refcount/domain refcount mismatch "
2166 "(refcount %d/domains refcount %d)\n",
2167 intel_power_well_name(power_well),
2168 intel_power_well_refcount(power_well),
2169 domains_count);
2170 dump_domain_info = true;
2171 }
2172 }
2173
2174 if (dump_domain_info) {
2175 static bool dumped;
2176
2177 if (!dumped) {
2178 intel_power_domains_dump_info(i915);
2179 dumped = true;
2180 }
2181 }
2182
2183 mutex_unlock(&power_domains->lock);
2184 }
2185
2186 #else
2187
intel_power_domains_verify_state(struct drm_i915_private * i915)2188 static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2189 {
2190 }
2191
2192 #endif
2193
intel_display_power_suspend_late(struct drm_i915_private * i915)2194 void intel_display_power_suspend_late(struct drm_i915_private *i915)
2195 {
2196 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2197 IS_BROXTON(i915)) {
2198 bxt_enable_dc9(i915);
2199 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2200 hsw_enable_pc8(i915);
2201 }
2202
2203 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2204 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2205 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2206 }
2207
intel_display_power_resume_early(struct drm_i915_private * i915)2208 void intel_display_power_resume_early(struct drm_i915_private *i915)
2209 {
2210 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2211 IS_BROXTON(i915)) {
2212 gen9_sanitize_dc_state(i915);
2213 bxt_disable_dc9(i915);
2214 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2215 hsw_disable_pc8(i915);
2216 }
2217
2218 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2219 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2220 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
2221 }
2222
intel_display_power_suspend(struct drm_i915_private * i915)2223 void intel_display_power_suspend(struct drm_i915_private *i915)
2224 {
2225 if (DISPLAY_VER(i915) >= 11) {
2226 icl_display_core_uninit(i915);
2227 bxt_enable_dc9(i915);
2228 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2229 bxt_display_core_uninit(i915);
2230 bxt_enable_dc9(i915);
2231 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2232 hsw_enable_pc8(i915);
2233 }
2234 }
2235
intel_display_power_resume(struct drm_i915_private * i915)2236 void intel_display_power_resume(struct drm_i915_private *i915)
2237 {
2238 if (DISPLAY_VER(i915) >= 11) {
2239 bxt_disable_dc9(i915);
2240 icl_display_core_init(i915, true);
2241 if (intel_dmc_has_payload(i915)) {
2242 if (i915->display.dmc.allowed_dc_mask &
2243 DC_STATE_EN_UPTO_DC6)
2244 skl_enable_dc6(i915);
2245 else if (i915->display.dmc.allowed_dc_mask &
2246 DC_STATE_EN_UPTO_DC5)
2247 gen9_enable_dc5(i915);
2248 }
2249 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2250 bxt_disable_dc9(i915);
2251 bxt_display_core_init(i915, true);
2252 if (intel_dmc_has_payload(i915) &&
2253 (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2254 gen9_enable_dc5(i915);
2255 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2256 hsw_disable_pc8(i915);
2257 }
2258 }
2259
intel_display_power_debug(struct drm_i915_private * i915,struct seq_file * m)2260 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
2261 {
2262 struct i915_power_domains *power_domains = &i915->display.power.domains;
2263 int i;
2264
2265 mutex_lock(&power_domains->lock);
2266
2267 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2268 for (i = 0; i < power_domains->power_well_count; i++) {
2269 struct i915_power_well *power_well;
2270 enum intel_display_power_domain power_domain;
2271
2272 power_well = &power_domains->power_wells[i];
2273 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well),
2274 intel_power_well_refcount(power_well));
2275
2276 for_each_power_domain(power_domain, intel_power_well_domains(power_well))
2277 seq_printf(m, " %-23s %d\n",
2278 intel_display_power_domain_str(power_domain),
2279 power_domains->domain_use_count[power_domain]);
2280 }
2281
2282 mutex_unlock(&power_domains->lock);
2283 }
2284
2285 struct intel_ddi_port_domains {
2286 enum port port_start;
2287 enum port port_end;
2288 enum aux_ch aux_ch_start;
2289 enum aux_ch aux_ch_end;
2290
2291 enum intel_display_power_domain ddi_lanes;
2292 enum intel_display_power_domain ddi_io;
2293 enum intel_display_power_domain aux_legacy_usbc;
2294 enum intel_display_power_domain aux_tbt;
2295 };
2296
2297 static const struct intel_ddi_port_domains
2298 i9xx_port_domains[] = {
2299 {
2300 .port_start = PORT_A,
2301 .port_end = PORT_F,
2302 .aux_ch_start = AUX_CH_A,
2303 .aux_ch_end = AUX_CH_F,
2304
2305 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2306 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2307 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2308 .aux_tbt = POWER_DOMAIN_INVALID,
2309 },
2310 };
2311
2312 static const struct intel_ddi_port_domains
2313 d11_port_domains[] = {
2314 {
2315 .port_start = PORT_A,
2316 .port_end = PORT_B,
2317 .aux_ch_start = AUX_CH_A,
2318 .aux_ch_end = AUX_CH_B,
2319
2320 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2321 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2322 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2323 .aux_tbt = POWER_DOMAIN_INVALID,
2324 }, {
2325 .port_start = PORT_C,
2326 .port_end = PORT_F,
2327 .aux_ch_start = AUX_CH_C,
2328 .aux_ch_end = AUX_CH_F,
2329
2330 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
2331 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
2332 .aux_legacy_usbc = POWER_DOMAIN_AUX_C,
2333 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2334 },
2335 };
2336
2337 static const struct intel_ddi_port_domains
2338 d12_port_domains[] = {
2339 {
2340 .port_start = PORT_A,
2341 .port_end = PORT_C,
2342 .aux_ch_start = AUX_CH_A,
2343 .aux_ch_end = AUX_CH_C,
2344
2345 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2346 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2347 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2348 .aux_tbt = POWER_DOMAIN_INVALID,
2349 }, {
2350 .port_start = PORT_TC1,
2351 .port_end = PORT_TC6,
2352 .aux_ch_start = AUX_CH_USBC1,
2353 .aux_ch_end = AUX_CH_USBC6,
2354
2355 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2356 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2357 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2358 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2359 },
2360 };
2361
2362 static const struct intel_ddi_port_domains
2363 d13_port_domains[] = {
2364 {
2365 .port_start = PORT_A,
2366 .port_end = PORT_C,
2367 .aux_ch_start = AUX_CH_A,
2368 .aux_ch_end = AUX_CH_C,
2369
2370 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2371 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2372 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2373 .aux_tbt = POWER_DOMAIN_INVALID,
2374 }, {
2375 .port_start = PORT_TC1,
2376 .port_end = PORT_TC4,
2377 .aux_ch_start = AUX_CH_USBC1,
2378 .aux_ch_end = AUX_CH_USBC4,
2379
2380 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2381 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2382 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2383 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2384 }, {
2385 .port_start = PORT_D_XELPD,
2386 .port_end = PORT_E_XELPD,
2387 .aux_ch_start = AUX_CH_D_XELPD,
2388 .aux_ch_end = AUX_CH_E_XELPD,
2389
2390 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
2391 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
2392 .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
2393 .aux_tbt = POWER_DOMAIN_INVALID,
2394 },
2395 };
2396
2397 static void
intel_port_domains_for_platform(struct drm_i915_private * i915,const struct intel_ddi_port_domains ** domains,int * domains_size)2398 intel_port_domains_for_platform(struct drm_i915_private *i915,
2399 const struct intel_ddi_port_domains **domains,
2400 int *domains_size)
2401 {
2402 if (DISPLAY_VER(i915) >= 13) {
2403 *domains = d13_port_domains;
2404 *domains_size = ARRAY_SIZE(d13_port_domains);
2405 } else if (DISPLAY_VER(i915) >= 12) {
2406 *domains = d12_port_domains;
2407 *domains_size = ARRAY_SIZE(d12_port_domains);
2408 } else if (DISPLAY_VER(i915) >= 11) {
2409 *domains = d11_port_domains;
2410 *domains_size = ARRAY_SIZE(d11_port_domains);
2411 } else {
2412 *domains = i9xx_port_domains;
2413 *domains_size = ARRAY_SIZE(i9xx_port_domains);
2414 }
2415 }
2416
2417 static const struct intel_ddi_port_domains *
intel_port_domains_for_port(struct drm_i915_private * i915,enum port port)2418 intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
2419 {
2420 const struct intel_ddi_port_domains *domains;
2421 int domains_size;
2422 int i;
2423
2424 intel_port_domains_for_platform(i915, &domains, &domains_size);
2425 for (i = 0; i < domains_size; i++)
2426 if (port >= domains[i].port_start && port <= domains[i].port_end)
2427 return &domains[i];
2428
2429 return NULL;
2430 }
2431
2432 enum intel_display_power_domain
intel_display_power_ddi_io_domain(struct drm_i915_private * i915,enum port port)2433 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
2434 {
2435 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2436
2437 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
2438 return POWER_DOMAIN_PORT_DDI_IO_A;
2439
2440 return domains->ddi_io + (int)(port - domains->port_start);
2441 }
2442
2443 enum intel_display_power_domain
intel_display_power_ddi_lanes_domain(struct drm_i915_private * i915,enum port port)2444 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port)
2445 {
2446 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2447
2448 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
2449 return POWER_DOMAIN_PORT_DDI_LANES_A;
2450
2451 return domains->ddi_lanes + (int)(port - domains->port_start);
2452 }
2453
2454 static const struct intel_ddi_port_domains *
intel_port_domains_for_aux_ch(struct drm_i915_private * i915,enum aux_ch aux_ch)2455 intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
2456 {
2457 const struct intel_ddi_port_domains *domains;
2458 int domains_size;
2459 int i;
2460
2461 intel_port_domains_for_platform(i915, &domains, &domains_size);
2462 for (i = 0; i < domains_size; i++)
2463 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end)
2464 return &domains[i];
2465
2466 return NULL;
2467 }
2468
2469 enum intel_display_power_domain
intel_display_power_legacy_aux_domain(struct drm_i915_private * i915,enum aux_ch aux_ch)2470 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2471 {
2472 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2473
2474 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
2475 return POWER_DOMAIN_AUX_A;
2476
2477 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
2478 }
2479
2480 enum intel_display_power_domain
intel_display_power_tbt_aux_domain(struct drm_i915_private * i915,enum aux_ch aux_ch)2481 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2482 {
2483 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2484
2485 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
2486 return POWER_DOMAIN_AUX_TBT1;
2487
2488 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);
2489 }
2490