1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/string_helpers.h>
26 
27 #include <drm/drm_print.h>
28 #include <drm/i915_pciids.h>
29 
30 #include "display/intel_cdclk.h"
31 #include "display/intel_de.h"
32 #include "intel_device_info.h"
33 #include "i915_drv.h"
34 #include "i915_utils.h"
35 
36 #define PLATFORM_NAME(x) [INTEL_##x] = #x
37 static const char * const platform_names[] = {
38 	PLATFORM_NAME(I830),
39 	PLATFORM_NAME(I845G),
40 	PLATFORM_NAME(I85X),
41 	PLATFORM_NAME(I865G),
42 	PLATFORM_NAME(I915G),
43 	PLATFORM_NAME(I915GM),
44 	PLATFORM_NAME(I945G),
45 	PLATFORM_NAME(I945GM),
46 	PLATFORM_NAME(G33),
47 	PLATFORM_NAME(PINEVIEW),
48 	PLATFORM_NAME(I965G),
49 	PLATFORM_NAME(I965GM),
50 	PLATFORM_NAME(G45),
51 	PLATFORM_NAME(GM45),
52 	PLATFORM_NAME(IRONLAKE),
53 	PLATFORM_NAME(SANDYBRIDGE),
54 	PLATFORM_NAME(IVYBRIDGE),
55 	PLATFORM_NAME(VALLEYVIEW),
56 	PLATFORM_NAME(HASWELL),
57 	PLATFORM_NAME(BROADWELL),
58 	PLATFORM_NAME(CHERRYVIEW),
59 	PLATFORM_NAME(SKYLAKE),
60 	PLATFORM_NAME(BROXTON),
61 	PLATFORM_NAME(KABYLAKE),
62 	PLATFORM_NAME(GEMINILAKE),
63 	PLATFORM_NAME(COFFEELAKE),
64 	PLATFORM_NAME(COMETLAKE),
65 	PLATFORM_NAME(ICELAKE),
66 	PLATFORM_NAME(ELKHARTLAKE),
67 	PLATFORM_NAME(JASPERLAKE),
68 	PLATFORM_NAME(TIGERLAKE),
69 	PLATFORM_NAME(ROCKETLAKE),
70 	PLATFORM_NAME(DG1),
71 	PLATFORM_NAME(ALDERLAKE_S),
72 	PLATFORM_NAME(ALDERLAKE_P),
73 	PLATFORM_NAME(XEHPSDV),
74 	PLATFORM_NAME(DG2),
75 	PLATFORM_NAME(PONTEVECCHIO),
76 	PLATFORM_NAME(METEORLAKE),
77 };
78 #undef PLATFORM_NAME
79 
intel_platform_name(enum intel_platform platform)80 const char *intel_platform_name(enum intel_platform platform)
81 {
82 	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
83 
84 	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
85 			 platform_names[platform] == NULL))
86 		return "<unknown>";
87 
88 	return platform_names[platform];
89 }
90 
intel_device_info_print(const struct intel_device_info * info,const struct intel_runtime_info * runtime,struct drm_printer * p)91 void intel_device_info_print(const struct intel_device_info *info,
92 			     const struct intel_runtime_info *runtime,
93 			     struct drm_printer *p)
94 {
95 	if (runtime->graphics.ip.rel)
96 		drm_printf(p, "graphics version: %u.%02u\n",
97 			   runtime->graphics.ip.ver,
98 			   runtime->graphics.ip.rel);
99 	else
100 		drm_printf(p, "graphics version: %u\n",
101 			   runtime->graphics.ip.ver);
102 
103 	if (runtime->media.ip.rel)
104 		drm_printf(p, "media version: %u.%02u\n",
105 			   runtime->media.ip.ver,
106 			   runtime->media.ip.rel);
107 	else
108 		drm_printf(p, "media version: %u\n",
109 			   runtime->media.ip.ver);
110 
111 	if (runtime->display.ip.rel)
112 		drm_printf(p, "display version: %u.%02u\n",
113 			   runtime->display.ip.ver,
114 			   runtime->display.ip.rel);
115 	else
116 		drm_printf(p, "display version: %u\n",
117 			   runtime->display.ip.ver);
118 
119 	drm_printf(p, "gt: %d\n", info->gt);
120 	drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
121 	drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
122 	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
123 	drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
124 	drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
125 	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
126 
127 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
128 	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
129 #undef PRINT_FLAG
130 
131 	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
132 
133 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
134 	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
135 #undef PRINT_FLAG
136 
137 	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
138 	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
139 	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
140 
141 	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
142 }
143 
144 #undef INTEL_VGA_DEVICE
145 #define INTEL_VGA_DEVICE(id, info) (id)
146 
147 static const u16 subplatform_ult_ids[] = {
148 	INTEL_HSW_ULT_GT1_IDS(0),
149 	INTEL_HSW_ULT_GT2_IDS(0),
150 	INTEL_HSW_ULT_GT3_IDS(0),
151 	INTEL_BDW_ULT_GT1_IDS(0),
152 	INTEL_BDW_ULT_GT2_IDS(0),
153 	INTEL_BDW_ULT_GT3_IDS(0),
154 	INTEL_BDW_ULT_RSVD_IDS(0),
155 	INTEL_SKL_ULT_GT1_IDS(0),
156 	INTEL_SKL_ULT_GT2_IDS(0),
157 	INTEL_SKL_ULT_GT3_IDS(0),
158 	INTEL_KBL_ULT_GT1_IDS(0),
159 	INTEL_KBL_ULT_GT2_IDS(0),
160 	INTEL_KBL_ULT_GT3_IDS(0),
161 	INTEL_CFL_U_GT2_IDS(0),
162 	INTEL_CFL_U_GT3_IDS(0),
163 	INTEL_WHL_U_GT1_IDS(0),
164 	INTEL_WHL_U_GT2_IDS(0),
165 	INTEL_WHL_U_GT3_IDS(0),
166 	INTEL_CML_U_GT1_IDS(0),
167 	INTEL_CML_U_GT2_IDS(0),
168 };
169 
170 static const u16 subplatform_ulx_ids[] = {
171 	INTEL_HSW_ULX_GT1_IDS(0),
172 	INTEL_HSW_ULX_GT2_IDS(0),
173 	INTEL_BDW_ULX_GT1_IDS(0),
174 	INTEL_BDW_ULX_GT2_IDS(0),
175 	INTEL_BDW_ULX_GT3_IDS(0),
176 	INTEL_BDW_ULX_RSVD_IDS(0),
177 	INTEL_SKL_ULX_GT1_IDS(0),
178 	INTEL_SKL_ULX_GT2_IDS(0),
179 	INTEL_KBL_ULX_GT1_IDS(0),
180 	INTEL_KBL_ULX_GT2_IDS(0),
181 	INTEL_AML_KBL_GT2_IDS(0),
182 	INTEL_AML_CFL_GT2_IDS(0),
183 };
184 
185 static const u16 subplatform_portf_ids[] = {
186 	INTEL_ICL_PORT_F_IDS(0),
187 };
188 
189 static const u16 subplatform_uy_ids[] = {
190 	INTEL_TGL_12_GT2_IDS(0),
191 };
192 
193 static const u16 subplatform_n_ids[] = {
194 	INTEL_ADLN_IDS(0),
195 };
196 
197 static const u16 subplatform_rpl_ids[] = {
198 	INTEL_RPLS_IDS(0),
199 	INTEL_RPLP_IDS(0),
200 };
201 
202 static const u16 subplatform_g10_ids[] = {
203 	INTEL_DG2_G10_IDS(0),
204 	INTEL_ATS_M150_IDS(0),
205 };
206 
207 static const u16 subplatform_g11_ids[] = {
208 	INTEL_DG2_G11_IDS(0),
209 	INTEL_ATS_M75_IDS(0),
210 };
211 
212 static const u16 subplatform_g12_ids[] = {
213 	INTEL_DG2_G12_IDS(0),
214 };
215 
216 static const u16 subplatform_m_ids[] = {
217 	INTEL_MTL_M_IDS(0),
218 };
219 
220 static const u16 subplatform_p_ids[] = {
221 	INTEL_MTL_P_IDS(0),
222 };
223 
find_devid(u16 id,const u16 * p,unsigned int num)224 static bool find_devid(u16 id, const u16 *p, unsigned int num)
225 {
226 	for (; num; num--, p++) {
227 		if (*p == id)
228 			return true;
229 	}
230 
231 	return false;
232 }
233 
intel_device_info_subplatform_init(struct drm_i915_private * i915)234 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
235 {
236 	const struct intel_device_info *info = INTEL_INFO(i915);
237 	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
238 	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
239 	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
240 	u16 devid = INTEL_DEVID(i915);
241 	u32 mask = 0;
242 
243 	/* Make sure IS_<platform> checks are working. */
244 	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
245 
246 	/* Find and mark subplatform bits based on the PCI device id. */
247 	if (find_devid(devid, subplatform_ult_ids,
248 		       ARRAY_SIZE(subplatform_ult_ids))) {
249 		mask = BIT(INTEL_SUBPLATFORM_ULT);
250 	} else if (find_devid(devid, subplatform_ulx_ids,
251 			      ARRAY_SIZE(subplatform_ulx_ids))) {
252 		mask = BIT(INTEL_SUBPLATFORM_ULX);
253 		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
254 			/* ULX machines are also considered ULT. */
255 			mask |= BIT(INTEL_SUBPLATFORM_ULT);
256 		}
257 	} else if (find_devid(devid, subplatform_portf_ids,
258 			      ARRAY_SIZE(subplatform_portf_ids))) {
259 		mask = BIT(INTEL_SUBPLATFORM_PORTF);
260 	} else if (find_devid(devid, subplatform_uy_ids,
261 			   ARRAY_SIZE(subplatform_uy_ids))) {
262 		mask = BIT(INTEL_SUBPLATFORM_UY);
263 	} else if (find_devid(devid, subplatform_n_ids,
264 				ARRAY_SIZE(subplatform_n_ids))) {
265 		mask = BIT(INTEL_SUBPLATFORM_N);
266 	} else if (find_devid(devid, subplatform_rpl_ids,
267 			      ARRAY_SIZE(subplatform_rpl_ids))) {
268 		mask = BIT(INTEL_SUBPLATFORM_RPL);
269 	} else if (find_devid(devid, subplatform_g10_ids,
270 			      ARRAY_SIZE(subplatform_g10_ids))) {
271 		mask = BIT(INTEL_SUBPLATFORM_G10);
272 	} else if (find_devid(devid, subplatform_g11_ids,
273 			      ARRAY_SIZE(subplatform_g11_ids))) {
274 		mask = BIT(INTEL_SUBPLATFORM_G11);
275 	} else if (find_devid(devid, subplatform_g12_ids,
276 			      ARRAY_SIZE(subplatform_g12_ids))) {
277 		mask = BIT(INTEL_SUBPLATFORM_G12);
278 	} else if (find_devid(devid, subplatform_m_ids,
279 			      ARRAY_SIZE(subplatform_m_ids))) {
280 		mask = BIT(INTEL_SUBPLATFORM_M);
281 	} else if (find_devid(devid, subplatform_p_ids,
282 			      ARRAY_SIZE(subplatform_p_ids))) {
283 		mask = BIT(INTEL_SUBPLATFORM_P);
284 	}
285 
286 	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
287 
288 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
289 }
290 
291 /**
292  * intel_device_info_runtime_init - initialize runtime info
293  * @dev_priv: the i915 device
294  *
295  * Determine various intel_device_info fields at runtime.
296  *
297  * Use it when either:
298  *   - it's judged too laborious to fill n static structures with the limit
299  *     when a simple if statement does the job,
300  *   - run-time checks (eg read fuse/strap registers) are needed.
301  *
302  * This function needs to be called:
303  *   - after the MMIO has been setup as we are reading registers,
304  *   - after the PCH has been detected,
305  *   - before the first usage of the fields it can tweak.
306  */
intel_device_info_runtime_init(struct drm_i915_private * dev_priv)307 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
308 {
309 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
310 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
311 	enum pipe pipe;
312 
313 	/* Wa_14011765242: adl-s A0,A1 */
314 	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
315 		for_each_pipe(dev_priv, pipe)
316 			runtime->num_scalers[pipe] = 0;
317 	else if (DISPLAY_VER(dev_priv) >= 11) {
318 		for_each_pipe(dev_priv, pipe)
319 			runtime->num_scalers[pipe] = 2;
320 	} else if (DISPLAY_VER(dev_priv) >= 9) {
321 		runtime->num_scalers[PIPE_A] = 2;
322 		runtime->num_scalers[PIPE_B] = 2;
323 		runtime->num_scalers[PIPE_C] = 1;
324 	}
325 
326 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
327 
328 	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
329 		for_each_pipe(dev_priv, pipe)
330 			runtime->num_sprites[pipe] = 4;
331 	else if (DISPLAY_VER(dev_priv) >= 11)
332 		for_each_pipe(dev_priv, pipe)
333 			runtime->num_sprites[pipe] = 6;
334 	else if (DISPLAY_VER(dev_priv) == 10)
335 		for_each_pipe(dev_priv, pipe)
336 			runtime->num_sprites[pipe] = 3;
337 	else if (IS_BROXTON(dev_priv)) {
338 		/*
339 		 * Skylake and Broxton currently don't expose the topmost plane as its
340 		 * use is exclusive with the legacy cursor and we only want to expose
341 		 * one of those, not both. Until we can safely expose the topmost plane
342 		 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
343 		 * we don't expose the topmost plane at all to prevent ABI breakage
344 		 * down the line.
345 		 */
346 
347 		runtime->num_sprites[PIPE_A] = 2;
348 		runtime->num_sprites[PIPE_B] = 2;
349 		runtime->num_sprites[PIPE_C] = 1;
350 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
351 		for_each_pipe(dev_priv, pipe)
352 			runtime->num_sprites[pipe] = 2;
353 	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
354 		for_each_pipe(dev_priv, pipe)
355 			runtime->num_sprites[pipe] = 1;
356 	}
357 
358 	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
359 	    HAS_PCH_SPLIT(dev_priv)) {
360 		u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
361 		u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
362 
363 		/*
364 		 * SFUSE_STRAP is supposed to have a bit signalling the display
365 		 * is fused off. Unfortunately it seems that, at least in
366 		 * certain cases, fused off display means that PCH display
367 		 * reads don't land anywhere. In that case, we read 0s.
368 		 *
369 		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
370 		 * should be set when taking over after the firmware.
371 		 */
372 		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
373 		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
374 		    (HAS_PCH_CPT(dev_priv) &&
375 		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
376 			drm_info(&dev_priv->drm,
377 				 "Display fused off, disabling\n");
378 			runtime->pipe_mask = 0;
379 			runtime->cpu_transcoder_mask = 0;
380 			runtime->fbc_mask = 0;
381 		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
382 			drm_info(&dev_priv->drm, "PipeC fused off\n");
383 			runtime->pipe_mask &= ~BIT(PIPE_C);
384 			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
385 		}
386 	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
387 		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
388 
389 		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
390 			runtime->pipe_mask &= ~BIT(PIPE_A);
391 			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
392 			runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
393 		}
394 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
395 			runtime->pipe_mask &= ~BIT(PIPE_B);
396 			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
397 		}
398 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
399 			runtime->pipe_mask &= ~BIT(PIPE_C);
400 			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
401 		}
402 
403 		if (DISPLAY_VER(dev_priv) >= 12 &&
404 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
405 			runtime->pipe_mask &= ~BIT(PIPE_D);
406 			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
407 		}
408 
409 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
410 			runtime->has_hdcp = 0;
411 
412 		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
413 			runtime->fbc_mask = 0;
414 
415 		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
416 			runtime->has_dmc = 0;
417 
418 		if (DISPLAY_VER(dev_priv) >= 10 &&
419 		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
420 			runtime->has_dsc = 0;
421 	}
422 
423 	if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
424 		drm_info(&dev_priv->drm,
425 			 "Disabling ppGTT for VT-d support\n");
426 		runtime->ppgtt_type = INTEL_PPGTT_NONE;
427 	}
428 
429 	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
430 	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
431 
432 	if (!HAS_DISPLAY(dev_priv)) {
433 		dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
434 						   DRIVER_ATOMIC);
435 		memset(&info->display, 0, sizeof(info->display));
436 
437 		runtime->cpu_transcoder_mask = 0;
438 		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
439 		memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
440 		runtime->fbc_mask = 0;
441 		runtime->has_hdcp = false;
442 		runtime->has_dmc = false;
443 		runtime->has_dsc = false;
444 	}
445 }
446 
intel_driver_caps_print(const struct intel_driver_caps * caps,struct drm_printer * p)447 void intel_driver_caps_print(const struct intel_driver_caps *caps,
448 			     struct drm_printer *p)
449 {
450 	drm_printf(p, "Has logical contexts? %s\n",
451 		   str_yes_no(caps->has_logical_contexts));
452 	drm_printf(p, "scheduler: %x\n", caps->scheduler);
453 }
454