1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 /**
25  * DOC: atomic plane helpers
26  *
27  * The functions here are used by the atomic plane helper functions to
28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
29  * drm_plane->disable_plane()).  This allows plane updates to use the
30  * atomic state infrastructure and perform plane updates as separate
31  * prepare/check/commit/cleanup steps.
32  */
33 
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_plane_helper.h>
37 
38 #include "gt/intel_rps.h"
39 
40 #include "intel_atomic_plane.h"
41 #include "intel_cdclk.h"
42 #include "intel_display_trace.h"
43 #include "intel_display_types.h"
44 #include "intel_fb.h"
45 #include "intel_fb_pin.h"
46 #include "intel_pm.h"
47 #include "intel_sprite.h"
48 #include "skl_scaler.h"
49 
intel_plane_state_reset(struct intel_plane_state * plane_state,struct intel_plane * plane)50 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
51 				    struct intel_plane *plane)
52 {
53 	memset(plane_state, 0, sizeof(*plane_state));
54 
55 	__drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
56 
57 	plane_state->scaler_id = -1;
58 }
59 
intel_plane_alloc(void)60 struct intel_plane *intel_plane_alloc(void)
61 {
62 	struct intel_plane_state *plane_state;
63 	struct intel_plane *plane;
64 
65 	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
66 	if (!plane)
67 		return ERR_PTR(-ENOMEM);
68 
69 	plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
70 	if (!plane_state) {
71 		kfree(plane);
72 		return ERR_PTR(-ENOMEM);
73 	}
74 
75 	intel_plane_state_reset(plane_state, plane);
76 
77 	plane->base.state = &plane_state->uapi;
78 
79 	return plane;
80 }
81 
intel_plane_free(struct intel_plane * plane)82 void intel_plane_free(struct intel_plane *plane)
83 {
84 	intel_plane_destroy_state(&plane->base, plane->base.state);
85 	kfree(plane);
86 }
87 
88 /**
89  * intel_plane_duplicate_state - duplicate plane state
90  * @plane: drm plane
91  *
92  * Allocates and returns a copy of the plane state (both common and
93  * Intel-specific) for the specified plane.
94  *
95  * Returns: The newly allocated plane state, or NULL on failure.
96  */
97 struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane * plane)98 intel_plane_duplicate_state(struct drm_plane *plane)
99 {
100 	struct intel_plane_state *intel_state;
101 
102 	intel_state = to_intel_plane_state(plane->state);
103 	intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
104 
105 	if (!intel_state)
106 		return NULL;
107 
108 	__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
109 
110 	intel_state->ggtt_vma = NULL;
111 	intel_state->dpt_vma = NULL;
112 	intel_state->flags = 0;
113 
114 	/* add reference to fb */
115 	if (intel_state->hw.fb)
116 		drm_framebuffer_get(intel_state->hw.fb);
117 
118 	return &intel_state->uapi;
119 }
120 
121 /**
122  * intel_plane_destroy_state - destroy plane state
123  * @plane: drm plane
124  * @state: state object to destroy
125  *
126  * Destroys the plane state (both common and Intel-specific) for the
127  * specified plane.
128  */
129 void
intel_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)130 intel_plane_destroy_state(struct drm_plane *plane,
131 			  struct drm_plane_state *state)
132 {
133 	struct intel_plane_state *plane_state = to_intel_plane_state(state);
134 
135 	drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
136 	drm_WARN_ON(plane->dev, plane_state->dpt_vma);
137 
138 	__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
139 	if (plane_state->hw.fb)
140 		drm_framebuffer_put(plane_state->hw.fb);
141 	kfree(plane_state);
142 }
143 
intel_adjusted_rate(const struct drm_rect * src,const struct drm_rect * dst,unsigned int rate)144 unsigned int intel_adjusted_rate(const struct drm_rect *src,
145 				 const struct drm_rect *dst,
146 				 unsigned int rate)
147 {
148 	unsigned int src_w, src_h, dst_w, dst_h;
149 
150 	src_w = drm_rect_width(src) >> 16;
151 	src_h = drm_rect_height(src) >> 16;
152 	dst_w = drm_rect_width(dst);
153 	dst_h = drm_rect_height(dst);
154 
155 	/* Downscaling limits the maximum pixel rate */
156 	dst_w = min(src_w, dst_w);
157 	dst_h = min(src_h, dst_h);
158 
159 	return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
160 				dst_w * dst_h);
161 }
162 
intel_plane_pixel_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)163 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
164 				    const struct intel_plane_state *plane_state)
165 {
166 	/*
167 	 * Note we don't check for plane visibility here as
168 	 * we want to use this when calculating the cursor
169 	 * watermarks even if the cursor is fully offscreen.
170 	 * That depends on the src/dst rectangles being
171 	 * correctly populated whenever the watermark code
172 	 * considers the cursor to be visible, whether or not
173 	 * it is actually visible.
174 	 *
175 	 * See: intel_wm_plane_visible() and intel_check_cursor()
176 	 */
177 
178 	return intel_adjusted_rate(&plane_state->uapi.src,
179 				   &plane_state->uapi.dst,
180 				   crtc_state->pixel_rate);
181 }
182 
intel_plane_data_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)183 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
184 				   const struct intel_plane_state *plane_state,
185 				   int color_plane)
186 {
187 	const struct drm_framebuffer *fb = plane_state->hw.fb;
188 
189 	if (!plane_state->uapi.visible)
190 		return 0;
191 
192 	return intel_plane_pixel_rate(crtc_state, plane_state) *
193 		fb->format->cpp[color_plane];
194 }
195 
196 static bool
use_min_ddb(const struct intel_crtc_state * crtc_state,struct intel_plane * plane)197 use_min_ddb(const struct intel_crtc_state *crtc_state,
198 	    struct intel_plane *plane)
199 {
200 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
201 
202 	return DISPLAY_VER(i915) >= 13 &&
203 	       crtc_state->uapi.async_flip &&
204 	       plane->async_flip;
205 }
206 
207 static unsigned int
intel_plane_relative_data_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)208 intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
209 			       const struct intel_plane_state *plane_state,
210 			       int color_plane)
211 {
212 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
213 	const struct drm_framebuffer *fb = plane_state->hw.fb;
214 	int width, height;
215 
216 	if (plane->id == PLANE_CURSOR)
217 		return 0;
218 
219 	if (!plane_state->uapi.visible)
220 		return 0;
221 
222 	/*
223 	 * We calculate extra ddb based on ratio plane rate/total data rate
224 	 * in case, in some cases we should not allocate extra ddb for the plane,
225 	 * so do not count its data rate, if this is the case.
226 	 */
227 	if (use_min_ddb(crtc_state, plane))
228 		return 0;
229 
230 	/*
231 	 * Src coordinates are already rotated by 270 degrees for
232 	 * the 90/270 degree plane rotation cases (to match the
233 	 * GTT mapping), hence no need to account for rotation here.
234 	 */
235 	width = drm_rect_width(&plane_state->uapi.src) >> 16;
236 	height = drm_rect_height(&plane_state->uapi.src) >> 16;
237 
238 	/* UV plane does 1/2 pixel sub-sampling */
239 	if (color_plane == 1) {
240 		width /= 2;
241 		height /= 2;
242 	}
243 
244 	return width * height * fb->format->cpp[color_plane];
245 }
246 
intel_plane_calc_min_cdclk(struct intel_atomic_state * state,struct intel_plane * plane,bool * need_cdclk_calc)247 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
248 			       struct intel_plane *plane,
249 			       bool *need_cdclk_calc)
250 {
251 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
252 	const struct intel_plane_state *plane_state =
253 		intel_atomic_get_new_plane_state(state, plane);
254 	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
255 	const struct intel_cdclk_state *cdclk_state;
256 	const struct intel_crtc_state *old_crtc_state;
257 	struct intel_crtc_state *new_crtc_state;
258 
259 	if (!plane_state->uapi.visible || !plane->min_cdclk)
260 		return 0;
261 
262 	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
263 	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
264 
265 	new_crtc_state->min_cdclk[plane->id] =
266 		plane->min_cdclk(new_crtc_state, plane_state);
267 
268 	/*
269 	 * No need to check against the cdclk state if
270 	 * the min cdclk for the plane doesn't increase.
271 	 *
272 	 * Ie. we only ever increase the cdclk due to plane
273 	 * requirements. This can reduce back and forth
274 	 * display blinking due to constant cdclk changes.
275 	 */
276 	if (new_crtc_state->min_cdclk[plane->id] <=
277 	    old_crtc_state->min_cdclk[plane->id])
278 		return 0;
279 
280 	cdclk_state = intel_atomic_get_cdclk_state(state);
281 	if (IS_ERR(cdclk_state))
282 		return PTR_ERR(cdclk_state);
283 
284 	/*
285 	 * No need to recalculate the cdclk state if
286 	 * the min cdclk for the pipe doesn't increase.
287 	 *
288 	 * Ie. we only ever increase the cdclk due to plane
289 	 * requirements. This can reduce back and forth
290 	 * display blinking due to constant cdclk changes.
291 	 */
292 	if (new_crtc_state->min_cdclk[plane->id] <=
293 	    cdclk_state->min_cdclk[crtc->pipe])
294 		return 0;
295 
296 	drm_dbg_kms(&dev_priv->drm,
297 		    "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
298 		    plane->base.base.id, plane->base.name,
299 		    new_crtc_state->min_cdclk[plane->id],
300 		    crtc->base.base.id, crtc->base.name,
301 		    cdclk_state->min_cdclk[crtc->pipe]);
302 	*need_cdclk_calc = true;
303 
304 	return 0;
305 }
306 
intel_plane_clear_hw_state(struct intel_plane_state * plane_state)307 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
308 {
309 	if (plane_state->hw.fb)
310 		drm_framebuffer_put(plane_state->hw.fb);
311 
312 	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
313 }
314 
intel_plane_copy_uapi_to_hw_state(struct intel_plane_state * plane_state,const struct intel_plane_state * from_plane_state,struct intel_crtc * crtc)315 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
316 				       const struct intel_plane_state *from_plane_state,
317 				       struct intel_crtc *crtc)
318 {
319 	intel_plane_clear_hw_state(plane_state);
320 
321 	/*
322 	 * For the bigjoiner slave uapi.crtc will point at
323 	 * the master crtc. So we explicitly assign the right
324 	 * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
325 	 * the plane is logically enabled on the uapi level.
326 	 */
327 	plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
328 
329 	plane_state->hw.fb = from_plane_state->uapi.fb;
330 	if (plane_state->hw.fb)
331 		drm_framebuffer_get(plane_state->hw.fb);
332 
333 	plane_state->hw.alpha = from_plane_state->uapi.alpha;
334 	plane_state->hw.pixel_blend_mode =
335 		from_plane_state->uapi.pixel_blend_mode;
336 	plane_state->hw.rotation = from_plane_state->uapi.rotation;
337 	plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
338 	plane_state->hw.color_range = from_plane_state->uapi.color_range;
339 	plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
340 
341 	plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
342 	plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
343 }
344 
intel_plane_copy_hw_state(struct intel_plane_state * plane_state,const struct intel_plane_state * from_plane_state)345 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
346 			       const struct intel_plane_state *from_plane_state)
347 {
348 	intel_plane_clear_hw_state(plane_state);
349 
350 	memcpy(&plane_state->hw, &from_plane_state->hw,
351 	       sizeof(plane_state->hw));
352 
353 	if (plane_state->hw.fb)
354 		drm_framebuffer_get(plane_state->hw.fb);
355 }
356 
intel_plane_set_invisible(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)357 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
358 			       struct intel_plane_state *plane_state)
359 {
360 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
361 
362 	crtc_state->active_planes &= ~BIT(plane->id);
363 	crtc_state->scaled_planes &= ~BIT(plane->id);
364 	crtc_state->nv12_planes &= ~BIT(plane->id);
365 	crtc_state->c8_planes &= ~BIT(plane->id);
366 	crtc_state->data_rate[plane->id] = 0;
367 	crtc_state->data_rate_y[plane->id] = 0;
368 	crtc_state->rel_data_rate[plane->id] = 0;
369 	crtc_state->rel_data_rate_y[plane->id] = 0;
370 	crtc_state->min_cdclk[plane->id] = 0;
371 
372 	plane_state->uapi.visible = false;
373 }
374 
375 /* FIXME nuke when all wm code is atomic */
intel_wm_need_update(const struct intel_plane_state * cur,struct intel_plane_state * new)376 static bool intel_wm_need_update(const struct intel_plane_state *cur,
377 				 struct intel_plane_state *new)
378 {
379 	/* Update watermarks on tiling or size changes. */
380 	if (new->uapi.visible != cur->uapi.visible)
381 		return true;
382 
383 	if (!cur->hw.fb || !new->hw.fb)
384 		return false;
385 
386 	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
387 	    cur->hw.rotation != new->hw.rotation ||
388 	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
389 	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
390 	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
391 	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
392 		return true;
393 
394 	return false;
395 }
396 
intel_plane_is_scaled(const struct intel_plane_state * plane_state)397 static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
398 {
399 	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
400 	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
401 	int dst_w = drm_rect_width(&plane_state->uapi.dst);
402 	int dst_h = drm_rect_height(&plane_state->uapi.dst);
403 
404 	return src_w != dst_w || src_h != dst_h;
405 }
406 
intel_plane_do_async_flip(struct intel_plane * plane,const struct intel_crtc_state * old_crtc_state,const struct intel_crtc_state * new_crtc_state)407 static bool intel_plane_do_async_flip(struct intel_plane *plane,
408 				      const struct intel_crtc_state *old_crtc_state,
409 				      const struct intel_crtc_state *new_crtc_state)
410 {
411 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
412 
413 	if (!plane->async_flip)
414 		return false;
415 
416 	if (!new_crtc_state->uapi.async_flip)
417 		return false;
418 
419 	/*
420 	 * In platforms after DISPLAY13, we might need to override
421 	 * first async flip in order to change watermark levels
422 	 * as part of optimization.
423 	 * So for those, we are checking if this is a first async flip.
424 	 * For platforms earlier than DISPLAY13 we always do async flip.
425 	 */
426 	return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
427 }
428 
intel_plane_atomic_calc_changes(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)429 static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
430 					   struct intel_crtc_state *new_crtc_state,
431 					   const struct intel_plane_state *old_plane_state,
432 					   struct intel_plane_state *new_plane_state)
433 {
434 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
435 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
436 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
437 	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
438 	bool was_crtc_enabled = old_crtc_state->hw.active;
439 	bool is_crtc_enabled = new_crtc_state->hw.active;
440 	bool turn_off, turn_on, visible, was_visible;
441 	int ret;
442 
443 	if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
444 		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
445 		if (ret)
446 			return ret;
447 	}
448 
449 	was_visible = old_plane_state->uapi.visible;
450 	visible = new_plane_state->uapi.visible;
451 
452 	if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
453 		was_visible = false;
454 
455 	/*
456 	 * Visibility is calculated as if the crtc was on, but
457 	 * after scaler setup everything depends on it being off
458 	 * when the crtc isn't active.
459 	 *
460 	 * FIXME this is wrong for watermarks. Watermarks should also
461 	 * be computed as if the pipe would be active. Perhaps move
462 	 * per-plane wm computation to the .check_plane() hook, and
463 	 * only combine the results from all planes in the current place?
464 	 */
465 	if (!is_crtc_enabled) {
466 		intel_plane_set_invisible(new_crtc_state, new_plane_state);
467 		visible = false;
468 	}
469 
470 	if (!was_visible && !visible)
471 		return 0;
472 
473 	turn_off = was_visible && (!visible || mode_changed);
474 	turn_on = visible && (!was_visible || mode_changed);
475 
476 	drm_dbg_atomic(&dev_priv->drm,
477 		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
478 		       crtc->base.base.id, crtc->base.name,
479 		       plane->base.base.id, plane->base.name,
480 		       was_visible, visible,
481 		       turn_off, turn_on, mode_changed);
482 
483 	if (turn_on) {
484 		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
485 			new_crtc_state->update_wm_pre = true;
486 
487 		/* must disable cxsr around plane enable/disable */
488 		if (plane->id != PLANE_CURSOR)
489 			new_crtc_state->disable_cxsr = true;
490 	} else if (turn_off) {
491 		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
492 			new_crtc_state->update_wm_post = true;
493 
494 		/* must disable cxsr around plane enable/disable */
495 		if (plane->id != PLANE_CURSOR)
496 			new_crtc_state->disable_cxsr = true;
497 	} else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
498 		if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
499 			/* FIXME bollocks */
500 			new_crtc_state->update_wm_pre = true;
501 			new_crtc_state->update_wm_post = true;
502 		}
503 	}
504 
505 	if (visible || was_visible)
506 		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
507 
508 	/*
509 	 * ILK/SNB DVSACNTR/Sprite Enable
510 	 * IVB SPR_CTL/Sprite Enable
511 	 * "When in Self Refresh Big FIFO mode, a write to enable the
512 	 *  plane will be internally buffered and delayed while Big FIFO
513 	 *  mode is exiting."
514 	 *
515 	 * Which means that enabling the sprite can take an extra frame
516 	 * when we start in big FIFO mode (LP1+). Thus we need to drop
517 	 * down to LP0 and wait for vblank in order to make sure the
518 	 * sprite gets enabled on the next vblank after the register write.
519 	 * Doing otherwise would risk enabling the sprite one frame after
520 	 * we've already signalled flip completion. We can resume LP1+
521 	 * once the sprite has been enabled.
522 	 *
523 	 *
524 	 * WaCxSRDisabledForSpriteScaling:ivb
525 	 * IVB SPR_SCALE/Scaling Enable
526 	 * "Low Power watermarks must be disabled for at least one
527 	 *  frame before enabling sprite scaling, and kept disabled
528 	 *  until sprite scaling is disabled."
529 	 *
530 	 * ILK/SNB DVSASCALE/Scaling Enable
531 	 * "When in Self Refresh Big FIFO mode, scaling enable will be
532 	 *  masked off while Big FIFO mode is exiting."
533 	 *
534 	 * Despite the w/a only being listed for IVB we assume that
535 	 * the ILK/SNB note has similar ramifications, hence we apply
536 	 * the w/a on all three platforms.
537 	 *
538 	 * With experimental results seems this is needed also for primary
539 	 * plane, not only sprite plane.
540 	 */
541 	if (plane->id != PLANE_CURSOR &&
542 	    (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
543 	     IS_IVYBRIDGE(dev_priv)) &&
544 	    (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
545 			 intel_plane_is_scaled(new_plane_state))))
546 		new_crtc_state->disable_lp_wm = true;
547 
548 	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
549 		new_crtc_state->do_async_flip = true;
550 
551 	return 0;
552 }
553 
intel_plane_atomic_check_with_state(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)554 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
555 					struct intel_crtc_state *new_crtc_state,
556 					const struct intel_plane_state *old_plane_state,
557 					struct intel_plane_state *new_plane_state)
558 {
559 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
560 	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
561 	int ret;
562 
563 	intel_plane_set_invisible(new_crtc_state, new_plane_state);
564 	new_crtc_state->enabled_planes &= ~BIT(plane->id);
565 
566 	if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
567 		return 0;
568 
569 	ret = plane->check_plane(new_crtc_state, new_plane_state);
570 	if (ret)
571 		return ret;
572 
573 	if (fb)
574 		new_crtc_state->enabled_planes |= BIT(plane->id);
575 
576 	/* FIXME pre-g4x don't work like this */
577 	if (new_plane_state->uapi.visible)
578 		new_crtc_state->active_planes |= BIT(plane->id);
579 
580 	if (new_plane_state->uapi.visible &&
581 	    intel_plane_is_scaled(new_plane_state))
582 		new_crtc_state->scaled_planes |= BIT(plane->id);
583 
584 	if (new_plane_state->uapi.visible &&
585 	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
586 		new_crtc_state->nv12_planes |= BIT(plane->id);
587 
588 	if (new_plane_state->uapi.visible &&
589 	    fb->format->format == DRM_FORMAT_C8)
590 		new_crtc_state->c8_planes |= BIT(plane->id);
591 
592 	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
593 		new_crtc_state->update_planes |= BIT(plane->id);
594 
595 	if (new_plane_state->uapi.visible &&
596 	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
597 		new_crtc_state->data_rate_y[plane->id] =
598 			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
599 		new_crtc_state->data_rate[plane->id] =
600 			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
601 
602 		new_crtc_state->rel_data_rate_y[plane->id] =
603 			intel_plane_relative_data_rate(new_crtc_state,
604 						       new_plane_state, 0);
605 		new_crtc_state->rel_data_rate[plane->id] =
606 			intel_plane_relative_data_rate(new_crtc_state,
607 						       new_plane_state, 1);
608 	} else if (new_plane_state->uapi.visible) {
609 		new_crtc_state->data_rate[plane->id] =
610 			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
611 
612 		new_crtc_state->rel_data_rate[plane->id] =
613 			intel_plane_relative_data_rate(new_crtc_state,
614 						       new_plane_state, 0);
615 	}
616 
617 	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
618 					       old_plane_state, new_plane_state);
619 }
620 
621 static struct intel_plane *
intel_crtc_get_plane(struct intel_crtc * crtc,enum plane_id plane_id)622 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
623 {
624 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
625 	struct intel_plane *plane;
626 
627 	for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
628 		if (plane->id == plane_id)
629 			return plane;
630 	}
631 
632 	return NULL;
633 }
634 
intel_plane_atomic_check(struct intel_atomic_state * state,struct intel_plane * plane)635 int intel_plane_atomic_check(struct intel_atomic_state *state,
636 			     struct intel_plane *plane)
637 {
638 	struct drm_i915_private *i915 = to_i915(state->base.dev);
639 	struct intel_plane_state *new_plane_state =
640 		intel_atomic_get_new_plane_state(state, plane);
641 	const struct intel_plane_state *old_plane_state =
642 		intel_atomic_get_old_plane_state(state, plane);
643 	const struct intel_plane_state *new_master_plane_state;
644 	struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
645 	const struct intel_crtc_state *old_crtc_state =
646 		intel_atomic_get_old_crtc_state(state, crtc);
647 	struct intel_crtc_state *new_crtc_state =
648 		intel_atomic_get_new_crtc_state(state, crtc);
649 
650 	if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
651 		struct intel_crtc *master_crtc =
652 			intel_master_crtc(new_crtc_state);
653 		struct intel_plane *master_plane =
654 			intel_crtc_get_plane(master_crtc, plane->id);
655 
656 		new_master_plane_state =
657 			intel_atomic_get_new_plane_state(state, master_plane);
658 	} else {
659 		new_master_plane_state = new_plane_state;
660 	}
661 
662 	intel_plane_copy_uapi_to_hw_state(new_plane_state,
663 					  new_master_plane_state,
664 					  crtc);
665 
666 	new_plane_state->uapi.visible = false;
667 	if (!new_crtc_state)
668 		return 0;
669 
670 	return intel_plane_atomic_check_with_state(old_crtc_state,
671 						   new_crtc_state,
672 						   old_plane_state,
673 						   new_plane_state);
674 }
675 
676 static struct intel_plane *
skl_next_plane_to_commit(struct intel_atomic_state * state,struct intel_crtc * crtc,struct skl_ddb_entry ddb[I915_MAX_PLANES],struct skl_ddb_entry ddb_y[I915_MAX_PLANES],unsigned int * update_mask)677 skl_next_plane_to_commit(struct intel_atomic_state *state,
678 			 struct intel_crtc *crtc,
679 			 struct skl_ddb_entry ddb[I915_MAX_PLANES],
680 			 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
681 			 unsigned int *update_mask)
682 {
683 	struct intel_crtc_state *crtc_state =
684 		intel_atomic_get_new_crtc_state(state, crtc);
685 	struct intel_plane_state *plane_state;
686 	struct intel_plane *plane;
687 	int i;
688 
689 	if (*update_mask == 0)
690 		return NULL;
691 
692 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
693 		enum plane_id plane_id = plane->id;
694 
695 		if (crtc->pipe != plane->pipe ||
696 		    !(*update_mask & BIT(plane_id)))
697 			continue;
698 
699 		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
700 						ddb, I915_MAX_PLANES, plane_id) ||
701 		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
702 						ddb_y, I915_MAX_PLANES, plane_id))
703 			continue;
704 
705 		*update_mask &= ~BIT(plane_id);
706 		ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
707 		ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
708 
709 		return plane;
710 	}
711 
712 	/* should never happen */
713 	drm_WARN_ON(state->base.dev, 1);
714 
715 	return NULL;
716 }
717 
intel_plane_update_noarm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)718 void intel_plane_update_noarm(struct intel_plane *plane,
719 			      const struct intel_crtc_state *crtc_state,
720 			      const struct intel_plane_state *plane_state)
721 {
722 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
723 
724 	trace_intel_plane_update_noarm(&plane->base, crtc);
725 
726 	if (plane->update_noarm)
727 		plane->update_noarm(plane, crtc_state, plane_state);
728 }
729 
intel_plane_update_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)730 void intel_plane_update_arm(struct intel_plane *plane,
731 			    const struct intel_crtc_state *crtc_state,
732 			    const struct intel_plane_state *plane_state)
733 {
734 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
735 
736 	trace_intel_plane_update_arm(&plane->base, crtc);
737 
738 	if (crtc_state->do_async_flip && plane->async_flip)
739 		plane->async_flip(plane, crtc_state, plane_state, true);
740 	else
741 		plane->update_arm(plane, crtc_state, plane_state);
742 }
743 
intel_plane_disable_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)744 void intel_plane_disable_arm(struct intel_plane *plane,
745 			     const struct intel_crtc_state *crtc_state)
746 {
747 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
748 
749 	trace_intel_plane_disable_arm(&plane->base, crtc);
750 	plane->disable_arm(plane, crtc_state);
751 }
752 
intel_crtc_planes_update_noarm(struct intel_atomic_state * state,struct intel_crtc * crtc)753 void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
754 				    struct intel_crtc *crtc)
755 {
756 	struct intel_crtc_state *new_crtc_state =
757 		intel_atomic_get_new_crtc_state(state, crtc);
758 	u32 update_mask = new_crtc_state->update_planes;
759 	struct intel_plane_state *new_plane_state;
760 	struct intel_plane *plane;
761 	int i;
762 
763 	if (new_crtc_state->do_async_flip)
764 		return;
765 
766 	/*
767 	 * Since we only write non-arming registers here,
768 	 * the order does not matter even for skl+.
769 	 */
770 	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
771 		if (crtc->pipe != plane->pipe ||
772 		    !(update_mask & BIT(plane->id)))
773 			continue;
774 
775 		/* TODO: for mailbox updates this should be skipped */
776 		if (new_plane_state->uapi.visible ||
777 		    new_plane_state->planar_slave)
778 			intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
779 	}
780 }
781 
skl_crtc_planes_update_arm(struct intel_atomic_state * state,struct intel_crtc * crtc)782 static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
783 				       struct intel_crtc *crtc)
784 {
785 	struct intel_crtc_state *old_crtc_state =
786 		intel_atomic_get_old_crtc_state(state, crtc);
787 	struct intel_crtc_state *new_crtc_state =
788 		intel_atomic_get_new_crtc_state(state, crtc);
789 	struct skl_ddb_entry ddb[I915_MAX_PLANES];
790 	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
791 	u32 update_mask = new_crtc_state->update_planes;
792 	struct intel_plane *plane;
793 
794 	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
795 	       sizeof(old_crtc_state->wm.skl.plane_ddb));
796 	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
797 	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
798 
799 	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
800 		struct intel_plane_state *new_plane_state =
801 			intel_atomic_get_new_plane_state(state, plane);
802 
803 		/*
804 		 * TODO: for mailbox updates intel_plane_update_noarm()
805 		 * would have to be called here as well.
806 		 */
807 		if (new_plane_state->uapi.visible ||
808 		    new_plane_state->planar_slave)
809 			intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
810 		else
811 			intel_plane_disable_arm(plane, new_crtc_state);
812 	}
813 }
814 
i9xx_crtc_planes_update_arm(struct intel_atomic_state * state,struct intel_crtc * crtc)815 static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
816 					struct intel_crtc *crtc)
817 {
818 	struct intel_crtc_state *new_crtc_state =
819 		intel_atomic_get_new_crtc_state(state, crtc);
820 	u32 update_mask = new_crtc_state->update_planes;
821 	struct intel_plane_state *new_plane_state;
822 	struct intel_plane *plane;
823 	int i;
824 
825 	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
826 		if (crtc->pipe != plane->pipe ||
827 		    !(update_mask & BIT(plane->id)))
828 			continue;
829 
830 		/*
831 		 * TODO: for mailbox updates intel_plane_update_noarm()
832 		 * would have to be called here as well.
833 		 */
834 		if (new_plane_state->uapi.visible)
835 			intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
836 		else
837 			intel_plane_disable_arm(plane, new_crtc_state);
838 	}
839 }
840 
intel_crtc_planes_update_arm(struct intel_atomic_state * state,struct intel_crtc * crtc)841 void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
842 				  struct intel_crtc *crtc)
843 {
844 	struct drm_i915_private *i915 = to_i915(state->base.dev);
845 
846 	if (DISPLAY_VER(i915) >= 9)
847 		skl_crtc_planes_update_arm(state, crtc);
848 	else
849 		i9xx_crtc_planes_update_arm(state, crtc);
850 }
851 
intel_atomic_plane_check_clipping(struct intel_plane_state * plane_state,struct intel_crtc_state * crtc_state,int min_scale,int max_scale,bool can_position)852 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
853 				      struct intel_crtc_state *crtc_state,
854 				      int min_scale, int max_scale,
855 				      bool can_position)
856 {
857 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
858 	struct drm_framebuffer *fb = plane_state->hw.fb;
859 	struct drm_rect *src = &plane_state->uapi.src;
860 	struct drm_rect *dst = &plane_state->uapi.dst;
861 	const struct drm_rect *clip = &crtc_state->pipe_src;
862 	unsigned int rotation = plane_state->hw.rotation;
863 	int hscale, vscale;
864 
865 	if (!fb) {
866 		plane_state->uapi.visible = false;
867 		return 0;
868 	}
869 
870 	drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
871 
872 	/* Check scaling */
873 	hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
874 	vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
875 	if (hscale < 0 || vscale < 0) {
876 		drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
877 		drm_rect_debug_print("src: ", src, true);
878 		drm_rect_debug_print("dst: ", dst, false);
879 		return -ERANGE;
880 	}
881 
882 	/*
883 	 * FIXME: This might need further adjustment for seamless scaling
884 	 * with phase information, for the 2p2 and 2p1 scenarios.
885 	 */
886 	plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
887 
888 	drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
889 
890 	if (!can_position && plane_state->uapi.visible &&
891 	    !drm_rect_equals(dst, clip)) {
892 		drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
893 		drm_rect_debug_print("dst: ", dst, false);
894 		drm_rect_debug_print("clip: ", clip, false);
895 		return -EINVAL;
896 	}
897 
898 	/* final plane coordinates will be relative to the plane's pipe */
899 	drm_rect_translate(dst, -clip->x1, -clip->y1);
900 
901 	return 0;
902 }
903 
904 struct wait_rps_boost {
905 	struct wait_queue_entry wait;
906 
907 	struct drm_crtc *crtc;
908 	struct i915_request *request;
909 };
910 
do_rps_boost(struct wait_queue_entry * _wait,unsigned mode,int sync,void * key)911 static int do_rps_boost(struct wait_queue_entry *_wait,
912 			unsigned mode, int sync, void *key)
913 {
914 	struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
915 	struct i915_request *rq = wait->request;
916 
917 	/*
918 	 * If we missed the vblank, but the request is already running it
919 	 * is reasonable to assume that it will complete before the next
920 	 * vblank without our intervention, so leave RPS alone.
921 	 */
922 	if (!i915_request_started(rq))
923 		intel_rps_boost(rq);
924 	i915_request_put(rq);
925 
926 	drm_crtc_vblank_put(wait->crtc);
927 
928 	list_del(&wait->wait.entry);
929 	kfree(wait);
930 	return 1;
931 }
932 
add_rps_boost_after_vblank(struct drm_crtc * crtc,struct dma_fence * fence)933 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
934 				       struct dma_fence *fence)
935 {
936 	struct wait_rps_boost *wait;
937 
938 	if (!dma_fence_is_i915(fence))
939 		return;
940 
941 	if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
942 		return;
943 
944 	if (drm_crtc_vblank_get(crtc))
945 		return;
946 
947 	wait = kmalloc(sizeof(*wait), GFP_KERNEL);
948 	if (!wait) {
949 		drm_crtc_vblank_put(crtc);
950 		return;
951 	}
952 
953 	wait->request = to_request(dma_fence_get(fence));
954 	wait->crtc = crtc;
955 
956 	wait->wait.func = do_rps_boost;
957 	wait->wait.flags = 0;
958 
959 	add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
960 }
961 
962 /**
963  * intel_prepare_plane_fb - Prepare fb for usage on plane
964  * @_plane: drm plane to prepare for
965  * @_new_plane_state: the plane state being prepared
966  *
967  * Prepares a framebuffer for usage on a display plane.  Generally this
968  * involves pinning the underlying object and updating the frontbuffer tracking
969  * bits.  Some older platforms need special physical address handling for
970  * cursor planes.
971  *
972  * Returns 0 on success, negative error code on failure.
973  */
974 static int
intel_prepare_plane_fb(struct drm_plane * _plane,struct drm_plane_state * _new_plane_state)975 intel_prepare_plane_fb(struct drm_plane *_plane,
976 		       struct drm_plane_state *_new_plane_state)
977 {
978 	struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
979 	struct intel_plane *plane = to_intel_plane(_plane);
980 	struct intel_plane_state *new_plane_state =
981 		to_intel_plane_state(_new_plane_state);
982 	struct intel_atomic_state *state =
983 		to_intel_atomic_state(new_plane_state->uapi.state);
984 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
985 	const struct intel_plane_state *old_plane_state =
986 		intel_atomic_get_old_plane_state(state, plane);
987 	struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
988 	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
989 	int ret;
990 
991 	if (old_obj) {
992 		const struct intel_crtc_state *crtc_state =
993 			intel_atomic_get_new_crtc_state(state,
994 							to_intel_crtc(old_plane_state->hw.crtc));
995 
996 		/* Big Hammer, we also need to ensure that any pending
997 		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
998 		 * current scanout is retired before unpinning the old
999 		 * framebuffer. Note that we rely on userspace rendering
1000 		 * into the buffer attached to the pipe they are waiting
1001 		 * on. If not, userspace generates a GPU hang with IPEHR
1002 		 * point to the MI_WAIT_FOR_EVENT.
1003 		 *
1004 		 * This should only fail upon a hung GPU, in which case we
1005 		 * can safely continue.
1006 		 */
1007 		if (intel_crtc_needs_modeset(crtc_state)) {
1008 			ret = i915_sw_fence_await_reservation(&state->commit_ready,
1009 							      old_obj->base.resv, NULL,
1010 							      false, 0,
1011 							      GFP_KERNEL);
1012 			if (ret < 0)
1013 				return ret;
1014 		}
1015 	}
1016 
1017 	if (new_plane_state->uapi.fence) { /* explicit fencing */
1018 		i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1019 					     &attr);
1020 		ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
1021 						    new_plane_state->uapi.fence,
1022 						    i915_fence_timeout(dev_priv),
1023 						    GFP_KERNEL);
1024 		if (ret < 0)
1025 			return ret;
1026 	}
1027 
1028 	if (!obj)
1029 		return 0;
1030 
1031 
1032 	ret = intel_plane_pin_fb(new_plane_state);
1033 	if (ret)
1034 		return ret;
1035 
1036 	i915_gem_object_wait_priority(obj, 0, &attr);
1037 
1038 	if (!new_plane_state->uapi.fence) { /* implicit fencing */
1039 		struct dma_resv_iter cursor;
1040 		struct dma_fence *fence;
1041 
1042 		ret = i915_sw_fence_await_reservation(&state->commit_ready,
1043 						      obj->base.resv, NULL,
1044 						      false,
1045 						      i915_fence_timeout(dev_priv),
1046 						      GFP_KERNEL);
1047 		if (ret < 0)
1048 			goto unpin_fb;
1049 
1050 		dma_resv_iter_begin(&cursor, obj->base.resv,
1051 				    DMA_RESV_USAGE_WRITE);
1052 		dma_resv_for_each_fence_unlocked(&cursor, fence) {
1053 			add_rps_boost_after_vblank(new_plane_state->hw.crtc,
1054 						   fence);
1055 		}
1056 		dma_resv_iter_end(&cursor);
1057 	} else {
1058 		add_rps_boost_after_vblank(new_plane_state->hw.crtc,
1059 					   new_plane_state->uapi.fence);
1060 	}
1061 
1062 	/*
1063 	 * We declare pageflips to be interactive and so merit a small bias
1064 	 * towards upclocking to deliver the frame on time. By only changing
1065 	 * the RPS thresholds to sample more regularly and aim for higher
1066 	 * clocks we can hopefully deliver low power workloads (like kodi)
1067 	 * that are not quite steady state without resorting to forcing
1068 	 * maximum clocks following a vblank miss (see do_rps_boost()).
1069 	 */
1070 	if (!state->rps_interactive) {
1071 		intel_rps_mark_interactive(&to_gt(dev_priv)->rps, true);
1072 		state->rps_interactive = true;
1073 	}
1074 
1075 	return 0;
1076 
1077 unpin_fb:
1078 	intel_plane_unpin_fb(new_plane_state);
1079 
1080 	return ret;
1081 }
1082 
1083 /**
1084  * intel_cleanup_plane_fb - Cleans up an fb after plane use
1085  * @plane: drm plane to clean up for
1086  * @_old_plane_state: the state from the previous modeset
1087  *
1088  * Cleans up a framebuffer that has just been removed from a plane.
1089  */
1090 static void
intel_cleanup_plane_fb(struct drm_plane * plane,struct drm_plane_state * _old_plane_state)1091 intel_cleanup_plane_fb(struct drm_plane *plane,
1092 		       struct drm_plane_state *_old_plane_state)
1093 {
1094 	struct intel_plane_state *old_plane_state =
1095 		to_intel_plane_state(_old_plane_state);
1096 	struct intel_atomic_state *state =
1097 		to_intel_atomic_state(old_plane_state->uapi.state);
1098 	struct drm_i915_private *dev_priv = to_i915(plane->dev);
1099 	struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
1100 
1101 	if (!obj)
1102 		return;
1103 
1104 	if (state->rps_interactive) {
1105 		intel_rps_mark_interactive(&to_gt(dev_priv)->rps, false);
1106 		state->rps_interactive = false;
1107 	}
1108 
1109 	/* Should only be called after a successful intel_prepare_plane_fb()! */
1110 	intel_plane_unpin_fb(old_plane_state);
1111 }
1112 
1113 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1114 	.prepare_fb = intel_prepare_plane_fb,
1115 	.cleanup_fb = intel_cleanup_plane_fb,
1116 };
1117 
intel_plane_helper_add(struct intel_plane * plane)1118 void intel_plane_helper_add(struct intel_plane *plane)
1119 {
1120 	drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1121 }
1122