1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 #include <linux/kernel.h>
6 #include <linux/pm_qos.h>
7 #include <linux/slab.h>
8 
9 #include <drm/drm_atomic_helper.h>
10 #include <drm/drm_fourcc.h>
11 #include <drm/drm_plane.h>
12 #include <drm/drm_vblank_work.h>
13 
14 #include "i915_irq.h"
15 #include "i915_vgpu.h"
16 #include "i9xx_plane.h"
17 #include "icl_dsi.h"
18 #include "intel_atomic.h"
19 #include "intel_atomic_plane.h"
20 #include "intel_color.h"
21 #include "intel_crtc.h"
22 #include "intel_cursor.h"
23 #include "intel_display_debugfs.h"
24 #include "intel_display_trace.h"
25 #include "intel_display_types.h"
26 #include "intel_drrs.h"
27 #include "intel_dsi.h"
28 #include "intel_pipe_crc.h"
29 #include "intel_psr.h"
30 #include "intel_sprite.h"
31 #include "intel_vrr.h"
32 #include "skl_universal_plane.h"
33 
assert_vblank_disabled(struct drm_crtc * crtc)34 static void assert_vblank_disabled(struct drm_crtc *crtc)
35 {
36 	if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
37 		drm_crtc_vblank_put(crtc);
38 }
39 
intel_first_crtc(struct drm_i915_private * i915)40 struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
41 {
42 	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
43 }
44 
intel_crtc_for_pipe(struct drm_i915_private * i915,enum pipe pipe)45 struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
46 				       enum pipe pipe)
47 {
48 	struct intel_crtc *crtc;
49 
50 	for_each_intel_crtc(&i915->drm, crtc) {
51 		if (crtc->pipe == pipe)
52 			return crtc;
53 	}
54 
55 	return NULL;
56 }
57 
intel_crtc_wait_for_next_vblank(struct intel_crtc * crtc)58 void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc)
59 {
60 	drm_crtc_wait_one_vblank(&crtc->base);
61 }
62 
intel_wait_for_vblank_if_active(struct drm_i915_private * i915,enum pipe pipe)63 void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
64 				     enum pipe pipe)
65 {
66 	struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
67 
68 	if (crtc->active)
69 		intel_crtc_wait_for_next_vblank(crtc);
70 }
71 
intel_crtc_get_vblank_counter(struct intel_crtc * crtc)72 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
73 {
74 	struct drm_device *dev = crtc->base.dev;
75 	struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
76 
77 	if (!crtc->active)
78 		return 0;
79 
80 	if (!vblank->max_vblank_count)
81 		return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
82 
83 	return crtc->base.funcs->get_vblank_counter(&crtc->base);
84 }
85 
intel_crtc_max_vblank_count(const struct intel_crtc_state * crtc_state)86 u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
87 {
88 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
89 
90 	/*
91 	 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
92 	 * have updated at the beginning of TE, if we want to use
93 	 * the hw counter, then we would find it updated in only
94 	 * the next TE, hence switching to sw counter.
95 	 */
96 	if (crtc_state->mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 |
97 				      I915_MODE_FLAG_DSI_USE_TE1))
98 		return 0;
99 
100 	/*
101 	 * On i965gm the hardware frame counter reads
102 	 * zero when the TV encoder is enabled :(
103 	 */
104 	if (IS_I965GM(dev_priv) &&
105 	    (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
106 		return 0;
107 
108 	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
109 		return 0xffffffff; /* full 32 bit counter */
110 	else if (DISPLAY_VER(dev_priv) >= 3)
111 		return 0xffffff; /* only 24 bits of frame count */
112 	else
113 		return 0; /* Gen2 doesn't have a hardware frame counter */
114 }
115 
intel_crtc_vblank_on(const struct intel_crtc_state * crtc_state)116 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
117 {
118 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
119 
120 	assert_vblank_disabled(&crtc->base);
121 	drm_crtc_set_max_vblank_count(&crtc->base,
122 				      intel_crtc_max_vblank_count(crtc_state));
123 	drm_crtc_vblank_on(&crtc->base);
124 
125 	/*
126 	 * Should really happen exactly when we enable the pipe
127 	 * but we want the frame counters in the trace, and that
128 	 * requires vblank support on some platforms/outputs.
129 	 */
130 	trace_intel_pipe_enable(crtc);
131 }
132 
intel_crtc_vblank_off(const struct intel_crtc_state * crtc_state)133 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
134 {
135 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
136 
137 	/*
138 	 * Should really happen exactly when we disable the pipe
139 	 * but we want the frame counters in the trace, and that
140 	 * requires vblank support on some platforms/outputs.
141 	 */
142 	trace_intel_pipe_disable(crtc);
143 
144 	drm_crtc_vblank_off(&crtc->base);
145 	assert_vblank_disabled(&crtc->base);
146 }
147 
intel_crtc_state_alloc(struct intel_crtc * crtc)148 struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
149 {
150 	struct intel_crtc_state *crtc_state;
151 
152 	crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
153 
154 	if (crtc_state)
155 		intel_crtc_state_reset(crtc_state, crtc);
156 
157 	return crtc_state;
158 }
159 
intel_crtc_state_reset(struct intel_crtc_state * crtc_state,struct intel_crtc * crtc)160 void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
161 			    struct intel_crtc *crtc)
162 {
163 	memset(crtc_state, 0, sizeof(*crtc_state));
164 
165 	__drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
166 
167 	crtc_state->cpu_transcoder = INVALID_TRANSCODER;
168 	crtc_state->master_transcoder = INVALID_TRANSCODER;
169 	crtc_state->hsw_workaround_pipe = INVALID_PIPE;
170 	crtc_state->scaler_state.scaler_id = -1;
171 	crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
172 }
173 
intel_crtc_alloc(void)174 static struct intel_crtc *intel_crtc_alloc(void)
175 {
176 	struct intel_crtc_state *crtc_state;
177 	struct intel_crtc *crtc;
178 
179 	crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
180 	if (!crtc)
181 		return ERR_PTR(-ENOMEM);
182 
183 	crtc_state = intel_crtc_state_alloc(crtc);
184 	if (!crtc_state) {
185 		kfree(crtc);
186 		return ERR_PTR(-ENOMEM);
187 	}
188 
189 	crtc->base.state = &crtc_state->uapi;
190 	crtc->config = crtc_state;
191 
192 	return crtc;
193 }
194 
intel_crtc_free(struct intel_crtc * crtc)195 static void intel_crtc_free(struct intel_crtc *crtc)
196 {
197 	intel_crtc_destroy_state(&crtc->base, crtc->base.state);
198 	kfree(crtc);
199 }
200 
intel_crtc_destroy(struct drm_crtc * _crtc)201 static void intel_crtc_destroy(struct drm_crtc *_crtc)
202 {
203 	struct intel_crtc *crtc = to_intel_crtc(_crtc);
204 
205 	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
206 
207 	drm_crtc_cleanup(&crtc->base);
208 	kfree(crtc);
209 }
210 
intel_crtc_late_register(struct drm_crtc * crtc)211 static int intel_crtc_late_register(struct drm_crtc *crtc)
212 {
213 	intel_crtc_debugfs_add(crtc);
214 	return 0;
215 }
216 
217 #define INTEL_CRTC_FUNCS \
218 	.set_config = drm_atomic_helper_set_config, \
219 	.destroy = intel_crtc_destroy, \
220 	.page_flip = drm_atomic_helper_page_flip, \
221 	.atomic_duplicate_state = intel_crtc_duplicate_state, \
222 	.atomic_destroy_state = intel_crtc_destroy_state, \
223 	.set_crc_source = intel_crtc_set_crc_source, \
224 	.verify_crc_source = intel_crtc_verify_crc_source, \
225 	.get_crc_sources = intel_crtc_get_crc_sources, \
226 	.late_register = intel_crtc_late_register
227 
228 static const struct drm_crtc_funcs bdw_crtc_funcs = {
229 	INTEL_CRTC_FUNCS,
230 
231 	.get_vblank_counter = g4x_get_vblank_counter,
232 	.enable_vblank = bdw_enable_vblank,
233 	.disable_vblank = bdw_disable_vblank,
234 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
235 };
236 
237 static const struct drm_crtc_funcs ilk_crtc_funcs = {
238 	INTEL_CRTC_FUNCS,
239 
240 	.get_vblank_counter = g4x_get_vblank_counter,
241 	.enable_vblank = ilk_enable_vblank,
242 	.disable_vblank = ilk_disable_vblank,
243 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
244 };
245 
246 static const struct drm_crtc_funcs g4x_crtc_funcs = {
247 	INTEL_CRTC_FUNCS,
248 
249 	.get_vblank_counter = g4x_get_vblank_counter,
250 	.enable_vblank = i965_enable_vblank,
251 	.disable_vblank = i965_disable_vblank,
252 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
253 };
254 
255 static const struct drm_crtc_funcs i965_crtc_funcs = {
256 	INTEL_CRTC_FUNCS,
257 
258 	.get_vblank_counter = i915_get_vblank_counter,
259 	.enable_vblank = i965_enable_vblank,
260 	.disable_vblank = i965_disable_vblank,
261 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
262 };
263 
264 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
265 	INTEL_CRTC_FUNCS,
266 
267 	.get_vblank_counter = i915_get_vblank_counter,
268 	.enable_vblank = i915gm_enable_vblank,
269 	.disable_vblank = i915gm_disable_vblank,
270 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
271 };
272 
273 static const struct drm_crtc_funcs i915_crtc_funcs = {
274 	INTEL_CRTC_FUNCS,
275 
276 	.get_vblank_counter = i915_get_vblank_counter,
277 	.enable_vblank = i8xx_enable_vblank,
278 	.disable_vblank = i8xx_disable_vblank,
279 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
280 };
281 
282 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
283 	INTEL_CRTC_FUNCS,
284 
285 	/* no hw vblank counter */
286 	.enable_vblank = i8xx_enable_vblank,
287 	.disable_vblank = i8xx_disable_vblank,
288 	.get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
289 };
290 
intel_crtc_init(struct drm_i915_private * dev_priv,enum pipe pipe)291 int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
292 {
293 	struct intel_plane *primary, *cursor;
294 	const struct drm_crtc_funcs *funcs;
295 	struct intel_crtc *crtc;
296 	int sprite, ret;
297 
298 	crtc = intel_crtc_alloc();
299 	if (IS_ERR(crtc))
300 		return PTR_ERR(crtc);
301 
302 	crtc->pipe = pipe;
303 	crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
304 
305 	if (DISPLAY_VER(dev_priv) >= 9)
306 		primary = skl_universal_plane_create(dev_priv, pipe,
307 						     PLANE_PRIMARY);
308 	else
309 		primary = intel_primary_plane_create(dev_priv, pipe);
310 	if (IS_ERR(primary)) {
311 		ret = PTR_ERR(primary);
312 		goto fail;
313 	}
314 	crtc->plane_ids_mask |= BIT(primary->id);
315 
316 	for_each_sprite(dev_priv, pipe, sprite) {
317 		struct intel_plane *plane;
318 
319 		if (DISPLAY_VER(dev_priv) >= 9)
320 			plane = skl_universal_plane_create(dev_priv, pipe,
321 							   PLANE_SPRITE0 + sprite);
322 		else
323 			plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
324 		if (IS_ERR(plane)) {
325 			ret = PTR_ERR(plane);
326 			goto fail;
327 		}
328 		crtc->plane_ids_mask |= BIT(plane->id);
329 	}
330 
331 	cursor = intel_cursor_plane_create(dev_priv, pipe);
332 	if (IS_ERR(cursor)) {
333 		ret = PTR_ERR(cursor);
334 		goto fail;
335 	}
336 	crtc->plane_ids_mask |= BIT(cursor->id);
337 
338 	if (HAS_GMCH(dev_priv)) {
339 		if (IS_CHERRYVIEW(dev_priv) ||
340 		    IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
341 			funcs = &g4x_crtc_funcs;
342 		else if (DISPLAY_VER(dev_priv) == 4)
343 			funcs = &i965_crtc_funcs;
344 		else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
345 			funcs = &i915gm_crtc_funcs;
346 		else if (DISPLAY_VER(dev_priv) == 3)
347 			funcs = &i915_crtc_funcs;
348 		else
349 			funcs = &i8xx_crtc_funcs;
350 	} else {
351 		if (DISPLAY_VER(dev_priv) >= 8)
352 			funcs = &bdw_crtc_funcs;
353 		else
354 			funcs = &ilk_crtc_funcs;
355 	}
356 
357 	ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
358 					&primary->base, &cursor->base,
359 					funcs, "pipe %c", pipe_name(pipe));
360 	if (ret)
361 		goto fail;
362 
363 	if (DISPLAY_VER(dev_priv) >= 11)
364 		drm_crtc_create_scaling_filter_property(&crtc->base,
365 						BIT(DRM_SCALING_FILTER_DEFAULT) |
366 						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
367 
368 	intel_color_init(crtc);
369 
370 	intel_crtc_drrs_init(crtc);
371 	intel_crtc_crc_init(crtc);
372 
373 	cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE);
374 
375 	drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
376 
377 	return 0;
378 
379 fail:
380 	intel_crtc_free(crtc);
381 
382 	return ret;
383 }
384 
intel_crtc_needs_vblank_work(const struct intel_crtc_state * crtc_state)385 static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state)
386 {
387 	return crtc_state->hw.active &&
388 		!intel_crtc_needs_modeset(crtc_state) &&
389 		!crtc_state->preload_luts &&
390 		(crtc_state->uapi.color_mgmt_changed ||
391 		 crtc_state->update_pipe);
392 }
393 
intel_crtc_vblank_work(struct kthread_work * base)394 static void intel_crtc_vblank_work(struct kthread_work *base)
395 {
396 	struct drm_vblank_work *work = to_drm_vblank_work(base);
397 	struct intel_crtc_state *crtc_state =
398 		container_of(work, typeof(*crtc_state), vblank_work);
399 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
400 
401 	trace_intel_crtc_vblank_work_start(crtc);
402 
403 	intel_color_load_luts(crtc_state);
404 
405 	if (crtc_state->uapi.event) {
406 		spin_lock_irq(&crtc->base.dev->event_lock);
407 		drm_crtc_send_vblank_event(&crtc->base, crtc_state->uapi.event);
408 		crtc_state->uapi.event = NULL;
409 		spin_unlock_irq(&crtc->base.dev->event_lock);
410 	}
411 
412 	trace_intel_crtc_vblank_work_end(crtc);
413 }
414 
intel_crtc_vblank_work_init(struct intel_crtc_state * crtc_state)415 static void intel_crtc_vblank_work_init(struct intel_crtc_state *crtc_state)
416 {
417 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
418 
419 	drm_vblank_work_init(&crtc_state->vblank_work, &crtc->base,
420 			     intel_crtc_vblank_work);
421 	/*
422 	 * Interrupt latency is critical for getting the vblank
423 	 * work executed as early as possible during the vblank.
424 	 */
425 	cpu_latency_qos_update_request(&crtc->vblank_pm_qos, 0);
426 }
427 
intel_wait_for_vblank_workers(struct intel_atomic_state * state)428 void intel_wait_for_vblank_workers(struct intel_atomic_state *state)
429 {
430 	struct intel_crtc_state *crtc_state;
431 	struct intel_crtc *crtc;
432 	int i;
433 
434 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
435 		if (!intel_crtc_needs_vblank_work(crtc_state))
436 			continue;
437 
438 		drm_vblank_work_flush(&crtc_state->vblank_work);
439 		cpu_latency_qos_update_request(&crtc->vblank_pm_qos,
440 					       PM_QOS_DEFAULT_VALUE);
441 	}
442 }
443 
intel_usecs_to_scanlines(const struct drm_display_mode * adjusted_mode,int usecs)444 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
445 			     int usecs)
446 {
447 	/* paranoia */
448 	if (!adjusted_mode->crtc_htotal)
449 		return 1;
450 
451 	return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
452 			    1000 * adjusted_mode->crtc_htotal);
453 }
454 
intel_mode_vblank_start(const struct drm_display_mode * mode)455 static int intel_mode_vblank_start(const struct drm_display_mode *mode)
456 {
457 	int vblank_start = mode->crtc_vblank_start;
458 
459 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
460 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
461 
462 	return vblank_start;
463 }
464 
465 /**
466  * intel_pipe_update_start() - start update of a set of display registers
467  * @new_crtc_state: the new crtc state
468  *
469  * Mark the start of an update to pipe registers that should be updated
470  * atomically regarding vblank. If the next vblank will happens within
471  * the next 100 us, this function waits until the vblank passes.
472  *
473  * After a successful call to this function, interrupts will be disabled
474  * until a subsequent call to intel_pipe_update_end(). That is done to
475  * avoid random delays.
476  */
intel_pipe_update_start(struct intel_crtc_state * new_crtc_state)477 void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
478 {
479 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
480 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
481 	const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
482 	long timeout = msecs_to_jiffies_timeout(1);
483 	int scanline, min, max, vblank_start;
484 	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
485 	bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
486 		intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
487 	DEFINE_WAIT(wait);
488 
489 	intel_psr_lock(new_crtc_state);
490 
491 	if (new_crtc_state->do_async_flip)
492 		return;
493 
494 	if (intel_crtc_needs_vblank_work(new_crtc_state))
495 		intel_crtc_vblank_work_init(new_crtc_state);
496 
497 	if (new_crtc_state->vrr.enable) {
498 		if (intel_vrr_is_push_sent(new_crtc_state))
499 			vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
500 		else
501 			vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
502 	} else {
503 		vblank_start = intel_mode_vblank_start(adjusted_mode);
504 	}
505 
506 	/* FIXME needs to be calibrated sensibly */
507 	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
508 						      VBLANK_EVASION_TIME_US);
509 	max = vblank_start - 1;
510 
511 	if (min <= 0 || max <= 0)
512 		goto irq_disable;
513 
514 	if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base)))
515 		goto irq_disable;
516 
517 	/*
518 	 * Wait for psr to idle out after enabling the VBL interrupts
519 	 * VBL interrupts will start the PSR exit and prevent a PSR
520 	 * re-entry as well.
521 	 */
522 	intel_psr_wait_for_idle_locked(new_crtc_state);
523 
524 	local_irq_disable();
525 
526 	crtc->debug.min_vbl = min;
527 	crtc->debug.max_vbl = max;
528 	trace_intel_pipe_update_start(crtc);
529 
530 	for (;;) {
531 		/*
532 		 * prepare_to_wait() has a memory barrier, which guarantees
533 		 * other CPUs can see the task state update by the time we
534 		 * read the scanline.
535 		 */
536 		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
537 
538 		scanline = intel_get_crtc_scanline(crtc);
539 		if (scanline < min || scanline > max)
540 			break;
541 
542 		if (!timeout) {
543 			drm_err(&dev_priv->drm,
544 				"Potential atomic update failure on pipe %c\n",
545 				pipe_name(crtc->pipe));
546 			break;
547 		}
548 
549 		local_irq_enable();
550 
551 		timeout = schedule_timeout(timeout);
552 
553 		local_irq_disable();
554 	}
555 
556 	finish_wait(wq, &wait);
557 
558 	drm_crtc_vblank_put(&crtc->base);
559 
560 	/*
561 	 * On VLV/CHV DSI the scanline counter would appear to
562 	 * increment approx. 1/3 of a scanline before start of vblank.
563 	 * The registers still get latched at start of vblank however.
564 	 * This means we must not write any registers on the first
565 	 * line of vblank (since not the whole line is actually in
566 	 * vblank). And unfortunately we can't use the interrupt to
567 	 * wait here since it will fire too soon. We could use the
568 	 * frame start interrupt instead since it will fire after the
569 	 * critical scanline, but that would require more changes
570 	 * in the interrupt code. So for now we'll just do the nasty
571 	 * thing and poll for the bad scanline to pass us by.
572 	 *
573 	 * FIXME figure out if BXT+ DSI suffers from this as well
574 	 */
575 	while (need_vlv_dsi_wa && scanline == vblank_start)
576 		scanline = intel_get_crtc_scanline(crtc);
577 
578 	crtc->debug.scanline_start = scanline;
579 	crtc->debug.start_vbl_time = ktime_get();
580 	crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
581 
582 	trace_intel_pipe_update_vblank_evaded(crtc);
583 	return;
584 
585 irq_disable:
586 	local_irq_disable();
587 }
588 
589 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
dbg_vblank_evade(struct intel_crtc * crtc,ktime_t end)590 static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end)
591 {
592 	u64 delta = ktime_to_ns(ktime_sub(end, crtc->debug.start_vbl_time));
593 	unsigned int h;
594 
595 	h = ilog2(delta >> 9);
596 	if (h >= ARRAY_SIZE(crtc->debug.vbl.times))
597 		h = ARRAY_SIZE(crtc->debug.vbl.times) - 1;
598 	crtc->debug.vbl.times[h]++;
599 
600 	crtc->debug.vbl.sum += delta;
601 	if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min)
602 		crtc->debug.vbl.min = delta;
603 	if (delta > crtc->debug.vbl.max)
604 		crtc->debug.vbl.max = delta;
605 
606 	if (delta > 1000 * VBLANK_EVASION_TIME_US) {
607 		drm_dbg_kms(crtc->base.dev,
608 			    "Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
609 			    pipe_name(crtc->pipe),
610 			    div_u64(delta, 1000),
611 			    VBLANK_EVASION_TIME_US);
612 		crtc->debug.vbl.over++;
613 	}
614 }
615 #else
dbg_vblank_evade(struct intel_crtc * crtc,ktime_t end)616 static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
617 #endif
618 
619 /**
620  * intel_pipe_update_end() - end update of a set of display registers
621  * @new_crtc_state: the new crtc state
622  *
623  * Mark the end of an update started with intel_pipe_update_start(). This
624  * re-enables interrupts and verifies the update was actually completed
625  * before a vblank.
626  */
intel_pipe_update_end(struct intel_crtc_state * new_crtc_state)627 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
628 {
629 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
630 	enum pipe pipe = crtc->pipe;
631 	int scanline_end = intel_get_crtc_scanline(crtc);
632 	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
633 	ktime_t end_vbl_time = ktime_get();
634 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
635 
636 	intel_psr_unlock(new_crtc_state);
637 
638 	if (new_crtc_state->do_async_flip)
639 		return;
640 
641 	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
642 
643 	/*
644 	 * Incase of mipi dsi command mode, we need to set frame update
645 	 * request for every commit.
646 	 */
647 	if (DISPLAY_VER(dev_priv) >= 11 &&
648 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
649 		icl_dsi_frame_update(new_crtc_state);
650 
651 	/* We're still in the vblank-evade critical section, this can't race.
652 	 * Would be slightly nice to just grab the vblank count and arm the
653 	 * event outside of the critical section - the spinlock might spin for a
654 	 * while ... */
655 	if (intel_crtc_needs_vblank_work(new_crtc_state)) {
656 		drm_vblank_work_schedule(&new_crtc_state->vblank_work,
657 					 drm_crtc_accurate_vblank_count(&crtc->base) + 1,
658 					 false);
659 	} else if (new_crtc_state->uapi.event) {
660 		drm_WARN_ON(&dev_priv->drm,
661 			    drm_crtc_vblank_get(&crtc->base) != 0);
662 
663 		spin_lock(&crtc->base.dev->event_lock);
664 		drm_crtc_arm_vblank_event(&crtc->base,
665 					  new_crtc_state->uapi.event);
666 		spin_unlock(&crtc->base.dev->event_lock);
667 
668 		new_crtc_state->uapi.event = NULL;
669 	}
670 
671 	/*
672 	 * Send VRR Push to terminate Vblank. If we are already in vblank
673 	 * this has to be done _after_ sampling the frame counter, as
674 	 * otherwise the push would immediately terminate the vblank and
675 	 * the sampled frame counter would correspond to the next frame
676 	 * instead of the current frame.
677 	 *
678 	 * There is a tiny race here (iff vblank evasion failed us) where
679 	 * we might sample the frame counter just before vmax vblank start
680 	 * but the push would be sent just after it. That would cause the
681 	 * push to affect the next frame instead of the current frame,
682 	 * which would cause the next frame to terminate already at vmin
683 	 * vblank start instead of vmax vblank start.
684 	 */
685 	intel_vrr_send_push(new_crtc_state);
686 
687 	local_irq_enable();
688 
689 	if (intel_vgpu_active(dev_priv))
690 		return;
691 
692 	if (crtc->debug.start_vbl_count &&
693 	    crtc->debug.start_vbl_count != end_vbl_count) {
694 		drm_err(&dev_priv->drm,
695 			"Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
696 			pipe_name(pipe), crtc->debug.start_vbl_count,
697 			end_vbl_count,
698 			ktime_us_delta(end_vbl_time,
699 				       crtc->debug.start_vbl_time),
700 			crtc->debug.min_vbl, crtc->debug.max_vbl,
701 			crtc->debug.scanline_start, scanline_end);
702 	}
703 
704 	dbg_vblank_evade(crtc, end_vbl_time);
705 }
706