1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <linux/util_macros.h>
7
8 #include "intel_ddi.h"
9 #include "intel_ddi_buf_trans.h"
10 #include "intel_de.h"
11 #include "intel_display_types.h"
12 #include "intel_snps_phy.h"
13 #include "intel_snps_phy_regs.h"
14
15 /**
16 * DOC: Synopsis PHY support
17 *
18 * Synopsis PHYs are primarily programmed by looking up magic register values
19 * in tables rather than calculating the necessary values at runtime.
20 *
21 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
22 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other
23 * platforms and must be programming directly during the modeset sequence
24 * since it is not handled by the shared DPLL framework as on other platforms.
25 */
26
intel_snps_phy_wait_for_calibration(struct drm_i915_private * i915)27 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
28 {
29 enum phy phy;
30
31 for_each_phy_masked(phy, ~0) {
32 if (!intel_phy_is_snps(i915, phy))
33 continue;
34
35 /*
36 * If calibration does not complete successfully, we'll remember
37 * which phy was affected and skip setup of the corresponding
38 * output later.
39 */
40 if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
41 DG2_PHY_DP_TX_ACK_MASK, 25))
42 i915->snps_phy_failed_calibration |= BIT(phy);
43 }
44 }
45
intel_snps_phy_update_psr_power_state(struct drm_i915_private * dev_priv,enum phy phy,bool enable)46 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
47 enum phy phy, bool enable)
48 {
49 u32 val;
50
51 if (!intel_phy_is_snps(dev_priv, phy))
52 return;
53
54 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
55 enable ? 2 : 3);
56 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy),
57 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
58 }
59
intel_snps_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)60 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
61 const struct intel_crtc_state *crtc_state)
62 {
63 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
64 const struct intel_ddi_buf_trans *trans;
65 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
66 int n_entries, ln;
67
68 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
69 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
70 return;
71
72 for (ln = 0; ln < 4; ln++) {
73 int level = intel_ddi_level(encoder, crtc_state, ln);
74 u32 val = 0;
75
76 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
77 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
78 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
79
80 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
81 }
82 }
83
84 /*
85 * Basic DP link rates with 100 MHz reference clock.
86 */
87
88 static const struct intel_mpllb_state dg2_dp_rbr_100 = {
89 .clock = 162000,
90 .ref_control =
91 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
92 .mpllb_cp =
93 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
94 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
95 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
96 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
97 .mpllb_div =
98 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
99 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
100 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
101 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
102 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
103 .mpllb_div2 =
104 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
105 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
106 .mpllb_fracn1 =
107 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
108 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
109 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
110 .mpllb_fracn2 =
111 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
112 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
113 };
114
115 static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
116 .clock = 270000,
117 .ref_control =
118 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
119 .mpllb_cp =
120 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
121 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
122 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
123 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
124 .mpllb_div =
125 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
126 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
127 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
128 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
129 .mpllb_div2 =
130 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
131 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
132 .mpllb_fracn1 =
133 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
134 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
135 };
136
137 static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
138 .clock = 540000,
139 .ref_control =
140 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
141 .mpllb_cp =
142 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
143 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
144 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
145 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
146 .mpllb_div =
147 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
148 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
149 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
150 .mpllb_div2 =
151 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
152 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
153 .mpllb_fracn1 =
154 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
155 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
156 };
157
158 static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
159 .clock = 810000,
160 .ref_control =
161 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
162 .mpllb_cp =
163 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
164 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
165 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
166 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
167 .mpllb_div =
168 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
169 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
170 .mpllb_div2 =
171 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
172 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
173 .mpllb_fracn1 =
174 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
175 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
176 };
177
178 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
179 .clock = 1000000,
180 .ref_control =
181 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
182 .mpllb_cp =
183 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
184 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |
185 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
186 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
187 .mpllb_div =
188 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
189 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
190 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
191 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
192 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
193 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
194 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
195 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
196 .mpllb_div2 =
197 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
198 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),
199 .mpllb_fracn1 =
200 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
201 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
202
203 /*
204 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
205 */
206 .mpllb_sscen =
207 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
208 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),
209 .mpllb_sscstep =
210 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
211 };
212
213 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
214 .clock = 1350000,
215 .ref_control =
216 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
217 .mpllb_cp =
218 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
219 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
220 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
221 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
222 .mpllb_div =
223 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
224 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
225 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
226 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
227 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
228 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
229 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
230 .mpllb_div2 =
231 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
232 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
233 .mpllb_fracn1 =
234 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
235 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
236
237 /*
238 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
239 */
240 .mpllb_sscen =
241 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
242 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
243 .mpllb_sscstep =
244 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
245 };
246
247 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
248 &dg2_dp_rbr_100,
249 &dg2_dp_hbr1_100,
250 &dg2_dp_hbr2_100,
251 &dg2_dp_hbr3_100,
252 &dg2_dp_uhbr10_100,
253 &dg2_dp_uhbr13_100,
254 NULL,
255 };
256
257 /*
258 * eDP link rates with 100 MHz reference clock.
259 */
260
261 static const struct intel_mpllb_state dg2_edp_r216 = {
262 .clock = 216000,
263 .ref_control =
264 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
265 .mpllb_cp =
266 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
267 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
268 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
269 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
270 .mpllb_div =
271 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
272 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
273 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
274 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
275 .mpllb_div2 =
276 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
277 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
278 .mpllb_fracn1 =
279 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
280 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
281 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
282 .mpllb_fracn2 =
283 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
284 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
285 .mpllb_sscen =
286 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
287 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
288 .mpllb_sscstep =
289 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
290 };
291
292 static const struct intel_mpllb_state dg2_edp_r243 = {
293 .clock = 243000,
294 .ref_control =
295 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
296 .mpllb_cp =
297 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
298 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
299 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
300 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
301 .mpllb_div =
302 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
303 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
304 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
305 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
306 .mpllb_div2 =
307 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
308 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
309 .mpllb_fracn1 =
310 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
311 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
312 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
313 .mpllb_fracn2 =
314 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
315 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
316 .mpllb_sscen =
317 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
318 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
319 .mpllb_sscstep =
320 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
321 };
322
323 static const struct intel_mpllb_state dg2_edp_r324 = {
324 .clock = 324000,
325 .ref_control =
326 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
327 .mpllb_cp =
328 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
329 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
330 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
331 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
332 .mpllb_div =
333 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
334 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
335 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
336 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
337 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
338 .mpllb_div2 =
339 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
340 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
341 .mpllb_fracn1 =
342 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
343 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
344 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
345 .mpllb_fracn2 =
346 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
347 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
348 .mpllb_sscen =
349 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
350 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
351 .mpllb_sscstep =
352 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
353 };
354
355 static const struct intel_mpllb_state dg2_edp_r432 = {
356 .clock = 432000,
357 .ref_control =
358 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
359 .mpllb_cp =
360 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
361 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
362 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
363 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
364 .mpllb_div =
365 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
366 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
367 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
368 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
369 .mpllb_div2 =
370 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
371 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
372 .mpllb_fracn1 =
373 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
374 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
375 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
376 .mpllb_fracn2 =
377 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
378 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
379 .mpllb_sscen =
380 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
381 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
382 .mpllb_sscstep =
383 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
384 };
385
386 static const struct intel_mpllb_state * const dg2_edp_tables[] = {
387 &dg2_dp_rbr_100,
388 &dg2_edp_r216,
389 &dg2_edp_r243,
390 &dg2_dp_hbr1_100,
391 &dg2_edp_r324,
392 &dg2_edp_r432,
393 &dg2_dp_hbr2_100,
394 &dg2_dp_hbr3_100,
395 NULL,
396 };
397
398 /*
399 * HDMI link rates with 100 MHz reference clock.
400 */
401
402 static const struct intel_mpllb_state dg2_hdmi_25_175 = {
403 .clock = 25175,
404 .ref_control =
405 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
406 .mpllb_cp =
407 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
408 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
409 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
410 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
411 .mpllb_div =
412 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
413 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
414 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
415 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
416 .mpllb_div2 =
417 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
418 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
419 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
420 .mpllb_fracn1 =
421 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
422 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
423 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
424 .mpllb_fracn2 =
425 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
426 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
427 .mpllb_sscen =
428 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
429 };
430
431 static const struct intel_mpllb_state dg2_hdmi_27_0 = {
432 .clock = 27000,
433 .ref_control =
434 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
435 .mpllb_cp =
436 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
437 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
438 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
439 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
440 .mpllb_div =
441 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
442 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
443 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
444 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
445 .mpllb_div2 =
446 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
447 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
448 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
449 .mpllb_fracn1 =
450 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
451 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
452 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
453 .mpllb_fracn2 =
454 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
455 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
456 .mpllb_sscen =
457 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
458 };
459
460 static const struct intel_mpllb_state dg2_hdmi_74_25 = {
461 .clock = 74250,
462 .ref_control =
463 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
464 .mpllb_cp =
465 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
466 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
467 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
468 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
469 .mpllb_div =
470 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
471 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
472 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
473 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
474 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
475 .mpllb_div2 =
476 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
477 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
478 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
479 .mpllb_fracn1 =
480 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
481 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
482 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
483 .mpllb_fracn2 =
484 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
485 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
486 .mpllb_sscen =
487 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
488 };
489
490 static const struct intel_mpllb_state dg2_hdmi_148_5 = {
491 .clock = 148500,
492 .ref_control =
493 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
494 .mpllb_cp =
495 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
496 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
497 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
498 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
499 .mpllb_div =
500 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
501 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
502 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
503 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
504 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
505 .mpllb_div2 =
506 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
507 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
508 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
509 .mpllb_fracn1 =
510 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
511 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
512 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
513 .mpllb_fracn2 =
514 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
515 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
516 .mpllb_sscen =
517 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
518 };
519
520 static const struct intel_mpllb_state dg2_hdmi_594 = {
521 .clock = 594000,
522 .ref_control =
523 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
524 .mpllb_cp =
525 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
526 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
527 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
528 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
529 .mpllb_div =
530 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
531 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
532 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
533 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
534 .mpllb_div2 =
535 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
536 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
537 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
538 .mpllb_fracn1 =
539 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
540 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
541 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
542 .mpllb_fracn2 =
543 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
544 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
545 .mpllb_sscen =
546 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
547 };
548
549 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
550 &dg2_hdmi_25_175,
551 &dg2_hdmi_27_0,
552 &dg2_hdmi_74_25,
553 &dg2_hdmi_148_5,
554 &dg2_hdmi_594,
555 NULL,
556 };
557
558 static const struct intel_mpllb_state * const *
intel_mpllb_tables_get(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder)559 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
560 struct intel_encoder *encoder)
561 {
562 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
563 return dg2_edp_tables;
564 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
565 return dg2_dp_100_tables;
566 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
567 return dg2_hdmi_tables;
568 }
569
570 MISSING_CASE(encoder->type);
571 return NULL;
572 }
573
intel_mpllb_calc_state(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder)574 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
575 struct intel_encoder *encoder)
576 {
577 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
578 const struct intel_mpllb_state * const *tables;
579 int i;
580
581 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
582 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
583 != MODE_OK) {
584 /*
585 * FIXME: Can only support fixed HDMI frequencies
586 * until we have a proper algorithm under a valid
587 * license.
588 */
589 drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
590 crtc_state->port_clock);
591 return -EINVAL;
592 }
593 }
594
595 tables = intel_mpllb_tables_get(crtc_state, encoder);
596 if (!tables)
597 return -EINVAL;
598
599 for (i = 0; tables[i]; i++) {
600 if (crtc_state->port_clock <= tables[i]->clock) {
601 crtc_state->mpllb_state = *tables[i];
602 return 0;
603 }
604 }
605
606 return -EINVAL;
607 }
608
intel_mpllb_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)609 void intel_mpllb_enable(struct intel_encoder *encoder,
610 const struct intel_crtc_state *crtc_state)
611 {
612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
613 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state;
614 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
615 i915_reg_t enable_reg = (phy <= PHY_D ?
616 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
617
618 /*
619 * 3. Software programs the following PLL registers for the desired
620 * frequency.
621 */
622 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
623 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
624 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
625 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
626 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
627 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
628 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
629
630 /*
631 * 4. If the frequency will result in a change to the voltage
632 * requirement, follow the Display Voltage Frequency Switching -
633 * Sequence Before Frequency Change.
634 *
635 * We handle this step in bxt_set_cdclk().
636 */
637
638 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
639 intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE);
640
641 /*
642 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
643 * will keep the PLL running during the DDI lane programming and any
644 * typeC DP cable disconnect. Do not set the force before enabling the
645 * PLL because that will start the PLL before it has sampled the
646 * divider values.
647 */
648 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
649 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
650
651 /*
652 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
653 * is locked at new settings. This register bit is sampling PHY
654 * dp_mpllb_state interface signal.
655 */
656 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
657 drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
658
659 /*
660 * 11. If the frequency will result in a change to the voltage
661 * requirement, follow the Display Voltage Frequency Switching -
662 * Sequence After Frequency Change.
663 *
664 * We handle this step in bxt_set_cdclk().
665 */
666 }
667
intel_mpllb_disable(struct intel_encoder * encoder)668 void intel_mpllb_disable(struct intel_encoder *encoder)
669 {
670 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
671 enum phy phy = intel_port_to_phy(i915, encoder->port);
672 i915_reg_t enable_reg = (phy <= PHY_D ?
673 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
674
675 /*
676 * 1. If the frequency will result in a change to the voltage
677 * requirement, follow the Display Voltage Frequency Switching -
678 * Sequence Before Frequency Change.
679 *
680 * We handle this step in bxt_set_cdclk().
681 */
682
683 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
684 intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0);
685
686 /*
687 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
688 * This will allow the PLL to stop running.
689 */
690 intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy),
691 SNPS_PHY_MPLLB_FORCE_EN, 0);
692
693 /*
694 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
695 * (dp_txX_ack) that the new transmitter setting request is completed.
696 */
697 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
698 drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
699
700 /*
701 * 6. If the frequency will result in a change to the voltage
702 * requirement, follow the Display Voltage Frequency Switching -
703 * Sequence After Frequency Change.
704 *
705 * We handle this step in bxt_set_cdclk().
706 */
707 }
708
intel_mpllb_calc_port_clock(struct intel_encoder * encoder,const struct intel_mpllb_state * pll_state)709 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
710 const struct intel_mpllb_state *pll_state)
711 {
712 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
713 unsigned int multiplier, tx_clk_div, refclk;
714 bool frac_en;
715
716 if (0)
717 refclk = 38400;
718 else
719 refclk = 100000;
720
721 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
722
723 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
724
725 if (frac_en) {
726 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
727 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
728 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
729 }
730
731 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
732
733 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
734
735 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
736 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
737 10 << (tx_clk_div + 16));
738 }
739
intel_mpllb_readout_hw_state(struct intel_encoder * encoder,struct intel_mpllb_state * pll_state)740 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
741 struct intel_mpllb_state *pll_state)
742 {
743 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
744 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
745
746 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy));
747 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy));
748 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy));
749 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy));
750 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy));
751 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy));
752 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy));
753
754 /*
755 * REF_CONTROL is under firmware control and never programmed by the
756 * driver; we read it only for sanity checking purposes. The bspec
757 * only tells us the expected value for one field in this register,
758 * so we'll only read out those specific bits here.
759 */
760 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) &
761 SNPS_PHY_REF_CONTROL_REF_RANGE;
762
763 /*
764 * MPLLB_DIV is programmed twice, once with the software-computed
765 * state, then again with the MPLLB_FORCE_EN bit added. Drop that
766 * extra bit during readout so that we return the actual expected
767 * software state.
768 */
769 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
770 }
771
intel_snps_phy_check_hdmi_link_rate(int clock)772 int intel_snps_phy_check_hdmi_link_rate(int clock)
773 {
774 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables;
775 int i;
776
777 for (i = 0; tables[i]; i++) {
778 if (clock == tables[i]->clock)
779 return MODE_OK;
780 }
781
782 return MODE_CLOCK_RANGE;
783 }
784