1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
32 #include "drmP.h"
33 #include "drm.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37
38 /* Intel GPIO access functions */
39
40 #define I2C_RISEFALL_TIME 10
41
42 static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter * i2c)43 to_intel_gmbus(struct i2c_adapter *i2c)
44 {
45 return container_of(i2c, struct intel_gmbus, adapter);
46 }
47
48 void
intel_i2c_reset(struct drm_device * dev)49 intel_i2c_reset(struct drm_device *dev)
50 {
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 if (HAS_PCH_SPLIT(dev))
53 I915_WRITE(PCH_GMBUS0, 0);
54 else
55 I915_WRITE(GMBUS0, 0);
56 }
57
intel_i2c_quirk_set(struct drm_i915_private * dev_priv,bool enable)58 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
59 {
60 u32 val;
61
62 /* When using bit bashing for I2C, this bit needs to be set to 1 */
63 if (!IS_PINEVIEW(dev_priv->dev))
64 return;
65
66 val = I915_READ(DSPCLK_GATE_D);
67 if (enable)
68 val |= DPCUNIT_CLOCK_GATE_DISABLE;
69 else
70 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
71 I915_WRITE(DSPCLK_GATE_D, val);
72 }
73
get_reserved(struct intel_gmbus * bus)74 static u32 get_reserved(struct intel_gmbus *bus)
75 {
76 struct drm_i915_private *dev_priv = bus->dev_priv;
77 struct drm_device *dev = dev_priv->dev;
78 u32 reserved = 0;
79
80 /* On most chips, these bits must be preserved in software. */
81 if (!IS_I830(dev) && !IS_845G(dev))
82 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
83 (GPIO_DATA_PULLUP_DISABLE |
84 GPIO_CLOCK_PULLUP_DISABLE);
85
86 return reserved;
87 }
88
get_clock(void * data)89 static int get_clock(void *data)
90 {
91 struct intel_gmbus *bus = data;
92 struct drm_i915_private *dev_priv = bus->dev_priv;
93 u32 reserved = get_reserved(bus);
94 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
95 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
96 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
97 }
98
get_data(void * data)99 static int get_data(void *data)
100 {
101 struct intel_gmbus *bus = data;
102 struct drm_i915_private *dev_priv = bus->dev_priv;
103 u32 reserved = get_reserved(bus);
104 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
105 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
106 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
107 }
108
set_clock(void * data,int state_high)109 static void set_clock(void *data, int state_high)
110 {
111 struct intel_gmbus *bus = data;
112 struct drm_i915_private *dev_priv = bus->dev_priv;
113 u32 reserved = get_reserved(bus);
114 u32 clock_bits;
115
116 if (state_high)
117 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
118 else
119 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
120 GPIO_CLOCK_VAL_MASK;
121
122 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
123 POSTING_READ(bus->gpio_reg);
124 }
125
set_data(void * data,int state_high)126 static void set_data(void *data, int state_high)
127 {
128 struct intel_gmbus *bus = data;
129 struct drm_i915_private *dev_priv = bus->dev_priv;
130 u32 reserved = get_reserved(bus);
131 u32 data_bits;
132
133 if (state_high)
134 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
135 else
136 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
137 GPIO_DATA_VAL_MASK;
138
139 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
140 POSTING_READ(bus->gpio_reg);
141 }
142
143 static bool
intel_gpio_setup(struct intel_gmbus * bus,u32 pin)144 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
145 {
146 struct drm_i915_private *dev_priv = bus->dev_priv;
147 static const int map_pin_to_reg[] = {
148 0,
149 GPIOB,
150 GPIOA,
151 GPIOC,
152 GPIOD,
153 GPIOE,
154 0,
155 GPIOF,
156 };
157 struct i2c_algo_bit_data *algo;
158
159 if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
160 return false;
161
162 algo = &bus->bit_algo;
163
164 bus->gpio_reg = map_pin_to_reg[pin];
165 if (HAS_PCH_SPLIT(dev_priv->dev))
166 bus->gpio_reg += PCH_GPIOA - GPIOA;
167
168 bus->adapter.algo_data = algo;
169 algo->setsda = set_data;
170 algo->setscl = set_clock;
171 algo->getsda = get_data;
172 algo->getscl = get_clock;
173 algo->udelay = I2C_RISEFALL_TIME;
174 algo->timeout = usecs_to_jiffies(2200);
175 algo->data = bus;
176
177 return true;
178 }
179
180 static int
intel_i2c_quirk_xfer(struct intel_gmbus * bus,struct i2c_msg * msgs,int num)181 intel_i2c_quirk_xfer(struct intel_gmbus *bus,
182 struct i2c_msg *msgs,
183 int num)
184 {
185 struct drm_i915_private *dev_priv = bus->dev_priv;
186 int ret;
187
188 intel_i2c_reset(dev_priv->dev);
189
190 intel_i2c_quirk_set(dev_priv, true);
191 set_data(bus, 1);
192 set_clock(bus, 1);
193 udelay(I2C_RISEFALL_TIME);
194
195 ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);
196
197 set_data(bus, 1);
198 set_clock(bus, 1);
199 intel_i2c_quirk_set(dev_priv, false);
200
201 return ret;
202 }
203
204 static int
gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)205 gmbus_xfer(struct i2c_adapter *adapter,
206 struct i2c_msg *msgs,
207 int num)
208 {
209 struct intel_gmbus *bus = container_of(adapter,
210 struct intel_gmbus,
211 adapter);
212 struct drm_i915_private *dev_priv = bus->dev_priv;
213 int i, reg_offset, ret;
214
215 mutex_lock(&dev_priv->gmbus_mutex);
216
217 if (bus->force_bit) {
218 ret = intel_i2c_quirk_xfer(bus, msgs, num);
219 goto out;
220 }
221
222 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
223
224 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
225
226 for (i = 0; i < num; i++) {
227 u16 len = msgs[i].len;
228 u8 *buf = msgs[i].buf;
229
230 if (msgs[i].flags & I2C_M_RD) {
231 I915_WRITE(GMBUS1 + reg_offset,
232 GMBUS_CYCLE_WAIT |
233 (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
234 (len << GMBUS_BYTE_COUNT_SHIFT) |
235 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
236 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
237 POSTING_READ(GMBUS2+reg_offset);
238 do {
239 u32 val, loop = 0;
240
241 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
242 goto timeout;
243 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
244 goto clear_err;
245
246 val = I915_READ(GMBUS3 + reg_offset);
247 do {
248 *buf++ = val & 0xff;
249 val >>= 8;
250 } while (--len && ++loop < 4);
251 } while (len);
252 } else {
253 u32 val, loop;
254
255 val = loop = 0;
256 do {
257 val |= *buf++ << (8 * loop);
258 } while (--len && ++loop < 4);
259
260 I915_WRITE(GMBUS3 + reg_offset, val);
261 I915_WRITE(GMBUS1 + reg_offset,
262 GMBUS_CYCLE_WAIT |
263 (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
264 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
265 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
266 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
267 POSTING_READ(GMBUS2+reg_offset);
268
269 while (len) {
270 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
271 goto timeout;
272 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
273 goto clear_err;
274
275 val = loop = 0;
276 do {
277 val |= *buf++ << (8 * loop);
278 } while (--len && ++loop < 4);
279
280 I915_WRITE(GMBUS3 + reg_offset, val);
281 POSTING_READ(GMBUS2+reg_offset);
282 }
283 }
284
285 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
286 goto timeout;
287 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
288 goto clear_err;
289 }
290
291 goto done;
292
293 clear_err:
294 /* Toggle the Software Clear Interrupt bit. This has the effect
295 * of resetting the GMBUS controller and so clearing the
296 * BUS_ERROR raised by the slave's NAK.
297 */
298 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
299 I915_WRITE(GMBUS1 + reg_offset, 0);
300
301 done:
302 /* Mark the GMBUS interface as disabled after waiting for idle.
303 * We will re-enable it at the start of the next xfer,
304 * till then let it sleep.
305 */
306 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 10))
307 DRM_INFO("GMBUS timed out waiting for idle\n");
308 I915_WRITE(GMBUS0 + reg_offset, 0);
309 ret = i;
310 goto out;
311
312 timeout:
313 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
314 bus->reg0 & 0xff, bus->adapter.name);
315 I915_WRITE(GMBUS0 + reg_offset, 0);
316
317 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
318 if (!bus->has_gpio) {
319 ret = -EIO;
320 } else {
321 bus->force_bit = true;
322 ret = intel_i2c_quirk_xfer(bus, msgs, num);
323 }
324 out:
325 mutex_unlock(&dev_priv->gmbus_mutex);
326 return ret;
327 }
328
gmbus_func(struct i2c_adapter * adapter)329 static u32 gmbus_func(struct i2c_adapter *adapter)
330 {
331 return i2c_bit_algo.functionality(adapter) &
332 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
333 /* I2C_FUNC_10BIT_ADDR | */
334 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
335 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
336 }
337
338 static const struct i2c_algorithm gmbus_algorithm = {
339 .master_xfer = gmbus_xfer,
340 .functionality = gmbus_func
341 };
342
343 /**
344 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
345 * @dev: DRM device
346 */
intel_setup_gmbus(struct drm_device * dev)347 int intel_setup_gmbus(struct drm_device *dev)
348 {
349 static const char *names[GMBUS_NUM_PORTS] = {
350 "disabled",
351 "ssc",
352 "vga",
353 "panel",
354 "dpc",
355 "dpb",
356 "reserved",
357 "dpd",
358 };
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 int ret, i;
361
362 dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
363 GFP_KERNEL);
364 if (dev_priv->gmbus == NULL)
365 return -ENOMEM;
366
367 mutex_init(&dev_priv->gmbus_mutex);
368
369 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
370 struct intel_gmbus *bus = &dev_priv->gmbus[i];
371
372 bus->adapter.owner = THIS_MODULE;
373 bus->adapter.class = I2C_CLASS_DDC;
374 snprintf(bus->adapter.name,
375 sizeof(bus->adapter.name),
376 "i915 gmbus %s",
377 names[i]);
378
379 bus->adapter.dev.parent = &dev->pdev->dev;
380 bus->dev_priv = dev_priv;
381
382 bus->adapter.algo = &gmbus_algorithm;
383 ret = i2c_add_adapter(&bus->adapter);
384 if (ret)
385 goto err;
386
387 /* By default use a conservative clock rate */
388 bus->reg0 = i | GMBUS_RATE_100KHZ;
389
390 bus->has_gpio = intel_gpio_setup(bus, i);
391
392 /* XXX force bit banging until GMBUS is fully debugged */
393 if (bus->has_gpio)
394 bus->force_bit = true;
395 }
396
397 intel_i2c_reset(dev_priv->dev);
398
399 return 0;
400
401 err:
402 while (--i) {
403 struct intel_gmbus *bus = &dev_priv->gmbus[i];
404 i2c_del_adapter(&bus->adapter);
405 }
406 kfree(dev_priv->gmbus);
407 dev_priv->gmbus = NULL;
408 return ret;
409 }
410
intel_gmbus_set_speed(struct i2c_adapter * adapter,int speed)411 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
412 {
413 struct intel_gmbus *bus = to_intel_gmbus(adapter);
414
415 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
416 }
417
intel_gmbus_force_bit(struct i2c_adapter * adapter,bool force_bit)418 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
419 {
420 struct intel_gmbus *bus = to_intel_gmbus(adapter);
421
422 if (bus->has_gpio)
423 bus->force_bit = force_bit;
424 }
425
intel_teardown_gmbus(struct drm_device * dev)426 void intel_teardown_gmbus(struct drm_device *dev)
427 {
428 struct drm_i915_private *dev_priv = dev->dev_private;
429 int i;
430
431 if (dev_priv->gmbus == NULL)
432 return;
433
434 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
435 struct intel_gmbus *bus = &dev_priv->gmbus[i];
436 i2c_del_adapter(&bus->adapter);
437 }
438
439 kfree(dev_priv->gmbus);
440 dev_priv->gmbus = NULL;
441 }
442