1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
34
35 #include <drm/display/drm_hdcp_helper.h>
36 #include <drm/display/drm_hdmi_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_edid.h>
41 #include <drm/intel_lpe_audio.h>
42
43 #include "i915_debugfs.h"
44 #include "i915_drv.h"
45 #include "intel_atomic.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
48 #include "intel_de.h"
49 #include "intel_display_types.h"
50 #include "intel_dp.h"
51 #include "intel_gmbus.h"
52 #include "intel_hdcp.h"
53 #include "intel_hdmi.h"
54 #include "intel_lspcon.h"
55 #include "intel_panel.h"
56 #include "intel_snps_phy.h"
57
intel_hdmi_to_i915(struct intel_hdmi * intel_hdmi)58 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
59 {
60 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
61 }
62
63 static void
assert_hdmi_port_disabled(struct intel_hdmi * intel_hdmi)64 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
65 {
66 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
67 u32 enabled_bits;
68
69 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
70
71 drm_WARN(&dev_priv->drm,
72 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
73 "HDMI port enabled, expecting disabled\n");
74 }
75
76 static void
assert_hdmi_transcoder_func_disabled(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)77 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
78 enum transcoder cpu_transcoder)
79 {
80 drm_WARN(&dev_priv->drm,
81 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
82 TRANS_DDI_FUNC_ENABLE,
83 "HDMI transcoder function enabled, expecting disabled\n");
84 }
85
g4x_infoframe_index(unsigned int type)86 static u32 g4x_infoframe_index(unsigned int type)
87 {
88 switch (type) {
89 case HDMI_PACKET_TYPE_GAMUT_METADATA:
90 return VIDEO_DIP_SELECT_GAMUT;
91 case HDMI_INFOFRAME_TYPE_AVI:
92 return VIDEO_DIP_SELECT_AVI;
93 case HDMI_INFOFRAME_TYPE_SPD:
94 return VIDEO_DIP_SELECT_SPD;
95 case HDMI_INFOFRAME_TYPE_VENDOR:
96 return VIDEO_DIP_SELECT_VENDOR;
97 default:
98 MISSING_CASE(type);
99 return 0;
100 }
101 }
102
g4x_infoframe_enable(unsigned int type)103 static u32 g4x_infoframe_enable(unsigned int type)
104 {
105 switch (type) {
106 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
107 return VIDEO_DIP_ENABLE_GCP;
108 case HDMI_PACKET_TYPE_GAMUT_METADATA:
109 return VIDEO_DIP_ENABLE_GAMUT;
110 case DP_SDP_VSC:
111 return 0;
112 case HDMI_INFOFRAME_TYPE_AVI:
113 return VIDEO_DIP_ENABLE_AVI;
114 case HDMI_INFOFRAME_TYPE_SPD:
115 return VIDEO_DIP_ENABLE_SPD;
116 case HDMI_INFOFRAME_TYPE_VENDOR:
117 return VIDEO_DIP_ENABLE_VENDOR;
118 case HDMI_INFOFRAME_TYPE_DRM:
119 return 0;
120 default:
121 MISSING_CASE(type);
122 return 0;
123 }
124 }
125
hsw_infoframe_enable(unsigned int type)126 static u32 hsw_infoframe_enable(unsigned int type)
127 {
128 switch (type) {
129 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
130 return VIDEO_DIP_ENABLE_GCP_HSW;
131 case HDMI_PACKET_TYPE_GAMUT_METADATA:
132 return VIDEO_DIP_ENABLE_GMP_HSW;
133 case DP_SDP_VSC:
134 return VIDEO_DIP_ENABLE_VSC_HSW;
135 case DP_SDP_PPS:
136 return VDIP_ENABLE_PPS;
137 case HDMI_INFOFRAME_TYPE_AVI:
138 return VIDEO_DIP_ENABLE_AVI_HSW;
139 case HDMI_INFOFRAME_TYPE_SPD:
140 return VIDEO_DIP_ENABLE_SPD_HSW;
141 case HDMI_INFOFRAME_TYPE_VENDOR:
142 return VIDEO_DIP_ENABLE_VS_HSW;
143 case HDMI_INFOFRAME_TYPE_DRM:
144 return VIDEO_DIP_ENABLE_DRM_GLK;
145 default:
146 MISSING_CASE(type);
147 return 0;
148 }
149 }
150
151 static i915_reg_t
hsw_dip_data_reg(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder,unsigned int type,int i)152 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
153 enum transcoder cpu_transcoder,
154 unsigned int type,
155 int i)
156 {
157 switch (type) {
158 case HDMI_PACKET_TYPE_GAMUT_METADATA:
159 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
160 case DP_SDP_VSC:
161 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
162 case DP_SDP_PPS:
163 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
164 case HDMI_INFOFRAME_TYPE_AVI:
165 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_SPD:
167 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_VENDOR:
169 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
170 case HDMI_INFOFRAME_TYPE_DRM:
171 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
172 default:
173 MISSING_CASE(type);
174 return INVALID_MMIO_REG;
175 }
176 }
177
hsw_dip_data_size(struct drm_i915_private * dev_priv,unsigned int type)178 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
179 unsigned int type)
180 {
181 switch (type) {
182 case DP_SDP_VSC:
183 return VIDEO_DIP_VSC_DATA_SIZE;
184 case DP_SDP_PPS:
185 return VIDEO_DIP_PPS_DATA_SIZE;
186 case HDMI_PACKET_TYPE_GAMUT_METADATA:
187 if (DISPLAY_VER(dev_priv) >= 11)
188 return VIDEO_DIP_GMP_DATA_SIZE;
189 else
190 return VIDEO_DIP_DATA_SIZE;
191 default:
192 return VIDEO_DIP_DATA_SIZE;
193 }
194 }
195
g4x_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)196 static void g4x_write_infoframe(struct intel_encoder *encoder,
197 const struct intel_crtc_state *crtc_state,
198 unsigned int type,
199 const void *frame, ssize_t len)
200 {
201 const u32 *data = frame;
202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
203 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
204 int i;
205
206 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
207 "Writing DIP with CTL reg disabled\n");
208
209 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
210 val |= g4x_infoframe_index(type);
211
212 val &= ~g4x_infoframe_enable(type);
213
214 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
215
216 for (i = 0; i < len; i += 4) {
217 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
218 data++;
219 }
220 /* Write every possible data byte to force correct ECC calculation. */
221 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
222 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
223
224 val |= g4x_infoframe_enable(type);
225 val &= ~VIDEO_DIP_FREQ_MASK;
226 val |= VIDEO_DIP_FREQ_VSYNC;
227
228 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
229 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
230 }
231
g4x_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)232 static void g4x_read_infoframe(struct intel_encoder *encoder,
233 const struct intel_crtc_state *crtc_state,
234 unsigned int type,
235 void *frame, ssize_t len)
236 {
237 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
238 u32 val, *data = frame;
239 int i;
240
241 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
242
243 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
244 val |= g4x_infoframe_index(type);
245
246 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
247
248 for (i = 0; i < len; i += 4)
249 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
250 }
251
g4x_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)252 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
253 const struct intel_crtc_state *pipe_config)
254 {
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
256 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
257
258 if ((val & VIDEO_DIP_ENABLE) == 0)
259 return 0;
260
261 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
262 return 0;
263
264 return val & (VIDEO_DIP_ENABLE_AVI |
265 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
266 }
267
ibx_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)268 static void ibx_write_infoframe(struct intel_encoder *encoder,
269 const struct intel_crtc_state *crtc_state,
270 unsigned int type,
271 const void *frame, ssize_t len)
272 {
273 const u32 *data = frame;
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
276 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
277 u32 val = intel_de_read(dev_priv, reg);
278 int i;
279
280 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
281 "Writing DIP with CTL reg disabled\n");
282
283 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
284 val |= g4x_infoframe_index(type);
285
286 val &= ~g4x_infoframe_enable(type);
287
288 intel_de_write(dev_priv, reg, val);
289
290 for (i = 0; i < len; i += 4) {
291 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
292 *data);
293 data++;
294 }
295 /* Write every possible data byte to force correct ECC calculation. */
296 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
297 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
298
299 val |= g4x_infoframe_enable(type);
300 val &= ~VIDEO_DIP_FREQ_MASK;
301 val |= VIDEO_DIP_FREQ_VSYNC;
302
303 intel_de_write(dev_priv, reg, val);
304 intel_de_posting_read(dev_priv, reg);
305 }
306
ibx_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)307 static void ibx_read_infoframe(struct intel_encoder *encoder,
308 const struct intel_crtc_state *crtc_state,
309 unsigned int type,
310 void *frame, ssize_t len)
311 {
312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
314 u32 val, *data = frame;
315 int i;
316
317 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
318
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
321
322 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
323
324 for (i = 0; i < len; i += 4)
325 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
326 }
327
ibx_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)328 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
329 const struct intel_crtc_state *pipe_config)
330 {
331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
332 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
333 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
334 u32 val = intel_de_read(dev_priv, reg);
335
336 if ((val & VIDEO_DIP_ENABLE) == 0)
337 return 0;
338
339 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
340 return 0;
341
342 return val & (VIDEO_DIP_ENABLE_AVI |
343 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
344 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
345 }
346
cpt_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)347 static void cpt_write_infoframe(struct intel_encoder *encoder,
348 const struct intel_crtc_state *crtc_state,
349 unsigned int type,
350 const void *frame, ssize_t len)
351 {
352 const u32 *data = frame;
353 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
354 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
355 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
356 u32 val = intel_de_read(dev_priv, reg);
357 int i;
358
359 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
360 "Writing DIP with CTL reg disabled\n");
361
362 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
363 val |= g4x_infoframe_index(type);
364
365 /* The DIP control register spec says that we need to update the AVI
366 * infoframe without clearing its enable bit */
367 if (type != HDMI_INFOFRAME_TYPE_AVI)
368 val &= ~g4x_infoframe_enable(type);
369
370 intel_de_write(dev_priv, reg, val);
371
372 for (i = 0; i < len; i += 4) {
373 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
374 *data);
375 data++;
376 }
377 /* Write every possible data byte to force correct ECC calculation. */
378 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
379 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
380
381 val |= g4x_infoframe_enable(type);
382 val &= ~VIDEO_DIP_FREQ_MASK;
383 val |= VIDEO_DIP_FREQ_VSYNC;
384
385 intel_de_write(dev_priv, reg, val);
386 intel_de_posting_read(dev_priv, reg);
387 }
388
cpt_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)389 static void cpt_read_infoframe(struct intel_encoder *encoder,
390 const struct intel_crtc_state *crtc_state,
391 unsigned int type,
392 void *frame, ssize_t len)
393 {
394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
396 u32 val, *data = frame;
397 int i;
398
399 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
400
401 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
402 val |= g4x_infoframe_index(type);
403
404 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
405
406 for (i = 0; i < len; i += 4)
407 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
408 }
409
cpt_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)410 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
411 const struct intel_crtc_state *pipe_config)
412 {
413 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
414 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
415 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
416
417 if ((val & VIDEO_DIP_ENABLE) == 0)
418 return 0;
419
420 return val & (VIDEO_DIP_ENABLE_AVI |
421 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
422 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
423 }
424
vlv_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)425 static void vlv_write_infoframe(struct intel_encoder *encoder,
426 const struct intel_crtc_state *crtc_state,
427 unsigned int type,
428 const void *frame, ssize_t len)
429 {
430 const u32 *data = frame;
431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
432 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
433 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
434 u32 val = intel_de_read(dev_priv, reg);
435 int i;
436
437 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
438 "Writing DIP with CTL reg disabled\n");
439
440 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
441 val |= g4x_infoframe_index(type);
442
443 val &= ~g4x_infoframe_enable(type);
444
445 intel_de_write(dev_priv, reg, val);
446
447 for (i = 0; i < len; i += 4) {
448 intel_de_write(dev_priv,
449 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
450 data++;
451 }
452 /* Write every possible data byte to force correct ECC calculation. */
453 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
454 intel_de_write(dev_priv,
455 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
456
457 val |= g4x_infoframe_enable(type);
458 val &= ~VIDEO_DIP_FREQ_MASK;
459 val |= VIDEO_DIP_FREQ_VSYNC;
460
461 intel_de_write(dev_priv, reg, val);
462 intel_de_posting_read(dev_priv, reg);
463 }
464
vlv_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)465 static void vlv_read_infoframe(struct intel_encoder *encoder,
466 const struct intel_crtc_state *crtc_state,
467 unsigned int type,
468 void *frame, ssize_t len)
469 {
470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
472 u32 val, *data = frame;
473 int i;
474
475 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
476
477 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
478 val |= g4x_infoframe_index(type);
479
480 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
481
482 for (i = 0; i < len; i += 4)
483 *data++ = intel_de_read(dev_priv,
484 VLV_TVIDEO_DIP_DATA(crtc->pipe));
485 }
486
vlv_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)487 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
488 const struct intel_crtc_state *pipe_config)
489 {
490 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
491 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
492 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
493
494 if ((val & VIDEO_DIP_ENABLE) == 0)
495 return 0;
496
497 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
498 return 0;
499
500 return val & (VIDEO_DIP_ENABLE_AVI |
501 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
502 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
503 }
504
hsw_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)505 void hsw_write_infoframe(struct intel_encoder *encoder,
506 const struct intel_crtc_state *crtc_state,
507 unsigned int type,
508 const void *frame, ssize_t len)
509 {
510 const u32 *data = frame;
511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
513 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
514 int data_size;
515 int i;
516 u32 val = intel_de_read(dev_priv, ctl_reg);
517
518 data_size = hsw_dip_data_size(dev_priv, type);
519
520 drm_WARN_ON(&dev_priv->drm, len > data_size);
521
522 val &= ~hsw_infoframe_enable(type);
523 intel_de_write(dev_priv, ctl_reg, val);
524
525 for (i = 0; i < len; i += 4) {
526 intel_de_write(dev_priv,
527 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
528 *data);
529 data++;
530 }
531 /* Write every possible data byte to force correct ECC calculation. */
532 for (; i < data_size; i += 4)
533 intel_de_write(dev_priv,
534 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
535 0);
536
537 /* Wa_14013475917 */
538 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
539 type == DP_SDP_VSC)
540 return;
541
542 val |= hsw_infoframe_enable(type);
543 intel_de_write(dev_priv, ctl_reg, val);
544 intel_de_posting_read(dev_priv, ctl_reg);
545 }
546
hsw_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)547 void hsw_read_infoframe(struct intel_encoder *encoder,
548 const struct intel_crtc_state *crtc_state,
549 unsigned int type, void *frame, ssize_t len)
550 {
551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
553 u32 *data = frame;
554 int i;
555
556 for (i = 0; i < len; i += 4)
557 *data++ = intel_de_read(dev_priv,
558 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
559 }
560
hsw_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)561 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
562 const struct intel_crtc_state *pipe_config)
563 {
564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
565 u32 val = intel_de_read(dev_priv,
566 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
567 u32 mask;
568
569 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
570 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
571 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
572
573 if (DISPLAY_VER(dev_priv) >= 10)
574 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
575
576 return val & mask;
577 }
578
579 static const u8 infoframe_type_to_idx[] = {
580 HDMI_PACKET_TYPE_GENERAL_CONTROL,
581 HDMI_PACKET_TYPE_GAMUT_METADATA,
582 DP_SDP_VSC,
583 HDMI_INFOFRAME_TYPE_AVI,
584 HDMI_INFOFRAME_TYPE_SPD,
585 HDMI_INFOFRAME_TYPE_VENDOR,
586 HDMI_INFOFRAME_TYPE_DRM,
587 };
588
intel_hdmi_infoframe_enable(unsigned int type)589 u32 intel_hdmi_infoframe_enable(unsigned int type)
590 {
591 int i;
592
593 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
594 if (infoframe_type_to_idx[i] == type)
595 return BIT(i);
596 }
597
598 return 0;
599 }
600
intel_hdmi_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)601 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
602 const struct intel_crtc_state *crtc_state)
603 {
604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
605 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
606 u32 val, ret = 0;
607 int i;
608
609 val = dig_port->infoframes_enabled(encoder, crtc_state);
610
611 /* map from hardware bits to dip idx */
612 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
613 unsigned int type = infoframe_type_to_idx[i];
614
615 if (HAS_DDI(dev_priv)) {
616 if (val & hsw_infoframe_enable(type))
617 ret |= BIT(i);
618 } else {
619 if (val & g4x_infoframe_enable(type))
620 ret |= BIT(i);
621 }
622 }
623
624 return ret;
625 }
626
627 /*
628 * The data we write to the DIP data buffer registers is 1 byte bigger than the
629 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
630 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
631 * used for both technologies.
632 *
633 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
634 * DW1: DB3 | DB2 | DB1 | DB0
635 * DW2: DB7 | DB6 | DB5 | DB4
636 * DW3: ...
637 *
638 * (HB is Header Byte, DB is Data Byte)
639 *
640 * The hdmi pack() functions don't know about that hardware specific hole so we
641 * trick them by giving an offset into the buffer and moving back the header
642 * bytes by one.
643 */
intel_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,enum hdmi_infoframe_type type,const union hdmi_infoframe * frame)644 static void intel_write_infoframe(struct intel_encoder *encoder,
645 const struct intel_crtc_state *crtc_state,
646 enum hdmi_infoframe_type type,
647 const union hdmi_infoframe *frame)
648 {
649 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
650 u8 buffer[VIDEO_DIP_DATA_SIZE];
651 ssize_t len;
652
653 if ((crtc_state->infoframes.enable &
654 intel_hdmi_infoframe_enable(type)) == 0)
655 return;
656
657 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
658 return;
659
660 /* see comment above for the reason for this offset */
661 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
662 if (drm_WARN_ON(encoder->base.dev, len < 0))
663 return;
664
665 /* Insert the 'hole' (see big comment above) at position 3 */
666 memmove(&buffer[0], &buffer[1], 3);
667 buffer[3] = 0;
668 len++;
669
670 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
671 }
672
intel_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,enum hdmi_infoframe_type type,union hdmi_infoframe * frame)673 void intel_read_infoframe(struct intel_encoder *encoder,
674 const struct intel_crtc_state *crtc_state,
675 enum hdmi_infoframe_type type,
676 union hdmi_infoframe *frame)
677 {
678 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
679 u8 buffer[VIDEO_DIP_DATA_SIZE];
680 int ret;
681
682 if ((crtc_state->infoframes.enable &
683 intel_hdmi_infoframe_enable(type)) == 0)
684 return;
685
686 dig_port->read_infoframe(encoder, crtc_state,
687 type, buffer, sizeof(buffer));
688
689 /* Fill the 'hole' (see big comment above) at position 3 */
690 memmove(&buffer[1], &buffer[0], 3);
691
692 /* see comment above for the reason for this offset */
693 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
694 if (ret) {
695 drm_dbg_kms(encoder->base.dev,
696 "Failed to unpack infoframe type 0x%02x\n", type);
697 return;
698 }
699
700 if (frame->any.type != type)
701 drm_dbg_kms(encoder->base.dev,
702 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
703 frame->any.type, type);
704 }
705
706 static bool
intel_hdmi_compute_avi_infoframe(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)707 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
708 struct intel_crtc_state *crtc_state,
709 struct drm_connector_state *conn_state)
710 {
711 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
712 const struct drm_display_mode *adjusted_mode =
713 &crtc_state->hw.adjusted_mode;
714 struct drm_connector *connector = conn_state->connector;
715 int ret;
716
717 if (!crtc_state->has_infoframe)
718 return true;
719
720 crtc_state->infoframes.enable |=
721 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
722
723 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
724 adjusted_mode);
725 if (ret)
726 return false;
727
728 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
729 frame->colorspace = HDMI_COLORSPACE_YUV420;
730 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
731 frame->colorspace = HDMI_COLORSPACE_YUV444;
732 else
733 frame->colorspace = HDMI_COLORSPACE_RGB;
734
735 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
736
737 /* nonsense combination */
738 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
739 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
740
741 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
742 drm_hdmi_avi_infoframe_quant_range(frame, connector,
743 adjusted_mode,
744 crtc_state->limited_color_range ?
745 HDMI_QUANTIZATION_RANGE_LIMITED :
746 HDMI_QUANTIZATION_RANGE_FULL);
747 } else {
748 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
749 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
750 }
751
752 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
753
754 /* TODO: handle pixel repetition for YCBCR420 outputs */
755
756 ret = hdmi_avi_infoframe_check(frame);
757 if (drm_WARN_ON(encoder->base.dev, ret))
758 return false;
759
760 return true;
761 }
762
763 static bool
intel_hdmi_compute_spd_infoframe(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)764 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
765 struct intel_crtc_state *crtc_state,
766 struct drm_connector_state *conn_state)
767 {
768 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
769 int ret;
770
771 if (!crtc_state->has_infoframe)
772 return true;
773
774 crtc_state->infoframes.enable |=
775 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
776
777 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
778 if (drm_WARN_ON(encoder->base.dev, ret))
779 return false;
780
781 frame->sdi = HDMI_SPD_SDI_PC;
782
783 ret = hdmi_spd_infoframe_check(frame);
784 if (drm_WARN_ON(encoder->base.dev, ret))
785 return false;
786
787 return true;
788 }
789
790 static bool
intel_hdmi_compute_hdmi_infoframe(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)791 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
792 struct intel_crtc_state *crtc_state,
793 struct drm_connector_state *conn_state)
794 {
795 struct hdmi_vendor_infoframe *frame =
796 &crtc_state->infoframes.hdmi.vendor.hdmi;
797 const struct drm_display_info *info =
798 &conn_state->connector->display_info;
799 int ret;
800
801 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
802 return true;
803
804 crtc_state->infoframes.enable |=
805 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
806
807 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
808 conn_state->connector,
809 &crtc_state->hw.adjusted_mode);
810 if (drm_WARN_ON(encoder->base.dev, ret))
811 return false;
812
813 ret = hdmi_vendor_infoframe_check(frame);
814 if (drm_WARN_ON(encoder->base.dev, ret))
815 return false;
816
817 return true;
818 }
819
820 static bool
intel_hdmi_compute_drm_infoframe(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)821 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
822 struct intel_crtc_state *crtc_state,
823 struct drm_connector_state *conn_state)
824 {
825 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
827 int ret;
828
829 if (DISPLAY_VER(dev_priv) < 10)
830 return true;
831
832 if (!crtc_state->has_infoframe)
833 return true;
834
835 if (!conn_state->hdr_output_metadata)
836 return true;
837
838 crtc_state->infoframes.enable |=
839 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
840
841 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
842 if (ret < 0) {
843 drm_dbg_kms(&dev_priv->drm,
844 "couldn't set HDR metadata in infoframe\n");
845 return false;
846 }
847
848 ret = hdmi_drm_infoframe_check(frame);
849 if (drm_WARN_ON(&dev_priv->drm, ret))
850 return false;
851
852 return true;
853 }
854
g4x_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)855 static void g4x_set_infoframes(struct intel_encoder *encoder,
856 bool enable,
857 const struct intel_crtc_state *crtc_state,
858 const struct drm_connector_state *conn_state)
859 {
860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
861 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
862 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
863 i915_reg_t reg = VIDEO_DIP_CTL;
864 u32 val = intel_de_read(dev_priv, reg);
865 u32 port = VIDEO_DIP_PORT(encoder->port);
866
867 assert_hdmi_port_disabled(intel_hdmi);
868
869 /* If the registers were not initialized yet, they might be zeroes,
870 * which means we're selecting the AVI DIP and we're setting its
871 * frequency to once. This seems to really confuse the HW and make
872 * things stop working (the register spec says the AVI always needs to
873 * be sent every VSync). So here we avoid writing to the register more
874 * than we need and also explicitly select the AVI DIP and explicitly
875 * set its frequency to every VSync. Avoiding to write it twice seems to
876 * be enough to solve the problem, but being defensive shouldn't hurt us
877 * either. */
878 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
879
880 if (!enable) {
881 if (!(val & VIDEO_DIP_ENABLE))
882 return;
883 if (port != (val & VIDEO_DIP_PORT_MASK)) {
884 drm_dbg_kms(&dev_priv->drm,
885 "video DIP still enabled on port %c\n",
886 (val & VIDEO_DIP_PORT_MASK) >> 29);
887 return;
888 }
889 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
890 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
891 intel_de_write(dev_priv, reg, val);
892 intel_de_posting_read(dev_priv, reg);
893 return;
894 }
895
896 if (port != (val & VIDEO_DIP_PORT_MASK)) {
897 if (val & VIDEO_DIP_ENABLE) {
898 drm_dbg_kms(&dev_priv->drm,
899 "video DIP already enabled on port %c\n",
900 (val & VIDEO_DIP_PORT_MASK) >> 29);
901 return;
902 }
903 val &= ~VIDEO_DIP_PORT_MASK;
904 val |= port;
905 }
906
907 val |= VIDEO_DIP_ENABLE;
908 val &= ~(VIDEO_DIP_ENABLE_AVI |
909 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
910
911 intel_de_write(dev_priv, reg, val);
912 intel_de_posting_read(dev_priv, reg);
913
914 intel_write_infoframe(encoder, crtc_state,
915 HDMI_INFOFRAME_TYPE_AVI,
916 &crtc_state->infoframes.avi);
917 intel_write_infoframe(encoder, crtc_state,
918 HDMI_INFOFRAME_TYPE_SPD,
919 &crtc_state->infoframes.spd);
920 intel_write_infoframe(encoder, crtc_state,
921 HDMI_INFOFRAME_TYPE_VENDOR,
922 &crtc_state->infoframes.hdmi);
923 }
924
925 /*
926 * Determine if default_phase=1 can be indicated in the GCP infoframe.
927 *
928 * From HDMI specification 1.4a:
929 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
930 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
931 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
932 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
933 * phase of 0
934 */
gcp_default_phase_possible(int pipe_bpp,const struct drm_display_mode * mode)935 static bool gcp_default_phase_possible(int pipe_bpp,
936 const struct drm_display_mode *mode)
937 {
938 unsigned int pixels_per_group;
939
940 switch (pipe_bpp) {
941 case 30:
942 /* 4 pixels in 5 clocks */
943 pixels_per_group = 4;
944 break;
945 case 36:
946 /* 2 pixels in 3 clocks */
947 pixels_per_group = 2;
948 break;
949 case 48:
950 /* 1 pixel in 2 clocks */
951 pixels_per_group = 1;
952 break;
953 default:
954 /* phase information not relevant for 8bpc */
955 return false;
956 }
957
958 return mode->crtc_hdisplay % pixels_per_group == 0 &&
959 mode->crtc_htotal % pixels_per_group == 0 &&
960 mode->crtc_hblank_start % pixels_per_group == 0 &&
961 mode->crtc_hblank_end % pixels_per_group == 0 &&
962 mode->crtc_hsync_start % pixels_per_group == 0 &&
963 mode->crtc_hsync_end % pixels_per_group == 0 &&
964 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
965 mode->crtc_htotal/2 % pixels_per_group == 0);
966 }
967
intel_hdmi_set_gcp_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)968 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
969 const struct intel_crtc_state *crtc_state,
970 const struct drm_connector_state *conn_state)
971 {
972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
973 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
974 i915_reg_t reg;
975
976 if ((crtc_state->infoframes.enable &
977 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
978 return false;
979
980 if (HAS_DDI(dev_priv))
981 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
982 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
983 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
984 else if (HAS_PCH_SPLIT(dev_priv))
985 reg = TVIDEO_DIP_GCP(crtc->pipe);
986 else
987 return false;
988
989 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
990
991 return true;
992 }
993
intel_hdmi_read_gcp_infoframe(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)994 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
995 struct intel_crtc_state *crtc_state)
996 {
997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
999 i915_reg_t reg;
1000
1001 if ((crtc_state->infoframes.enable &
1002 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1003 return;
1004
1005 if (HAS_DDI(dev_priv))
1006 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1007 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1008 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1009 else if (HAS_PCH_SPLIT(dev_priv))
1010 reg = TVIDEO_DIP_GCP(crtc->pipe);
1011 else
1012 return;
1013
1014 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1015 }
1016
intel_hdmi_compute_gcp_infoframe(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)1017 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1018 struct intel_crtc_state *crtc_state,
1019 struct drm_connector_state *conn_state)
1020 {
1021 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1022
1023 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1024 return;
1025
1026 crtc_state->infoframes.enable |=
1027 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1028
1029 /* Indicate color indication for deep color mode */
1030 if (crtc_state->pipe_bpp > 24)
1031 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1032
1033 /* Enable default_phase whenever the display mode is suitably aligned */
1034 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1035 &crtc_state->hw.adjusted_mode))
1036 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1037 }
1038
ibx_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1039 static void ibx_set_infoframes(struct intel_encoder *encoder,
1040 bool enable,
1041 const struct intel_crtc_state *crtc_state,
1042 const struct drm_connector_state *conn_state)
1043 {
1044 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1045 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1046 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1047 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1048 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1049 u32 val = intel_de_read(dev_priv, reg);
1050 u32 port = VIDEO_DIP_PORT(encoder->port);
1051
1052 assert_hdmi_port_disabled(intel_hdmi);
1053
1054 /* See the big comment in g4x_set_infoframes() */
1055 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1056
1057 if (!enable) {
1058 if (!(val & VIDEO_DIP_ENABLE))
1059 return;
1060 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1061 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1062 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1063 intel_de_write(dev_priv, reg, val);
1064 intel_de_posting_read(dev_priv, reg);
1065 return;
1066 }
1067
1068 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1069 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1070 "DIP already enabled on port %c\n",
1071 (val & VIDEO_DIP_PORT_MASK) >> 29);
1072 val &= ~VIDEO_DIP_PORT_MASK;
1073 val |= port;
1074 }
1075
1076 val |= VIDEO_DIP_ENABLE;
1077 val &= ~(VIDEO_DIP_ENABLE_AVI |
1078 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1079 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1080
1081 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1082 val |= VIDEO_DIP_ENABLE_GCP;
1083
1084 intel_de_write(dev_priv, reg, val);
1085 intel_de_posting_read(dev_priv, reg);
1086
1087 intel_write_infoframe(encoder, crtc_state,
1088 HDMI_INFOFRAME_TYPE_AVI,
1089 &crtc_state->infoframes.avi);
1090 intel_write_infoframe(encoder, crtc_state,
1091 HDMI_INFOFRAME_TYPE_SPD,
1092 &crtc_state->infoframes.spd);
1093 intel_write_infoframe(encoder, crtc_state,
1094 HDMI_INFOFRAME_TYPE_VENDOR,
1095 &crtc_state->infoframes.hdmi);
1096 }
1097
cpt_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1098 static void cpt_set_infoframes(struct intel_encoder *encoder,
1099 bool enable,
1100 const struct intel_crtc_state *crtc_state,
1101 const struct drm_connector_state *conn_state)
1102 {
1103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1104 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1105 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1106 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1107 u32 val = intel_de_read(dev_priv, reg);
1108
1109 assert_hdmi_port_disabled(intel_hdmi);
1110
1111 /* See the big comment in g4x_set_infoframes() */
1112 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1113
1114 if (!enable) {
1115 if (!(val & VIDEO_DIP_ENABLE))
1116 return;
1117 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1118 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1119 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1120 intel_de_write(dev_priv, reg, val);
1121 intel_de_posting_read(dev_priv, reg);
1122 return;
1123 }
1124
1125 /* Set both together, unset both together: see the spec. */
1126 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1127 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1128 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1129
1130 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1131 val |= VIDEO_DIP_ENABLE_GCP;
1132
1133 intel_de_write(dev_priv, reg, val);
1134 intel_de_posting_read(dev_priv, reg);
1135
1136 intel_write_infoframe(encoder, crtc_state,
1137 HDMI_INFOFRAME_TYPE_AVI,
1138 &crtc_state->infoframes.avi);
1139 intel_write_infoframe(encoder, crtc_state,
1140 HDMI_INFOFRAME_TYPE_SPD,
1141 &crtc_state->infoframes.spd);
1142 intel_write_infoframe(encoder, crtc_state,
1143 HDMI_INFOFRAME_TYPE_VENDOR,
1144 &crtc_state->infoframes.hdmi);
1145 }
1146
vlv_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1147 static void vlv_set_infoframes(struct intel_encoder *encoder,
1148 bool enable,
1149 const struct intel_crtc_state *crtc_state,
1150 const struct drm_connector_state *conn_state)
1151 {
1152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1153 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1154 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1155 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1156 u32 val = intel_de_read(dev_priv, reg);
1157 u32 port = VIDEO_DIP_PORT(encoder->port);
1158
1159 assert_hdmi_port_disabled(intel_hdmi);
1160
1161 /* See the big comment in g4x_set_infoframes() */
1162 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1163
1164 if (!enable) {
1165 if (!(val & VIDEO_DIP_ENABLE))
1166 return;
1167 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1168 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1169 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1170 intel_de_write(dev_priv, reg, val);
1171 intel_de_posting_read(dev_priv, reg);
1172 return;
1173 }
1174
1175 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1176 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1177 "DIP already enabled on port %c\n",
1178 (val & VIDEO_DIP_PORT_MASK) >> 29);
1179 val &= ~VIDEO_DIP_PORT_MASK;
1180 val |= port;
1181 }
1182
1183 val |= VIDEO_DIP_ENABLE;
1184 val &= ~(VIDEO_DIP_ENABLE_AVI |
1185 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1186 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1187
1188 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1189 val |= VIDEO_DIP_ENABLE_GCP;
1190
1191 intel_de_write(dev_priv, reg, val);
1192 intel_de_posting_read(dev_priv, reg);
1193
1194 intel_write_infoframe(encoder, crtc_state,
1195 HDMI_INFOFRAME_TYPE_AVI,
1196 &crtc_state->infoframes.avi);
1197 intel_write_infoframe(encoder, crtc_state,
1198 HDMI_INFOFRAME_TYPE_SPD,
1199 &crtc_state->infoframes.spd);
1200 intel_write_infoframe(encoder, crtc_state,
1201 HDMI_INFOFRAME_TYPE_VENDOR,
1202 &crtc_state->infoframes.hdmi);
1203 }
1204
hsw_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1205 static void hsw_set_infoframes(struct intel_encoder *encoder,
1206 bool enable,
1207 const struct intel_crtc_state *crtc_state,
1208 const struct drm_connector_state *conn_state)
1209 {
1210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1211 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1212 u32 val = intel_de_read(dev_priv, reg);
1213
1214 assert_hdmi_transcoder_func_disabled(dev_priv,
1215 crtc_state->cpu_transcoder);
1216
1217 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1218 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1219 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1220 VIDEO_DIP_ENABLE_DRM_GLK);
1221
1222 if (!enable) {
1223 intel_de_write(dev_priv, reg, val);
1224 intel_de_posting_read(dev_priv, reg);
1225 return;
1226 }
1227
1228 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1229 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1230
1231 intel_de_write(dev_priv, reg, val);
1232 intel_de_posting_read(dev_priv, reg);
1233
1234 intel_write_infoframe(encoder, crtc_state,
1235 HDMI_INFOFRAME_TYPE_AVI,
1236 &crtc_state->infoframes.avi);
1237 intel_write_infoframe(encoder, crtc_state,
1238 HDMI_INFOFRAME_TYPE_SPD,
1239 &crtc_state->infoframes.spd);
1240 intel_write_infoframe(encoder, crtc_state,
1241 HDMI_INFOFRAME_TYPE_VENDOR,
1242 &crtc_state->infoframes.hdmi);
1243 intel_write_infoframe(encoder, crtc_state,
1244 HDMI_INFOFRAME_TYPE_DRM,
1245 &crtc_state->infoframes.drm);
1246 }
1247
intel_dp_dual_mode_set_tmds_output(struct intel_hdmi * hdmi,bool enable)1248 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1249 {
1250 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1251 struct i2c_adapter *adapter;
1252
1253 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1254 return;
1255
1256 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1257
1258 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1259 enable ? "Enabling" : "Disabling");
1260
1261 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1262 }
1263
intel_hdmi_hdcp_read(struct intel_digital_port * dig_port,unsigned int offset,void * buffer,size_t size)1264 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1265 unsigned int offset, void *buffer, size_t size)
1266 {
1267 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1268 struct intel_hdmi *hdmi = &dig_port->hdmi;
1269 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1270 hdmi->ddc_bus);
1271 int ret;
1272 u8 start = offset & 0xff;
1273 struct i2c_msg msgs[] = {
1274 {
1275 .addr = DRM_HDCP_DDC_ADDR,
1276 .flags = 0,
1277 .len = 1,
1278 .buf = &start,
1279 },
1280 {
1281 .addr = DRM_HDCP_DDC_ADDR,
1282 .flags = I2C_M_RD,
1283 .len = size,
1284 .buf = buffer
1285 }
1286 };
1287 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1288 if (ret == ARRAY_SIZE(msgs))
1289 return 0;
1290 return ret >= 0 ? -EIO : ret;
1291 }
1292
intel_hdmi_hdcp_write(struct intel_digital_port * dig_port,unsigned int offset,void * buffer,size_t size)1293 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1294 unsigned int offset, void *buffer, size_t size)
1295 {
1296 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1297 struct intel_hdmi *hdmi = &dig_port->hdmi;
1298 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1299 hdmi->ddc_bus);
1300 int ret;
1301 u8 *write_buf;
1302 struct i2c_msg msg;
1303
1304 write_buf = kzalloc(size + 1, GFP_KERNEL);
1305 if (!write_buf)
1306 return -ENOMEM;
1307
1308 write_buf[0] = offset & 0xff;
1309 memcpy(&write_buf[1], buffer, size);
1310
1311 msg.addr = DRM_HDCP_DDC_ADDR;
1312 msg.flags = 0,
1313 msg.len = size + 1,
1314 msg.buf = write_buf;
1315
1316 ret = i2c_transfer(adapter, &msg, 1);
1317 if (ret == 1)
1318 ret = 0;
1319 else if (ret >= 0)
1320 ret = -EIO;
1321
1322 kfree(write_buf);
1323 return ret;
1324 }
1325
1326 static
intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port * dig_port,u8 * an)1327 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1328 u8 *an)
1329 {
1330 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1331 struct intel_hdmi *hdmi = &dig_port->hdmi;
1332 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1333 hdmi->ddc_bus);
1334 int ret;
1335
1336 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1337 DRM_HDCP_AN_LEN);
1338 if (ret) {
1339 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1340 ret);
1341 return ret;
1342 }
1343
1344 ret = intel_gmbus_output_aksv(adapter);
1345 if (ret < 0) {
1346 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1347 return ret;
1348 }
1349 return 0;
1350 }
1351
intel_hdmi_hdcp_read_bksv(struct intel_digital_port * dig_port,u8 * bksv)1352 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1353 u8 *bksv)
1354 {
1355 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1356
1357 int ret;
1358 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1359 DRM_HDCP_KSV_LEN);
1360 if (ret)
1361 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1362 ret);
1363 return ret;
1364 }
1365
1366 static
intel_hdmi_hdcp_read_bstatus(struct intel_digital_port * dig_port,u8 * bstatus)1367 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1368 u8 *bstatus)
1369 {
1370 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1371
1372 int ret;
1373 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1374 bstatus, DRM_HDCP_BSTATUS_LEN);
1375 if (ret)
1376 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1377 ret);
1378 return ret;
1379 }
1380
1381 static
intel_hdmi_hdcp_repeater_present(struct intel_digital_port * dig_port,bool * repeater_present)1382 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1383 bool *repeater_present)
1384 {
1385 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1386 int ret;
1387 u8 val;
1388
1389 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1390 if (ret) {
1391 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1392 ret);
1393 return ret;
1394 }
1395 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1396 return 0;
1397 }
1398
1399 static
intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port * dig_port,u8 * ri_prime)1400 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1401 u8 *ri_prime)
1402 {
1403 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1404
1405 int ret;
1406 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1407 ri_prime, DRM_HDCP_RI_LEN);
1408 if (ret)
1409 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1410 ret);
1411 return ret;
1412 }
1413
1414 static
intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port * dig_port,bool * ksv_ready)1415 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1416 bool *ksv_ready)
1417 {
1418 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1419 int ret;
1420 u8 val;
1421
1422 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1423 if (ret) {
1424 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1425 ret);
1426 return ret;
1427 }
1428 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1429 return 0;
1430 }
1431
1432 static
intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port * dig_port,int num_downstream,u8 * ksv_fifo)1433 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1434 int num_downstream, u8 *ksv_fifo)
1435 {
1436 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1437 int ret;
1438 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1439 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1440 if (ret) {
1441 drm_dbg_kms(&i915->drm,
1442 "Read ksv fifo over DDC failed (%d)\n", ret);
1443 return ret;
1444 }
1445 return 0;
1446 }
1447
1448 static
intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port * dig_port,int i,u32 * part)1449 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1450 int i, u32 *part)
1451 {
1452 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1453 int ret;
1454
1455 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1456 return -EINVAL;
1457
1458 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1459 part, DRM_HDCP_V_PRIME_PART_LEN);
1460 if (ret)
1461 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1462 i, ret);
1463 return ret;
1464 }
1465
kbl_repositioning_enc_en_signal(struct intel_connector * connector,enum transcoder cpu_transcoder)1466 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1467 enum transcoder cpu_transcoder)
1468 {
1469 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1470 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1471 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1472 u32 scanline;
1473 int ret;
1474
1475 for (;;) {
1476 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1477 if (scanline > 100 && scanline < 200)
1478 break;
1479 usleep_range(25, 50);
1480 }
1481
1482 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1483 false, TRANS_DDI_HDCP_SIGNALLING);
1484 if (ret) {
1485 drm_err(&dev_priv->drm,
1486 "Disable HDCP signalling failed (%d)\n", ret);
1487 return ret;
1488 }
1489
1490 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1491 true, TRANS_DDI_HDCP_SIGNALLING);
1492 if (ret) {
1493 drm_err(&dev_priv->drm,
1494 "Enable HDCP signalling failed (%d)\n", ret);
1495 return ret;
1496 }
1497
1498 return 0;
1499 }
1500
1501 static
intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port * dig_port,enum transcoder cpu_transcoder,bool enable)1502 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1503 enum transcoder cpu_transcoder,
1504 bool enable)
1505 {
1506 struct intel_hdmi *hdmi = &dig_port->hdmi;
1507 struct intel_connector *connector = hdmi->attached_connector;
1508 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1509 int ret;
1510
1511 if (!enable)
1512 usleep_range(6, 60); /* Bspec says >= 6us */
1513
1514 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1515 cpu_transcoder, enable,
1516 TRANS_DDI_HDCP_SIGNALLING);
1517 if (ret) {
1518 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1519 enable ? "Enable" : "Disable", ret);
1520 return ret;
1521 }
1522
1523 /*
1524 * WA: To fix incorrect positioning of the window of
1525 * opportunity and enc_en signalling in KABYLAKE.
1526 */
1527 if (IS_KABYLAKE(dev_priv) && enable)
1528 return kbl_repositioning_enc_en_signal(connector,
1529 cpu_transcoder);
1530
1531 return 0;
1532 }
1533
1534 static
intel_hdmi_hdcp_check_link_once(struct intel_digital_port * dig_port,struct intel_connector * connector)1535 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1536 struct intel_connector *connector)
1537 {
1538 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1539 enum port port = dig_port->base.port;
1540 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1541 int ret;
1542 union {
1543 u32 reg;
1544 u8 shim[DRM_HDCP_RI_LEN];
1545 } ri;
1546
1547 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1548 if (ret)
1549 return false;
1550
1551 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1552
1553 /* Wait for Ri prime match */
1554 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1556 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1557 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1558 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1559 port)));
1560 return false;
1561 }
1562 return true;
1563 }
1564
1565 static
intel_hdmi_hdcp_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)1566 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1567 struct intel_connector *connector)
1568 {
1569 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1570 int retry;
1571
1572 for (retry = 0; retry < 3; retry++)
1573 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1574 return true;
1575
1576 drm_err(&i915->drm, "Link check failed\n");
1577 return false;
1578 }
1579
1580 struct hdcp2_hdmi_msg_timeout {
1581 u8 msg_id;
1582 u16 timeout;
1583 };
1584
1585 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1586 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1587 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1588 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1589 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1590 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1591 };
1592
1593 static
intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port * dig_port,u8 * rx_status)1594 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1595 u8 *rx_status)
1596 {
1597 return intel_hdmi_hdcp_read(dig_port,
1598 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1599 rx_status,
1600 HDCP_2_2_HDMI_RXSTATUS_LEN);
1601 }
1602
get_hdcp2_msg_timeout(u8 msg_id,bool is_paired)1603 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1604 {
1605 int i;
1606
1607 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1608 if (is_paired)
1609 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1610 else
1611 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1612 }
1613
1614 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1615 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1616 return hdcp2_msg_timeout[i].timeout;
1617 }
1618
1619 return -EINVAL;
1620 }
1621
1622 static int
hdcp2_detect_msg_availability(struct intel_digital_port * dig_port,u8 msg_id,bool * msg_ready,ssize_t * msg_sz)1623 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1624 u8 msg_id, bool *msg_ready,
1625 ssize_t *msg_sz)
1626 {
1627 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1628 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1629 int ret;
1630
1631 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1632 if (ret < 0) {
1633 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1634 ret);
1635 return ret;
1636 }
1637
1638 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1639 rx_status[0]);
1640
1641 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1642 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1643 *msg_sz);
1644 else
1645 *msg_ready = *msg_sz;
1646
1647 return 0;
1648 }
1649
1650 static ssize_t
intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port * dig_port,u8 msg_id,bool paired)1651 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1652 u8 msg_id, bool paired)
1653 {
1654 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1655 bool msg_ready = false;
1656 int timeout, ret;
1657 ssize_t msg_sz = 0;
1658
1659 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1660 if (timeout < 0)
1661 return timeout;
1662
1663 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1664 msg_id, &msg_ready,
1665 &msg_sz),
1666 !ret && msg_ready && msg_sz, timeout * 1000,
1667 1000, 5 * 1000);
1668 if (ret)
1669 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1670 msg_id, ret, timeout);
1671
1672 return ret ? ret : msg_sz;
1673 }
1674
1675 static
intel_hdmi_hdcp2_write_msg(struct intel_digital_port * dig_port,void * buf,size_t size)1676 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1677 void *buf, size_t size)
1678 {
1679 unsigned int offset;
1680
1681 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1682 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1683 }
1684
1685 static
intel_hdmi_hdcp2_read_msg(struct intel_digital_port * dig_port,u8 msg_id,void * buf,size_t size)1686 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1687 u8 msg_id, void *buf, size_t size)
1688 {
1689 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1690 struct intel_hdmi *hdmi = &dig_port->hdmi;
1691 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1692 unsigned int offset;
1693 ssize_t ret;
1694
1695 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1696 hdcp->is_paired);
1697 if (ret < 0)
1698 return ret;
1699
1700 /*
1701 * Available msg size should be equal to or lesser than the
1702 * available buffer.
1703 */
1704 if (ret > size) {
1705 drm_dbg_kms(&i915->drm,
1706 "msg_sz(%zd) is more than exp size(%zu)\n",
1707 ret, size);
1708 return -EINVAL;
1709 }
1710
1711 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1712 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1713 if (ret)
1714 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1715 msg_id, ret);
1716
1717 return ret;
1718 }
1719
1720 static
intel_hdmi_hdcp2_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)1721 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1722 struct intel_connector *connector)
1723 {
1724 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1725 int ret;
1726
1727 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1728 if (ret)
1729 return ret;
1730
1731 /*
1732 * Re-auth request and Link Integrity Failures are represented by
1733 * same bit. i.e reauth_req.
1734 */
1735 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1736 ret = HDCP_REAUTH_REQUEST;
1737 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1738 ret = HDCP_TOPOLOGY_CHANGE;
1739
1740 return ret;
1741 }
1742
1743 static
intel_hdmi_hdcp2_capable(struct intel_digital_port * dig_port,bool * capable)1744 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1745 bool *capable)
1746 {
1747 u8 hdcp2_version;
1748 int ret;
1749
1750 *capable = false;
1751 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1752 &hdcp2_version, sizeof(hdcp2_version));
1753 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1754 *capable = true;
1755
1756 return ret;
1757 }
1758
1759 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1760 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1761 .read_bksv = intel_hdmi_hdcp_read_bksv,
1762 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1763 .repeater_present = intel_hdmi_hdcp_repeater_present,
1764 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1765 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1766 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1767 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1768 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1769 .check_link = intel_hdmi_hdcp_check_link,
1770 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1771 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1772 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1773 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1774 .protocol = HDCP_PROTOCOL_HDMI,
1775 };
1776
intel_hdmi_source_max_tmds_clock(struct intel_encoder * encoder)1777 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1778 {
1779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1780 int max_tmds_clock, vbt_max_tmds_clock;
1781
1782 if (DISPLAY_VER(dev_priv) >= 10)
1783 max_tmds_clock = 594000;
1784 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1785 max_tmds_clock = 300000;
1786 else if (DISPLAY_VER(dev_priv) >= 5)
1787 max_tmds_clock = 225000;
1788 else
1789 max_tmds_clock = 165000;
1790
1791 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1792 if (vbt_max_tmds_clock)
1793 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1794
1795 return max_tmds_clock;
1796 }
1797
intel_has_hdmi_sink(struct intel_hdmi * hdmi,const struct drm_connector_state * conn_state)1798 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1799 const struct drm_connector_state *conn_state)
1800 {
1801 return hdmi->has_hdmi_sink &&
1802 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1803 }
1804
intel_hdmi_is_ycbcr420(const struct intel_crtc_state * crtc_state)1805 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1806 {
1807 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1808 }
1809
hdmi_port_clock_limit(struct intel_hdmi * hdmi,bool respect_downstream_limits,bool has_hdmi_sink)1810 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1811 bool respect_downstream_limits,
1812 bool has_hdmi_sink)
1813 {
1814 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1815 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1816
1817 if (respect_downstream_limits) {
1818 struct intel_connector *connector = hdmi->attached_connector;
1819 const struct drm_display_info *info = &connector->base.display_info;
1820
1821 if (hdmi->dp_dual_mode.max_tmds_clock)
1822 max_tmds_clock = min(max_tmds_clock,
1823 hdmi->dp_dual_mode.max_tmds_clock);
1824
1825 if (info->max_tmds_clock)
1826 max_tmds_clock = min(max_tmds_clock,
1827 info->max_tmds_clock);
1828 else if (!has_hdmi_sink)
1829 max_tmds_clock = min(max_tmds_clock, 165000);
1830 }
1831
1832 return max_tmds_clock;
1833 }
1834
1835 static enum drm_mode_status
hdmi_port_clock_valid(struct intel_hdmi * hdmi,int clock,bool respect_downstream_limits,bool has_hdmi_sink)1836 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1837 int clock, bool respect_downstream_limits,
1838 bool has_hdmi_sink)
1839 {
1840 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1841 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1842
1843 if (clock < 25000)
1844 return MODE_CLOCK_LOW;
1845 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1846 has_hdmi_sink))
1847 return MODE_CLOCK_HIGH;
1848
1849 /* GLK DPLL can't generate 446-480 MHz */
1850 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1851 return MODE_CLOCK_RANGE;
1852
1853 /* BXT/GLK DPLL can't generate 223-240 MHz */
1854 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1855 clock > 223333 && clock < 240000)
1856 return MODE_CLOCK_RANGE;
1857
1858 /* CHV DPLL can't generate 216-240 MHz */
1859 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1860 return MODE_CLOCK_RANGE;
1861
1862 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1863 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1864 return MODE_CLOCK_RANGE;
1865
1866 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1867 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1868 return MODE_CLOCK_RANGE;
1869
1870 /*
1871 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1872 * set of link rates.
1873 *
1874 * FIXME: We will hopefully get an algorithmic way of programming
1875 * the MPLLB for HDMI in the future.
1876 */
1877 if (IS_DG2(dev_priv))
1878 return intel_snps_phy_check_hdmi_link_rate(clock);
1879
1880 return MODE_OK;
1881 }
1882
intel_hdmi_tmds_clock(int clock,int bpc,bool ycbcr420_output)1883 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1884 {
1885 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1886 if (ycbcr420_output)
1887 clock /= 2;
1888
1889 /*
1890 * Need to adjust the port link by:
1891 * 1.5x for 12bpc
1892 * 1.25x for 10bpc
1893 */
1894 return clock * bpc / 8;
1895 }
1896
intel_hdmi_source_bpc_possible(struct drm_i915_private * i915,int bpc)1897 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1898 {
1899 switch (bpc) {
1900 case 12:
1901 return !HAS_GMCH(i915);
1902 case 10:
1903 return DISPLAY_VER(i915) >= 11;
1904 case 8:
1905 return true;
1906 default:
1907 MISSING_CASE(bpc);
1908 return false;
1909 }
1910 }
1911
intel_hdmi_sink_bpc_possible(struct drm_connector * connector,int bpc,bool has_hdmi_sink,bool ycbcr420_output)1912 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1913 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1914 {
1915 const struct drm_display_info *info = &connector->display_info;
1916 const struct drm_hdmi_info *hdmi = &info->hdmi;
1917
1918 switch (bpc) {
1919 case 12:
1920 if (!has_hdmi_sink)
1921 return false;
1922
1923 if (ycbcr420_output)
1924 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1925 else
1926 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1927 case 10:
1928 if (!has_hdmi_sink)
1929 return false;
1930
1931 if (ycbcr420_output)
1932 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1933 else
1934 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1935 case 8:
1936 return true;
1937 default:
1938 MISSING_CASE(bpc);
1939 return false;
1940 }
1941 }
1942
1943 static enum drm_mode_status
intel_hdmi_mode_clock_valid(struct drm_connector * connector,int clock,bool has_hdmi_sink,bool ycbcr420_output)1944 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1945 bool has_hdmi_sink, bool ycbcr420_output)
1946 {
1947 struct drm_i915_private *i915 = to_i915(connector->dev);
1948 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1949 enum drm_mode_status status = MODE_OK;
1950 int bpc;
1951
1952 /*
1953 * Try all color depths since valid port clock range
1954 * can have holes. Any mode that can be used with at
1955 * least one color depth is accepted.
1956 */
1957 for (bpc = 12; bpc >= 8; bpc -= 2) {
1958 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1959
1960 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1961 continue;
1962
1963 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1964 continue;
1965
1966 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1967 if (status == MODE_OK)
1968 return MODE_OK;
1969 }
1970
1971 /* can never happen */
1972 drm_WARN_ON(&i915->drm, status == MODE_OK);
1973
1974 return status;
1975 }
1976
1977 static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1978 intel_hdmi_mode_valid(struct drm_connector *connector,
1979 struct drm_display_mode *mode)
1980 {
1981 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1982 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1983 enum drm_mode_status status;
1984 int clock = mode->clock;
1985 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1986 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1987 bool ycbcr_420_only;
1988
1989 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1990 return MODE_NO_DBLESCAN;
1991
1992 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1993 clock *= 2;
1994
1995 if (clock > max_dotclk)
1996 return MODE_CLOCK_HIGH;
1997
1998 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1999 if (!has_hdmi_sink)
2000 return MODE_CLOCK_LOW;
2001 clock *= 2;
2002 }
2003
2004 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2005
2006 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2007 if (status != MODE_OK) {
2008 if (ycbcr_420_only ||
2009 !connector->ycbcr_420_allowed ||
2010 !drm_mode_is_420_also(&connector->display_info, mode))
2011 return status;
2012
2013 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2014 if (status != MODE_OK)
2015 return status;
2016 }
2017
2018 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2019 }
2020
intel_hdmi_bpc_possible(const struct intel_crtc_state * crtc_state,int bpc,bool has_hdmi_sink,bool ycbcr420_output)2021 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2022 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2023 {
2024 struct drm_atomic_state *state = crtc_state->uapi.state;
2025 struct drm_connector_state *connector_state;
2026 struct drm_connector *connector;
2027 int i;
2028
2029 for_each_new_connector_in_state(state, connector, connector_state, i) {
2030 if (connector_state->crtc != crtc_state->uapi.crtc)
2031 continue;
2032
2033 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2034 return false;
2035 }
2036
2037 return true;
2038 }
2039
hdmi_bpc_possible(const struct intel_crtc_state * crtc_state,int bpc)2040 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2041 {
2042 struct drm_i915_private *dev_priv =
2043 to_i915(crtc_state->uapi.crtc->dev);
2044 const struct drm_display_mode *adjusted_mode =
2045 &crtc_state->hw.adjusted_mode;
2046
2047 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2048 return false;
2049
2050 /*
2051 * HDMI deep color affects the clocks, so it's only possible
2052 * when not cloning with other encoder types.
2053 */
2054 if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2055 return false;
2056
2057 /* Display Wa_1405510057:icl,ehl */
2058 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2059 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2060 (adjusted_mode->crtc_hblank_end -
2061 adjusted_mode->crtc_hblank_start) % 8 == 2)
2062 return false;
2063
2064 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2065 intel_hdmi_is_ycbcr420(crtc_state));
2066 }
2067
intel_hdmi_compute_bpc(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,int clock,bool respect_downstream_limits)2068 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2069 struct intel_crtc_state *crtc_state,
2070 int clock, bool respect_downstream_limits)
2071 {
2072 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2073 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2074 int bpc;
2075
2076 /*
2077 * pipe_bpp could already be below 8bpc due to FDI
2078 * bandwidth constraints. HDMI minimum is 8bpc however.
2079 */
2080 bpc = max(crtc_state->pipe_bpp / 3, 8);
2081
2082 /*
2083 * We will never exceed downstream TMDS clock limits while
2084 * attempting deep color. If the user insists on forcing an
2085 * out of spec mode they will have to be satisfied with 8bpc.
2086 */
2087 if (!respect_downstream_limits)
2088 bpc = 8;
2089
2090 for (; bpc >= 8; bpc -= 2) {
2091 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2092
2093 if (hdmi_bpc_possible(crtc_state, bpc) &&
2094 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2095 respect_downstream_limits,
2096 crtc_state->has_hdmi_sink) == MODE_OK)
2097 return bpc;
2098 }
2099
2100 return -EINVAL;
2101 }
2102
intel_hdmi_compute_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,bool respect_downstream_limits)2103 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2104 struct intel_crtc_state *crtc_state,
2105 bool respect_downstream_limits)
2106 {
2107 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2108 const struct drm_display_mode *adjusted_mode =
2109 &crtc_state->hw.adjusted_mode;
2110 int bpc, clock = adjusted_mode->crtc_clock;
2111
2112 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2113 clock *= 2;
2114
2115 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2116 respect_downstream_limits);
2117 if (bpc < 0)
2118 return bpc;
2119
2120 crtc_state->port_clock =
2121 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2122
2123 /*
2124 * pipe_bpp could already be below 8bpc due to
2125 * FDI bandwidth constraints. We shouldn't bump it
2126 * back up to the HDMI minimum 8bpc in that case.
2127 */
2128 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2129
2130 drm_dbg_kms(&i915->drm,
2131 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2132 bpc, crtc_state->pipe_bpp);
2133
2134 return 0;
2135 }
2136
intel_hdmi_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2137 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2138 const struct drm_connector_state *conn_state)
2139 {
2140 const struct intel_digital_connector_state *intel_conn_state =
2141 to_intel_digital_connector_state(conn_state);
2142 const struct drm_display_mode *adjusted_mode =
2143 &crtc_state->hw.adjusted_mode;
2144
2145 /*
2146 * Our YCbCr output is always limited range.
2147 * crtc_state->limited_color_range only applies to RGB,
2148 * and it must never be set for YCbCr or we risk setting
2149 * some conflicting bits in PIPECONF which will mess up
2150 * the colors on the monitor.
2151 */
2152 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2153 return false;
2154
2155 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2156 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2157 return crtc_state->has_hdmi_sink &&
2158 drm_default_rgb_quant_range(adjusted_mode) ==
2159 HDMI_QUANTIZATION_RANGE_LIMITED;
2160 } else {
2161 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2162 }
2163 }
2164
intel_hdmi_has_audio(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2165 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2166 const struct intel_crtc_state *crtc_state,
2167 const struct drm_connector_state *conn_state)
2168 {
2169 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2170 const struct intel_digital_connector_state *intel_conn_state =
2171 to_intel_digital_connector_state(conn_state);
2172
2173 if (!crtc_state->has_hdmi_sink)
2174 return false;
2175
2176 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2177 return intel_hdmi->has_audio;
2178 else
2179 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2180 }
2181
2182 static enum intel_output_format
intel_hdmi_output_format(struct intel_connector * connector,bool ycbcr_420_output)2183 intel_hdmi_output_format(struct intel_connector *connector,
2184 bool ycbcr_420_output)
2185 {
2186 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2187 return INTEL_OUTPUT_FORMAT_YCBCR420;
2188 else
2189 return INTEL_OUTPUT_FORMAT_RGB;
2190 }
2191
intel_hdmi_compute_output_format(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,bool respect_downstream_limits)2192 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2193 struct intel_crtc_state *crtc_state,
2194 const struct drm_connector_state *conn_state,
2195 bool respect_downstream_limits)
2196 {
2197 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2198 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2199 const struct drm_display_info *info = &connector->base.display_info;
2200 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2201 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2202 int ret;
2203
2204 crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
2205
2206 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2207 drm_dbg_kms(&i915->drm,
2208 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2209 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2210 }
2211
2212 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2213 if (ret) {
2214 if (intel_hdmi_is_ycbcr420(crtc_state) ||
2215 !connector->base.ycbcr_420_allowed ||
2216 !drm_mode_is_420_also(info, adjusted_mode))
2217 return ret;
2218
2219 crtc_state->output_format = intel_hdmi_output_format(connector, true);
2220 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2221 }
2222
2223 return ret;
2224 }
2225
intel_hdmi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)2226 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2227 struct intel_crtc_state *pipe_config,
2228 struct drm_connector_state *conn_state)
2229 {
2230 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2231 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2232 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2233 struct drm_connector *connector = conn_state->connector;
2234 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2235 int ret;
2236
2237 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2238 return -EINVAL;
2239
2240 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2241 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2242 conn_state);
2243
2244 if (pipe_config->has_hdmi_sink)
2245 pipe_config->has_infoframe = true;
2246
2247 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2248 pipe_config->pixel_multiplier = 2;
2249
2250 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2251 pipe_config->has_pch_encoder = true;
2252
2253 pipe_config->has_audio =
2254 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2255
2256 /*
2257 * Try to respect downstream TMDS clock limits first, if
2258 * that fails assume the user might know something we don't.
2259 */
2260 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2261 if (ret)
2262 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2263 if (ret) {
2264 drm_dbg_kms(&dev_priv->drm,
2265 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2266 pipe_config->hw.adjusted_mode.crtc_clock);
2267 return ret;
2268 }
2269
2270 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2271 ret = intel_panel_fitting(pipe_config, conn_state);
2272 if (ret)
2273 return ret;
2274 }
2275
2276 pipe_config->limited_color_range =
2277 intel_hdmi_limited_color_range(pipe_config, conn_state);
2278
2279 if (conn_state->picture_aspect_ratio)
2280 adjusted_mode->picture_aspect_ratio =
2281 conn_state->picture_aspect_ratio;
2282
2283 pipe_config->lane_count = 4;
2284
2285 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2286 if (scdc->scrambling.low_rates)
2287 pipe_config->hdmi_scrambling = true;
2288
2289 if (pipe_config->port_clock > 340000) {
2290 pipe_config->hdmi_scrambling = true;
2291 pipe_config->hdmi_high_tmds_clock_ratio = true;
2292 }
2293 }
2294
2295 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2296 conn_state);
2297
2298 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2299 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2300 return -EINVAL;
2301 }
2302
2303 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2304 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2305 return -EINVAL;
2306 }
2307
2308 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2309 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2310 return -EINVAL;
2311 }
2312
2313 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2314 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2315 return -EINVAL;
2316 }
2317
2318 return 0;
2319 }
2320
intel_hdmi_encoder_shutdown(struct intel_encoder * encoder)2321 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2322 {
2323 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2324
2325 /*
2326 * Give a hand to buggy BIOSen which forget to turn
2327 * the TMDS output buffers back on after a reboot.
2328 */
2329 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2330 }
2331
2332 static void
intel_hdmi_unset_edid(struct drm_connector * connector)2333 intel_hdmi_unset_edid(struct drm_connector *connector)
2334 {
2335 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2336
2337 intel_hdmi->has_hdmi_sink = false;
2338 intel_hdmi->has_audio = false;
2339
2340 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2341 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2342
2343 kfree(to_intel_connector(connector)->detect_edid);
2344 to_intel_connector(connector)->detect_edid = NULL;
2345 }
2346
2347 static void
intel_hdmi_dp_dual_mode_detect(struct drm_connector * connector,bool has_edid)2348 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2349 {
2350 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2351 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2352 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2353 struct i2c_adapter *adapter =
2354 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2355 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2356
2357 /*
2358 * Type 1 DVI adaptors are not required to implement any
2359 * registers, so we can't always detect their presence.
2360 * Ideally we should be able to check the state of the
2361 * CONFIG1 pin, but no such luck on our hardware.
2362 *
2363 * The only method left to us is to check the VBT to see
2364 * if the port is a dual mode capable DP port. But let's
2365 * only do that when we sucesfully read the EDID, to avoid
2366 * confusing log messages about DP dual mode adaptors when
2367 * there's nothing connected to the port.
2368 */
2369 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2370 /* An overridden EDID imply that we want this port for testing.
2371 * Make sure not to set limits for that port.
2372 */
2373 if (has_edid && !connector->override_edid &&
2374 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2375 drm_dbg_kms(&dev_priv->drm,
2376 "Assuming DP dual mode adaptor presence based on VBT\n");
2377 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2378 } else {
2379 type = DRM_DP_DUAL_MODE_NONE;
2380 }
2381 }
2382
2383 if (type == DRM_DP_DUAL_MODE_NONE)
2384 return;
2385
2386 hdmi->dp_dual_mode.type = type;
2387 hdmi->dp_dual_mode.max_tmds_clock =
2388 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2389
2390 drm_dbg_kms(&dev_priv->drm,
2391 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2392 drm_dp_get_dual_mode_type_name(type),
2393 hdmi->dp_dual_mode.max_tmds_clock);
2394
2395 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2396 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2397 !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2398 drm_dbg_kms(&dev_priv->drm,
2399 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2400 hdmi->dp_dual_mode.max_tmds_clock = 0;
2401 }
2402 }
2403
2404 static bool
intel_hdmi_set_edid(struct drm_connector * connector)2405 intel_hdmi_set_edid(struct drm_connector *connector)
2406 {
2407 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2408 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2409 intel_wakeref_t wakeref;
2410 struct edid *edid;
2411 bool connected = false;
2412 struct i2c_adapter *i2c;
2413
2414 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2415
2416 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2417
2418 edid = drm_get_edid(connector, i2c);
2419
2420 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2421 drm_dbg_kms(&dev_priv->drm,
2422 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2423 intel_gmbus_force_bit(i2c, true);
2424 edid = drm_get_edid(connector, i2c);
2425 intel_gmbus_force_bit(i2c, false);
2426 }
2427
2428 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2429
2430 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2431
2432 to_intel_connector(connector)->detect_edid = edid;
2433 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2434 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2435 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2436
2437 connected = true;
2438 }
2439
2440 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2441
2442 return connected;
2443 }
2444
2445 static enum drm_connector_status
intel_hdmi_detect(struct drm_connector * connector,bool force)2446 intel_hdmi_detect(struct drm_connector *connector, bool force)
2447 {
2448 enum drm_connector_status status = connector_status_disconnected;
2449 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2450 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2451 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2452 intel_wakeref_t wakeref;
2453
2454 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2455 connector->base.id, connector->name);
2456
2457 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2458 return connector_status_disconnected;
2459
2460 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2461
2462 if (DISPLAY_VER(dev_priv) >= 11 &&
2463 !intel_digital_port_connected(encoder))
2464 goto out;
2465
2466 intel_hdmi_unset_edid(connector);
2467
2468 if (intel_hdmi_set_edid(connector))
2469 status = connector_status_connected;
2470
2471 out:
2472 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2473
2474 if (status != connector_status_connected)
2475 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2476
2477 /*
2478 * Make sure the refs for power wells enabled during detect are
2479 * dropped to avoid a new detect cycle triggered by HPD polling.
2480 */
2481 intel_display_power_flush_work(dev_priv);
2482
2483 return status;
2484 }
2485
2486 static void
intel_hdmi_force(struct drm_connector * connector)2487 intel_hdmi_force(struct drm_connector *connector)
2488 {
2489 struct drm_i915_private *i915 = to_i915(connector->dev);
2490
2491 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2492 connector->base.id, connector->name);
2493
2494 intel_hdmi_unset_edid(connector);
2495
2496 if (connector->status != connector_status_connected)
2497 return;
2498
2499 intel_hdmi_set_edid(connector);
2500 }
2501
intel_hdmi_get_modes(struct drm_connector * connector)2502 static int intel_hdmi_get_modes(struct drm_connector *connector)
2503 {
2504 struct edid *edid;
2505
2506 edid = to_intel_connector(connector)->detect_edid;
2507 if (edid == NULL)
2508 return 0;
2509
2510 return intel_connector_update_modes(connector, edid);
2511 }
2512
2513 static struct i2c_adapter *
intel_hdmi_get_i2c_adapter(struct drm_connector * connector)2514 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2515 {
2516 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2517 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2518
2519 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2520 }
2521
intel_hdmi_create_i2c_symlink(struct drm_connector * connector)2522 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2523 {
2524 struct drm_i915_private *i915 = to_i915(connector->dev);
2525 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2526 struct kobject *i2c_kobj = &adapter->dev.kobj;
2527 struct kobject *connector_kobj = &connector->kdev->kobj;
2528 int ret;
2529
2530 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2531 if (ret)
2532 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2533 }
2534
intel_hdmi_remove_i2c_symlink(struct drm_connector * connector)2535 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2536 {
2537 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2538 struct kobject *i2c_kobj = &adapter->dev.kobj;
2539 struct kobject *connector_kobj = &connector->kdev->kobj;
2540
2541 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2542 }
2543
2544 static int
intel_hdmi_connector_register(struct drm_connector * connector)2545 intel_hdmi_connector_register(struct drm_connector *connector)
2546 {
2547 int ret;
2548
2549 ret = intel_connector_register(connector);
2550 if (ret)
2551 return ret;
2552
2553 intel_hdmi_create_i2c_symlink(connector);
2554
2555 return ret;
2556 }
2557
intel_hdmi_connector_unregister(struct drm_connector * connector)2558 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2559 {
2560 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2561
2562 cec_notifier_conn_unregister(n);
2563
2564 intel_hdmi_remove_i2c_symlink(connector);
2565 intel_connector_unregister(connector);
2566 }
2567
2568 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2569 .detect = intel_hdmi_detect,
2570 .force = intel_hdmi_force,
2571 .fill_modes = drm_helper_probe_single_connector_modes,
2572 .atomic_get_property = intel_digital_connector_atomic_get_property,
2573 .atomic_set_property = intel_digital_connector_atomic_set_property,
2574 .late_register = intel_hdmi_connector_register,
2575 .early_unregister = intel_hdmi_connector_unregister,
2576 .destroy = intel_connector_destroy,
2577 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2578 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2579 };
2580
2581 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2582 .get_modes = intel_hdmi_get_modes,
2583 .mode_valid = intel_hdmi_mode_valid,
2584 .atomic_check = intel_digital_connector_atomic_check,
2585 };
2586
2587 static void
intel_hdmi_add_properties(struct intel_hdmi * intel_hdmi,struct drm_connector * connector)2588 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2589 {
2590 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2591
2592 intel_attach_force_audio_property(connector);
2593 intel_attach_broadcast_rgb_property(connector);
2594 intel_attach_aspect_ratio_property(connector);
2595
2596 intel_attach_hdmi_colorspace_property(connector);
2597 drm_connector_attach_content_type_property(connector);
2598
2599 if (DISPLAY_VER(dev_priv) >= 10)
2600 drm_connector_attach_hdr_output_metadata_property(connector);
2601
2602 if (!HAS_GMCH(dev_priv))
2603 drm_connector_attach_max_bpc_property(connector, 8, 12);
2604 }
2605
2606 /*
2607 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2608 * @encoder: intel_encoder
2609 * @connector: drm_connector
2610 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2611 * or reset the high tmds clock ratio for scrambling
2612 * @scrambling: bool to Indicate if the function needs to set or reset
2613 * sink scrambling
2614 *
2615 * This function handles scrambling on HDMI 2.0 capable sinks.
2616 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2617 * it enables scrambling. This should be called before enabling the HDMI
2618 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2619 * detect a scrambled clock within 100 ms.
2620 *
2621 * Returns:
2622 * True on success, false on failure.
2623 */
intel_hdmi_handle_sink_scrambling(struct intel_encoder * encoder,struct drm_connector * connector,bool high_tmds_clock_ratio,bool scrambling)2624 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2625 struct drm_connector *connector,
2626 bool high_tmds_clock_ratio,
2627 bool scrambling)
2628 {
2629 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2630 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2631 struct drm_scrambling *sink_scrambling =
2632 &connector->display_info.hdmi.scdc.scrambling;
2633 struct i2c_adapter *adapter =
2634 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2635
2636 if (!sink_scrambling->supported)
2637 return true;
2638
2639 drm_dbg_kms(&dev_priv->drm,
2640 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2641 connector->base.id, connector->name,
2642 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2643
2644 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2645 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2646 high_tmds_clock_ratio) &&
2647 drm_scdc_set_scrambling(adapter, scrambling);
2648 }
2649
chv_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2650 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2651 {
2652 u8 ddc_pin;
2653
2654 switch (port) {
2655 case PORT_B:
2656 ddc_pin = GMBUS_PIN_DPB;
2657 break;
2658 case PORT_C:
2659 ddc_pin = GMBUS_PIN_DPC;
2660 break;
2661 case PORT_D:
2662 ddc_pin = GMBUS_PIN_DPD_CHV;
2663 break;
2664 default:
2665 MISSING_CASE(port);
2666 ddc_pin = GMBUS_PIN_DPB;
2667 break;
2668 }
2669 return ddc_pin;
2670 }
2671
bxt_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2672 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2673 {
2674 u8 ddc_pin;
2675
2676 switch (port) {
2677 case PORT_B:
2678 ddc_pin = GMBUS_PIN_1_BXT;
2679 break;
2680 case PORT_C:
2681 ddc_pin = GMBUS_PIN_2_BXT;
2682 break;
2683 default:
2684 MISSING_CASE(port);
2685 ddc_pin = GMBUS_PIN_1_BXT;
2686 break;
2687 }
2688 return ddc_pin;
2689 }
2690
cnp_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2691 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2692 enum port port)
2693 {
2694 u8 ddc_pin;
2695
2696 switch (port) {
2697 case PORT_B:
2698 ddc_pin = GMBUS_PIN_1_BXT;
2699 break;
2700 case PORT_C:
2701 ddc_pin = GMBUS_PIN_2_BXT;
2702 break;
2703 case PORT_D:
2704 ddc_pin = GMBUS_PIN_4_CNP;
2705 break;
2706 case PORT_F:
2707 ddc_pin = GMBUS_PIN_3_BXT;
2708 break;
2709 default:
2710 MISSING_CASE(port);
2711 ddc_pin = GMBUS_PIN_1_BXT;
2712 break;
2713 }
2714 return ddc_pin;
2715 }
2716
icl_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2717 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2718 {
2719 enum phy phy = intel_port_to_phy(dev_priv, port);
2720
2721 if (intel_phy_is_combo(dev_priv, phy))
2722 return GMBUS_PIN_1_BXT + port;
2723 else if (intel_phy_is_tc(dev_priv, phy))
2724 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2725
2726 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2727 return GMBUS_PIN_2_BXT;
2728 }
2729
mcc_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2730 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2731 {
2732 enum phy phy = intel_port_to_phy(dev_priv, port);
2733 u8 ddc_pin;
2734
2735 switch (phy) {
2736 case PHY_A:
2737 ddc_pin = GMBUS_PIN_1_BXT;
2738 break;
2739 case PHY_B:
2740 ddc_pin = GMBUS_PIN_2_BXT;
2741 break;
2742 case PHY_C:
2743 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2744 break;
2745 default:
2746 MISSING_CASE(phy);
2747 ddc_pin = GMBUS_PIN_1_BXT;
2748 break;
2749 }
2750 return ddc_pin;
2751 }
2752
rkl_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2753 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2754 {
2755 enum phy phy = intel_port_to_phy(dev_priv, port);
2756
2757 WARN_ON(port == PORT_C);
2758
2759 /*
2760 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2761 * final two outputs use type-c pins, even though they're actually
2762 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2763 * all outputs.
2764 */
2765 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2766 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2767
2768 return GMBUS_PIN_1_BXT + phy;
2769 }
2770
gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private * i915,enum port port)2771 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2772 {
2773 enum phy phy = intel_port_to_phy(i915, port);
2774
2775 drm_WARN_ON(&i915->drm, port == PORT_A);
2776
2777 /*
2778 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2779 * final two outputs use type-c pins, even though they're actually
2780 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2781 * all outputs.
2782 */
2783 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2784 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2785
2786 return GMBUS_PIN_1_BXT + phy;
2787 }
2788
dg1_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2789 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2790 {
2791 return intel_port_to_phy(dev_priv, port) + 1;
2792 }
2793
adls_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2794 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2795 {
2796 enum phy phy = intel_port_to_phy(dev_priv, port);
2797
2798 WARN_ON(port == PORT_B || port == PORT_C);
2799
2800 /*
2801 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2802 * except first combo output.
2803 */
2804 if (phy == PHY_A)
2805 return GMBUS_PIN_1_BXT;
2806
2807 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2808 }
2809
g4x_port_to_ddc_pin(struct drm_i915_private * dev_priv,enum port port)2810 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2811 enum port port)
2812 {
2813 u8 ddc_pin;
2814
2815 switch (port) {
2816 case PORT_B:
2817 ddc_pin = GMBUS_PIN_DPB;
2818 break;
2819 case PORT_C:
2820 ddc_pin = GMBUS_PIN_DPC;
2821 break;
2822 case PORT_D:
2823 ddc_pin = GMBUS_PIN_DPD;
2824 break;
2825 default:
2826 MISSING_CASE(port);
2827 ddc_pin = GMBUS_PIN_DPB;
2828 break;
2829 }
2830 return ddc_pin;
2831 }
2832
intel_hdmi_ddc_pin(struct intel_encoder * encoder)2833 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2834 {
2835 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2836 enum port port = encoder->port;
2837 u8 ddc_pin;
2838
2839 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2840 if (ddc_pin) {
2841 drm_dbg_kms(&dev_priv->drm,
2842 "Using DDC pin 0x%x for port %c (VBT)\n",
2843 ddc_pin, port_name(port));
2844 return ddc_pin;
2845 }
2846
2847 if (IS_ALDERLAKE_S(dev_priv))
2848 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2849 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2850 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2851 else if (IS_ROCKETLAKE(dev_priv))
2852 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2853 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2854 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2855 else if (HAS_PCH_MCC(dev_priv))
2856 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2857 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2858 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2859 else if (HAS_PCH_CNP(dev_priv))
2860 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2861 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2862 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2863 else if (IS_CHERRYVIEW(dev_priv))
2864 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2865 else
2866 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2867
2868 drm_dbg_kms(&dev_priv->drm,
2869 "Using DDC pin 0x%x for port %c (platform default)\n",
2870 ddc_pin, port_name(port));
2871
2872 return ddc_pin;
2873 }
2874
intel_infoframe_init(struct intel_digital_port * dig_port)2875 void intel_infoframe_init(struct intel_digital_port *dig_port)
2876 {
2877 struct drm_i915_private *dev_priv =
2878 to_i915(dig_port->base.base.dev);
2879
2880 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2881 dig_port->write_infoframe = vlv_write_infoframe;
2882 dig_port->read_infoframe = vlv_read_infoframe;
2883 dig_port->set_infoframes = vlv_set_infoframes;
2884 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2885 } else if (IS_G4X(dev_priv)) {
2886 dig_port->write_infoframe = g4x_write_infoframe;
2887 dig_port->read_infoframe = g4x_read_infoframe;
2888 dig_port->set_infoframes = g4x_set_infoframes;
2889 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2890 } else if (HAS_DDI(dev_priv)) {
2891 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2892 dig_port->write_infoframe = lspcon_write_infoframe;
2893 dig_port->read_infoframe = lspcon_read_infoframe;
2894 dig_port->set_infoframes = lspcon_set_infoframes;
2895 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2896 } else {
2897 dig_port->write_infoframe = hsw_write_infoframe;
2898 dig_port->read_infoframe = hsw_read_infoframe;
2899 dig_port->set_infoframes = hsw_set_infoframes;
2900 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2901 }
2902 } else if (HAS_PCH_IBX(dev_priv)) {
2903 dig_port->write_infoframe = ibx_write_infoframe;
2904 dig_port->read_infoframe = ibx_read_infoframe;
2905 dig_port->set_infoframes = ibx_set_infoframes;
2906 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2907 } else {
2908 dig_port->write_infoframe = cpt_write_infoframe;
2909 dig_port->read_infoframe = cpt_read_infoframe;
2910 dig_port->set_infoframes = cpt_set_infoframes;
2911 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2912 }
2913 }
2914
intel_hdmi_init_connector(struct intel_digital_port * dig_port,struct intel_connector * intel_connector)2915 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2916 struct intel_connector *intel_connector)
2917 {
2918 struct drm_connector *connector = &intel_connector->base;
2919 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2920 struct intel_encoder *intel_encoder = &dig_port->base;
2921 struct drm_device *dev = intel_encoder->base.dev;
2922 struct drm_i915_private *dev_priv = to_i915(dev);
2923 struct i2c_adapter *ddc;
2924 enum port port = intel_encoder->port;
2925 struct cec_connector_info conn_info;
2926
2927 drm_dbg_kms(&dev_priv->drm,
2928 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2929 intel_encoder->base.base.id, intel_encoder->base.name);
2930
2931 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2932 return;
2933
2934 if (drm_WARN(dev, dig_port->max_lanes < 4,
2935 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2936 dig_port->max_lanes, intel_encoder->base.base.id,
2937 intel_encoder->base.name))
2938 return;
2939
2940 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2941 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2942
2943 drm_connector_init_with_ddc(dev, connector,
2944 &intel_hdmi_connector_funcs,
2945 DRM_MODE_CONNECTOR_HDMIA,
2946 ddc);
2947 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2948
2949 connector->interlace_allowed = 1;
2950 connector->doublescan_allowed = 0;
2951 connector->stereo_allowed = 1;
2952
2953 if (DISPLAY_VER(dev_priv) >= 10)
2954 connector->ycbcr_420_allowed = true;
2955
2956 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2957
2958 if (HAS_DDI(dev_priv))
2959 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2960 else
2961 intel_connector->get_hw_state = intel_connector_get_hw_state;
2962
2963 intel_hdmi_add_properties(intel_hdmi, connector);
2964
2965 intel_connector_attach_encoder(intel_connector, intel_encoder);
2966 intel_hdmi->attached_connector = intel_connector;
2967
2968 if (is_hdcp_supported(dev_priv, port)) {
2969 int ret = intel_hdcp_init(intel_connector, dig_port,
2970 &intel_hdmi_hdcp_shim);
2971 if (ret)
2972 drm_dbg_kms(&dev_priv->drm,
2973 "HDCP init failed, skipping.\n");
2974 }
2975
2976 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2977 * 0xd. Failure to do so will result in spurious interrupts being
2978 * generated on the port when a cable is not attached.
2979 */
2980 if (IS_G45(dev_priv)) {
2981 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2982 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2983 (temp & ~0xf) | 0xd);
2984 }
2985
2986 cec_fill_conn_info_from_drm(&conn_info, connector);
2987
2988 intel_hdmi->cec_notifier =
2989 cec_notifier_conn_register(dev->dev, port_identifier(port),
2990 &conn_info);
2991 if (!intel_hdmi->cec_notifier)
2992 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2993 }
2994
2995 /*
2996 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2997 * @vactive: Vactive of a display mode
2998 *
2999 * @return: appropriate dsc slice height for a given mode.
3000 */
intel_hdmi_dsc_get_slice_height(int vactive)3001 int intel_hdmi_dsc_get_slice_height(int vactive)
3002 {
3003 int slice_height;
3004
3005 /*
3006 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3007 * Select smallest slice height >=96, that results in a valid PPS and
3008 * requires minimum padding lines required for final slice.
3009 *
3010 * Assumption : Vactive is even.
3011 */
3012 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3013 if (vactive % slice_height == 0)
3014 return slice_height;
3015
3016 return 0;
3017 }
3018
3019 /*
3020 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3021 * and dsc decoder capabilities
3022 *
3023 * @crtc_state: intel crtc_state
3024 * @src_max_slices: maximum slices supported by the DSC encoder
3025 * @src_max_slice_width: maximum slice width supported by DSC encoder
3026 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3027 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3028 *
3029 * @return: num of dsc slices that can be supported by the dsc encoder
3030 * and decoder.
3031 */
3032 int
intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state * crtc_state,int src_max_slices,int src_max_slice_width,int hdmi_max_slices,int hdmi_throughput)3033 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3034 int src_max_slices, int src_max_slice_width,
3035 int hdmi_max_slices, int hdmi_throughput)
3036 {
3037 /* Pixel rates in KPixels/sec */
3038 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3039 /*
3040 * Rates at which the source and sink are required to process pixels in each
3041 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3042 */
3043 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3044 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3045
3046 /* Spec limits the slice width to 2720 pixels */
3047 #define MAX_HDMI_SLICE_WIDTH 2720
3048 int kslice_adjust;
3049 int adjusted_clk_khz;
3050 int min_slices;
3051 int target_slices;
3052 int max_throughput; /* max clock freq. in khz per slice */
3053 int max_slice_width;
3054 int slice_width;
3055 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3056
3057 if (!hdmi_throughput)
3058 return 0;
3059
3060 /*
3061 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3062 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3063 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3064 * dividing adjusted clock value by 10.
3065 */
3066 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3067 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3068 kslice_adjust = 10;
3069 else
3070 kslice_adjust = 5;
3071
3072 /*
3073 * As per spec, the rate at which the source and the sink process
3074 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3075 * This depends upon the pixel clock rate and output formats
3076 * (kslice adjust).
3077 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3078 * at max 340MHz, otherwise they can be processed at max 400MHz.
3079 */
3080
3081 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3082
3083 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3084 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3085 else
3086 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3087
3088 /*
3089 * Taking into account the sink's capability for maximum
3090 * clock per slice (in MHz) as read from HF-VSDB.
3091 */
3092 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3093
3094 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3095 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3096
3097 /*
3098 * Keep on increasing the num of slices/line, starting from min_slices
3099 * per line till we get such a number, for which the slice_width is
3100 * just less than max_slice_width. The slices/line selected should be
3101 * less than or equal to the max horizontal slices that the combination
3102 * of PCON encoder and HDMI decoder can support.
3103 */
3104 slice_width = max_slice_width;
3105
3106 do {
3107 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3108 target_slices = 1;
3109 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3110 target_slices = 2;
3111 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3112 target_slices = 4;
3113 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3114 target_slices = 8;
3115 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3116 target_slices = 12;
3117 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3118 target_slices = 16;
3119 else
3120 return 0;
3121
3122 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3123 if (slice_width >= max_slice_width)
3124 min_slices = target_slices + 1;
3125 } while (slice_width >= max_slice_width);
3126
3127 return target_slices;
3128 }
3129
3130 /*
3131 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3132 * source and sink capabilities.
3133 *
3134 * @src_fraction_bpp: fractional bpp supported by the source
3135 * @slice_width: dsc slice width supported by the source and sink
3136 * @num_slices: num of slices supported by the source and sink
3137 * @output_format: video output format
3138 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3139 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3140 *
3141 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3142 */
3143 int
intel_hdmi_dsc_get_bpp(int src_fractional_bpp,int slice_width,int num_slices,int output_format,bool hdmi_all_bpp,int hdmi_max_chunk_bytes)3144 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3145 int output_format, bool hdmi_all_bpp,
3146 int hdmi_max_chunk_bytes)
3147 {
3148 int max_dsc_bpp, min_dsc_bpp;
3149 int target_bytes;
3150 bool bpp_found = false;
3151 int bpp_decrement_x16;
3152 int bpp_target;
3153 int bpp_target_x16;
3154
3155 /*
3156 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3157 * Start with the max bpp and keep on decrementing with
3158 * fractional bpp, if supported by PCON DSC encoder
3159 *
3160 * for each bpp we check if no of bytes can be supported by HDMI sink
3161 */
3162
3163 /* Assuming: bpc as 8*/
3164 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3165 min_dsc_bpp = 6;
3166 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3167 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3168 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3169 min_dsc_bpp = 8;
3170 max_dsc_bpp = 3 * 8; /* 3*bpc */
3171 } else {
3172 /* Assuming 4:2:2 encoding */
3173 min_dsc_bpp = 7;
3174 max_dsc_bpp = 2 * 8; /* 2*bpc */
3175 }
3176
3177 /*
3178 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3179 * Section 7.7.34 : Source shall not enable compressed Video
3180 * Transport with bpp_target settings above 12 bpp unless
3181 * DSC_all_bpp is set to 1.
3182 */
3183 if (!hdmi_all_bpp)
3184 max_dsc_bpp = min(max_dsc_bpp, 12);
3185
3186 /*
3187 * The Sink has a limit of compressed data in bytes for a scanline,
3188 * as described in max_chunk_bytes field in HFVSDB block of edid.
3189 * The no. of bytes depend on the target bits per pixel that the
3190 * source configures. So we start with the max_bpp and calculate
3191 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3192 * till we get the target_chunk_bytes just less than what the sink's
3193 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3194 *
3195 * The decrement is according to the fractional support from PCON DSC
3196 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3197 *
3198 * bpp_target_x16 = bpp_target * 16
3199 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3200 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3201 */
3202
3203 bpp_target = max_dsc_bpp;
3204
3205 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3206 if (!src_fractional_bpp)
3207 src_fractional_bpp = 1;
3208 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3209 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3210
3211 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3212 int bpp;
3213
3214 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3215 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3216 if (target_bytes <= hdmi_max_chunk_bytes) {
3217 bpp_found = true;
3218 break;
3219 }
3220 bpp_target_x16 -= bpp_decrement_x16;
3221 }
3222 if (bpp_found)
3223 return bpp_target_x16;
3224
3225 return 0;
3226 }
3227