1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
26 *
27 * Contributors:
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 *
32 */
33
34 #include "i915_drv.h"
35 #include "gvt.h"
36 #include "i915_pvinfo.h"
37
populate_pvinfo_page(struct intel_vgpu * vgpu)38 void populate_pvinfo_page(struct intel_vgpu *vgpu)
39 {
40 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
41 /* setup the ballooning information */
42 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
43 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
44 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
45 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
47
48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
51
52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
53 vgpu_aperture_gmadr_base(vgpu);
54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
55 vgpu_aperture_sz(vgpu);
56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
57 vgpu_hidden_gmadr_base(vgpu);
58 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
59 vgpu_hidden_sz(vgpu);
60
61 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
62
63 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
64 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
65
66 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
67 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
68 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
69 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
70 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
71 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
72
73 drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
74 }
75
76 /*
77 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
78 * generation type (e.g V4 as BDW server, V5 as SKL server).
79 *
80 * Depening on the physical SKU resource, we might see vGPU types like
81 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of
82 * vGPU on same physical GPU depending on available resource. Each vGPU
83 * type will have a different number of avail_instance to indicate how
84 * many vGPU instance can be created for this type.
85 */
86 #define VGPU_MAX_WEIGHT 16
87 #define VGPU_WEIGHT(vgpu_num) \
88 (VGPU_MAX_WEIGHT / (vgpu_num))
89
90 static const struct intel_vgpu_config intel_vgpu_configs[] = {
91 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
92 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
93 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
94 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
95 };
96
97 /**
98 * intel_gvt_init_vgpu_types - initialize vGPU type list
99 * @gvt : GVT device
100 *
101 * Initialize vGPU type list based on available resource.
102 *
103 */
intel_gvt_init_vgpu_types(struct intel_gvt * gvt)104 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
105 {
106 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
107 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
108 unsigned int num_types = ARRAY_SIZE(intel_vgpu_configs);
109 unsigned int i;
110
111 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
112 GFP_KERNEL);
113 if (!gvt->types)
114 return -ENOMEM;
115
116 gvt->mdev_types = kcalloc(num_types, sizeof(*gvt->mdev_types),
117 GFP_KERNEL);
118 if (!gvt->mdev_types)
119 goto out_free_types;
120
121 for (i = 0; i < num_types; ++i) {
122 const struct intel_vgpu_config *conf = &intel_vgpu_configs[i];
123
124 if (low_avail / conf->low_mm == 0)
125 break;
126 if (conf->weight < 1 || conf->weight > VGPU_MAX_WEIGHT)
127 goto out_free_mdev_types;
128
129 sprintf(gvt->types[i].name, "GVTg_V%u_%s",
130 GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name);
131 gvt->types[i].conf = conf;
132
133 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
134 i, gvt->types[i].name,
135 min(low_avail / conf->low_mm,
136 high_avail / conf->high_mm),
137 conf->low_mm, conf->high_mm, conf->fence,
138 conf->weight, vgpu_edid_str(conf->edid));
139
140 gvt->mdev_types[i] = &gvt->types[i].type;
141 gvt->mdev_types[i]->sysfs_name = gvt->types[i].name;
142 }
143
144 gvt->num_types = i;
145 return 0;
146
147 out_free_mdev_types:
148 kfree(gvt->mdev_types);
149 out_free_types:
150 kfree(gvt->types);
151 return -EINVAL;
152 }
153
intel_gvt_clean_vgpu_types(struct intel_gvt * gvt)154 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
155 {
156 kfree(gvt->mdev_types);
157 kfree(gvt->types);
158 }
159
160 /**
161 * intel_gvt_active_vgpu - activate a virtual GPU
162 * @vgpu: virtual GPU
163 *
164 * This function is called when user wants to activate a virtual GPU.
165 *
166 */
intel_gvt_activate_vgpu(struct intel_vgpu * vgpu)167 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
168 {
169 mutex_lock(&vgpu->vgpu_lock);
170 vgpu->active = true;
171 mutex_unlock(&vgpu->vgpu_lock);
172 }
173
174 /**
175 * intel_gvt_deactive_vgpu - deactivate a virtual GPU
176 * @vgpu: virtual GPU
177 *
178 * This function is called when user wants to deactivate a virtual GPU.
179 * The virtual GPU will be stopped.
180 *
181 */
intel_gvt_deactivate_vgpu(struct intel_vgpu * vgpu)182 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
183 {
184 mutex_lock(&vgpu->vgpu_lock);
185
186 vgpu->active = false;
187
188 if (atomic_read(&vgpu->submission.running_workload_num)) {
189 mutex_unlock(&vgpu->vgpu_lock);
190 intel_gvt_wait_vgpu_idle(vgpu);
191 mutex_lock(&vgpu->vgpu_lock);
192 }
193
194 intel_vgpu_stop_schedule(vgpu);
195
196 mutex_unlock(&vgpu->vgpu_lock);
197 }
198
199 /**
200 * intel_gvt_release_vgpu - release a virtual GPU
201 * @vgpu: virtual GPU
202 *
203 * This function is called when user wants to release a virtual GPU.
204 * The virtual GPU will be stopped and all runtime information will be
205 * destroyed.
206 *
207 */
intel_gvt_release_vgpu(struct intel_vgpu * vgpu)208 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
209 {
210 intel_gvt_deactivate_vgpu(vgpu);
211
212 mutex_lock(&vgpu->vgpu_lock);
213 vgpu->d3_entered = false;
214 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
215 intel_vgpu_dmabuf_cleanup(vgpu);
216 mutex_unlock(&vgpu->vgpu_lock);
217 }
218
219 /**
220 * intel_gvt_destroy_vgpu - destroy a virtual GPU
221 * @vgpu: virtual GPU
222 *
223 * This function is called when user wants to destroy a virtual GPU.
224 *
225 */
intel_gvt_destroy_vgpu(struct intel_vgpu * vgpu)226 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
227 {
228 struct intel_gvt *gvt = vgpu->gvt;
229 struct drm_i915_private *i915 = gvt->gt->i915;
230
231 drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");
232
233 /*
234 * remove idr first so later clean can judge if need to stop
235 * service if no active vgpu.
236 */
237 mutex_lock(&gvt->lock);
238 idr_remove(&gvt->vgpu_idr, vgpu->id);
239 mutex_unlock(&gvt->lock);
240
241 mutex_lock(&vgpu->vgpu_lock);
242 intel_gvt_debugfs_remove_vgpu(vgpu);
243 intel_vgpu_clean_sched_policy(vgpu);
244 intel_vgpu_clean_submission(vgpu);
245 intel_vgpu_clean_display(vgpu);
246 intel_vgpu_clean_opregion(vgpu);
247 intel_vgpu_reset_ggtt(vgpu, true);
248 intel_vgpu_clean_gtt(vgpu);
249 intel_vgpu_detach_regions(vgpu);
250 intel_vgpu_free_resource(vgpu);
251 intel_vgpu_clean_mmio(vgpu);
252 intel_vgpu_dmabuf_cleanup(vgpu);
253 mutex_unlock(&vgpu->vgpu_lock);
254 }
255
256 #define IDLE_VGPU_IDR 0
257
258 /**
259 * intel_gvt_create_idle_vgpu - create an idle virtual GPU
260 * @gvt: GVT device
261 *
262 * This function is called when user wants to create an idle virtual GPU.
263 *
264 * Returns:
265 * pointer to intel_vgpu, error pointer if failed.
266 */
intel_gvt_create_idle_vgpu(struct intel_gvt * gvt)267 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
268 {
269 struct intel_vgpu *vgpu;
270 enum intel_engine_id i;
271 int ret;
272
273 vgpu = vzalloc(sizeof(*vgpu));
274 if (!vgpu)
275 return ERR_PTR(-ENOMEM);
276
277 vgpu->id = IDLE_VGPU_IDR;
278 vgpu->gvt = gvt;
279 mutex_init(&vgpu->vgpu_lock);
280
281 for (i = 0; i < I915_NUM_ENGINES; i++)
282 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
283
284 ret = intel_vgpu_init_sched_policy(vgpu);
285 if (ret)
286 goto out_free_vgpu;
287
288 vgpu->active = false;
289
290 return vgpu;
291
292 out_free_vgpu:
293 vfree(vgpu);
294 return ERR_PTR(ret);
295 }
296
297 /**
298 * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
299 * @vgpu: virtual GPU
300 *
301 * This function is called when user wants to destroy an idle virtual GPU.
302 *
303 */
intel_gvt_destroy_idle_vgpu(struct intel_vgpu * vgpu)304 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
305 {
306 mutex_lock(&vgpu->vgpu_lock);
307 intel_vgpu_clean_sched_policy(vgpu);
308 mutex_unlock(&vgpu->vgpu_lock);
309
310 vfree(vgpu);
311 }
312
intel_gvt_create_vgpu(struct intel_vgpu * vgpu,const struct intel_vgpu_config * conf)313 int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
314 const struct intel_vgpu_config *conf)
315 {
316 struct intel_gvt *gvt = vgpu->gvt;
317 struct drm_i915_private *dev_priv = gvt->gt->i915;
318 int ret;
319
320 gvt_dbg_core("low %u MB high %u MB fence %u\n",
321 BYTES_TO_MB(conf->low_mm), BYTES_TO_MB(conf->high_mm),
322 conf->fence);
323
324 mutex_lock(&gvt->lock);
325 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
326 GFP_KERNEL);
327 if (ret < 0)
328 goto out_unlock;;
329
330 vgpu->id = ret;
331 vgpu->sched_ctl.weight = conf->weight;
332 mutex_init(&vgpu->vgpu_lock);
333 mutex_init(&vgpu->dmabuf_lock);
334 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
335 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
336 idr_init_base(&vgpu->object_idr, 1);
337 intel_vgpu_init_cfg_space(vgpu, 1);
338 vgpu->d3_entered = false;
339
340 ret = intel_vgpu_init_mmio(vgpu);
341 if (ret)
342 goto out_clean_idr;
343
344 ret = intel_vgpu_alloc_resource(vgpu, conf);
345 if (ret)
346 goto out_clean_vgpu_mmio;
347
348 populate_pvinfo_page(vgpu);
349
350 ret = intel_vgpu_init_gtt(vgpu);
351 if (ret)
352 goto out_clean_vgpu_resource;
353
354 ret = intel_vgpu_init_opregion(vgpu);
355 if (ret)
356 goto out_clean_gtt;
357
358 ret = intel_vgpu_init_display(vgpu, conf->edid);
359 if (ret)
360 goto out_clean_opregion;
361
362 ret = intel_vgpu_setup_submission(vgpu);
363 if (ret)
364 goto out_clean_display;
365
366 ret = intel_vgpu_init_sched_policy(vgpu);
367 if (ret)
368 goto out_clean_submission;
369
370 intel_gvt_debugfs_add_vgpu(vgpu);
371
372 ret = intel_gvt_set_opregion(vgpu);
373 if (ret)
374 goto out_clean_sched_policy;
375
376 if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))
377 ret = intel_gvt_set_edid(vgpu, PORT_B);
378 else
379 ret = intel_gvt_set_edid(vgpu, PORT_D);
380 if (ret)
381 goto out_clean_sched_policy;
382
383 intel_gvt_update_reg_whitelist(vgpu);
384 mutex_unlock(&gvt->lock);
385 return 0;
386
387 out_clean_sched_policy:
388 intel_vgpu_clean_sched_policy(vgpu);
389 out_clean_submission:
390 intel_vgpu_clean_submission(vgpu);
391 out_clean_display:
392 intel_vgpu_clean_display(vgpu);
393 out_clean_opregion:
394 intel_vgpu_clean_opregion(vgpu);
395 out_clean_gtt:
396 intel_vgpu_clean_gtt(vgpu);
397 out_clean_vgpu_resource:
398 intel_vgpu_free_resource(vgpu);
399 out_clean_vgpu_mmio:
400 intel_vgpu_clean_mmio(vgpu);
401 out_clean_idr:
402 idr_remove(&gvt->vgpu_idr, vgpu->id);
403 out_unlock:
404 mutex_unlock(&gvt->lock);
405 return ret;
406 }
407
408 /**
409 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
410 * @vgpu: virtual GPU
411 * @dmlr: vGPU Device Model Level Reset or GT Reset
412 * @engine_mask: engines to reset for GT reset
413 *
414 * This function is called when user wants to reset a virtual GPU through
415 * device model reset or GT reset. The caller should hold the vgpu lock.
416 *
417 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
418 * the whole vGPU to default state as when it is created. This vGPU function
419 * is required both for functionary and security concerns.The ultimate goal
420 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
421 * assign a vGPU to a virtual machine we must isse such reset first.
422 *
423 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
424 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
425 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
426 * the reset request. Guest driver can issue a GT reset by programming the
427 * virtual GDRST register to reset specific virtual GPU engine or all
428 * engines.
429 *
430 * The parameter dev_level is to identify if we will do DMLR or GT reset.
431 * The parameter engine_mask is to specific the engines that need to be
432 * resetted. If value ALL_ENGINES is given for engine_mask, it means
433 * the caller requests a full GT reset that we will reset all virtual
434 * GPU engines. For FLR, engine_mask is ignored.
435 */
intel_gvt_reset_vgpu_locked(struct intel_vgpu * vgpu,bool dmlr,intel_engine_mask_t engine_mask)436 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
437 intel_engine_mask_t engine_mask)
438 {
439 struct intel_gvt *gvt = vgpu->gvt;
440 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
441 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
442
443 gvt_dbg_core("------------------------------------------\n");
444 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
445 vgpu->id, dmlr, engine_mask);
446
447 vgpu->resetting_eng = resetting_eng;
448
449 intel_vgpu_stop_schedule(vgpu);
450 /*
451 * The current_vgpu will set to NULL after stopping the
452 * scheduler when the reset is triggered by current vgpu.
453 */
454 if (scheduler->current_vgpu == NULL) {
455 mutex_unlock(&vgpu->vgpu_lock);
456 intel_gvt_wait_vgpu_idle(vgpu);
457 mutex_lock(&vgpu->vgpu_lock);
458 }
459
460 intel_vgpu_reset_submission(vgpu, resetting_eng);
461 /* full GPU reset or device model level reset */
462 if (engine_mask == ALL_ENGINES || dmlr) {
463 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
464 if (engine_mask == ALL_ENGINES)
465 intel_vgpu_invalidate_ppgtt(vgpu);
466 /*fence will not be reset during virtual reset */
467 if (dmlr) {
468 if(!vgpu->d3_entered) {
469 intel_vgpu_invalidate_ppgtt(vgpu);
470 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
471 }
472 intel_vgpu_reset_ggtt(vgpu, true);
473 intel_vgpu_reset_resource(vgpu);
474 }
475
476 intel_vgpu_reset_mmio(vgpu, dmlr);
477 populate_pvinfo_page(vgpu);
478
479 if (dmlr) {
480 intel_vgpu_reset_display(vgpu);
481 intel_vgpu_reset_cfg_space(vgpu);
482 /* only reset the failsafe mode when dmlr reset */
483 vgpu->failsafe = false;
484 /*
485 * PCI_D0 is set before dmlr, so reset d3_entered here
486 * after done using.
487 */
488 if(vgpu->d3_entered)
489 vgpu->d3_entered = false;
490 else
491 vgpu->pv_notified = false;
492 }
493 }
494
495 vgpu->resetting_eng = 0;
496 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
497 gvt_dbg_core("------------------------------------------\n");
498 }
499
500 /**
501 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
502 * @vgpu: virtual GPU
503 *
504 * This function is called when user wants to reset a virtual GPU.
505 *
506 */
intel_gvt_reset_vgpu(struct intel_vgpu * vgpu)507 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
508 {
509 mutex_lock(&vgpu->vgpu_lock);
510 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
511 mutex_unlock(&vgpu->vgpu_lock);
512 }
513