1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2014-2019 Intel Corporation
4  */
5 
6 #include "gem/i915_gem_lmem.h"
7 #include "gt/intel_gt.h"
8 #include "gt/intel_gt_irq.h"
9 #include "gt/intel_gt_pm_irq.h"
10 #include "gt/intel_gt_regs.h"
11 #include "intel_guc.h"
12 #include "intel_guc_ads.h"
13 #include "intel_guc_capture.h"
14 #include "intel_guc_slpc.h"
15 #include "intel_guc_submission.h"
16 #include "i915_drv.h"
17 #include "i915_irq.h"
18 
19 /**
20  * DOC: GuC
21  *
22  * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
23  * designed to offload some of the functionality usually performed by the host
24  * driver; currently the main operations it can take care of are:
25  *
26  * - Authentication of the HuC, which is required to fully enable HuC usage.
27  * - Low latency graphics context scheduling (a.k.a. GuC submission).
28  * - GT Power management.
29  *
30  * The enable_guc module parameter can be used to select which of those
31  * operations to enable within GuC. Note that not all the operations are
32  * supported on all gen9+ platforms.
33  *
34  * Enabling the GuC is not mandatory and therefore the firmware is only loaded
35  * if at least one of the operations is selected. However, not loading the GuC
36  * might result in the loss of some features that do require the GuC (currently
37  * just the HuC, but more are expected to land in the future).
38  */
39 
intel_guc_notify(struct intel_guc * guc)40 void intel_guc_notify(struct intel_guc *guc)
41 {
42 	struct intel_gt *gt = guc_to_gt(guc);
43 
44 	/*
45 	 * On Gen11+, the value written to the register is passes as a payload
46 	 * to the FW. However, the FW currently treats all values the same way
47 	 * (H2G interrupt), so we can just write the value that the HW expects
48 	 * on older gens.
49 	 */
50 	intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER);
51 }
52 
guc_send_reg(struct intel_guc * guc,u32 i)53 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
54 {
55 	GEM_BUG_ON(!guc->send_regs.base);
56 	GEM_BUG_ON(!guc->send_regs.count);
57 	GEM_BUG_ON(i >= guc->send_regs.count);
58 
59 	return _MMIO(guc->send_regs.base + 4 * i);
60 }
61 
intel_guc_init_send_regs(struct intel_guc * guc)62 void intel_guc_init_send_regs(struct intel_guc *guc)
63 {
64 	struct intel_gt *gt = guc_to_gt(guc);
65 	enum forcewake_domains fw_domains = 0;
66 	unsigned int i;
67 
68 	GEM_BUG_ON(!guc->send_regs.base);
69 	GEM_BUG_ON(!guc->send_regs.count);
70 
71 	for (i = 0; i < guc->send_regs.count; i++) {
72 		fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
73 					guc_send_reg(guc, i),
74 					FW_REG_READ | FW_REG_WRITE);
75 	}
76 	guc->send_regs.fw_domains = fw_domains;
77 }
78 
gen9_reset_guc_interrupts(struct intel_guc * guc)79 static void gen9_reset_guc_interrupts(struct intel_guc *guc)
80 {
81 	struct intel_gt *gt = guc_to_gt(guc);
82 
83 	assert_rpm_wakelock_held(&gt->i915->runtime_pm);
84 
85 	spin_lock_irq(gt->irq_lock);
86 	gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
87 	spin_unlock_irq(gt->irq_lock);
88 }
89 
gen9_enable_guc_interrupts(struct intel_guc * guc)90 static void gen9_enable_guc_interrupts(struct intel_guc *guc)
91 {
92 	struct intel_gt *gt = guc_to_gt(guc);
93 
94 	assert_rpm_wakelock_held(&gt->i915->runtime_pm);
95 
96 	spin_lock_irq(gt->irq_lock);
97 	WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
98 		     gt->pm_guc_events);
99 	gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
100 	spin_unlock_irq(gt->irq_lock);
101 }
102 
gen9_disable_guc_interrupts(struct intel_guc * guc)103 static void gen9_disable_guc_interrupts(struct intel_guc *guc)
104 {
105 	struct intel_gt *gt = guc_to_gt(guc);
106 
107 	assert_rpm_wakelock_held(&gt->i915->runtime_pm);
108 
109 	spin_lock_irq(gt->irq_lock);
110 
111 	gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
112 
113 	spin_unlock_irq(gt->irq_lock);
114 	intel_synchronize_irq(gt->i915);
115 
116 	gen9_reset_guc_interrupts(guc);
117 }
118 
gen11_reset_guc_interrupts(struct intel_guc * guc)119 static void gen11_reset_guc_interrupts(struct intel_guc *guc)
120 {
121 	struct intel_gt *gt = guc_to_gt(guc);
122 
123 	spin_lock_irq(gt->irq_lock);
124 	gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
125 	spin_unlock_irq(gt->irq_lock);
126 }
127 
gen11_enable_guc_interrupts(struct intel_guc * guc)128 static void gen11_enable_guc_interrupts(struct intel_guc *guc)
129 {
130 	struct intel_gt *gt = guc_to_gt(guc);
131 	u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
132 
133 	spin_lock_irq(gt->irq_lock);
134 	WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
135 	intel_uncore_write(gt->uncore,
136 			   GEN11_GUC_SG_INTR_ENABLE, events);
137 	intel_uncore_write(gt->uncore,
138 			   GEN11_GUC_SG_INTR_MASK, ~events);
139 	spin_unlock_irq(gt->irq_lock);
140 }
141 
gen11_disable_guc_interrupts(struct intel_guc * guc)142 static void gen11_disable_guc_interrupts(struct intel_guc *guc)
143 {
144 	struct intel_gt *gt = guc_to_gt(guc);
145 
146 	spin_lock_irq(gt->irq_lock);
147 
148 	intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
149 	intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
150 
151 	spin_unlock_irq(gt->irq_lock);
152 	intel_synchronize_irq(gt->i915);
153 
154 	gen11_reset_guc_interrupts(guc);
155 }
156 
intel_guc_init_early(struct intel_guc * guc)157 void intel_guc_init_early(struct intel_guc *guc)
158 {
159 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
160 
161 	intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC);
162 	intel_guc_ct_init_early(&guc->ct);
163 	intel_guc_log_init_early(&guc->log);
164 	intel_guc_submission_init_early(guc);
165 	intel_guc_slpc_init_early(&guc->slpc);
166 	intel_guc_rc_init_early(guc);
167 
168 	mutex_init(&guc->send_mutex);
169 	spin_lock_init(&guc->irq_lock);
170 	if (GRAPHICS_VER(i915) >= 11) {
171 		guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
172 		guc->interrupts.reset = gen11_reset_guc_interrupts;
173 		guc->interrupts.enable = gen11_enable_guc_interrupts;
174 		guc->interrupts.disable = gen11_disable_guc_interrupts;
175 		guc->send_regs.base =
176 			i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
177 		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
178 
179 	} else {
180 		guc->notify_reg = GUC_SEND_INTERRUPT;
181 		guc->interrupts.reset = gen9_reset_guc_interrupts;
182 		guc->interrupts.enable = gen9_enable_guc_interrupts;
183 		guc->interrupts.disable = gen9_disable_guc_interrupts;
184 		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
185 		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
186 		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
187 	}
188 
189 	intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_EXCEPTION |
190 				  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
191 }
192 
intel_guc_init_late(struct intel_guc * guc)193 void intel_guc_init_late(struct intel_guc *guc)
194 {
195 	intel_guc_ads_init_late(guc);
196 }
197 
guc_ctl_debug_flags(struct intel_guc * guc)198 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
199 {
200 	u32 level = intel_guc_log_get_level(&guc->log);
201 	u32 flags = 0;
202 
203 	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
204 		flags |= GUC_LOG_DISABLED;
205 	else
206 		flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
207 			 GUC_LOG_VERBOSITY_SHIFT;
208 
209 	return flags;
210 }
211 
guc_ctl_feature_flags(struct intel_guc * guc)212 static u32 guc_ctl_feature_flags(struct intel_guc *guc)
213 {
214 	u32 flags = 0;
215 
216 	if (!intel_guc_submission_is_used(guc))
217 		flags |= GUC_CTL_DISABLE_SCHEDULER;
218 
219 	if (intel_guc_slpc_is_used(guc))
220 		flags |= GUC_CTL_ENABLE_SLPC;
221 
222 	return flags;
223 }
224 
guc_ctl_log_params_flags(struct intel_guc * guc)225 static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
226 {
227 	struct intel_guc_log *log = &guc->log;
228 	u32 offset, flags;
229 
230 	GEM_BUG_ON(!log->sizes_initialised);
231 
232 	offset = intel_guc_ggtt_offset(guc, log->vma) >> PAGE_SHIFT;
233 
234 	flags = GUC_LOG_VALID |
235 		GUC_LOG_NOTIFY_ON_HALF_FULL |
236 		log->sizes[GUC_LOG_SECTIONS_DEBUG].flag |
237 		log->sizes[GUC_LOG_SECTIONS_CAPTURE].flag |
238 		(log->sizes[GUC_LOG_SECTIONS_CRASH].count << GUC_LOG_CRASH_SHIFT) |
239 		(log->sizes[GUC_LOG_SECTIONS_DEBUG].count << GUC_LOG_DEBUG_SHIFT) |
240 		(log->sizes[GUC_LOG_SECTIONS_CAPTURE].count << GUC_LOG_CAPTURE_SHIFT) |
241 		(offset << GUC_LOG_BUF_ADDR_SHIFT);
242 
243 	return flags;
244 }
245 
guc_ctl_ads_flags(struct intel_guc * guc)246 static u32 guc_ctl_ads_flags(struct intel_guc *guc)
247 {
248 	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
249 	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
250 
251 	return flags;
252 }
253 
guc_ctl_wa_flags(struct intel_guc * guc)254 static u32 guc_ctl_wa_flags(struct intel_guc *guc)
255 {
256 	struct intel_gt *gt = guc_to_gt(guc);
257 	u32 flags = 0;
258 
259 	/* Wa_22012773006:gen11,gen12 < XeHP */
260 	if (GRAPHICS_VER(gt->i915) >= 11 &&
261 	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
262 		flags |= GUC_WA_POLLCS;
263 
264 	/* Wa_16011759253:dg2_g10:a0 */
265 	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
266 		flags |= GUC_WA_GAM_CREDITS;
267 
268 	/* Wa_14014475959:dg2 */
269 	if (IS_DG2(gt->i915))
270 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
271 
272 	/*
273 	 * Wa_14012197797:dg2_g10:a0,dg2_g11:a0
274 	 * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12
275 	 *
276 	 * The same WA bit is used for both and 22011391025 is applicable to
277 	 * all DG2.
278 	 */
279 	if (IS_DG2(gt->i915))
280 		flags |= GUC_WA_DUAL_QUEUE;
281 
282 	/* Wa_22011802037: graphics version 11/12 */
283 	if (IS_GRAPHICS_VER(gt->i915, 11, 12))
284 		flags |= GUC_WA_PRE_PARSER;
285 
286 	/* Wa_16011777198:dg2 */
287 	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
288 	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
289 		flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
290 
291 	/*
292 	 * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..)
293 	 * Wa_22012727685:dg2_g11[a0..)
294 	 */
295 	if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
296 	    IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
297 		flags |= GUC_WA_CONTEXT_ISOLATION;
298 
299 	/* Wa_16015675438 */
300 	if (!RCS_MASK(gt))
301 		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
302 
303 	return flags;
304 }
305 
guc_ctl_devid(struct intel_guc * guc)306 static u32 guc_ctl_devid(struct intel_guc *guc)
307 {
308 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
309 
310 	return (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915);
311 }
312 
313 /*
314  * Initialise the GuC parameter block before starting the firmware
315  * transfer. These parameters are read by the firmware on startup
316  * and cannot be changed thereafter.
317  */
guc_init_params(struct intel_guc * guc)318 static void guc_init_params(struct intel_guc *guc)
319 {
320 	u32 *params = guc->params;
321 	int i;
322 
323 	BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
324 
325 	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
326 	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
327 	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
328 	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
329 	params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);
330 	params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
331 
332 	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
333 		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
334 }
335 
336 /*
337  * Initialise the GuC parameter block before starting the firmware
338  * transfer. These parameters are read by the firmware on startup
339  * and cannot be changed thereafter.
340  */
intel_guc_write_params(struct intel_guc * guc)341 void intel_guc_write_params(struct intel_guc *guc)
342 {
343 	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
344 	int i;
345 
346 	/*
347 	 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and
348 	 * they are power context saved so it's ok to release forcewake
349 	 * when we are done here and take it again at xfer time.
350 	 */
351 	intel_uncore_forcewake_get(uncore, FORCEWAKE_GT);
352 
353 	intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
354 
355 	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
356 		intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
357 
358 	intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
359 }
360 
intel_guc_dump_time_info(struct intel_guc * guc,struct drm_printer * p)361 void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p)
362 {
363 	struct intel_gt *gt = guc_to_gt(guc);
364 	intel_wakeref_t wakeref;
365 	u32 stamp = 0;
366 	u64 ktime;
367 
368 	with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
369 		stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
370 	ktime = ktime_get_boottime_ns();
371 
372 	drm_printf(p, "Kernel timestamp: 0x%08llX [%llu]\n", ktime, ktime);
373 	drm_printf(p, "GuC timestamp: 0x%08X [%u]\n", stamp, stamp);
374 	drm_printf(p, "CS timestamp frequency: %u Hz, %u ns\n",
375 		   gt->clock_frequency, gt->clock_period_ns);
376 }
377 
intel_guc_init(struct intel_guc * guc)378 int intel_guc_init(struct intel_guc *guc)
379 {
380 	struct intel_gt *gt = guc_to_gt(guc);
381 	int ret;
382 
383 	ret = intel_uc_fw_init(&guc->fw);
384 	if (ret)
385 		goto out;
386 
387 	ret = intel_guc_log_create(&guc->log);
388 	if (ret)
389 		goto err_fw;
390 
391 	ret = intel_guc_capture_init(guc);
392 	if (ret)
393 		goto err_log;
394 
395 	ret = intel_guc_ads_create(guc);
396 	if (ret)
397 		goto err_capture;
398 
399 	GEM_BUG_ON(!guc->ads_vma);
400 
401 	ret = intel_guc_ct_init(&guc->ct);
402 	if (ret)
403 		goto err_ads;
404 
405 	if (intel_guc_submission_is_used(guc)) {
406 		/*
407 		 * This is stuff we need to have available at fw load time
408 		 * if we are planning to enable submission later
409 		 */
410 		ret = intel_guc_submission_init(guc);
411 		if (ret)
412 			goto err_ct;
413 	}
414 
415 	if (intel_guc_slpc_is_used(guc)) {
416 		ret = intel_guc_slpc_init(&guc->slpc);
417 		if (ret)
418 			goto err_submission;
419 	}
420 
421 	/* now that everything is perma-pinned, initialize the parameters */
422 	guc_init_params(guc);
423 
424 	/* We need to notify the guc whenever we change the GGTT */
425 	i915_ggtt_enable_guc(gt->ggtt);
426 
427 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE);
428 
429 	return 0;
430 
431 err_submission:
432 	intel_guc_submission_fini(guc);
433 err_ct:
434 	intel_guc_ct_fini(&guc->ct);
435 err_ads:
436 	intel_guc_ads_destroy(guc);
437 err_capture:
438 	intel_guc_capture_destroy(guc);
439 err_log:
440 	intel_guc_log_destroy(&guc->log);
441 err_fw:
442 	intel_uc_fw_fini(&guc->fw);
443 out:
444 	i915_probe_error(gt->i915, "failed with %d\n", ret);
445 	return ret;
446 }
447 
intel_guc_fini(struct intel_guc * guc)448 void intel_guc_fini(struct intel_guc *guc)
449 {
450 	struct intel_gt *gt = guc_to_gt(guc);
451 
452 	if (!intel_uc_fw_is_loadable(&guc->fw))
453 		return;
454 
455 	i915_ggtt_disable_guc(gt->ggtt);
456 
457 	if (intel_guc_slpc_is_used(guc))
458 		intel_guc_slpc_fini(&guc->slpc);
459 
460 	if (intel_guc_submission_is_used(guc))
461 		intel_guc_submission_fini(guc);
462 
463 	intel_guc_ct_fini(&guc->ct);
464 
465 	intel_guc_ads_destroy(guc);
466 	intel_guc_capture_destroy(guc);
467 	intel_guc_log_destroy(&guc->log);
468 	intel_uc_fw_fini(&guc->fw);
469 }
470 
471 /*
472  * This function implements the MMIO based host to GuC interface.
473  */
intel_guc_send_mmio(struct intel_guc * guc,const u32 * request,u32 len,u32 * response_buf,u32 response_buf_size)474 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
475 			u32 *response_buf, u32 response_buf_size)
476 {
477 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
478 	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
479 	u32 header;
480 	int i;
481 	int ret;
482 
483 	GEM_BUG_ON(!len);
484 	GEM_BUG_ON(len > guc->send_regs.count);
485 
486 	GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST);
487 	GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST);
488 
489 	mutex_lock(&guc->send_mutex);
490 	intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
491 
492 retry:
493 	for (i = 0; i < len; i++)
494 		intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]);
495 
496 	intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
497 
498 	intel_guc_notify(guc);
499 
500 	/*
501 	 * No GuC command should ever take longer than 10ms.
502 	 * Fast commands should still complete in 10us.
503 	 */
504 	ret = __intel_wait_for_register_fw(uncore,
505 					   guc_send_reg(guc, 0),
506 					   GUC_HXG_MSG_0_ORIGIN,
507 					   FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
508 						      GUC_HXG_ORIGIN_GUC),
509 					   10, 10, &header);
510 	if (unlikely(ret)) {
511 timeout:
512 		drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
513 			request[0], header);
514 		goto out;
515 	}
516 
517 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
518 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \
519 		FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \
520 		FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; })
521 
522 		ret = wait_for(done, 1000);
523 		if (unlikely(ret))
524 			goto timeout;
525 		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
526 				       GUC_HXG_ORIGIN_GUC))
527 			goto proto;
528 #undef done
529 	}
530 
531 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
532 		u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
533 
534 		drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
535 			request[0], reason);
536 		goto retry;
537 	}
538 
539 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) {
540 		u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
541 		u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
542 
543 		drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
544 			request[0], error, hint);
545 		ret = -ENXIO;
546 		goto out;
547 	}
548 
549 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
550 proto:
551 		drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
552 			request[0], header);
553 		ret = -EPROTO;
554 		goto out;
555 	}
556 
557 	if (response_buf) {
558 		int count = min(response_buf_size, guc->send_regs.count);
559 
560 		GEM_BUG_ON(!count);
561 
562 		response_buf[0] = header;
563 
564 		for (i = 1; i < count; i++)
565 			response_buf[i] = intel_uncore_read(uncore,
566 							    guc_send_reg(guc, i));
567 
568 		/* Use number of copied dwords as our return value */
569 		ret = count;
570 	} else {
571 		/* Use data from the GuC response as our return value */
572 		ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);
573 	}
574 
575 out:
576 	intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
577 	mutex_unlock(&guc->send_mutex);
578 
579 	return ret;
580 }
581 
intel_guc_to_host_process_recv_msg(struct intel_guc * guc,const u32 * payload,u32 len)582 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
583 				       const u32 *payload, u32 len)
584 {
585 	u32 msg;
586 
587 	if (unlikely(!len))
588 		return -EPROTO;
589 
590 	/* Make sure to handle only enabled messages */
591 	msg = payload[0] & guc->msg_enabled_mask;
592 
593 	if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
594 		drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
595 	if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
596 		drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
597 
598 	return 0;
599 }
600 
601 /**
602  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
603  * @guc: intel_guc structure
604  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
605  *
606  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
607  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
608  * intel_huc_auth().
609  *
610  * Return:	non-zero code on error
611  */
intel_guc_auth_huc(struct intel_guc * guc,u32 rsa_offset)612 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
613 {
614 	u32 action[] = {
615 		INTEL_GUC_ACTION_AUTHENTICATE_HUC,
616 		rsa_offset
617 	};
618 
619 	return intel_guc_send(guc, action, ARRAY_SIZE(action));
620 }
621 
622 /**
623  * intel_guc_suspend() - notify GuC entering suspend state
624  * @guc:	the guc
625  */
intel_guc_suspend(struct intel_guc * guc)626 int intel_guc_suspend(struct intel_guc *guc)
627 {
628 	int ret;
629 	u32 action[] = {
630 		INTEL_GUC_ACTION_CLIENT_SOFT_RESET,
631 	};
632 
633 	if (!intel_guc_is_ready(guc))
634 		return 0;
635 
636 	if (intel_guc_submission_is_used(guc)) {
637 		/*
638 		 * This H2G MMIO command tears down the GuC in two steps. First it will
639 		 * generate a G2H CTB for every active context indicating a reset. In
640 		 * practice the i915 shouldn't ever get a G2H as suspend should only be
641 		 * called when the GPU is idle. Next, it tears down the CTBs and this
642 		 * H2G MMIO command completes.
643 		 *
644 		 * Don't abort on a failure code from the GuC. Keep going and do the
645 		 * clean up in santize() and re-initialisation on resume and hopefully
646 		 * the error here won't be problematic.
647 		 */
648 		ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
649 		if (ret)
650 			DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
651 	}
652 
653 	/* Signal that the GuC isn't running. */
654 	intel_guc_sanitize(guc);
655 
656 	return 0;
657 }
658 
659 /**
660  * intel_guc_resume() - notify GuC resuming from suspend state
661  * @guc:	the guc
662  */
intel_guc_resume(struct intel_guc * guc)663 int intel_guc_resume(struct intel_guc *guc)
664 {
665 	/*
666 	 * NB: This function can still be called even if GuC submission is
667 	 * disabled, e.g. if GuC is enabled for HuC authentication only. Thus,
668 	 * if any code is later added here, it must be support doing nothing
669 	 * if submission is disabled (as per intel_guc_suspend).
670 	 */
671 	return 0;
672 }
673 
674 /**
675  * DOC: GuC Memory Management
676  *
677  * GuC can't allocate any memory for its own usage, so all the allocations must
678  * be handled by the host driver. GuC accesses the memory via the GGTT, with the
679  * exception of the top and bottom parts of the 4GB address space, which are
680  * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
681  * or other parts of the HW. The driver must take care not to place objects that
682  * the GuC is going to access in these reserved ranges. The layout of the GuC
683  * address space is shown below:
684  *
685  * ::
686  *
687  *     +===========> +====================+ <== FFFF_FFFF
688  *     ^             |      Reserved      |
689  *     |             +====================+ <== GUC_GGTT_TOP
690  *     |             |                    |
691  *     |             |        DRAM        |
692  *    GuC            |                    |
693  *  Address    +===> +====================+ <== GuC ggtt_pin_bias
694  *   Space     ^     |                    |
695  *     |       |     |                    |
696  *     |      GuC    |        GuC         |
697  *     |     WOPCM   |       WOPCM        |
698  *     |      Size   |                    |
699  *     |       |     |                    |
700  *     v       v     |                    |
701  *     +=======+===> +====================+ <== 0000_0000
702  *
703  * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
704  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
705  * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
706  */
707 
708 /**
709  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
710  * @guc:	the guc
711  * @size:	size of area to allocate (both virtual space and memory)
712  *
713  * This is a wrapper to create an object for use with the GuC. In order to
714  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
715  * both some backing storage and a range inside the Global GTT. We must pin
716  * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
717  * range is reserved inside GuC.
718  *
719  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
720  */
intel_guc_allocate_vma(struct intel_guc * guc,u32 size)721 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
722 {
723 	struct intel_gt *gt = guc_to_gt(guc);
724 	struct drm_i915_gem_object *obj;
725 	struct i915_vma *vma;
726 	u64 flags;
727 	int ret;
728 
729 	if (HAS_LMEM(gt->i915))
730 		obj = i915_gem_object_create_lmem(gt->i915, size,
731 						  I915_BO_ALLOC_CPU_CLEAR |
732 						  I915_BO_ALLOC_CONTIGUOUS |
733 						  I915_BO_ALLOC_PM_EARLY);
734 	else
735 		obj = i915_gem_object_create_shmem(gt->i915, size);
736 
737 	if (IS_ERR(obj))
738 		return ERR_CAST(obj);
739 
740 	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
741 	if (IS_ERR(vma))
742 		goto err;
743 
744 	flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
745 	ret = i915_ggtt_pin(vma, NULL, 0, flags);
746 	if (ret) {
747 		vma = ERR_PTR(ret);
748 		goto err;
749 	}
750 
751 	return i915_vma_make_unshrinkable(vma);
752 
753 err:
754 	i915_gem_object_put(obj);
755 	return vma;
756 }
757 
758 /**
759  * intel_guc_allocate_and_map_vma() - Allocate and map VMA for GuC usage
760  * @guc:	the guc
761  * @size:	size of area to allocate (both virtual space and memory)
762  * @out_vma:	return variable for the allocated vma pointer
763  * @out_vaddr:	return variable for the obj mapping
764  *
765  * This wrapper calls intel_guc_allocate_vma() and then maps the allocated
766  * object with I915_MAP_WB.
767  *
768  * Return:	0 if successful, a negative errno code otherwise.
769  */
intel_guc_allocate_and_map_vma(struct intel_guc * guc,u32 size,struct i915_vma ** out_vma,void ** out_vaddr)770 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
771 				   struct i915_vma **out_vma, void **out_vaddr)
772 {
773 	struct i915_vma *vma;
774 	void *vaddr;
775 
776 	vma = intel_guc_allocate_vma(guc, size);
777 	if (IS_ERR(vma))
778 		return PTR_ERR(vma);
779 
780 	vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
781 						 i915_coherent_map_type(guc_to_gt(guc)->i915,
782 									vma->obj, true));
783 	if (IS_ERR(vaddr)) {
784 		i915_vma_unpin_and_release(&vma, 0);
785 		return PTR_ERR(vaddr);
786 	}
787 
788 	*out_vma = vma;
789 	*out_vaddr = vaddr;
790 
791 	return 0;
792 }
793 
__guc_action_self_cfg(struct intel_guc * guc,u16 key,u16 len,u64 value)794 static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
795 {
796 	u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {
797 		FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
798 		FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |
799 		FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SELF_CFG),
800 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |
801 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),
802 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)),
803 		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)),
804 	};
805 	int ret;
806 
807 	GEM_BUG_ON(len > 2);
808 	GEM_BUG_ON(len == 1 && upper_32_bits(value));
809 
810 	/* Self config must go over MMIO */
811 	ret = intel_guc_send_mmio(guc, request, ARRAY_SIZE(request), NULL, 0);
812 
813 	if (unlikely(ret < 0))
814 		return ret;
815 	if (unlikely(ret > 1))
816 		return -EPROTO;
817 	if (unlikely(!ret))
818 		return -ENOKEY;
819 
820 	return 0;
821 }
822 
__guc_self_cfg(struct intel_guc * guc,u16 key,u16 len,u64 value)823 static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
824 {
825 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
826 	int err = __guc_action_self_cfg(guc, key, len, value);
827 
828 	if (unlikely(err))
829 		i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
830 				 ERR_PTR(err), key, value);
831 	return err;
832 }
833 
intel_guc_self_cfg32(struct intel_guc * guc,u16 key,u32 value)834 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value)
835 {
836 	return __guc_self_cfg(guc, key, 1, value);
837 }
838 
intel_guc_self_cfg64(struct intel_guc * guc,u16 key,u64 value)839 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)
840 {
841 	return __guc_self_cfg(guc, key, 2, value);
842 }
843 
844 /**
845  * intel_guc_load_status - dump information about GuC load status
846  * @guc: the GuC
847  * @p: the &drm_printer
848  *
849  * Pretty printer for GuC load status.
850  */
intel_guc_load_status(struct intel_guc * guc,struct drm_printer * p)851 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
852 {
853 	struct intel_gt *gt = guc_to_gt(guc);
854 	struct intel_uncore *uncore = gt->uncore;
855 	intel_wakeref_t wakeref;
856 
857 	if (!intel_guc_is_supported(guc)) {
858 		drm_printf(p, "GuC not supported\n");
859 		return;
860 	}
861 
862 	if (!intel_guc_is_wanted(guc)) {
863 		drm_printf(p, "GuC disabled\n");
864 		return;
865 	}
866 
867 	intel_uc_fw_dump(&guc->fw, p);
868 
869 	with_intel_runtime_pm(uncore->rpm, wakeref) {
870 		u32 status = intel_uncore_read(uncore, GUC_STATUS);
871 		u32 i;
872 
873 		drm_printf(p, "\nGuC status 0x%08x:\n", status);
874 		drm_printf(p, "\tBootrom status = 0x%x\n",
875 			   (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
876 		drm_printf(p, "\tuKernel status = 0x%x\n",
877 			   (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
878 		drm_printf(p, "\tMIA Core status = 0x%x\n",
879 			   (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
880 		drm_puts(p, "\nScratch registers:\n");
881 		for (i = 0; i < 16; i++) {
882 			drm_printf(p, "\t%2d: \t0x%x\n",
883 				   i, intel_uncore_read(uncore, SOFT_SCRATCH(i)));
884 		}
885 	}
886 }
887 
intel_guc_write_barrier(struct intel_guc * guc)888 void intel_guc_write_barrier(struct intel_guc *guc)
889 {
890 	struct intel_gt *gt = guc_to_gt(guc);
891 
892 	if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
893 		/*
894 		 * Ensure intel_uncore_write_fw can be used rather than
895 		 * intel_uncore_write.
896 		 */
897 		GEM_BUG_ON(guc->send_regs.fw_domains);
898 
899 		/*
900 		 * This register is used by the i915 and GuC for MMIO based
901 		 * communication. Once we are in this code CTBs are the only
902 		 * method the i915 uses to communicate with the GuC so it is
903 		 * safe to write to this register (a value of 0 is NOP for MMIO
904 		 * communication). If we ever start mixing CTBs and MMIOs a new
905 		 * register will have to be chosen. This function is also used
906 		 * to enforce ordering of a work queue item write and an update
907 		 * to the process descriptor. When a work queue is being used,
908 		 * CTBs are also the only mechanism of communication.
909 		 */
910 		intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
911 	} else {
912 		/* wmb() sufficient for a barrier if in smem */
913 		wmb();
914 	}
915 }
916