1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_pci.h"
8 #include "i915_reg.h"
9 #include "intel_memory_region.h"
10 #include "intel_pci_config.h"
11 #include "intel_region_lmem.h"
12 #include "intel_region_ttm.h"
13 #include "gem/i915_gem_lmem.h"
14 #include "gem/i915_gem_region.h"
15 #include "gem/i915_gem_ttm.h"
16 #include "gt/intel_gt.h"
17 #include "gt/intel_gt_mcr.h"
18 #include "gt/intel_gt_regs.h"
19
20 #ifdef CONFIG_64BIT
_release_bars(struct pci_dev * pdev)21 static void _release_bars(struct pci_dev *pdev)
22 {
23 int resno;
24
25 for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
26 if (pci_resource_len(pdev, resno))
27 pci_release_resource(pdev, resno);
28 }
29 }
30
31 static void
_resize_bar(struct drm_i915_private * i915,int resno,resource_size_t size)32 _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
33 {
34 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
35 int bar_size = pci_rebar_bytes_to_size(size);
36 int ret;
37
38 _release_bars(pdev);
39
40 ret = pci_resize_resource(pdev, resno, bar_size);
41 if (ret) {
42 drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
43 resno, 1 << bar_size, ERR_PTR(ret));
44 return;
45 }
46
47 drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
48 }
49
i915_resize_lmem_bar(struct drm_i915_private * i915,resource_size_t lmem_size)50 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size)
51 {
52 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
53 struct pci_bus *root = pdev->bus;
54 struct resource *root_res;
55 resource_size_t rebar_size;
56 resource_size_t current_size;
57 u32 pci_cmd;
58 int i;
59
60 current_size = roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR));
61
62 if (i915->params.lmem_bar_size) {
63 u32 bar_sizes;
64
65 rebar_size = i915->params.lmem_bar_size *
66 (resource_size_t)SZ_1M;
67 bar_sizes = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR);
68
69 if (rebar_size == current_size)
70 return;
71
72 if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
73 rebar_size >= roundup_pow_of_two(lmem_size)) {
74 rebar_size = lmem_size;
75
76 drm_info(&i915->drm,
77 "Given bar size is not within supported size, setting it to default: %llu\n",
78 (u64)lmem_size >> 20);
79 }
80 } else {
81 rebar_size = current_size;
82
83 if (rebar_size != roundup_pow_of_two(lmem_size))
84 rebar_size = lmem_size;
85 else
86 return;
87 }
88
89 /* Find out if root bus contains 64bit memory addressing */
90 while (root->parent)
91 root = root->parent;
92
93 pci_bus_for_each_resource(root, root_res, i) {
94 if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
95 root_res->start > 0x100000000ull)
96 break;
97 }
98
99 /* pci_resize_resource will fail anyways */
100 if (!root_res) {
101 drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
102 return;
103 }
104
105 /* First disable PCI memory decoding references */
106 pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
107 pci_write_config_dword(pdev, PCI_COMMAND,
108 pci_cmd & ~PCI_COMMAND_MEMORY);
109
110 _resize_bar(i915, GEN12_LMEM_BAR, rebar_size);
111
112 pci_assign_unassigned_bus_resources(pdev->bus);
113 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
114 }
115 #else
i915_resize_lmem_bar(struct drm_i915_private * i915,resource_size_t lmem_size)116 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size) {}
117 #endif
118
119 static int
region_lmem_release(struct intel_memory_region * mem)120 region_lmem_release(struct intel_memory_region *mem)
121 {
122 int ret;
123
124 ret = intel_region_ttm_fini(mem);
125 io_mapping_fini(&mem->iomap);
126
127 return ret;
128 }
129
130 static int
region_lmem_init(struct intel_memory_region * mem)131 region_lmem_init(struct intel_memory_region *mem)
132 {
133 int ret;
134
135 if (!io_mapping_init_wc(&mem->iomap,
136 mem->io_start,
137 mem->io_size))
138 return -EIO;
139
140 ret = intel_region_ttm_init(mem);
141 if (ret)
142 goto out_no_buddy;
143
144 return 0;
145
146 out_no_buddy:
147 io_mapping_fini(&mem->iomap);
148
149 return ret;
150 }
151
152 static const struct intel_memory_region_ops intel_region_lmem_ops = {
153 .init = region_lmem_init,
154 .release = region_lmem_release,
155 .init_object = __i915_gem_ttm_object_init,
156 };
157
get_legacy_lowmem_region(struct intel_uncore * uncore,u64 * start,u32 * size)158 static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
159 u64 *start, u32 *size)
160 {
161 if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
162 return false;
163
164 *start = 0;
165 *size = SZ_1M;
166
167 drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
168 *start, *start + *size);
169
170 return true;
171 }
172
reserve_lowmem_region(struct intel_uncore * uncore,struct intel_memory_region * mem)173 static int reserve_lowmem_region(struct intel_uncore *uncore,
174 struct intel_memory_region *mem)
175 {
176 u64 reserve_start;
177 u32 reserve_size;
178 int ret;
179
180 if (!get_legacy_lowmem_region(uncore, &reserve_start, &reserve_size))
181 return 0;
182
183 ret = intel_memory_region_reserve(mem, reserve_start, reserve_size);
184 if (ret)
185 drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n");
186
187 return ret;
188 }
189
setup_lmem(struct intel_gt * gt)190 static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
191 {
192 struct drm_i915_private *i915 = gt->i915;
193 struct intel_uncore *uncore = gt->uncore;
194 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
195 struct intel_memory_region *mem;
196 resource_size_t min_page_size;
197 resource_size_t io_start;
198 resource_size_t io_size;
199 resource_size_t lmem_size;
200 int err;
201
202 if (!IS_DGFX(i915))
203 return ERR_PTR(-ENODEV);
204
205 if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
206 return ERR_PTR(-ENXIO);
207
208 if (HAS_FLAT_CCS(i915)) {
209 resource_size_t lmem_range;
210 u64 tile_stolen, flat_ccs_base;
211
212 lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
213 lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
214 lmem_size *= SZ_1G;
215
216 flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
217 flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
218
219 if (GEM_WARN_ON(lmem_size < flat_ccs_base))
220 return ERR_PTR(-EIO);
221
222 tile_stolen = lmem_size - flat_ccs_base;
223
224 /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */
225 if (tile_stolen == lmem_size)
226 drm_err(&i915->drm,
227 "CCS_BASE_ADDR register did not have expected value\n");
228
229 lmem_size -= tile_stolen;
230 } else {
231 /* Stolen starts from GSMBASE without CCS */
232 lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
233 }
234
235 i915_resize_lmem_bar(i915, lmem_size);
236
237 if (i915->params.lmem_size > 0) {
238 lmem_size = min_t(resource_size_t, lmem_size,
239 mul_u32_u32(i915->params.lmem_size, SZ_1M));
240 }
241
242 io_start = pci_resource_start(pdev, GEN12_LMEM_BAR);
243 io_size = min(pci_resource_len(pdev, GEN12_LMEM_BAR), lmem_size);
244 if (!io_size)
245 return ERR_PTR(-EIO);
246
247 min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
248 I915_GTT_PAGE_SIZE_4K;
249 mem = intel_memory_region_create(i915,
250 0,
251 lmem_size,
252 min_page_size,
253 io_start,
254 io_size,
255 INTEL_MEMORY_LOCAL,
256 0,
257 &intel_region_lmem_ops);
258 if (IS_ERR(mem))
259 return mem;
260
261 err = reserve_lowmem_region(uncore, mem);
262 if (err)
263 goto err_region_put;
264
265 drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
266 drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
267 &mem->io_start);
268 drm_info(&i915->drm, "Local memory IO size: %pa\n",
269 &mem->io_size);
270 drm_info(&i915->drm, "Local memory available: %pa\n",
271 &lmem_size);
272
273 if (io_size < lmem_size)
274 drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
275 (u64)io_size >> 20);
276
277 return mem;
278
279 err_region_put:
280 intel_memory_region_destroy(mem);
281 return ERR_PTR(err);
282 }
283
intel_gt_setup_lmem(struct intel_gt * gt)284 struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt)
285 {
286 return setup_lmem(gt);
287 }
288