1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30 #include <linux/export.h>
31 #include <linux/i2c-algo-bit.h>
32 #include <linux/i2c.h>
33
34 #include <drm/display/drm_hdcp_helper.h>
35
36 #include "i915_drv.h"
37 #include "intel_de.h"
38 #include "intel_display_types.h"
39 #include "intel_gmbus.h"
40
41 struct intel_gmbus {
42 struct i2c_adapter adapter;
43 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
44 u32 force_bit;
45 u32 reg0;
46 i915_reg_t gpio_reg;
47 struct i2c_algo_bit_data bit_algo;
48 struct drm_i915_private *dev_priv;
49 };
50
51 struct gmbus_pin {
52 const char *name;
53 enum i915_gpio gpio;
54 };
55
56 /* Map gmbus pin pairs to names and registers. */
57 static const struct gmbus_pin gmbus_pins[] = {
58 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
59 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
60 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
61 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
62 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
63 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
64 };
65
66 static const struct gmbus_pin gmbus_pins_bdw[] = {
67 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
68 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
69 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
70 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
71 };
72
73 static const struct gmbus_pin gmbus_pins_skl[] = {
74 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
75 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
76 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
77 };
78
79 static const struct gmbus_pin gmbus_pins_bxt[] = {
80 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
81 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
82 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
83 };
84
85 static const struct gmbus_pin gmbus_pins_cnp[] = {
86 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
87 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
88 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
89 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
90 };
91
92 static const struct gmbus_pin gmbus_pins_icp[] = {
93 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
94 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
95 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
96 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
97 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
98 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
99 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
100 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
101 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
102 };
103
104 static const struct gmbus_pin gmbus_pins_dg1[] = {
105 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
106 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
107 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
108 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
109 };
110
111 static const struct gmbus_pin gmbus_pins_dg2[] = {
112 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
113 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
114 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
115 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
116 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
117 };
118
get_gmbus_pin(struct drm_i915_private * i915,unsigned int pin)119 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
120 unsigned int pin)
121 {
122 const struct gmbus_pin *pins;
123 size_t size;
124
125 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
126 pins = gmbus_pins_dg2;
127 size = ARRAY_SIZE(gmbus_pins_dg2);
128 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
129 pins = gmbus_pins_dg1;
130 size = ARRAY_SIZE(gmbus_pins_dg1);
131 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
132 pins = gmbus_pins_icp;
133 size = ARRAY_SIZE(gmbus_pins_icp);
134 } else if (HAS_PCH_CNP(i915)) {
135 pins = gmbus_pins_cnp;
136 size = ARRAY_SIZE(gmbus_pins_cnp);
137 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
138 pins = gmbus_pins_bxt;
139 size = ARRAY_SIZE(gmbus_pins_bxt);
140 } else if (DISPLAY_VER(i915) == 9) {
141 pins = gmbus_pins_skl;
142 size = ARRAY_SIZE(gmbus_pins_skl);
143 } else if (IS_BROADWELL(i915)) {
144 pins = gmbus_pins_bdw;
145 size = ARRAY_SIZE(gmbus_pins_bdw);
146 } else {
147 pins = gmbus_pins;
148 size = ARRAY_SIZE(gmbus_pins);
149 }
150
151 if (pin >= size || !pins[pin].name)
152 return NULL;
153
154 return &pins[pin];
155 }
156
intel_gmbus_is_valid_pin(struct drm_i915_private * i915,unsigned int pin)157 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
158 {
159 return get_gmbus_pin(i915, pin);
160 }
161
162 /* Intel GPIO access functions */
163
164 #define I2C_RISEFALL_TIME 10
165
166 static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter * i2c)167 to_intel_gmbus(struct i2c_adapter *i2c)
168 {
169 return container_of(i2c, struct intel_gmbus, adapter);
170 }
171
172 void
intel_gmbus_reset(struct drm_i915_private * dev_priv)173 intel_gmbus_reset(struct drm_i915_private *dev_priv)
174 {
175 intel_de_write(dev_priv, GMBUS0, 0);
176 intel_de_write(dev_priv, GMBUS4, 0);
177 }
178
pnv_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)179 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
180 bool enable)
181 {
182 u32 val;
183
184 /* When using bit bashing for I2C, this bit needs to be set to 1 */
185 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
186 if (!enable)
187 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
188 else
189 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
190 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
191 }
192
pch_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)193 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
194 bool enable)
195 {
196 u32 val;
197
198 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
199 if (!enable)
200 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
201 else
202 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
203 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
204 }
205
bxt_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)206 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
207 bool enable)
208 {
209 u32 val;
210
211 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
212 if (!enable)
213 val |= BXT_GMBUS_GATING_DIS;
214 else
215 val &= ~BXT_GMBUS_GATING_DIS;
216 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
217 }
218
get_reserved(struct intel_gmbus * bus)219 static u32 get_reserved(struct intel_gmbus *bus)
220 {
221 struct drm_i915_private *i915 = bus->dev_priv;
222 struct intel_uncore *uncore = &i915->uncore;
223 u32 reserved = 0;
224
225 /* On most chips, these bits must be preserved in software. */
226 if (!IS_I830(i915) && !IS_I845G(i915))
227 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
228 (GPIO_DATA_PULLUP_DISABLE |
229 GPIO_CLOCK_PULLUP_DISABLE);
230
231 return reserved;
232 }
233
get_clock(void * data)234 static int get_clock(void *data)
235 {
236 struct intel_gmbus *bus = data;
237 struct intel_uncore *uncore = &bus->dev_priv->uncore;
238 u32 reserved = get_reserved(bus);
239
240 intel_uncore_write_notrace(uncore,
241 bus->gpio_reg,
242 reserved | GPIO_CLOCK_DIR_MASK);
243 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
244
245 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
246 GPIO_CLOCK_VAL_IN) != 0;
247 }
248
get_data(void * data)249 static int get_data(void *data)
250 {
251 struct intel_gmbus *bus = data;
252 struct intel_uncore *uncore = &bus->dev_priv->uncore;
253 u32 reserved = get_reserved(bus);
254
255 intel_uncore_write_notrace(uncore,
256 bus->gpio_reg,
257 reserved | GPIO_DATA_DIR_MASK);
258 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
259
260 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
261 GPIO_DATA_VAL_IN) != 0;
262 }
263
set_clock(void * data,int state_high)264 static void set_clock(void *data, int state_high)
265 {
266 struct intel_gmbus *bus = data;
267 struct intel_uncore *uncore = &bus->dev_priv->uncore;
268 u32 reserved = get_reserved(bus);
269 u32 clock_bits;
270
271 if (state_high)
272 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
273 else
274 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
275 GPIO_CLOCK_VAL_MASK;
276
277 intel_uncore_write_notrace(uncore,
278 bus->gpio_reg,
279 reserved | clock_bits);
280 intel_uncore_posting_read(uncore, bus->gpio_reg);
281 }
282
set_data(void * data,int state_high)283 static void set_data(void *data, int state_high)
284 {
285 struct intel_gmbus *bus = data;
286 struct intel_uncore *uncore = &bus->dev_priv->uncore;
287 u32 reserved = get_reserved(bus);
288 u32 data_bits;
289
290 if (state_high)
291 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
292 else
293 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
294 GPIO_DATA_VAL_MASK;
295
296 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
297 intel_uncore_posting_read(uncore, bus->gpio_reg);
298 }
299
300 static int
intel_gpio_pre_xfer(struct i2c_adapter * adapter)301 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
302 {
303 struct intel_gmbus *bus = to_intel_gmbus(adapter);
304 struct drm_i915_private *dev_priv = bus->dev_priv;
305
306 intel_gmbus_reset(dev_priv);
307
308 if (IS_PINEVIEW(dev_priv))
309 pnv_gmbus_clock_gating(dev_priv, false);
310
311 set_data(bus, 1);
312 set_clock(bus, 1);
313 udelay(I2C_RISEFALL_TIME);
314 return 0;
315 }
316
317 static void
intel_gpio_post_xfer(struct i2c_adapter * adapter)318 intel_gpio_post_xfer(struct i2c_adapter *adapter)
319 {
320 struct intel_gmbus *bus = to_intel_gmbus(adapter);
321 struct drm_i915_private *dev_priv = bus->dev_priv;
322
323 set_data(bus, 1);
324 set_clock(bus, 1);
325
326 if (IS_PINEVIEW(dev_priv))
327 pnv_gmbus_clock_gating(dev_priv, true);
328 }
329
330 static void
intel_gpio_setup(struct intel_gmbus * bus,i915_reg_t gpio_reg)331 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
332 {
333 struct i2c_algo_bit_data *algo;
334
335 algo = &bus->bit_algo;
336
337 bus->gpio_reg = gpio_reg;
338 bus->adapter.algo_data = algo;
339 algo->setsda = set_data;
340 algo->setscl = set_clock;
341 algo->getsda = get_data;
342 algo->getscl = get_clock;
343 algo->pre_xfer = intel_gpio_pre_xfer;
344 algo->post_xfer = intel_gpio_post_xfer;
345 algo->udelay = I2C_RISEFALL_TIME;
346 algo->timeout = usecs_to_jiffies(2200);
347 algo->data = bus;
348 }
349
has_gmbus_irq(struct drm_i915_private * i915)350 static bool has_gmbus_irq(struct drm_i915_private *i915)
351 {
352 /*
353 * encoder->shutdown() may want to use GMBUS
354 * after irqs have already been disabled.
355 */
356 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
357 }
358
gmbus_wait(struct drm_i915_private * dev_priv,u32 status,u32 irq_en)359 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
360 {
361 DEFINE_WAIT(wait);
362 u32 gmbus2;
363 int ret;
364
365 /* Important: The hw handles only the first bit, so set only one! Since
366 * we also need to check for NAKs besides the hw ready/idle signal, we
367 * need to wake up periodically and check that ourselves.
368 */
369 if (!has_gmbus_irq(dev_priv))
370 irq_en = 0;
371
372 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
373 intel_de_write_fw(dev_priv, GMBUS4, irq_en);
374
375 status |= GMBUS_SATOER;
376 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
377 2);
378 if (ret)
379 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
380 50);
381
382 intel_de_write_fw(dev_priv, GMBUS4, 0);
383 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
384
385 if (gmbus2 & GMBUS_SATOER)
386 return -ENXIO;
387
388 return ret;
389 }
390
391 static int
gmbus_wait_idle(struct drm_i915_private * dev_priv)392 gmbus_wait_idle(struct drm_i915_private *dev_priv)
393 {
394 DEFINE_WAIT(wait);
395 u32 irq_enable;
396 int ret;
397
398 /* Important: The hw handles only the first bit, so set only one! */
399 irq_enable = 0;
400 if (has_gmbus_irq(dev_priv))
401 irq_enable = GMBUS_IDLE_EN;
402
403 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
404 intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
405
406 ret = intel_wait_for_register_fw(&dev_priv->uncore,
407 GMBUS2, GMBUS_ACTIVE, 0,
408 10);
409
410 intel_de_write_fw(dev_priv, GMBUS4, 0);
411 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
412
413 return ret;
414 }
415
gmbus_max_xfer_size(struct drm_i915_private * dev_priv)416 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
417 {
418 return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
419 GMBUS_BYTE_COUNT_MAX;
420 }
421
422 static int
gmbus_xfer_read_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus0_reg,u32 gmbus1_index)423 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
424 unsigned short addr, u8 *buf, unsigned int len,
425 u32 gmbus0_reg, u32 gmbus1_index)
426 {
427 unsigned int size = len;
428 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
429 bool extra_byte_added = false;
430
431 if (burst_read) {
432 /*
433 * As per HW Spec, for 512Bytes need to read extra Byte and
434 * Ignore the extra byte read.
435 */
436 if (len == 512) {
437 extra_byte_added = true;
438 len++;
439 }
440 size = len % 256 + 256;
441 intel_de_write_fw(dev_priv, GMBUS0,
442 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
443 }
444
445 intel_de_write_fw(dev_priv, GMBUS1,
446 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
447 while (len) {
448 int ret;
449 u32 val, loop = 0;
450
451 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
452 if (ret)
453 return ret;
454
455 val = intel_de_read_fw(dev_priv, GMBUS3);
456 do {
457 if (extra_byte_added && len == 1)
458 break;
459
460 *buf++ = val & 0xff;
461 val >>= 8;
462 } while (--len && ++loop < 4);
463
464 if (burst_read && len == size - 4)
465 /* Reset the override bit */
466 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
467 }
468
469 return 0;
470 }
471
472 /*
473 * HW spec says that 512Bytes in Burst read need special treatment.
474 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
475 * an I2C slave, which supports such a lengthy burst read too for experiments.
476 *
477 * So until things get clarified on HW support, to avoid the burst read length
478 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
479 */
480 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
481
482 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus0_reg,u32 gmbus1_index)483 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
484 u32 gmbus0_reg, u32 gmbus1_index)
485 {
486 u8 *buf = msg->buf;
487 unsigned int rx_size = msg->len;
488 unsigned int len;
489 int ret;
490
491 do {
492 if (HAS_GMBUS_BURST_READ(dev_priv))
493 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
494 else
495 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
496
497 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
498 gmbus0_reg, gmbus1_index);
499 if (ret)
500 return ret;
501
502 rx_size -= len;
503 buf += len;
504 } while (rx_size != 0);
505
506 return 0;
507 }
508
509 static int
gmbus_xfer_write_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus1_index)510 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
511 unsigned short addr, u8 *buf, unsigned int len,
512 u32 gmbus1_index)
513 {
514 unsigned int chunk_size = len;
515 u32 val, loop;
516
517 val = loop = 0;
518 while (len && loop < 4) {
519 val |= *buf++ << (8 * loop++);
520 len -= 1;
521 }
522
523 intel_de_write_fw(dev_priv, GMBUS3, val);
524 intel_de_write_fw(dev_priv, GMBUS1,
525 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
526 while (len) {
527 int ret;
528
529 val = loop = 0;
530 do {
531 val |= *buf++ << (8 * loop);
532 } while (--len && ++loop < 4);
533
534 intel_de_write_fw(dev_priv, GMBUS3, val);
535
536 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
537 if (ret)
538 return ret;
539 }
540
541 return 0;
542 }
543
544 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus1_index)545 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
546 u32 gmbus1_index)
547 {
548 u8 *buf = msg->buf;
549 unsigned int tx_size = msg->len;
550 unsigned int len;
551 int ret;
552
553 do {
554 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
555
556 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
557 gmbus1_index);
558 if (ret)
559 return ret;
560
561 buf += len;
562 tx_size -= len;
563 } while (tx_size != 0);
564
565 return 0;
566 }
567
568 /*
569 * The gmbus controller can combine a 1 or 2 byte write with another read/write
570 * that immediately follows it by using an "INDEX" cycle.
571 */
572 static bool
gmbus_is_index_xfer(struct i2c_msg * msgs,int i,int num)573 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
574 {
575 return (i + 1 < num &&
576 msgs[i].addr == msgs[i + 1].addr &&
577 !(msgs[i].flags & I2C_M_RD) &&
578 (msgs[i].len == 1 || msgs[i].len == 2) &&
579 msgs[i + 1].len > 0);
580 }
581
582 static int
gmbus_index_xfer(struct drm_i915_private * dev_priv,struct i2c_msg * msgs,u32 gmbus0_reg)583 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
584 u32 gmbus0_reg)
585 {
586 u32 gmbus1_index = 0;
587 u32 gmbus5 = 0;
588 int ret;
589
590 if (msgs[0].len == 2)
591 gmbus5 = GMBUS_2BYTE_INDEX_EN |
592 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
593 if (msgs[0].len == 1)
594 gmbus1_index = GMBUS_CYCLE_INDEX |
595 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
596
597 /* GMBUS5 holds 16-bit index */
598 if (gmbus5)
599 intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
600
601 if (msgs[1].flags & I2C_M_RD)
602 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
603 gmbus1_index);
604 else
605 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
606
607 /* Clear GMBUS5 after each index transfer */
608 if (gmbus5)
609 intel_de_write_fw(dev_priv, GMBUS5, 0);
610
611 return ret;
612 }
613
614 static int
do_gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,u32 gmbus0_source)615 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
616 u32 gmbus0_source)
617 {
618 struct intel_gmbus *bus = to_intel_gmbus(adapter);
619 struct drm_i915_private *dev_priv = bus->dev_priv;
620 int i = 0, inc, try = 0;
621 int ret = 0;
622
623 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
624 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
625 bxt_gmbus_clock_gating(dev_priv, false);
626 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
627 pch_gmbus_clock_gating(dev_priv, false);
628
629 retry:
630 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
631
632 for (; i < num; i += inc) {
633 inc = 1;
634 if (gmbus_is_index_xfer(msgs, i, num)) {
635 ret = gmbus_index_xfer(dev_priv, &msgs[i],
636 gmbus0_source | bus->reg0);
637 inc = 2; /* an index transmission is two msgs */
638 } else if (msgs[i].flags & I2C_M_RD) {
639 ret = gmbus_xfer_read(dev_priv, &msgs[i],
640 gmbus0_source | bus->reg0, 0);
641 } else {
642 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
643 }
644
645 if (!ret)
646 ret = gmbus_wait(dev_priv,
647 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
648 if (ret == -ETIMEDOUT)
649 goto timeout;
650 else if (ret)
651 goto clear_err;
652 }
653
654 /* Generate a STOP condition on the bus. Note that gmbus can't generata
655 * a STOP on the very first cycle. To simplify the code we
656 * unconditionally generate the STOP condition with an additional gmbus
657 * cycle. */
658 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
659
660 /* Mark the GMBUS interface as disabled after waiting for idle.
661 * We will re-enable it at the start of the next xfer,
662 * till then let it sleep.
663 */
664 if (gmbus_wait_idle(dev_priv)) {
665 drm_dbg_kms(&dev_priv->drm,
666 "GMBUS [%s] timed out waiting for idle\n",
667 adapter->name);
668 ret = -ETIMEDOUT;
669 }
670 intel_de_write_fw(dev_priv, GMBUS0, 0);
671 ret = ret ?: i;
672 goto out;
673
674 clear_err:
675 /*
676 * Wait for bus to IDLE before clearing NAK.
677 * If we clear the NAK while bus is still active, then it will stay
678 * active and the next transaction may fail.
679 *
680 * If no ACK is received during the address phase of a transaction, the
681 * adapter must report -ENXIO. It is not clear what to return if no ACK
682 * is received at other times. But we have to be careful to not return
683 * spurious -ENXIO because that will prevent i2c and drm edid functions
684 * from retrying. So return -ENXIO only when gmbus properly quiescents -
685 * timing out seems to happen when there _is_ a ddc chip present, but
686 * it's slow responding and only answers on the 2nd retry.
687 */
688 ret = -ENXIO;
689 if (gmbus_wait_idle(dev_priv)) {
690 drm_dbg_kms(&dev_priv->drm,
691 "GMBUS [%s] timed out after NAK\n",
692 adapter->name);
693 ret = -ETIMEDOUT;
694 }
695
696 /* Toggle the Software Clear Interrupt bit. This has the effect
697 * of resetting the GMBUS controller and so clearing the
698 * BUS_ERROR raised by the slave's NAK.
699 */
700 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
701 intel_de_write_fw(dev_priv, GMBUS1, 0);
702 intel_de_write_fw(dev_priv, GMBUS0, 0);
703
704 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
705 adapter->name, msgs[i].addr,
706 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
707
708 /*
709 * Passive adapters sometimes NAK the first probe. Retry the first
710 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
711 * has retries internally. See also the retry loop in
712 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
713 */
714 if (ret == -ENXIO && i == 0 && try++ == 0) {
715 drm_dbg_kms(&dev_priv->drm,
716 "GMBUS [%s] NAK on first message, retry\n",
717 adapter->name);
718 goto retry;
719 }
720
721 goto out;
722
723 timeout:
724 drm_dbg_kms(&dev_priv->drm,
725 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
726 bus->adapter.name, bus->reg0 & 0xff);
727 intel_de_write_fw(dev_priv, GMBUS0, 0);
728
729 /*
730 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
731 * instead. Use EAGAIN to have i2c core retry.
732 */
733 ret = -EAGAIN;
734
735 out:
736 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
737 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
738 bxt_gmbus_clock_gating(dev_priv, true);
739 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
740 pch_gmbus_clock_gating(dev_priv, true);
741
742 return ret;
743 }
744
745 static int
gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)746 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
747 {
748 struct intel_gmbus *bus = to_intel_gmbus(adapter);
749 struct drm_i915_private *dev_priv = bus->dev_priv;
750 intel_wakeref_t wakeref;
751 int ret;
752
753 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
754
755 if (bus->force_bit) {
756 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
757 if (ret < 0)
758 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
759 } else {
760 ret = do_gmbus_xfer(adapter, msgs, num, 0);
761 if (ret == -EAGAIN)
762 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
763 }
764
765 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
766
767 return ret;
768 }
769
intel_gmbus_output_aksv(struct i2c_adapter * adapter)770 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
771 {
772 struct intel_gmbus *bus = to_intel_gmbus(adapter);
773 struct drm_i915_private *dev_priv = bus->dev_priv;
774 u8 cmd = DRM_HDCP_DDC_AKSV;
775 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
776 struct i2c_msg msgs[] = {
777 {
778 .addr = DRM_HDCP_DDC_ADDR,
779 .flags = 0,
780 .len = sizeof(cmd),
781 .buf = &cmd,
782 },
783 {
784 .addr = DRM_HDCP_DDC_ADDR,
785 .flags = 0,
786 .len = sizeof(buf),
787 .buf = buf,
788 }
789 };
790 intel_wakeref_t wakeref;
791 int ret;
792
793 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
794 mutex_lock(&dev_priv->gmbus_mutex);
795
796 /*
797 * In order to output Aksv to the receiver, use an indexed write to
798 * pass the i2c command, and tell GMBUS to use the HW-provided value
799 * instead of sourcing GMBUS3 for the data.
800 */
801 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
802
803 mutex_unlock(&dev_priv->gmbus_mutex);
804 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
805
806 return ret;
807 }
808
gmbus_func(struct i2c_adapter * adapter)809 static u32 gmbus_func(struct i2c_adapter *adapter)
810 {
811 return i2c_bit_algo.functionality(adapter) &
812 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
813 /* I2C_FUNC_10BIT_ADDR | */
814 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
815 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
816 }
817
818 static const struct i2c_algorithm gmbus_algorithm = {
819 .master_xfer = gmbus_xfer,
820 .functionality = gmbus_func
821 };
822
gmbus_lock_bus(struct i2c_adapter * adapter,unsigned int flags)823 static void gmbus_lock_bus(struct i2c_adapter *adapter,
824 unsigned int flags)
825 {
826 struct intel_gmbus *bus = to_intel_gmbus(adapter);
827 struct drm_i915_private *dev_priv = bus->dev_priv;
828
829 mutex_lock(&dev_priv->gmbus_mutex);
830 }
831
gmbus_trylock_bus(struct i2c_adapter * adapter,unsigned int flags)832 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
833 unsigned int flags)
834 {
835 struct intel_gmbus *bus = to_intel_gmbus(adapter);
836 struct drm_i915_private *dev_priv = bus->dev_priv;
837
838 return mutex_trylock(&dev_priv->gmbus_mutex);
839 }
840
gmbus_unlock_bus(struct i2c_adapter * adapter,unsigned int flags)841 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
842 unsigned int flags)
843 {
844 struct intel_gmbus *bus = to_intel_gmbus(adapter);
845 struct drm_i915_private *dev_priv = bus->dev_priv;
846
847 mutex_unlock(&dev_priv->gmbus_mutex);
848 }
849
850 static const struct i2c_lock_operations gmbus_lock_ops = {
851 .lock_bus = gmbus_lock_bus,
852 .trylock_bus = gmbus_trylock_bus,
853 .unlock_bus = gmbus_unlock_bus,
854 };
855
856 /**
857 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
858 * @dev_priv: i915 device private
859 */
intel_gmbus_setup(struct drm_i915_private * dev_priv)860 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
861 {
862 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
863 unsigned int pin;
864 int ret;
865
866 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
867 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
868 else if (!HAS_GMCH(dev_priv))
869 /*
870 * Broxton uses the same PCH offsets for South Display Engine,
871 * even though it doesn't have a PCH.
872 */
873 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
874
875 mutex_init(&dev_priv->gmbus_mutex);
876 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
877
878 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
879 const struct gmbus_pin *gmbus_pin;
880 struct intel_gmbus *bus;
881
882 gmbus_pin = get_gmbus_pin(dev_priv, pin);
883 if (!gmbus_pin)
884 continue;
885
886 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
887 if (!bus) {
888 ret = -ENOMEM;
889 goto err;
890 }
891
892 bus->adapter.owner = THIS_MODULE;
893 bus->adapter.class = I2C_CLASS_DDC;
894 snprintf(bus->adapter.name,
895 sizeof(bus->adapter.name),
896 "i915 gmbus %s", gmbus_pin->name);
897
898 bus->adapter.dev.parent = &pdev->dev;
899 bus->dev_priv = dev_priv;
900
901 bus->adapter.algo = &gmbus_algorithm;
902 bus->adapter.lock_ops = &gmbus_lock_ops;
903
904 /*
905 * We wish to retry with bit banging
906 * after a timed out GMBUS attempt.
907 */
908 bus->adapter.retries = 1;
909
910 /* By default use a conservative clock rate */
911 bus->reg0 = pin | GMBUS_RATE_100KHZ;
912
913 /* gmbus seems to be broken on i830 */
914 if (IS_I830(dev_priv))
915 bus->force_bit = 1;
916
917 intel_gpio_setup(bus, GPIO(gmbus_pin->gpio));
918
919 ret = i2c_add_adapter(&bus->adapter);
920 if (ret) {
921 kfree(bus);
922 goto err;
923 }
924
925 dev_priv->gmbus[pin] = bus;
926 }
927
928 intel_gmbus_reset(dev_priv);
929
930 return 0;
931
932 err:
933 intel_gmbus_teardown(dev_priv);
934
935 return ret;
936 }
937
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned int pin)938 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
939 unsigned int pin)
940 {
941 if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->gmbus) ||
942 !dev_priv->gmbus[pin]))
943 return NULL;
944
945 return &dev_priv->gmbus[pin]->adapter;
946 }
947
intel_gmbus_force_bit(struct i2c_adapter * adapter,bool force_bit)948 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
949 {
950 struct intel_gmbus *bus = to_intel_gmbus(adapter);
951 struct drm_i915_private *dev_priv = bus->dev_priv;
952
953 mutex_lock(&dev_priv->gmbus_mutex);
954
955 bus->force_bit += force_bit ? 1 : -1;
956 drm_dbg_kms(&dev_priv->drm,
957 "%sabling bit-banging on %s. force bit now %d\n",
958 force_bit ? "en" : "dis", adapter->name,
959 bus->force_bit);
960
961 mutex_unlock(&dev_priv->gmbus_mutex);
962 }
963
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)964 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
965 {
966 struct intel_gmbus *bus = to_intel_gmbus(adapter);
967
968 return bus->force_bit;
969 }
970
intel_gmbus_teardown(struct drm_i915_private * dev_priv)971 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
972 {
973 unsigned int pin;
974
975 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
976 struct intel_gmbus *bus;
977
978 bus = dev_priv->gmbus[pin];
979 if (!bus)
980 continue;
981
982 i2c_del_adapter(&bus->adapter);
983
984 kfree(bus);
985 dev_priv->gmbus[pin] = NULL;
986 }
987 }
988