1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2016 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include <drm/drm_print.h>
9
10 #include "gem/i915_gem_context.h"
11 #include "gem/i915_gem_internal.h"
12 #include "gt/intel_gt_regs.h"
13
14 #include "i915_cmd_parser.h"
15 #include "i915_drv.h"
16 #include "intel_breadcrumbs.h"
17 #include "intel_context.h"
18 #include "intel_engine.h"
19 #include "intel_engine_pm.h"
20 #include "intel_engine_regs.h"
21 #include "intel_engine_user.h"
22 #include "intel_execlists_submission.h"
23 #include "intel_gt.h"
24 #include "intel_gt_mcr.h"
25 #include "intel_gt_pm.h"
26 #include "intel_gt_requests.h"
27 #include "intel_lrc.h"
28 #include "intel_lrc_reg.h"
29 #include "intel_reset.h"
30 #include "intel_ring.h"
31 #include "uc/intel_guc_submission.h"
32
33 /* Haswell does have the CXT_SIZE register however it does not appear to be
34 * valid. Now, docs explain in dwords what is in the context object. The full
35 * size is 70720 bytes, however, the power context and execlist context will
36 * never be saved (power context is stored elsewhere, and execlists don't work
37 * on HSW) - so the final size, including the extra state required for the
38 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
39 */
40 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
41
42 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
43 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
44 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
45 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
46
47 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
48
49 #define MAX_MMIO_BASES 3
50 struct engine_info {
51 u8 class;
52 u8 instance;
53 /* mmio bases table *must* be sorted in reverse graphics_ver order */
54 struct engine_mmio_base {
55 u32 graphics_ver : 8;
56 u32 base : 24;
57 } mmio_bases[MAX_MMIO_BASES];
58 };
59
60 static const struct engine_info intel_engines[] = {
61 [RCS0] = {
62 .class = RENDER_CLASS,
63 .instance = 0,
64 .mmio_bases = {
65 { .graphics_ver = 1, .base = RENDER_RING_BASE }
66 },
67 },
68 [BCS0] = {
69 .class = COPY_ENGINE_CLASS,
70 .instance = 0,
71 .mmio_bases = {
72 { .graphics_ver = 6, .base = BLT_RING_BASE }
73 },
74 },
75 [BCS1] = {
76 .class = COPY_ENGINE_CLASS,
77 .instance = 1,
78 .mmio_bases = {
79 { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
80 },
81 },
82 [BCS2] = {
83 .class = COPY_ENGINE_CLASS,
84 .instance = 2,
85 .mmio_bases = {
86 { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
87 },
88 },
89 [BCS3] = {
90 .class = COPY_ENGINE_CLASS,
91 .instance = 3,
92 .mmio_bases = {
93 { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
94 },
95 },
96 [BCS4] = {
97 .class = COPY_ENGINE_CLASS,
98 .instance = 4,
99 .mmio_bases = {
100 { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
101 },
102 },
103 [BCS5] = {
104 .class = COPY_ENGINE_CLASS,
105 .instance = 5,
106 .mmio_bases = {
107 { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
108 },
109 },
110 [BCS6] = {
111 .class = COPY_ENGINE_CLASS,
112 .instance = 6,
113 .mmio_bases = {
114 { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
115 },
116 },
117 [BCS7] = {
118 .class = COPY_ENGINE_CLASS,
119 .instance = 7,
120 .mmio_bases = {
121 { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
122 },
123 },
124 [BCS8] = {
125 .class = COPY_ENGINE_CLASS,
126 .instance = 8,
127 .mmio_bases = {
128 { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
129 },
130 },
131 [VCS0] = {
132 .class = VIDEO_DECODE_CLASS,
133 .instance = 0,
134 .mmio_bases = {
135 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
136 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
137 { .graphics_ver = 4, .base = BSD_RING_BASE }
138 },
139 },
140 [VCS1] = {
141 .class = VIDEO_DECODE_CLASS,
142 .instance = 1,
143 .mmio_bases = {
144 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
145 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
146 },
147 },
148 [VCS2] = {
149 .class = VIDEO_DECODE_CLASS,
150 .instance = 2,
151 .mmio_bases = {
152 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
153 },
154 },
155 [VCS3] = {
156 .class = VIDEO_DECODE_CLASS,
157 .instance = 3,
158 .mmio_bases = {
159 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
160 },
161 },
162 [VCS4] = {
163 .class = VIDEO_DECODE_CLASS,
164 .instance = 4,
165 .mmio_bases = {
166 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
167 },
168 },
169 [VCS5] = {
170 .class = VIDEO_DECODE_CLASS,
171 .instance = 5,
172 .mmio_bases = {
173 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
174 },
175 },
176 [VCS6] = {
177 .class = VIDEO_DECODE_CLASS,
178 .instance = 6,
179 .mmio_bases = {
180 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
181 },
182 },
183 [VCS7] = {
184 .class = VIDEO_DECODE_CLASS,
185 .instance = 7,
186 .mmio_bases = {
187 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
188 },
189 },
190 [VECS0] = {
191 .class = VIDEO_ENHANCEMENT_CLASS,
192 .instance = 0,
193 .mmio_bases = {
194 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
195 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
196 },
197 },
198 [VECS1] = {
199 .class = VIDEO_ENHANCEMENT_CLASS,
200 .instance = 1,
201 .mmio_bases = {
202 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
203 },
204 },
205 [VECS2] = {
206 .class = VIDEO_ENHANCEMENT_CLASS,
207 .instance = 2,
208 .mmio_bases = {
209 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
210 },
211 },
212 [VECS3] = {
213 .class = VIDEO_ENHANCEMENT_CLASS,
214 .instance = 3,
215 .mmio_bases = {
216 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
217 },
218 },
219 [CCS0] = {
220 .class = COMPUTE_CLASS,
221 .instance = 0,
222 .mmio_bases = {
223 { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
224 }
225 },
226 [CCS1] = {
227 .class = COMPUTE_CLASS,
228 .instance = 1,
229 .mmio_bases = {
230 { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
231 }
232 },
233 [CCS2] = {
234 .class = COMPUTE_CLASS,
235 .instance = 2,
236 .mmio_bases = {
237 { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
238 }
239 },
240 [CCS3] = {
241 .class = COMPUTE_CLASS,
242 .instance = 3,
243 .mmio_bases = {
244 { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
245 }
246 },
247 };
248
249 /**
250 * intel_engine_context_size() - return the size of the context for an engine
251 * @gt: the gt
252 * @class: engine class
253 *
254 * Each engine class may require a different amount of space for a context
255 * image.
256 *
257 * Return: size (in bytes) of an engine class specific context image
258 *
259 * Note: this size includes the HWSP, which is part of the context image
260 * in LRC mode, but does not include the "shared data page" used with
261 * GuC submission. The caller should account for this if using the GuC.
262 */
intel_engine_context_size(struct intel_gt * gt,u8 class)263 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
264 {
265 struct intel_uncore *uncore = gt->uncore;
266 u32 cxt_size;
267
268 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
269
270 switch (class) {
271 case COMPUTE_CLASS:
272 fallthrough;
273 case RENDER_CLASS:
274 switch (GRAPHICS_VER(gt->i915)) {
275 default:
276 MISSING_CASE(GRAPHICS_VER(gt->i915));
277 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
278 case 12:
279 case 11:
280 return GEN11_LR_CONTEXT_RENDER_SIZE;
281 case 9:
282 return GEN9_LR_CONTEXT_RENDER_SIZE;
283 case 8:
284 return GEN8_LR_CONTEXT_RENDER_SIZE;
285 case 7:
286 if (IS_HASWELL(gt->i915))
287 return HSW_CXT_TOTAL_SIZE;
288
289 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
290 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
291 PAGE_SIZE);
292 case 6:
293 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
294 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
295 PAGE_SIZE);
296 case 5:
297 case 4:
298 /*
299 * There is a discrepancy here between the size reported
300 * by the register and the size of the context layout
301 * in the docs. Both are described as authorative!
302 *
303 * The discrepancy is on the order of a few cachelines,
304 * but the total is under one page (4k), which is our
305 * minimum allocation anyway so it should all come
306 * out in the wash.
307 */
308 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
309 drm_dbg(>->i915->drm,
310 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
311 GRAPHICS_VER(gt->i915), cxt_size * 64,
312 cxt_size - 1);
313 return round_up(cxt_size * 64, PAGE_SIZE);
314 case 3:
315 case 2:
316 /* For the special day when i810 gets merged. */
317 case 1:
318 return 0;
319 }
320 break;
321 default:
322 MISSING_CASE(class);
323 fallthrough;
324 case VIDEO_DECODE_CLASS:
325 case VIDEO_ENHANCEMENT_CLASS:
326 case COPY_ENGINE_CLASS:
327 if (GRAPHICS_VER(gt->i915) < 8)
328 return 0;
329 return GEN8_LR_CONTEXT_OTHER_SIZE;
330 }
331 }
332
__engine_mmio_base(struct drm_i915_private * i915,const struct engine_mmio_base * bases)333 static u32 __engine_mmio_base(struct drm_i915_private *i915,
334 const struct engine_mmio_base *bases)
335 {
336 int i;
337
338 for (i = 0; i < MAX_MMIO_BASES; i++)
339 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
340 break;
341
342 GEM_BUG_ON(i == MAX_MMIO_BASES);
343 GEM_BUG_ON(!bases[i].base);
344
345 return bases[i].base;
346 }
347
__sprint_engine_name(struct intel_engine_cs * engine)348 static void __sprint_engine_name(struct intel_engine_cs *engine)
349 {
350 /*
351 * Before we know what the uABI name for this engine will be,
352 * we still would like to keep track of this engine in the debug logs.
353 * We throw in a ' here as a reminder that this isn't its final name.
354 */
355 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
356 intel_engine_class_repr(engine->class),
357 engine->instance) >= sizeof(engine->name));
358 }
359
intel_engine_set_hwsp_writemask(struct intel_engine_cs * engine,u32 mask)360 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
361 {
362 /*
363 * Though they added more rings on g4x/ilk, they did not add
364 * per-engine HWSTAM until gen6.
365 */
366 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
367 return;
368
369 if (GRAPHICS_VER(engine->i915) >= 3)
370 ENGINE_WRITE(engine, RING_HWSTAM, mask);
371 else
372 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
373 }
374
intel_engine_sanitize_mmio(struct intel_engine_cs * engine)375 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
376 {
377 /* Mask off all writes into the unknown HWSP */
378 intel_engine_set_hwsp_writemask(engine, ~0u);
379 }
380
nop_irq_handler(struct intel_engine_cs * engine,u16 iir)381 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
382 {
383 GEM_DEBUG_WARN_ON(iir);
384 }
385
get_reset_domain(u8 ver,enum intel_engine_id id)386 static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
387 {
388 u32 reset_domain;
389
390 if (ver >= 11) {
391 static const u32 engine_reset_domains[] = {
392 [RCS0] = GEN11_GRDOM_RENDER,
393 [BCS0] = GEN11_GRDOM_BLT,
394 [BCS1] = XEHPC_GRDOM_BLT1,
395 [BCS2] = XEHPC_GRDOM_BLT2,
396 [BCS3] = XEHPC_GRDOM_BLT3,
397 [BCS4] = XEHPC_GRDOM_BLT4,
398 [BCS5] = XEHPC_GRDOM_BLT5,
399 [BCS6] = XEHPC_GRDOM_BLT6,
400 [BCS7] = XEHPC_GRDOM_BLT7,
401 [BCS8] = XEHPC_GRDOM_BLT8,
402 [VCS0] = GEN11_GRDOM_MEDIA,
403 [VCS1] = GEN11_GRDOM_MEDIA2,
404 [VCS2] = GEN11_GRDOM_MEDIA3,
405 [VCS3] = GEN11_GRDOM_MEDIA4,
406 [VCS4] = GEN11_GRDOM_MEDIA5,
407 [VCS5] = GEN11_GRDOM_MEDIA6,
408 [VCS6] = GEN11_GRDOM_MEDIA7,
409 [VCS7] = GEN11_GRDOM_MEDIA8,
410 [VECS0] = GEN11_GRDOM_VECS,
411 [VECS1] = GEN11_GRDOM_VECS2,
412 [VECS2] = GEN11_GRDOM_VECS3,
413 [VECS3] = GEN11_GRDOM_VECS4,
414 [CCS0] = GEN11_GRDOM_RENDER,
415 [CCS1] = GEN11_GRDOM_RENDER,
416 [CCS2] = GEN11_GRDOM_RENDER,
417 [CCS3] = GEN11_GRDOM_RENDER,
418 };
419 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
420 !engine_reset_domains[id]);
421 reset_domain = engine_reset_domains[id];
422 } else {
423 static const u32 engine_reset_domains[] = {
424 [RCS0] = GEN6_GRDOM_RENDER,
425 [BCS0] = GEN6_GRDOM_BLT,
426 [VCS0] = GEN6_GRDOM_MEDIA,
427 [VCS1] = GEN8_GRDOM_MEDIA2,
428 [VECS0] = GEN6_GRDOM_VECS,
429 };
430 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
431 !engine_reset_domains[id]);
432 reset_domain = engine_reset_domains[id];
433 }
434
435 return reset_domain;
436 }
437
intel_engine_setup(struct intel_gt * gt,enum intel_engine_id id,u8 logical_instance)438 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
439 u8 logical_instance)
440 {
441 const struct engine_info *info = &intel_engines[id];
442 struct drm_i915_private *i915 = gt->i915;
443 struct intel_engine_cs *engine;
444 u8 guc_class;
445
446 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
447 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
448 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
449 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
450
451 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
452 return -EINVAL;
453
454 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
455 return -EINVAL;
456
457 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
458 return -EINVAL;
459
460 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
461 return -EINVAL;
462
463 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
464 if (!engine)
465 return -ENOMEM;
466
467 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
468
469 INIT_LIST_HEAD(&engine->pinned_contexts_list);
470 engine->id = id;
471 engine->legacy_idx = INVALID_ENGINE;
472 engine->mask = BIT(id);
473 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
474 id);
475 engine->i915 = i915;
476 engine->gt = gt;
477 engine->uncore = gt->uncore;
478 guc_class = engine_class_to_guc_class(info->class);
479 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
480 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
481
482 engine->irq_handler = nop_irq_handler;
483
484 engine->class = info->class;
485 engine->instance = info->instance;
486 engine->logical_mask = BIT(logical_instance);
487 __sprint_engine_name(engine);
488
489 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
490 __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
491 engine->class == RENDER_CLASS)
492 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
493
494 /* features common between engines sharing EUs */
495 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
496 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
497 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
498 }
499
500 engine->props.heartbeat_interval_ms =
501 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
502 engine->props.max_busywait_duration_ns =
503 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
504 engine->props.preempt_timeout_ms =
505 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
506 engine->props.stop_timeout_ms =
507 CONFIG_DRM_I915_STOP_TIMEOUT;
508 engine->props.timeslice_duration_ms =
509 CONFIG_DRM_I915_TIMESLICE_DURATION;
510
511 /* Override to uninterruptible for OpenCL workloads. */
512 if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
513 engine->props.preempt_timeout_ms = 0;
514
515 /* Cap properties according to any system limits */
516 #define CLAMP_PROP(field) \
517 do { \
518 u64 clamp = intel_clamp_##field(engine, engine->props.field); \
519 if (clamp != engine->props.field) { \
520 drm_notice(&engine->i915->drm, \
521 "Warning, clamping %s to %lld to prevent overflow\n", \
522 #field, clamp); \
523 engine->props.field = clamp; \
524 } \
525 } while (0)
526
527 CLAMP_PROP(heartbeat_interval_ms);
528 CLAMP_PROP(max_busywait_duration_ns);
529 CLAMP_PROP(preempt_timeout_ms);
530 CLAMP_PROP(stop_timeout_ms);
531 CLAMP_PROP(timeslice_duration_ms);
532
533 #undef CLAMP_PROP
534
535 engine->defaults = engine->props; /* never to change again */
536
537 engine->context_size = intel_engine_context_size(gt, engine->class);
538 if (WARN_ON(engine->context_size > BIT(20)))
539 engine->context_size = 0;
540 if (engine->context_size)
541 DRIVER_CAPS(i915)->has_logical_contexts = true;
542
543 ewma__engine_latency_init(&engine->latency);
544 seqcount_init(&engine->stats.execlists.lock);
545
546 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
547
548 /* Scrub mmio state on takeover */
549 intel_engine_sanitize_mmio(engine);
550
551 gt->engine_class[info->class][info->instance] = engine;
552 gt->engine[id] = engine;
553
554 return 0;
555 }
556
intel_clamp_heartbeat_interval_ms(struct intel_engine_cs * engine,u64 value)557 u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)
558 {
559 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
560
561 return value;
562 }
563
intel_clamp_max_busywait_duration_ns(struct intel_engine_cs * engine,u64 value)564 u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)
565 {
566 value = min(value, jiffies_to_nsecs(2));
567
568 return value;
569 }
570
intel_clamp_preempt_timeout_ms(struct intel_engine_cs * engine,u64 value)571 u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)
572 {
573 /*
574 * NB: The GuC API only supports 32bit values. However, the limit is further
575 * reduced due to internal calculations which would otherwise overflow.
576 */
577 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
578 value = min_t(u64, value, guc_policy_max_preempt_timeout_ms());
579
580 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
581
582 return value;
583 }
584
intel_clamp_stop_timeout_ms(struct intel_engine_cs * engine,u64 value)585 u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)
586 {
587 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
588
589 return value;
590 }
591
intel_clamp_timeslice_duration_ms(struct intel_engine_cs * engine,u64 value)592 u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)
593 {
594 /*
595 * NB: The GuC API only supports 32bit values. However, the limit is further
596 * reduced due to internal calculations which would otherwise overflow.
597 */
598 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
599 value = min_t(u64, value, guc_policy_max_exec_quantum_ms());
600
601 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
602
603 return value;
604 }
605
__setup_engine_capabilities(struct intel_engine_cs * engine)606 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
607 {
608 struct drm_i915_private *i915 = engine->i915;
609
610 if (engine->class == VIDEO_DECODE_CLASS) {
611 /*
612 * HEVC support is present on first engine instance
613 * before Gen11 and on all instances afterwards.
614 */
615 if (GRAPHICS_VER(i915) >= 11 ||
616 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
617 engine->uabi_capabilities |=
618 I915_VIDEO_CLASS_CAPABILITY_HEVC;
619
620 /*
621 * SFC block is present only on even logical engine
622 * instances.
623 */
624 if ((GRAPHICS_VER(i915) >= 11 &&
625 (engine->gt->info.vdbox_sfc_access &
626 BIT(engine->instance))) ||
627 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
628 engine->uabi_capabilities |=
629 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
630 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
631 if (GRAPHICS_VER(i915) >= 9 &&
632 engine->gt->info.sfc_mask & BIT(engine->instance))
633 engine->uabi_capabilities |=
634 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
635 }
636 }
637
intel_setup_engine_capabilities(struct intel_gt * gt)638 static void intel_setup_engine_capabilities(struct intel_gt *gt)
639 {
640 struct intel_engine_cs *engine;
641 enum intel_engine_id id;
642
643 for_each_engine(engine, gt, id)
644 __setup_engine_capabilities(engine);
645 }
646
647 /**
648 * intel_engines_release() - free the resources allocated for Command Streamers
649 * @gt: pointer to struct intel_gt
650 */
intel_engines_release(struct intel_gt * gt)651 void intel_engines_release(struct intel_gt *gt)
652 {
653 struct intel_engine_cs *engine;
654 enum intel_engine_id id;
655
656 /*
657 * Before we release the resources held by engine, we must be certain
658 * that the HW is no longer accessing them -- having the GPU scribble
659 * to or read from a page being used for something else causes no end
660 * of fun.
661 *
662 * The GPU should be reset by this point, but assume the worst just
663 * in case we aborted before completely initialising the engines.
664 */
665 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
666 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
667 __intel_gt_reset(gt, ALL_ENGINES);
668
669 /* Decouple the backend; but keep the layout for late GPU resets */
670 for_each_engine(engine, gt, id) {
671 if (!engine->release)
672 continue;
673
674 intel_wakeref_wait_for_idle(&engine->wakeref);
675 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
676
677 engine->release(engine);
678 engine->release = NULL;
679
680 memset(&engine->reset, 0, sizeof(engine->reset));
681 }
682 }
683
intel_engine_free_request_pool(struct intel_engine_cs * engine)684 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
685 {
686 if (!engine->request_pool)
687 return;
688
689 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
690 }
691
intel_engines_free(struct intel_gt * gt)692 void intel_engines_free(struct intel_gt *gt)
693 {
694 struct intel_engine_cs *engine;
695 enum intel_engine_id id;
696
697 /* Free the requests! dma-resv keeps fences around for an eternity */
698 rcu_barrier();
699
700 for_each_engine(engine, gt, id) {
701 intel_engine_free_request_pool(engine);
702 kfree(engine);
703 gt->engine[id] = NULL;
704 }
705 }
706
707 static
gen11_vdbox_has_sfc(struct intel_gt * gt,unsigned int physical_vdbox,unsigned int logical_vdbox,u16 vdbox_mask)708 bool gen11_vdbox_has_sfc(struct intel_gt *gt,
709 unsigned int physical_vdbox,
710 unsigned int logical_vdbox, u16 vdbox_mask)
711 {
712 struct drm_i915_private *i915 = gt->i915;
713
714 /*
715 * In Gen11, only even numbered logical VDBOXes are hooked
716 * up to an SFC (Scaler & Format Converter) unit.
717 * In Gen12, Even numbered physical instance always are connected
718 * to an SFC. Odd numbered physical instances have SFC only if
719 * previous even instance is fused off.
720 *
721 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
722 * in the fuse register that tells us whether a specific SFC is present.
723 */
724 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
725 return false;
726 else if (MEDIA_VER(i915) >= 12)
727 return (physical_vdbox % 2 == 0) ||
728 !(BIT(physical_vdbox - 1) & vdbox_mask);
729 else if (MEDIA_VER(i915) == 11)
730 return logical_vdbox % 2 == 0;
731
732 return false;
733 }
734
engine_mask_apply_media_fuses(struct intel_gt * gt)735 static void engine_mask_apply_media_fuses(struct intel_gt *gt)
736 {
737 struct drm_i915_private *i915 = gt->i915;
738 unsigned int logical_vdbox = 0;
739 unsigned int i;
740 u32 media_fuse, fuse1;
741 u16 vdbox_mask;
742 u16 vebox_mask;
743
744 if (MEDIA_VER(gt->i915) < 11)
745 return;
746
747 /*
748 * On newer platforms the fusing register is called 'enable' and has
749 * enable semantics, while on older platforms it is called 'disable'
750 * and bits have disable semantices.
751 */
752 media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
753 if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
754 media_fuse = ~media_fuse;
755
756 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
757 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
758 GEN11_GT_VEBOX_DISABLE_SHIFT;
759
760 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
761 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
762 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
763 } else {
764 gt->info.sfc_mask = ~0;
765 }
766
767 for (i = 0; i < I915_MAX_VCS; i++) {
768 if (!HAS_ENGINE(gt, _VCS(i))) {
769 vdbox_mask &= ~BIT(i);
770 continue;
771 }
772
773 if (!(BIT(i) & vdbox_mask)) {
774 gt->info.engine_mask &= ~BIT(_VCS(i));
775 drm_dbg(&i915->drm, "vcs%u fused off\n", i);
776 continue;
777 }
778
779 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
780 gt->info.vdbox_sfc_access |= BIT(i);
781 logical_vdbox++;
782 }
783 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
784 vdbox_mask, VDBOX_MASK(gt));
785 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
786
787 for (i = 0; i < I915_MAX_VECS; i++) {
788 if (!HAS_ENGINE(gt, _VECS(i))) {
789 vebox_mask &= ~BIT(i);
790 continue;
791 }
792
793 if (!(BIT(i) & vebox_mask)) {
794 gt->info.engine_mask &= ~BIT(_VECS(i));
795 drm_dbg(&i915->drm, "vecs%u fused off\n", i);
796 }
797 }
798 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
799 vebox_mask, VEBOX_MASK(gt));
800 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
801 }
802
engine_mask_apply_compute_fuses(struct intel_gt * gt)803 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
804 {
805 struct drm_i915_private *i915 = gt->i915;
806 struct intel_gt_info *info = >->info;
807 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
808 unsigned long ccs_mask;
809 unsigned int i;
810
811 if (GRAPHICS_VER(i915) < 11)
812 return;
813
814 if (hweight32(CCS_MASK(gt)) <= 1)
815 return;
816
817 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
818 ss_per_ccs);
819 /*
820 * If all DSS in a quadrant are fused off, the corresponding CCS
821 * engine is not available for use.
822 */
823 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
824 info->engine_mask &= ~BIT(_CCS(i));
825 drm_dbg(&i915->drm, "ccs%u fused off\n", i);
826 }
827 }
828
engine_mask_apply_copy_fuses(struct intel_gt * gt)829 static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
830 {
831 struct drm_i915_private *i915 = gt->i915;
832 struct intel_gt_info *info = >->info;
833 unsigned long meml3_mask;
834 unsigned long quad;
835
836 if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
837 GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
838 return;
839
840 meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
841 meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
842
843 /*
844 * Link Copy engines may be fused off according to meml3_mask. Each
845 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
846 */
847 for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
848 unsigned int instance = quad * 2 + 1;
849 intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
850 _BCS(instance));
851
852 if (mask & info->engine_mask) {
853 drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
854 drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
855
856 info->engine_mask &= ~mask;
857 }
858 }
859 }
860
861 /*
862 * Determine which engines are fused off in our particular hardware.
863 * Note that we have a catch-22 situation where we need to be able to access
864 * the blitter forcewake domain to read the engine fuses, but at the same time
865 * we need to know which engines are available on the system to know which
866 * forcewake domains are present. We solve this by intializing the forcewake
867 * domains based on the full engine mask in the platform capabilities before
868 * calling this function and pruning the domains for fused-off engines
869 * afterwards.
870 */
init_engine_mask(struct intel_gt * gt)871 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
872 {
873 struct intel_gt_info *info = >->info;
874
875 GEM_BUG_ON(!info->engine_mask);
876
877 engine_mask_apply_media_fuses(gt);
878 engine_mask_apply_compute_fuses(gt);
879 engine_mask_apply_copy_fuses(gt);
880
881 return info->engine_mask;
882 }
883
populate_logical_ids(struct intel_gt * gt,u8 * logical_ids,u8 class,const u8 * map,u8 num_instances)884 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
885 u8 class, const u8 *map, u8 num_instances)
886 {
887 int i, j;
888 u8 current_logical_id = 0;
889
890 for (j = 0; j < num_instances; ++j) {
891 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
892 if (!HAS_ENGINE(gt, i) ||
893 intel_engines[i].class != class)
894 continue;
895
896 if (intel_engines[i].instance == map[j]) {
897 logical_ids[intel_engines[i].instance] =
898 current_logical_id++;
899 break;
900 }
901 }
902 }
903 }
904
setup_logical_ids(struct intel_gt * gt,u8 * logical_ids,u8 class)905 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
906 {
907 /*
908 * Logical to physical mapping is needed for proper support
909 * to split-frame feature.
910 */
911 if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
912 const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
913
914 populate_logical_ids(gt, logical_ids, class,
915 map, ARRAY_SIZE(map));
916 } else {
917 int i;
918 u8 map[MAX_ENGINE_INSTANCE + 1];
919
920 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
921 map[i] = i;
922 populate_logical_ids(gt, logical_ids, class,
923 map, ARRAY_SIZE(map));
924 }
925 }
926
927 /**
928 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
929 * @gt: pointer to struct intel_gt
930 *
931 * Return: non-zero if the initialization failed.
932 */
intel_engines_init_mmio(struct intel_gt * gt)933 int intel_engines_init_mmio(struct intel_gt *gt)
934 {
935 struct drm_i915_private *i915 = gt->i915;
936 const unsigned int engine_mask = init_engine_mask(gt);
937 unsigned int mask = 0;
938 unsigned int i, class;
939 u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
940 int err;
941
942 drm_WARN_ON(&i915->drm, engine_mask == 0);
943 drm_WARN_ON(&i915->drm, engine_mask &
944 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
945
946 if (i915_inject_probe_failure(i915))
947 return -ENODEV;
948
949 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
950 setup_logical_ids(gt, logical_ids, class);
951
952 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
953 u8 instance = intel_engines[i].instance;
954
955 if (intel_engines[i].class != class ||
956 !HAS_ENGINE(gt, i))
957 continue;
958
959 err = intel_engine_setup(gt, i,
960 logical_ids[instance]);
961 if (err)
962 goto cleanup;
963
964 mask |= BIT(i);
965 }
966 }
967
968 /*
969 * Catch failures to update intel_engines table when the new engines
970 * are added to the driver by a warning and disabling the forgotten
971 * engines.
972 */
973 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
974 gt->info.engine_mask = mask;
975
976 gt->info.num_engines = hweight32(mask);
977
978 intel_gt_check_and_clear_faults(gt);
979
980 intel_setup_engine_capabilities(gt);
981
982 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
983
984 return 0;
985
986 cleanup:
987 intel_engines_free(gt);
988 return err;
989 }
990
intel_engine_init_execlists(struct intel_engine_cs * engine)991 void intel_engine_init_execlists(struct intel_engine_cs *engine)
992 {
993 struct intel_engine_execlists * const execlists = &engine->execlists;
994
995 execlists->port_mask = 1;
996 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
997 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
998
999 memset(execlists->pending, 0, sizeof(execlists->pending));
1000 execlists->active =
1001 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1002 }
1003
cleanup_status_page(struct intel_engine_cs * engine)1004 static void cleanup_status_page(struct intel_engine_cs *engine)
1005 {
1006 struct i915_vma *vma;
1007
1008 /* Prevent writes into HWSP after returning the page to the system */
1009 intel_engine_set_hwsp_writemask(engine, ~0u);
1010
1011 vma = fetch_and_zero(&engine->status_page.vma);
1012 if (!vma)
1013 return;
1014
1015 if (!HWS_NEEDS_PHYSICAL(engine->i915))
1016 i915_vma_unpin(vma);
1017
1018 i915_gem_object_unpin_map(vma->obj);
1019 i915_gem_object_put(vma->obj);
1020 }
1021
pin_ggtt_status_page(struct intel_engine_cs * engine,struct i915_gem_ww_ctx * ww,struct i915_vma * vma)1022 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
1023 struct i915_gem_ww_ctx *ww,
1024 struct i915_vma *vma)
1025 {
1026 unsigned int flags;
1027
1028 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
1029 /*
1030 * On g33, we cannot place HWS above 256MiB, so
1031 * restrict its pinning to the low mappable arena.
1032 * Though this restriction is not documented for
1033 * gen4, gen5, or byt, they also behave similarly
1034 * and hang if the HWS is placed at the top of the
1035 * GTT. To generalise, it appears that all !llc
1036 * platforms have issues with us placing the HWS
1037 * above the mappable region (even though we never
1038 * actually map it).
1039 */
1040 flags = PIN_MAPPABLE;
1041 else
1042 flags = PIN_HIGH;
1043
1044 return i915_ggtt_pin(vma, ww, 0, flags);
1045 }
1046
init_status_page(struct intel_engine_cs * engine)1047 static int init_status_page(struct intel_engine_cs *engine)
1048 {
1049 struct drm_i915_gem_object *obj;
1050 struct i915_gem_ww_ctx ww;
1051 struct i915_vma *vma;
1052 void *vaddr;
1053 int ret;
1054
1055 INIT_LIST_HEAD(&engine->status_page.timelines);
1056
1057 /*
1058 * Though the HWS register does support 36bit addresses, historically
1059 * we have had hangs and corruption reported due to wild writes if
1060 * the HWS is placed above 4G. We only allow objects to be allocated
1061 * in GFP_DMA32 for i965, and no earlier physical address users had
1062 * access to more than 4G.
1063 */
1064 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
1065 if (IS_ERR(obj)) {
1066 drm_err(&engine->i915->drm,
1067 "Failed to allocate status page\n");
1068 return PTR_ERR(obj);
1069 }
1070
1071 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1072
1073 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1074 if (IS_ERR(vma)) {
1075 ret = PTR_ERR(vma);
1076 goto err_put;
1077 }
1078
1079 i915_gem_ww_ctx_init(&ww, true);
1080 retry:
1081 ret = i915_gem_object_lock(obj, &ww);
1082 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1083 ret = pin_ggtt_status_page(engine, &ww, vma);
1084 if (ret)
1085 goto err;
1086
1087 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1088 if (IS_ERR(vaddr)) {
1089 ret = PTR_ERR(vaddr);
1090 goto err_unpin;
1091 }
1092
1093 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1094 engine->status_page.vma = vma;
1095
1096 err_unpin:
1097 if (ret)
1098 i915_vma_unpin(vma);
1099 err:
1100 if (ret == -EDEADLK) {
1101 ret = i915_gem_ww_ctx_backoff(&ww);
1102 if (!ret)
1103 goto retry;
1104 }
1105 i915_gem_ww_ctx_fini(&ww);
1106 err_put:
1107 if (ret)
1108 i915_gem_object_put(obj);
1109 return ret;
1110 }
1111
engine_setup_common(struct intel_engine_cs * engine)1112 static int engine_setup_common(struct intel_engine_cs *engine)
1113 {
1114 int err;
1115
1116 init_llist_head(&engine->barrier_tasks);
1117
1118 err = init_status_page(engine);
1119 if (err)
1120 return err;
1121
1122 engine->breadcrumbs = intel_breadcrumbs_create(engine);
1123 if (!engine->breadcrumbs) {
1124 err = -ENOMEM;
1125 goto err_status;
1126 }
1127
1128 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1129 if (!engine->sched_engine) {
1130 err = -ENOMEM;
1131 goto err_sched_engine;
1132 }
1133 engine->sched_engine->private_data = engine;
1134
1135 err = intel_engine_init_cmd_parser(engine);
1136 if (err)
1137 goto err_cmd_parser;
1138
1139 intel_engine_init_execlists(engine);
1140 intel_engine_init__pm(engine);
1141 intel_engine_init_retire(engine);
1142
1143 /* Use the whole device by default */
1144 engine->sseu =
1145 intel_sseu_from_device_info(&engine->gt->info.sseu);
1146
1147 intel_engine_init_workarounds(engine);
1148 intel_engine_init_whitelist(engine);
1149 intel_engine_init_ctx_wa(engine);
1150
1151 if (GRAPHICS_VER(engine->i915) >= 12)
1152 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1153
1154 return 0;
1155
1156 err_cmd_parser:
1157 i915_sched_engine_put(engine->sched_engine);
1158 err_sched_engine:
1159 intel_breadcrumbs_put(engine->breadcrumbs);
1160 err_status:
1161 cleanup_status_page(engine);
1162 return err;
1163 }
1164
1165 struct measure_breadcrumb {
1166 struct i915_request rq;
1167 struct intel_ring ring;
1168 u32 cs[2048];
1169 };
1170
measure_breadcrumb_dw(struct intel_context * ce)1171 static int measure_breadcrumb_dw(struct intel_context *ce)
1172 {
1173 struct intel_engine_cs *engine = ce->engine;
1174 struct measure_breadcrumb *frame;
1175 int dw;
1176
1177 GEM_BUG_ON(!engine->gt->scratch);
1178
1179 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1180 if (!frame)
1181 return -ENOMEM;
1182
1183 frame->rq.engine = engine;
1184 frame->rq.context = ce;
1185 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1186 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1187
1188 frame->ring.vaddr = frame->cs;
1189 frame->ring.size = sizeof(frame->cs);
1190 frame->ring.wrap =
1191 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1192 frame->ring.effective_size = frame->ring.size;
1193 intel_ring_update_space(&frame->ring);
1194 frame->rq.ring = &frame->ring;
1195
1196 mutex_lock(&ce->timeline->mutex);
1197 spin_lock_irq(&engine->sched_engine->lock);
1198
1199 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1200
1201 spin_unlock_irq(&engine->sched_engine->lock);
1202 mutex_unlock(&ce->timeline->mutex);
1203
1204 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1205
1206 kfree(frame);
1207 return dw;
1208 }
1209
1210 struct intel_context *
intel_engine_create_pinned_context(struct intel_engine_cs * engine,struct i915_address_space * vm,unsigned int ring_size,unsigned int hwsp,struct lock_class_key * key,const char * name)1211 intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1212 struct i915_address_space *vm,
1213 unsigned int ring_size,
1214 unsigned int hwsp,
1215 struct lock_class_key *key,
1216 const char *name)
1217 {
1218 struct intel_context *ce;
1219 int err;
1220
1221 ce = intel_context_create(engine);
1222 if (IS_ERR(ce))
1223 return ce;
1224
1225 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1226 ce->timeline = page_pack_bits(NULL, hwsp);
1227 ce->ring = NULL;
1228 ce->ring_size = ring_size;
1229
1230 i915_vm_put(ce->vm);
1231 ce->vm = i915_vm_get(vm);
1232
1233 err = intel_context_pin(ce); /* perma-pin so it is always available */
1234 if (err) {
1235 intel_context_put(ce);
1236 return ERR_PTR(err);
1237 }
1238
1239 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1240
1241 /*
1242 * Give our perma-pinned kernel timelines a separate lockdep class,
1243 * so that we can use them from within the normal user timelines
1244 * should we need to inject GPU operations during their request
1245 * construction.
1246 */
1247 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1248
1249 return ce;
1250 }
1251
intel_engine_destroy_pinned_context(struct intel_context * ce)1252 void intel_engine_destroy_pinned_context(struct intel_context *ce)
1253 {
1254 struct intel_engine_cs *engine = ce->engine;
1255 struct i915_vma *hwsp = engine->status_page.vma;
1256
1257 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1258
1259 mutex_lock(&hwsp->vm->mutex);
1260 list_del(&ce->timeline->engine_link);
1261 mutex_unlock(&hwsp->vm->mutex);
1262
1263 list_del(&ce->pinned_contexts_link);
1264 intel_context_unpin(ce);
1265 intel_context_put(ce);
1266 }
1267
1268 static struct intel_context *
create_kernel_context(struct intel_engine_cs * engine)1269 create_kernel_context(struct intel_engine_cs *engine)
1270 {
1271 static struct lock_class_key kernel;
1272
1273 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1274 I915_GEM_HWS_SEQNO_ADDR,
1275 &kernel, "kernel_context");
1276 }
1277
1278 /**
1279 * intel_engines_init_common - initialize cengine state which might require hw access
1280 * @engine: Engine to initialize.
1281 *
1282 * Initializes @engine@ structure members shared between legacy and execlists
1283 * submission modes which do require hardware access.
1284 *
1285 * Typcally done at later stages of submission mode specific engine setup.
1286 *
1287 * Returns zero on success or an error code on failure.
1288 */
engine_init_common(struct intel_engine_cs * engine)1289 static int engine_init_common(struct intel_engine_cs *engine)
1290 {
1291 struct intel_context *ce;
1292 int ret;
1293
1294 engine->set_default_submission(engine);
1295
1296 /*
1297 * We may need to do things with the shrinker which
1298 * require us to immediately switch back to the default
1299 * context. This can cause a problem as pinning the
1300 * default context also requires GTT space which may not
1301 * be available. To avoid this we always pin the default
1302 * context.
1303 */
1304 ce = create_kernel_context(engine);
1305 if (IS_ERR(ce))
1306 return PTR_ERR(ce);
1307
1308 ret = measure_breadcrumb_dw(ce);
1309 if (ret < 0)
1310 goto err_context;
1311
1312 engine->emit_fini_breadcrumb_dw = ret;
1313 engine->kernel_context = ce;
1314
1315 return 0;
1316
1317 err_context:
1318 intel_engine_destroy_pinned_context(ce);
1319 return ret;
1320 }
1321
intel_engines_init(struct intel_gt * gt)1322 int intel_engines_init(struct intel_gt *gt)
1323 {
1324 int (*setup)(struct intel_engine_cs *engine);
1325 struct intel_engine_cs *engine;
1326 enum intel_engine_id id;
1327 int err;
1328
1329 if (intel_uc_uses_guc_submission(>->uc)) {
1330 gt->submission_method = INTEL_SUBMISSION_GUC;
1331 setup = intel_guc_submission_setup;
1332 } else if (HAS_EXECLISTS(gt->i915)) {
1333 gt->submission_method = INTEL_SUBMISSION_ELSP;
1334 setup = intel_execlists_submission_setup;
1335 } else {
1336 gt->submission_method = INTEL_SUBMISSION_RING;
1337 setup = intel_ring_submission_setup;
1338 }
1339
1340 for_each_engine(engine, gt, id) {
1341 err = engine_setup_common(engine);
1342 if (err)
1343 return err;
1344
1345 err = setup(engine);
1346 if (err) {
1347 intel_engine_cleanup_common(engine);
1348 return err;
1349 }
1350
1351 /* The backend should now be responsible for cleanup */
1352 GEM_BUG_ON(engine->release == NULL);
1353
1354 err = engine_init_common(engine);
1355 if (err)
1356 return err;
1357
1358 intel_engine_add_user(engine);
1359 }
1360
1361 return 0;
1362 }
1363
1364 /**
1365 * intel_engines_cleanup_common - cleans up the engine state created by
1366 * the common initiailizers.
1367 * @engine: Engine to cleanup.
1368 *
1369 * This cleans up everything created by the common helpers.
1370 */
intel_engine_cleanup_common(struct intel_engine_cs * engine)1371 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1372 {
1373 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1374
1375 i915_sched_engine_put(engine->sched_engine);
1376 intel_breadcrumbs_put(engine->breadcrumbs);
1377
1378 intel_engine_fini_retire(engine);
1379 intel_engine_cleanup_cmd_parser(engine);
1380
1381 if (engine->default_state)
1382 fput(engine->default_state);
1383
1384 if (engine->kernel_context)
1385 intel_engine_destroy_pinned_context(engine->kernel_context);
1386
1387 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1388 cleanup_status_page(engine);
1389
1390 intel_wa_list_free(&engine->ctx_wa_list);
1391 intel_wa_list_free(&engine->wa_list);
1392 intel_wa_list_free(&engine->whitelist);
1393 }
1394
1395 /**
1396 * intel_engine_resume - re-initializes the HW state of the engine
1397 * @engine: Engine to resume.
1398 *
1399 * Returns zero on success or an error code on failure.
1400 */
intel_engine_resume(struct intel_engine_cs * engine)1401 int intel_engine_resume(struct intel_engine_cs *engine)
1402 {
1403 intel_engine_apply_workarounds(engine);
1404 intel_engine_apply_whitelist(engine);
1405
1406 return engine->resume(engine);
1407 }
1408
intel_engine_get_active_head(const struct intel_engine_cs * engine)1409 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1410 {
1411 struct drm_i915_private *i915 = engine->i915;
1412
1413 u64 acthd;
1414
1415 if (GRAPHICS_VER(i915) >= 8)
1416 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1417 else if (GRAPHICS_VER(i915) >= 4)
1418 acthd = ENGINE_READ(engine, RING_ACTHD);
1419 else
1420 acthd = ENGINE_READ(engine, ACTHD);
1421
1422 return acthd;
1423 }
1424
intel_engine_get_last_batch_head(const struct intel_engine_cs * engine)1425 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1426 {
1427 u64 bbaddr;
1428
1429 if (GRAPHICS_VER(engine->i915) >= 8)
1430 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1431 else
1432 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1433
1434 return bbaddr;
1435 }
1436
stop_timeout(const struct intel_engine_cs * engine)1437 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1438 {
1439 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1440 return 0;
1441
1442 /*
1443 * If we are doing a normal GPU reset, we can take our time and allow
1444 * the engine to quiesce. We've stopped submission to the engine, and
1445 * if we wait long enough an innocent context should complete and
1446 * leave the engine idle. So they should not be caught unaware by
1447 * the forthcoming GPU reset (which usually follows the stop_cs)!
1448 */
1449 return READ_ONCE(engine->props.stop_timeout_ms);
1450 }
1451
__intel_engine_stop_cs(struct intel_engine_cs * engine,int fast_timeout_us,int slow_timeout_ms)1452 static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1453 int fast_timeout_us,
1454 int slow_timeout_ms)
1455 {
1456 struct intel_uncore *uncore = engine->uncore;
1457 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1458 int err;
1459
1460 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1461
1462 /*
1463 * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
1464 * stopped, set ring stop bit and prefetch disable bit to halt CS
1465 */
1466 if (IS_GRAPHICS_VER(engine->i915, 11, 12))
1467 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1468 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1469
1470 err = __intel_wait_for_register_fw(engine->uncore, mode,
1471 MODE_IDLE, MODE_IDLE,
1472 fast_timeout_us,
1473 slow_timeout_ms,
1474 NULL);
1475
1476 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1477 intel_uncore_posting_read_fw(uncore, mode);
1478 return err;
1479 }
1480
intel_engine_stop_cs(struct intel_engine_cs * engine)1481 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1482 {
1483 int err = 0;
1484
1485 if (GRAPHICS_VER(engine->i915) < 3)
1486 return -ENODEV;
1487
1488 ENGINE_TRACE(engine, "\n");
1489 /*
1490 * TODO: Find out why occasionally stopping the CS times out. Seen
1491 * especially with gem_eio tests.
1492 *
1493 * Occasionally trying to stop the cs times out, but does not adversely
1494 * affect functionality. The timeout is set as a config parameter that
1495 * defaults to 100ms. In most cases the follow up operation is to wait
1496 * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1497 * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1498 * caused, the caller must check and handle the return from this
1499 * function.
1500 */
1501 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1502 ENGINE_TRACE(engine,
1503 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1504 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1505 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1506
1507 /*
1508 * Sometimes we observe that the idle flag is not
1509 * set even though the ring is empty. So double
1510 * check before giving up.
1511 */
1512 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1513 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1514 err = -ETIMEDOUT;
1515 }
1516
1517 return err;
1518 }
1519
intel_engine_cancel_stop_cs(struct intel_engine_cs * engine)1520 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1521 {
1522 ENGINE_TRACE(engine, "\n");
1523
1524 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1525 }
1526
__cs_pending_mi_force_wakes(struct intel_engine_cs * engine)1527 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1528 {
1529 static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1530 [RCS0] = MSG_IDLE_CS,
1531 [BCS0] = MSG_IDLE_BCS,
1532 [VCS0] = MSG_IDLE_VCS0,
1533 [VCS1] = MSG_IDLE_VCS1,
1534 [VCS2] = MSG_IDLE_VCS2,
1535 [VCS3] = MSG_IDLE_VCS3,
1536 [VCS4] = MSG_IDLE_VCS4,
1537 [VCS5] = MSG_IDLE_VCS5,
1538 [VCS6] = MSG_IDLE_VCS6,
1539 [VCS7] = MSG_IDLE_VCS7,
1540 [VECS0] = MSG_IDLE_VECS0,
1541 [VECS1] = MSG_IDLE_VECS1,
1542 [VECS2] = MSG_IDLE_VECS2,
1543 [VECS3] = MSG_IDLE_VECS3,
1544 [CCS0] = MSG_IDLE_CS,
1545 [CCS1] = MSG_IDLE_CS,
1546 [CCS2] = MSG_IDLE_CS,
1547 [CCS3] = MSG_IDLE_CS,
1548 };
1549 u32 val;
1550
1551 if (!_reg[engine->id].reg) {
1552 drm_err(&engine->i915->drm,
1553 "MSG IDLE undefined for engine id %u\n", engine->id);
1554 return 0;
1555 }
1556
1557 val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1558
1559 /* bits[29:25] & bits[13:9] >> shift */
1560 return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1561 }
1562
__gpm_wait_for_fw_complete(struct intel_gt * gt,u32 fw_mask)1563 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1564 {
1565 int ret;
1566
1567 /* Ensure GPM receives fw up/down after CS is stopped */
1568 udelay(1);
1569
1570 /* Wait for forcewake request to complete in GPM */
1571 ret = __intel_wait_for_register_fw(gt->uncore,
1572 GEN9_PWRGT_DOMAIN_STATUS,
1573 fw_mask, fw_mask, 5000, 0, NULL);
1574
1575 /* Ensure CS receives fw ack from GPM */
1576 udelay(1);
1577
1578 if (ret)
1579 GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1580 }
1581
1582 /*
1583 * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1584 * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1585 * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1586 * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1587 * are concerned only with the gt reset here, we use a logical OR of pending
1588 * forcewakeups from all reset domains and then wait for them to complete by
1589 * querying PWRGT_DOMAIN_STATUS.
1590 */
intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs * engine)1591 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1592 {
1593 u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1594
1595 if (fw_pending)
1596 __gpm_wait_for_fw_complete(engine->gt, fw_pending);
1597 }
1598
1599 /* NB: please notice the memset */
intel_engine_get_instdone(const struct intel_engine_cs * engine,struct intel_instdone * instdone)1600 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1601 struct intel_instdone *instdone)
1602 {
1603 struct drm_i915_private *i915 = engine->i915;
1604 struct intel_uncore *uncore = engine->uncore;
1605 u32 mmio_base = engine->mmio_base;
1606 int slice;
1607 int subslice;
1608 int iter;
1609
1610 memset(instdone, 0, sizeof(*instdone));
1611
1612 if (GRAPHICS_VER(i915) >= 8) {
1613 instdone->instdone =
1614 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1615
1616 if (engine->id != RCS0)
1617 return;
1618
1619 instdone->slice_common =
1620 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1621 if (GRAPHICS_VER(i915) >= 12) {
1622 instdone->slice_common_extra[0] =
1623 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1624 instdone->slice_common_extra[1] =
1625 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1626 }
1627
1628 for_each_ss_steering(iter, engine->gt, slice, subslice) {
1629 instdone->sampler[slice][subslice] =
1630 intel_gt_mcr_read(engine->gt,
1631 GEN7_SAMPLER_INSTDONE,
1632 slice, subslice);
1633 instdone->row[slice][subslice] =
1634 intel_gt_mcr_read(engine->gt,
1635 GEN7_ROW_INSTDONE,
1636 slice, subslice);
1637 }
1638
1639 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1640 for_each_ss_steering(iter, engine->gt, slice, subslice)
1641 instdone->geom_svg[slice][subslice] =
1642 intel_gt_mcr_read(engine->gt,
1643 XEHPG_INSTDONE_GEOM_SVG,
1644 slice, subslice);
1645 }
1646 } else if (GRAPHICS_VER(i915) >= 7) {
1647 instdone->instdone =
1648 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1649
1650 if (engine->id != RCS0)
1651 return;
1652
1653 instdone->slice_common =
1654 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1655 instdone->sampler[0][0] =
1656 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1657 instdone->row[0][0] =
1658 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1659 } else if (GRAPHICS_VER(i915) >= 4) {
1660 instdone->instdone =
1661 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1662 if (engine->id == RCS0)
1663 /* HACK: Using the wrong struct member */
1664 instdone->slice_common =
1665 intel_uncore_read(uncore, GEN4_INSTDONE1);
1666 } else {
1667 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1668 }
1669 }
1670
ring_is_idle(struct intel_engine_cs * engine)1671 static bool ring_is_idle(struct intel_engine_cs *engine)
1672 {
1673 bool idle = true;
1674
1675 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1676 return true;
1677
1678 if (!intel_engine_pm_get_if_awake(engine))
1679 return true;
1680
1681 /* First check that no commands are left in the ring */
1682 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1683 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1684 idle = false;
1685
1686 /* No bit for gen2, so assume the CS parser is idle */
1687 if (GRAPHICS_VER(engine->i915) > 2 &&
1688 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1689 idle = false;
1690
1691 intel_engine_pm_put(engine);
1692
1693 return idle;
1694 }
1695
__intel_engine_flush_submission(struct intel_engine_cs * engine,bool sync)1696 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1697 {
1698 struct tasklet_struct *t = &engine->sched_engine->tasklet;
1699
1700 if (!t->callback)
1701 return;
1702
1703 local_bh_disable();
1704 if (tasklet_trylock(t)) {
1705 /* Must wait for any GPU reset in progress. */
1706 if (__tasklet_is_enabled(t))
1707 t->callback(t);
1708 tasklet_unlock(t);
1709 }
1710 local_bh_enable();
1711
1712 /* Synchronise and wait for the tasklet on another CPU */
1713 if (sync)
1714 tasklet_unlock_wait(t);
1715 }
1716
1717 /**
1718 * intel_engine_is_idle() - Report if the engine has finished process all work
1719 * @engine: the intel_engine_cs
1720 *
1721 * Return true if there are no requests pending, nothing left to be submitted
1722 * to hardware, and that the engine is idle.
1723 */
intel_engine_is_idle(struct intel_engine_cs * engine)1724 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1725 {
1726 /* More white lies, if wedged, hw state is inconsistent */
1727 if (intel_gt_is_wedged(engine->gt))
1728 return true;
1729
1730 if (!intel_engine_pm_is_awake(engine))
1731 return true;
1732
1733 /* Waiting to drain ELSP? */
1734 intel_synchronize_hardirq(engine->i915);
1735 intel_engine_flush_submission(engine);
1736
1737 /* ELSP is empty, but there are ready requests? E.g. after reset */
1738 if (!i915_sched_engine_is_empty(engine->sched_engine))
1739 return false;
1740
1741 /* Ring stopped? */
1742 return ring_is_idle(engine);
1743 }
1744
intel_engines_are_idle(struct intel_gt * gt)1745 bool intel_engines_are_idle(struct intel_gt *gt)
1746 {
1747 struct intel_engine_cs *engine;
1748 enum intel_engine_id id;
1749
1750 /*
1751 * If the driver is wedged, HW state may be very inconsistent and
1752 * report that it is still busy, even though we have stopped using it.
1753 */
1754 if (intel_gt_is_wedged(gt))
1755 return true;
1756
1757 /* Already parked (and passed an idleness test); must still be idle */
1758 if (!READ_ONCE(gt->awake))
1759 return true;
1760
1761 for_each_engine(engine, gt, id) {
1762 if (!intel_engine_is_idle(engine))
1763 return false;
1764 }
1765
1766 return true;
1767 }
1768
intel_engine_irq_enable(struct intel_engine_cs * engine)1769 bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1770 {
1771 if (!engine->irq_enable)
1772 return false;
1773
1774 /* Caller disables interrupts */
1775 spin_lock(engine->gt->irq_lock);
1776 engine->irq_enable(engine);
1777 spin_unlock(engine->gt->irq_lock);
1778
1779 return true;
1780 }
1781
intel_engine_irq_disable(struct intel_engine_cs * engine)1782 void intel_engine_irq_disable(struct intel_engine_cs *engine)
1783 {
1784 if (!engine->irq_disable)
1785 return;
1786
1787 /* Caller disables interrupts */
1788 spin_lock(engine->gt->irq_lock);
1789 engine->irq_disable(engine);
1790 spin_unlock(engine->gt->irq_lock);
1791 }
1792
intel_engines_reset_default_submission(struct intel_gt * gt)1793 void intel_engines_reset_default_submission(struct intel_gt *gt)
1794 {
1795 struct intel_engine_cs *engine;
1796 enum intel_engine_id id;
1797
1798 for_each_engine(engine, gt, id) {
1799 if (engine->sanitize)
1800 engine->sanitize(engine);
1801
1802 engine->set_default_submission(engine);
1803 }
1804 }
1805
intel_engine_can_store_dword(struct intel_engine_cs * engine)1806 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1807 {
1808 switch (GRAPHICS_VER(engine->i915)) {
1809 case 2:
1810 return false; /* uses physical not virtual addresses */
1811 case 3:
1812 /* maybe only uses physical not virtual addresses */
1813 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1814 case 4:
1815 return !IS_I965G(engine->i915); /* who knows! */
1816 case 6:
1817 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1818 default:
1819 return true;
1820 }
1821 }
1822
get_timeline(struct i915_request * rq)1823 static struct intel_timeline *get_timeline(struct i915_request *rq)
1824 {
1825 struct intel_timeline *tl;
1826
1827 /*
1828 * Even though we are holding the engine->sched_engine->lock here, there
1829 * is no control over the submission queue per-se and we are
1830 * inspecting the active state at a random point in time, with an
1831 * unknown queue. Play safe and make sure the timeline remains valid.
1832 * (Only being used for pretty printing, one extra kref shouldn't
1833 * cause a camel stampede!)
1834 */
1835 rcu_read_lock();
1836 tl = rcu_dereference(rq->timeline);
1837 if (!kref_get_unless_zero(&tl->kref))
1838 tl = NULL;
1839 rcu_read_unlock();
1840
1841 return tl;
1842 }
1843
print_ring(char * buf,int sz,struct i915_request * rq)1844 static int print_ring(char *buf, int sz, struct i915_request *rq)
1845 {
1846 int len = 0;
1847
1848 if (!i915_request_signaled(rq)) {
1849 struct intel_timeline *tl = get_timeline(rq);
1850
1851 len = scnprintf(buf, sz,
1852 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1853 i915_ggtt_offset(rq->ring->vma),
1854 tl ? tl->hwsp_offset : 0,
1855 hwsp_seqno(rq),
1856 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1857 1000 * 1000));
1858
1859 if (tl)
1860 intel_timeline_put(tl);
1861 }
1862
1863 return len;
1864 }
1865
hexdump(struct drm_printer * m,const void * buf,size_t len)1866 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1867 {
1868 const size_t rowsize = 8 * sizeof(u32);
1869 const void *prev = NULL;
1870 bool skip = false;
1871 size_t pos;
1872
1873 for (pos = 0; pos < len; pos += rowsize) {
1874 char line[128];
1875
1876 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1877 if (!skip) {
1878 drm_printf(m, "*\n");
1879 skip = true;
1880 }
1881 continue;
1882 }
1883
1884 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1885 rowsize, sizeof(u32),
1886 line, sizeof(line),
1887 false) >= sizeof(line));
1888 drm_printf(m, "[%04zx] %s\n", pos, line);
1889
1890 prev = buf + pos;
1891 skip = false;
1892 }
1893 }
1894
repr_timer(const struct timer_list * t)1895 static const char *repr_timer(const struct timer_list *t)
1896 {
1897 if (!READ_ONCE(t->expires))
1898 return "inactive";
1899
1900 if (timer_pending(t))
1901 return "active";
1902
1903 return "expired";
1904 }
1905
intel_engine_print_registers(struct intel_engine_cs * engine,struct drm_printer * m)1906 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1907 struct drm_printer *m)
1908 {
1909 struct drm_i915_private *dev_priv = engine->i915;
1910 struct intel_engine_execlists * const execlists = &engine->execlists;
1911 u64 addr;
1912
1913 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
1914 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1915 if (HAS_EXECLISTS(dev_priv)) {
1916 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1917 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1918 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1919 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1920 }
1921 drm_printf(m, "\tRING_START: 0x%08x\n",
1922 ENGINE_READ(engine, RING_START));
1923 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
1924 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1925 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
1926 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1927 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
1928 ENGINE_READ(engine, RING_CTL),
1929 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1930 if (GRAPHICS_VER(engine->i915) > 2) {
1931 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
1932 ENGINE_READ(engine, RING_MI_MODE),
1933 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1934 }
1935
1936 if (GRAPHICS_VER(dev_priv) >= 6) {
1937 drm_printf(m, "\tRING_IMR: 0x%08x\n",
1938 ENGINE_READ(engine, RING_IMR));
1939 drm_printf(m, "\tRING_ESR: 0x%08x\n",
1940 ENGINE_READ(engine, RING_ESR));
1941 drm_printf(m, "\tRING_EMR: 0x%08x\n",
1942 ENGINE_READ(engine, RING_EMR));
1943 drm_printf(m, "\tRING_EIR: 0x%08x\n",
1944 ENGINE_READ(engine, RING_EIR));
1945 }
1946
1947 addr = intel_engine_get_active_head(engine);
1948 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
1949 upper_32_bits(addr), lower_32_bits(addr));
1950 addr = intel_engine_get_last_batch_head(engine);
1951 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1952 upper_32_bits(addr), lower_32_bits(addr));
1953 if (GRAPHICS_VER(dev_priv) >= 8)
1954 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1955 else if (GRAPHICS_VER(dev_priv) >= 4)
1956 addr = ENGINE_READ(engine, RING_DMA_FADD);
1957 else
1958 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1959 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1960 upper_32_bits(addr), lower_32_bits(addr));
1961 if (GRAPHICS_VER(dev_priv) >= 4) {
1962 drm_printf(m, "\tIPEIR: 0x%08x\n",
1963 ENGINE_READ(engine, RING_IPEIR));
1964 drm_printf(m, "\tIPEHR: 0x%08x\n",
1965 ENGINE_READ(engine, RING_IPEHR));
1966 } else {
1967 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1968 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1969 }
1970
1971 if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {
1972 struct i915_request * const *port, *rq;
1973 const u32 *hws =
1974 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1975 const u8 num_entries = execlists->csb_size;
1976 unsigned int idx;
1977 u8 read, write;
1978
1979 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1980 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
1981 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
1982 repr_timer(&engine->execlists.preempt),
1983 repr_timer(&engine->execlists.timer));
1984
1985 read = execlists->csb_head;
1986 write = READ_ONCE(*execlists->csb_write);
1987
1988 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1989 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1990 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1991 read, write, num_entries);
1992
1993 if (read >= num_entries)
1994 read = 0;
1995 if (write >= num_entries)
1996 write = 0;
1997 if (read > write)
1998 write += num_entries;
1999 while (read < write) {
2000 idx = ++read % num_entries;
2001 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
2002 idx, hws[idx * 2], hws[idx * 2 + 1]);
2003 }
2004
2005 i915_sched_engine_active_lock_bh(engine->sched_engine);
2006 rcu_read_lock();
2007 for (port = execlists->active; (rq = *port); port++) {
2008 char hdr[160];
2009 int len;
2010
2011 len = scnprintf(hdr, sizeof(hdr),
2012 "\t\tActive[%d]: ccid:%08x%s%s, ",
2013 (int)(port - execlists->active),
2014 rq->context->lrc.ccid,
2015 intel_context_is_closed(rq->context) ? "!" : "",
2016 intel_context_is_banned(rq->context) ? "*" : "");
2017 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2018 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2019 i915_request_show(m, rq, hdr, 0);
2020 }
2021 for (port = execlists->pending; (rq = *port); port++) {
2022 char hdr[160];
2023 int len;
2024
2025 len = scnprintf(hdr, sizeof(hdr),
2026 "\t\tPending[%d]: ccid:%08x%s%s, ",
2027 (int)(port - execlists->pending),
2028 rq->context->lrc.ccid,
2029 intel_context_is_closed(rq->context) ? "!" : "",
2030 intel_context_is_banned(rq->context) ? "*" : "");
2031 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2032 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2033 i915_request_show(m, rq, hdr, 0);
2034 }
2035 rcu_read_unlock();
2036 i915_sched_engine_active_unlock_bh(engine->sched_engine);
2037 } else if (GRAPHICS_VER(dev_priv) > 6) {
2038 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
2039 ENGINE_READ(engine, RING_PP_DIR_BASE));
2040 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
2041 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
2042 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
2043 ENGINE_READ(engine, RING_PP_DIR_DCLV));
2044 }
2045 }
2046
print_request_ring(struct drm_printer * m,struct i915_request * rq)2047 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
2048 {
2049 struct i915_vma_resource *vma_res = rq->batch_res;
2050 void *ring;
2051 int size;
2052
2053 drm_printf(m,
2054 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
2055 rq->head, rq->postfix, rq->tail,
2056 vma_res ? upper_32_bits(vma_res->start) : ~0u,
2057 vma_res ? lower_32_bits(vma_res->start) : ~0u);
2058
2059 size = rq->tail - rq->head;
2060 if (rq->tail < rq->head)
2061 size += rq->ring->size;
2062
2063 ring = kmalloc(size, GFP_ATOMIC);
2064 if (ring) {
2065 const void *vaddr = rq->ring->vaddr;
2066 unsigned int head = rq->head;
2067 unsigned int len = 0;
2068
2069 if (rq->tail < head) {
2070 len = rq->ring->size - head;
2071 memcpy(ring, vaddr + head, len);
2072 head = 0;
2073 }
2074 memcpy(ring + len, vaddr + head, size - len);
2075
2076 hexdump(m, ring, size);
2077 kfree(ring);
2078 }
2079 }
2080
list_count(struct list_head * list)2081 static unsigned long list_count(struct list_head *list)
2082 {
2083 struct list_head *pos;
2084 unsigned long count = 0;
2085
2086 list_for_each(pos, list)
2087 count++;
2088
2089 return count;
2090 }
2091
read_ul(void * p,size_t x)2092 static unsigned long read_ul(void *p, size_t x)
2093 {
2094 return *(unsigned long *)(p + x);
2095 }
2096
print_properties(struct intel_engine_cs * engine,struct drm_printer * m)2097 static void print_properties(struct intel_engine_cs *engine,
2098 struct drm_printer *m)
2099 {
2100 static const struct pmap {
2101 size_t offset;
2102 const char *name;
2103 } props[] = {
2104 #define P(x) { \
2105 .offset = offsetof(typeof(engine->props), x), \
2106 .name = #x \
2107 }
2108 P(heartbeat_interval_ms),
2109 P(max_busywait_duration_ns),
2110 P(preempt_timeout_ms),
2111 P(stop_timeout_ms),
2112 P(timeslice_duration_ms),
2113
2114 {},
2115 #undef P
2116 };
2117 const struct pmap *p;
2118
2119 drm_printf(m, "\tProperties:\n");
2120 for (p = props; p->name; p++)
2121 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2122 p->name,
2123 read_ul(&engine->props, p->offset),
2124 read_ul(&engine->defaults, p->offset));
2125 }
2126
engine_dump_request(struct i915_request * rq,struct drm_printer * m,const char * msg)2127 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2128 {
2129 struct intel_timeline *tl = get_timeline(rq);
2130
2131 i915_request_show(m, rq, msg, 0);
2132
2133 drm_printf(m, "\t\tring->start: 0x%08x\n",
2134 i915_ggtt_offset(rq->ring->vma));
2135 drm_printf(m, "\t\tring->head: 0x%08x\n",
2136 rq->ring->head);
2137 drm_printf(m, "\t\tring->tail: 0x%08x\n",
2138 rq->ring->tail);
2139 drm_printf(m, "\t\tring->emit: 0x%08x\n",
2140 rq->ring->emit);
2141 drm_printf(m, "\t\tring->space: 0x%08x\n",
2142 rq->ring->space);
2143
2144 if (tl) {
2145 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
2146 tl->hwsp_offset);
2147 intel_timeline_put(tl);
2148 }
2149
2150 print_request_ring(m, rq);
2151
2152 if (rq->context->lrc_reg_state) {
2153 drm_printf(m, "Logical Ring Context:\n");
2154 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2155 }
2156 }
2157
intel_engine_dump_active_requests(struct list_head * requests,struct i915_request * hung_rq,struct drm_printer * m)2158 void intel_engine_dump_active_requests(struct list_head *requests,
2159 struct i915_request *hung_rq,
2160 struct drm_printer *m)
2161 {
2162 struct i915_request *rq;
2163 const char *msg;
2164 enum i915_request_state state;
2165
2166 list_for_each_entry(rq, requests, sched.link) {
2167 if (rq == hung_rq)
2168 continue;
2169
2170 state = i915_test_request_state(rq);
2171 if (state < I915_REQUEST_QUEUED)
2172 continue;
2173
2174 if (state == I915_REQUEST_ACTIVE)
2175 msg = "\t\tactive on engine";
2176 else
2177 msg = "\t\tactive in queue";
2178
2179 engine_dump_request(rq, m, msg);
2180 }
2181 }
2182
engine_dump_active_requests(struct intel_engine_cs * engine,struct drm_printer * m)2183 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m)
2184 {
2185 struct i915_request *hung_rq = NULL;
2186 struct intel_context *ce;
2187 bool guc;
2188
2189 /*
2190 * No need for an engine->irq_seqno_barrier() before the seqno reads.
2191 * The GPU is still running so requests are still executing and any
2192 * hardware reads will be out of date by the time they are reported.
2193 * But the intention here is just to report an instantaneous snapshot
2194 * so that's fine.
2195 */
2196 lockdep_assert_held(&engine->sched_engine->lock);
2197
2198 drm_printf(m, "\tRequests:\n");
2199
2200 guc = intel_uc_uses_guc_submission(&engine->gt->uc);
2201 if (guc) {
2202 ce = intel_engine_get_hung_context(engine);
2203 if (ce)
2204 hung_rq = intel_context_find_active_request(ce);
2205 } else {
2206 hung_rq = intel_engine_execlist_find_hung_request(engine);
2207 }
2208
2209 if (hung_rq)
2210 engine_dump_request(hung_rq, m, "\t\thung");
2211
2212 if (guc)
2213 intel_guc_dump_active_requests(engine, hung_rq, m);
2214 else
2215 intel_engine_dump_active_requests(&engine->sched_engine->requests,
2216 hung_rq, m);
2217 }
2218
intel_engine_dump(struct intel_engine_cs * engine,struct drm_printer * m,const char * header,...)2219 void intel_engine_dump(struct intel_engine_cs *engine,
2220 struct drm_printer *m,
2221 const char *header, ...)
2222 {
2223 struct i915_gpu_error * const error = &engine->i915->gpu_error;
2224 struct i915_request *rq;
2225 intel_wakeref_t wakeref;
2226 unsigned long flags;
2227 ktime_t dummy;
2228
2229 if (header) {
2230 va_list ap;
2231
2232 va_start(ap, header);
2233 drm_vprintf(m, header, &ap);
2234 va_end(ap);
2235 }
2236
2237 if (intel_gt_is_wedged(engine->gt))
2238 drm_printf(m, "*** WEDGED ***\n");
2239
2240 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2241 drm_printf(m, "\tBarriers?: %s\n",
2242 str_yes_no(!llist_empty(&engine->barrier_tasks)));
2243 drm_printf(m, "\tLatency: %luus\n",
2244 ewma__engine_latency_read(&engine->latency));
2245 if (intel_engine_supports_stats(engine))
2246 drm_printf(m, "\tRuntime: %llums\n",
2247 ktime_to_ms(intel_engine_get_busy_time(engine,
2248 &dummy)));
2249 drm_printf(m, "\tForcewake: %x domains, %d active\n",
2250 engine->fw_domain, READ_ONCE(engine->fw_active));
2251
2252 rcu_read_lock();
2253 rq = READ_ONCE(engine->heartbeat.systole);
2254 if (rq)
2255 drm_printf(m, "\tHeartbeat: %d ms ago\n",
2256 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2257 rcu_read_unlock();
2258 drm_printf(m, "\tReset count: %d (global %d)\n",
2259 i915_reset_engine_count(error, engine),
2260 i915_reset_count(error));
2261 print_properties(engine, m);
2262
2263 spin_lock_irqsave(&engine->sched_engine->lock, flags);
2264 engine_dump_active_requests(engine, m);
2265
2266 drm_printf(m, "\tOn hold?: %lu\n",
2267 list_count(&engine->sched_engine->hold));
2268 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2269
2270 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
2271 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2272 if (wakeref) {
2273 intel_engine_print_registers(engine, m);
2274 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2275 } else {
2276 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2277 }
2278
2279 intel_execlists_show_requests(engine, m, i915_request_show, 8);
2280
2281 drm_printf(m, "HWSP:\n");
2282 hexdump(m, engine->status_page.addr, PAGE_SIZE);
2283
2284 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2285
2286 intel_engine_print_breadcrumbs(engine, m);
2287 }
2288
2289 /**
2290 * intel_engine_get_busy_time() - Return current accumulated engine busyness
2291 * @engine: engine to report on
2292 * @now: monotonic timestamp of sampling
2293 *
2294 * Returns accumulated time @engine was busy since engine stats were enabled.
2295 */
intel_engine_get_busy_time(struct intel_engine_cs * engine,ktime_t * now)2296 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2297 {
2298 return engine->busyness(engine, now);
2299 }
2300
2301 struct intel_context *
intel_engine_create_virtual(struct intel_engine_cs ** siblings,unsigned int count,unsigned long flags)2302 intel_engine_create_virtual(struct intel_engine_cs **siblings,
2303 unsigned int count, unsigned long flags)
2304 {
2305 if (count == 0)
2306 return ERR_PTR(-EINVAL);
2307
2308 if (count == 1 && !(flags & FORCE_VIRTUAL))
2309 return intel_context_create(siblings[0]);
2310
2311 GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2312 return siblings[0]->cops->create_virtual(siblings, count, flags);
2313 }
2314
2315 struct i915_request *
intel_engine_execlist_find_hung_request(struct intel_engine_cs * engine)2316 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2317 {
2318 struct i915_request *request, *active = NULL;
2319
2320 /*
2321 * This search does not work in GuC submission mode. However, the GuC
2322 * will report the hanging context directly to the driver itself. So
2323 * the driver should never get here when in GuC mode.
2324 */
2325 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2326
2327 /*
2328 * We are called by the error capture, reset and to dump engine
2329 * state at random points in time. In particular, note that neither is
2330 * crucially ordered with an interrupt. After a hang, the GPU is dead
2331 * and we assume that no more writes can happen (we waited long enough
2332 * for all writes that were in transaction to be flushed) - adding an
2333 * extra delay for a recent interrupt is pointless. Hence, we do
2334 * not need an engine->irq_seqno_barrier() before the seqno reads.
2335 * At all other times, we must assume the GPU is still running, but
2336 * we only care about the snapshot of this moment.
2337 */
2338 lockdep_assert_held(&engine->sched_engine->lock);
2339
2340 rcu_read_lock();
2341 request = execlists_active(&engine->execlists);
2342 if (request) {
2343 struct intel_timeline *tl = request->context->timeline;
2344
2345 list_for_each_entry_from_reverse(request, &tl->requests, link) {
2346 if (__i915_request_is_complete(request))
2347 break;
2348
2349 active = request;
2350 }
2351 }
2352 rcu_read_unlock();
2353 if (active)
2354 return active;
2355
2356 list_for_each_entry(request, &engine->sched_engine->requests,
2357 sched.link) {
2358 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2359 continue;
2360
2361 active = request;
2362 break;
2363 }
2364
2365 return active;
2366 }
2367
xehp_enable_ccs_engines(struct intel_engine_cs * engine)2368 void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2369 {
2370 /*
2371 * If there are any non-fused-off CCS engines, we need to enable CCS
2372 * support in the RCU_MODE register. This only needs to be done once,
2373 * so for simplicity we'll take care of this in the RCS engine's
2374 * resume handler; since the RCS and all CCS engines belong to the
2375 * same reset domain and are reset together, this will also take care
2376 * of re-applying the setting after i915-triggered resets.
2377 */
2378 if (!CCS_MASK(engine->gt))
2379 return;
2380
2381 intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2382 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2383 }
2384
2385 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2386 #include "mock_engine.c"
2387 #include "selftest_engine.c"
2388 #include "selftest_engine_cs.c"
2389 #endif
2390