1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8 #include <linux/limits.h>
9
10 #include <drm/display/drm_dsc_helper.h>
11
12 #include "i915_drv.h"
13 #include "intel_crtc.h"
14 #include "intel_de.h"
15 #include "intel_display_types.h"
16 #include "intel_dsi.h"
17 #include "intel_qp_tables.h"
18 #include "intel_vdsc.h"
19
20 enum ROW_INDEX_BPP {
21 ROW_INDEX_6BPP = 0,
22 ROW_INDEX_8BPP,
23 ROW_INDEX_10BPP,
24 ROW_INDEX_12BPP,
25 ROW_INDEX_15BPP,
26 MAX_ROW_INDEX
27 };
28
29 enum COLUMN_INDEX_BPC {
30 COLUMN_INDEX_8BPC = 0,
31 COLUMN_INDEX_10BPC,
32 COLUMN_INDEX_12BPC,
33 COLUMN_INDEX_14BPC,
34 COLUMN_INDEX_16BPC,
35 MAX_COLUMN_INDEX
36 };
37
38 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
39 static const u16 rc_buf_thresh[] = {
40 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
41 7744, 7872, 8000, 8064
42 };
43
44 struct rc_parameters {
45 u16 initial_xmit_delay;
46 u8 first_line_bpg_offset;
47 u16 initial_offset;
48 u8 flatness_min_qp;
49 u8 flatness_max_qp;
50 u8 rc_quant_incr_limit0;
51 u8 rc_quant_incr_limit1;
52 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
53 };
54
55 /*
56 * Selected Rate Control Related Parameter Recommended Values
57 * from DSC_v1.11 spec & C Model release: DSC_model_20161212
58 */
59 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
60 {
61 /* 6BPP/8BPC */
62 { 768, 15, 6144, 3, 13, 11, 11, {
63 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
64 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
65 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
66 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
67 }
68 },
69 /* 6BPP/10BPC */
70 { 768, 15, 6144, 7, 17, 15, 15, {
71 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
72 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
73 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
74 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
75 { 17, 18, -12 }
76 }
77 },
78 /* 6BPP/12BPC */
79 { 768, 15, 6144, 11, 21, 19, 19, {
80 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
81 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
82 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
83 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
84 { 21, 22, -12 }
85 }
86 },
87 /* 6BPP/14BPC */
88 { 768, 15, 6144, 15, 25, 23, 27, {
89 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
90 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
91 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
92 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
93 { 25, 26, -12 }
94 }
95 },
96 /* 6BPP/16BPC */
97 { 768, 15, 6144, 19, 29, 27, 27, {
98 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
99 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
100 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
101 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
102 { 29, 30, -12 }
103 }
104 },
105 },
106 {
107 /* 8BPP/8BPC */
108 { 512, 12, 6144, 3, 12, 11, 11, {
109 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
110 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
111 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
112 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
113 }
114 },
115 /* 8BPP/10BPC */
116 { 512, 12, 6144, 7, 16, 15, 15, {
117 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
118 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
119 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
120 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
121 }
122 },
123 /* 8BPP/12BPC */
124 { 512, 12, 6144, 11, 20, 19, 19, {
125 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
126 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
127 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
128 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
129 { 21, 23, -12 }
130 }
131 },
132 /* 8BPP/14BPC */
133 { 512, 12, 6144, 15, 24, 23, 23, {
134 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
135 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
136 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
137 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
138 { 24, 25, -12 }
139 }
140 },
141 /* 8BPP/16BPC */
142 { 512, 12, 6144, 19, 28, 27, 27, {
143 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
144 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
145 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
146 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
147 { 28, 29, -12 }
148 }
149 },
150 },
151 {
152 /* 10BPP/8BPC */
153 { 410, 15, 5632, 3, 12, 11, 11, {
154 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
155 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
156 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
157 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
158 }
159 },
160 /* 10BPP/10BPC */
161 { 410, 15, 5632, 7, 16, 15, 15, {
162 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
163 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
164 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
165 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
166 }
167 },
168 /* 10BPP/12BPC */
169 { 410, 15, 5632, 11, 20, 19, 19, {
170 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
171 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
172 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
173 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
174 { 19, 20, -12 }
175 }
176 },
177 /* 10BPP/14BPC */
178 { 410, 15, 5632, 15, 24, 23, 23, {
179 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
180 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
181 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
182 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
183 { 23, 24, -12 }
184 }
185 },
186 /* 10BPP/16BPC */
187 { 410, 15, 5632, 19, 28, 27, 27, {
188 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
189 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
190 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
191 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
192 { 27, 28, -12 }
193 }
194 },
195 },
196 {
197 /* 12BPP/8BPC */
198 { 341, 15, 2048, 3, 12, 11, 11, {
199 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
200 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
201 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
202 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
203 }
204 },
205 /* 12BPP/10BPC */
206 { 341, 15, 2048, 7, 16, 15, 15, {
207 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
208 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
209 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
210 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
211 }
212 },
213 /* 12BPP/12BPC */
214 { 341, 15, 2048, 11, 20, 19, 19, {
215 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
216 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
217 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
218 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
219 { 21, 23, -12 }
220 }
221 },
222 /* 12BPP/14BPC */
223 { 341, 15, 2048, 15, 24, 23, 23, {
224 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
225 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
226 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
227 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
228 { 22, 23, -12 }
229 }
230 },
231 /* 12BPP/16BPC */
232 { 341, 15, 2048, 19, 28, 27, 27, {
233 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
234 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
235 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
236 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
237 { 26, 27, -12 }
238 }
239 },
240 },
241 {
242 /* 15BPP/8BPC */
243 { 273, 15, 2048, 3, 12, 11, 11, {
244 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
245 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
246 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
247 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
248 }
249 },
250 /* 15BPP/10BPC */
251 { 273, 15, 2048, 7, 16, 15, 15, {
252 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
253 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
254 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
255 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
256 }
257 },
258 /* 15BPP/12BPC */
259 { 273, 15, 2048, 11, 20, 19, 19, {
260 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
261 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
262 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
263 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
264 { 16, 17, -12 }
265 }
266 },
267 /* 15BPP/14BPC */
268 { 273, 15, 2048, 15, 24, 23, 23, {
269 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
270 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
271 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
272 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
273 { 20, 21, -12 }
274 }
275 },
276 /* 15BPP/16BPC */
277 { 273, 15, 2048, 19, 28, 27, 27, {
278 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
279 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
280 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
281 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
282 { 24, 25, -12 }
283 }
284 }
285 }
286
287 };
288
get_row_index_for_rc_params(u16 compressed_bpp)289 static int get_row_index_for_rc_params(u16 compressed_bpp)
290 {
291 switch (compressed_bpp) {
292 case 6:
293 return ROW_INDEX_6BPP;
294 case 8:
295 return ROW_INDEX_8BPP;
296 case 10:
297 return ROW_INDEX_10BPP;
298 case 12:
299 return ROW_INDEX_12BPP;
300 case 15:
301 return ROW_INDEX_15BPP;
302 default:
303 return -EINVAL;
304 }
305 }
306
get_column_index_for_rc_params(u8 bits_per_component)307 static int get_column_index_for_rc_params(u8 bits_per_component)
308 {
309 switch (bits_per_component) {
310 case 8:
311 return COLUMN_INDEX_8BPC;
312 case 10:
313 return COLUMN_INDEX_10BPC;
314 case 12:
315 return COLUMN_INDEX_12BPC;
316 case 14:
317 return COLUMN_INDEX_14BPC;
318 case 16:
319 return COLUMN_INDEX_16BPC;
320 default:
321 return -EINVAL;
322 }
323 }
324
get_rc_params(u16 compressed_bpp,u8 bits_per_component)325 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
326 u8 bits_per_component)
327 {
328 int row_index, column_index;
329
330 row_index = get_row_index_for_rc_params(compressed_bpp);
331 if (row_index < 0)
332 return NULL;
333
334 column_index = get_column_index_for_rc_params(bits_per_component);
335 if (column_index < 0)
336 return NULL;
337
338 return &rc_parameters[row_index][column_index];
339 }
340
intel_dsc_source_support(const struct intel_crtc_state * crtc_state)341 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
342 {
343 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
344 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
345 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
346
347 if (!RUNTIME_INFO(i915)->has_dsc)
348 return false;
349
350 if (DISPLAY_VER(i915) >= 12)
351 return true;
352
353 if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
354 return true;
355
356 return false;
357 }
358
is_pipe_dsc(struct intel_crtc * crtc,enum transcoder cpu_transcoder)359 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
360 {
361 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
362
363 if (DISPLAY_VER(i915) >= 12)
364 return true;
365
366 if (cpu_transcoder == TRANSCODER_EDP ||
367 cpu_transcoder == TRANSCODER_DSI_0 ||
368 cpu_transcoder == TRANSCODER_DSI_1)
369 return false;
370
371 /* There's no pipe A DSC engine on ICL */
372 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
373
374 return true;
375 }
376
377 static void
calculate_rc_params(struct rc_parameters * rc,struct drm_dsc_config * vdsc_cfg)378 calculate_rc_params(struct rc_parameters *rc,
379 struct drm_dsc_config *vdsc_cfg)
380 {
381 int bpc = vdsc_cfg->bits_per_component;
382 int bpp = vdsc_cfg->bits_per_pixel >> 4;
383 static const s8 ofs_und6[] = {
384 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
385 };
386 static const s8 ofs_und8[] = {
387 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
388 };
389 static const s8 ofs_und12[] = {
390 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
391 };
392 static const s8 ofs_und15[] = {
393 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
394 };
395 int qp_bpc_modifier = (bpc - 8) * 2;
396 u32 res, buf_i, bpp_i;
397
398 if (vdsc_cfg->slice_height >= 8)
399 rc->first_line_bpg_offset =
400 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
401 else
402 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
403
404 /* Our hw supports only 444 modes as of today */
405 if (bpp >= 12)
406 rc->initial_offset = 2048;
407 else if (bpp >= 10)
408 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
409 else if (bpp >= 8)
410 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
411 else
412 rc->initial_offset = 6144;
413
414 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
415 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
416
417 rc->flatness_min_qp = 3 + qp_bpc_modifier;
418 rc->flatness_max_qp = 12 + qp_bpc_modifier;
419
420 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
421 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
422
423 bpp_i = (2 * (bpp - 6));
424 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
425 /* Read range_minqp and range_max_qp from qp tables */
426 rc->rc_range_params[buf_i].range_min_qp =
427 intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
428 rc->rc_range_params[buf_i].range_max_qp =
429 intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
430
431 /* Calculate range_bgp_offset */
432 if (bpp <= 6) {
433 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
434 } else if (bpp <= 8) {
435 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
436 rc->rc_range_params[buf_i].range_bpg_offset =
437 ofs_und6[buf_i] + res;
438 } else if (bpp <= 12) {
439 rc->rc_range_params[buf_i].range_bpg_offset =
440 ofs_und8[buf_i];
441 } else if (bpp <= 15) {
442 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
443 rc->rc_range_params[buf_i].range_bpg_offset =
444 ofs_und12[buf_i] + res;
445 } else {
446 rc->rc_range_params[buf_i].range_bpg_offset =
447 ofs_und15[buf_i];
448 }
449 }
450 }
451
intel_dsc_compute_params(struct intel_crtc_state * pipe_config)452 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
453 {
454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
456 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
457 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
458 const struct rc_parameters *rc_params;
459 struct rc_parameters *rc = NULL;
460 u8 i = 0;
461
462 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
463 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
464 pipe_config->dsc.slice_count);
465
466 /* Gen 11 does not support YCbCr */
467 vdsc_cfg->simple_422 = false;
468 /* Gen 11 does not support VBR */
469 vdsc_cfg->vbr_enable = false;
470
471 /* Gen 11 only supports integral values of bpp */
472 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
473 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
474
475 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
476 /*
477 * six 0s are appended to the lsb of each threshold value
478 * internally in h/w.
479 * Only 8 bits are allowed for programming RcBufThreshold
480 */
481 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
482 }
483
484 /*
485 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
486 * as per C Model
487 */
488 if (compressed_bpp == 6) {
489 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
490 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
491 }
492
493 /*
494 * From XE_LPD onwards we supports compression bpps in steps of 1
495 * upto uncompressed bpp-1, hence add calculations for all the rc
496 * parameters
497 */
498 if (DISPLAY_VER(dev_priv) >= 13) {
499 rc = kmalloc(sizeof(*rc), GFP_KERNEL);
500 if (!rc)
501 return -ENOMEM;
502
503 calculate_rc_params(rc, vdsc_cfg);
504 rc_params = rc;
505 } else {
506 rc_params = get_rc_params(compressed_bpp,
507 vdsc_cfg->bits_per_component);
508 if (!rc_params)
509 return -EINVAL;
510 }
511
512 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
513 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
514 vdsc_cfg->initial_offset = rc_params->initial_offset;
515 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
516 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
517 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
518 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
519
520 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
521 vdsc_cfg->rc_range_params[i].range_min_qp =
522 rc_params->rc_range_params[i].range_min_qp;
523 vdsc_cfg->rc_range_params[i].range_max_qp =
524 rc_params->rc_range_params[i].range_max_qp;
525 /*
526 * Range BPG Offset uses 2's complement and is only a 6 bits. So
527 * mask it to get only 6 bits.
528 */
529 vdsc_cfg->rc_range_params[i].range_bpg_offset =
530 rc_params->rc_range_params[i].range_bpg_offset &
531 DSC_RANGE_BPG_OFFSET_MASK;
532 }
533
534 /*
535 * BitsPerComponent value determines mux_word_size:
536 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
537 * 48 bits otherwise 64
538 */
539 if (vdsc_cfg->bits_per_component <= 10)
540 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
541 else
542 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
543
544 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
545 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
546 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
547
548 kfree(rc);
549
550 return 0;
551 }
552
553 enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc * crtc,enum transcoder cpu_transcoder)554 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
555 {
556 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
557 enum pipe pipe = crtc->pipe;
558
559 /*
560 * VDSC/joining uses a separate power well, PW2, and requires
561 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
562 *
563 * - ICL eDP/DSI transcoder
564 * - Display version 12 (except RKL) pipe A
565 *
566 * For any other pipe, VDSC/joining uses the power well associated with
567 * the pipe in use. Hence another reference on the pipe power domain
568 * will suffice. (Except no VDSC/joining on ICL pipe A.)
569 */
570 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
571 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
572 else if (is_pipe_dsc(crtc, cpu_transcoder))
573 return POWER_DOMAIN_PIPE(pipe);
574 else
575 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
576 }
577
intel_dsc_pps_configure(const struct intel_crtc_state * crtc_state)578 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
579 {
580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
582 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
583 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
584 enum pipe pipe = crtc->pipe;
585 u32 pps_val = 0;
586 u32 rc_buf_thresh_dword[4];
587 u32 rc_range_params_dword[8];
588 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
589 int i = 0;
590
591 if (crtc_state->bigjoiner_pipes)
592 num_vdsc_instances *= 2;
593
594 /* Populate PICTURE_PARAMETER_SET_0 registers */
595 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
596 DSC_VER_MIN_SHIFT |
597 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
598 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
599 if (vdsc_cfg->dsc_version_minor == 2)
600 pps_val |= DSC_ALT_ICH_SEL;
601 if (vdsc_cfg->block_pred_enable)
602 pps_val |= DSC_BLOCK_PREDICTION;
603 if (vdsc_cfg->convert_rgb)
604 pps_val |= DSC_COLOR_SPACE_CONVERSION;
605 if (vdsc_cfg->simple_422)
606 pps_val |= DSC_422_ENABLE;
607 if (vdsc_cfg->vbr_enable)
608 pps_val |= DSC_VBR_ENABLE;
609 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
610 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
611 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
612 pps_val);
613 /*
614 * If 2 VDSC instances are needed, configure PPS for second
615 * VDSC
616 */
617 if (crtc_state->dsc.dsc_split)
618 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
619 pps_val);
620 } else {
621 intel_de_write(dev_priv,
622 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
623 pps_val);
624 if (crtc_state->dsc.dsc_split)
625 intel_de_write(dev_priv,
626 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
627 pps_val);
628 }
629
630 /* Populate PICTURE_PARAMETER_SET_1 registers */
631 pps_val = 0;
632 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
633 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
634 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
635 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
636 pps_val);
637 /*
638 * If 2 VDSC instances are needed, configure PPS for second
639 * VDSC
640 */
641 if (crtc_state->dsc.dsc_split)
642 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
643 pps_val);
644 } else {
645 intel_de_write(dev_priv,
646 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
647 pps_val);
648 if (crtc_state->dsc.dsc_split)
649 intel_de_write(dev_priv,
650 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
651 pps_val);
652 }
653
654 /* Populate PICTURE_PARAMETER_SET_2 registers */
655 pps_val = 0;
656 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
657 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
658 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
659 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
660 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
661 pps_val);
662 /*
663 * If 2 VDSC instances are needed, configure PPS for second
664 * VDSC
665 */
666 if (crtc_state->dsc.dsc_split)
667 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
668 pps_val);
669 } else {
670 intel_de_write(dev_priv,
671 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
672 pps_val);
673 if (crtc_state->dsc.dsc_split)
674 intel_de_write(dev_priv,
675 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
676 pps_val);
677 }
678
679 /* Populate PICTURE_PARAMETER_SET_3 registers */
680 pps_val = 0;
681 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
682 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
683 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
684 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
685 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
686 pps_val);
687 /*
688 * If 2 VDSC instances are needed, configure PPS for second
689 * VDSC
690 */
691 if (crtc_state->dsc.dsc_split)
692 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
693 pps_val);
694 } else {
695 intel_de_write(dev_priv,
696 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
697 pps_val);
698 if (crtc_state->dsc.dsc_split)
699 intel_de_write(dev_priv,
700 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
701 pps_val);
702 }
703
704 /* Populate PICTURE_PARAMETER_SET_4 registers */
705 pps_val = 0;
706 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
707 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
708 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
709 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
710 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
711 pps_val);
712 /*
713 * If 2 VDSC instances are needed, configure PPS for second
714 * VDSC
715 */
716 if (crtc_state->dsc.dsc_split)
717 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
718 pps_val);
719 } else {
720 intel_de_write(dev_priv,
721 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
722 pps_val);
723 if (crtc_state->dsc.dsc_split)
724 intel_de_write(dev_priv,
725 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
726 pps_val);
727 }
728
729 /* Populate PICTURE_PARAMETER_SET_5 registers */
730 pps_val = 0;
731 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
732 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
733 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
734 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
735 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
736 pps_val);
737 /*
738 * If 2 VDSC instances are needed, configure PPS for second
739 * VDSC
740 */
741 if (crtc_state->dsc.dsc_split)
742 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
743 pps_val);
744 } else {
745 intel_de_write(dev_priv,
746 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
747 pps_val);
748 if (crtc_state->dsc.dsc_split)
749 intel_de_write(dev_priv,
750 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
751 pps_val);
752 }
753
754 /* Populate PICTURE_PARAMETER_SET_6 registers */
755 pps_val = 0;
756 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
757 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
758 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
759 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
760 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
761 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
762 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
763 pps_val);
764 /*
765 * If 2 VDSC instances are needed, configure PPS for second
766 * VDSC
767 */
768 if (crtc_state->dsc.dsc_split)
769 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
770 pps_val);
771 } else {
772 intel_de_write(dev_priv,
773 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
774 pps_val);
775 if (crtc_state->dsc.dsc_split)
776 intel_de_write(dev_priv,
777 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
778 pps_val);
779 }
780
781 /* Populate PICTURE_PARAMETER_SET_7 registers */
782 pps_val = 0;
783 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
784 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
785 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
786 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
787 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
788 pps_val);
789 /*
790 * If 2 VDSC instances are needed, configure PPS for second
791 * VDSC
792 */
793 if (crtc_state->dsc.dsc_split)
794 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
795 pps_val);
796 } else {
797 intel_de_write(dev_priv,
798 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
799 pps_val);
800 if (crtc_state->dsc.dsc_split)
801 intel_de_write(dev_priv,
802 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
803 pps_val);
804 }
805
806 /* Populate PICTURE_PARAMETER_SET_8 registers */
807 pps_val = 0;
808 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
809 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
810 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
811 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
812 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
813 pps_val);
814 /*
815 * If 2 VDSC instances are needed, configure PPS for second
816 * VDSC
817 */
818 if (crtc_state->dsc.dsc_split)
819 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
820 pps_val);
821 } else {
822 intel_de_write(dev_priv,
823 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
824 pps_val);
825 if (crtc_state->dsc.dsc_split)
826 intel_de_write(dev_priv,
827 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
828 pps_val);
829 }
830
831 /* Populate PICTURE_PARAMETER_SET_9 registers */
832 pps_val = 0;
833 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
834 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
835 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
836 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
837 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
838 pps_val);
839 /*
840 * If 2 VDSC instances are needed, configure PPS for second
841 * VDSC
842 */
843 if (crtc_state->dsc.dsc_split)
844 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
845 pps_val);
846 } else {
847 intel_de_write(dev_priv,
848 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
849 pps_val);
850 if (crtc_state->dsc.dsc_split)
851 intel_de_write(dev_priv,
852 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
853 pps_val);
854 }
855
856 /* Populate PICTURE_PARAMETER_SET_10 registers */
857 pps_val = 0;
858 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
859 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
860 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
861 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
862 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
863 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
864 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
865 pps_val);
866 /*
867 * If 2 VDSC instances are needed, configure PPS for second
868 * VDSC
869 */
870 if (crtc_state->dsc.dsc_split)
871 intel_de_write(dev_priv,
872 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
873 } else {
874 intel_de_write(dev_priv,
875 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
876 pps_val);
877 if (crtc_state->dsc.dsc_split)
878 intel_de_write(dev_priv,
879 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
880 pps_val);
881 }
882
883 /* Populate Picture parameter set 16 */
884 pps_val = 0;
885 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
886 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
887 vdsc_cfg->slice_width) |
888 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
889 vdsc_cfg->slice_height);
890 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
891 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
892 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
893 pps_val);
894 /*
895 * If 2 VDSC instances are needed, configure PPS for second
896 * VDSC
897 */
898 if (crtc_state->dsc.dsc_split)
899 intel_de_write(dev_priv,
900 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
901 } else {
902 intel_de_write(dev_priv,
903 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
904 pps_val);
905 if (crtc_state->dsc.dsc_split)
906 intel_de_write(dev_priv,
907 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
908 pps_val);
909 }
910
911 /* Populate the RC_BUF_THRESH registers */
912 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
913 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
914 rc_buf_thresh_dword[i / 4] |=
915 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
916 BITS_PER_BYTE * (i % 4));
917 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
918 rc_buf_thresh_dword[i / 4]);
919 }
920 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
921 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
922 rc_buf_thresh_dword[0]);
923 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
924 rc_buf_thresh_dword[1]);
925 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
926 rc_buf_thresh_dword[2]);
927 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
928 rc_buf_thresh_dword[3]);
929 if (crtc_state->dsc.dsc_split) {
930 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
931 rc_buf_thresh_dword[0]);
932 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
933 rc_buf_thresh_dword[1]);
934 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
935 rc_buf_thresh_dword[2]);
936 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
937 rc_buf_thresh_dword[3]);
938 }
939 } else {
940 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
941 rc_buf_thresh_dword[0]);
942 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
943 rc_buf_thresh_dword[1]);
944 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
945 rc_buf_thresh_dword[2]);
946 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
947 rc_buf_thresh_dword[3]);
948 if (crtc_state->dsc.dsc_split) {
949 intel_de_write(dev_priv,
950 ICL_DSC1_RC_BUF_THRESH_0(pipe),
951 rc_buf_thresh_dword[0]);
952 intel_de_write(dev_priv,
953 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
954 rc_buf_thresh_dword[1]);
955 intel_de_write(dev_priv,
956 ICL_DSC1_RC_BUF_THRESH_1(pipe),
957 rc_buf_thresh_dword[2]);
958 intel_de_write(dev_priv,
959 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
960 rc_buf_thresh_dword[3]);
961 }
962 }
963
964 /* Populate the RC_RANGE_PARAMETERS registers */
965 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
966 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
967 rc_range_params_dword[i / 2] |=
968 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
969 RC_BPG_OFFSET_SHIFT) |
970 (vdsc_cfg->rc_range_params[i].range_max_qp <<
971 RC_MAX_QP_SHIFT) |
972 (vdsc_cfg->rc_range_params[i].range_min_qp <<
973 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
974 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
975 rc_range_params_dword[i / 2]);
976 }
977 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
978 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
979 rc_range_params_dword[0]);
980 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
981 rc_range_params_dword[1]);
982 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
983 rc_range_params_dword[2]);
984 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
985 rc_range_params_dword[3]);
986 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
987 rc_range_params_dword[4]);
988 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
989 rc_range_params_dword[5]);
990 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
991 rc_range_params_dword[6]);
992 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
993 rc_range_params_dword[7]);
994 if (crtc_state->dsc.dsc_split) {
995 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
996 rc_range_params_dword[0]);
997 intel_de_write(dev_priv,
998 DSCC_RC_RANGE_PARAMETERS_0_UDW,
999 rc_range_params_dword[1]);
1000 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
1001 rc_range_params_dword[2]);
1002 intel_de_write(dev_priv,
1003 DSCC_RC_RANGE_PARAMETERS_1_UDW,
1004 rc_range_params_dword[3]);
1005 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
1006 rc_range_params_dword[4]);
1007 intel_de_write(dev_priv,
1008 DSCC_RC_RANGE_PARAMETERS_2_UDW,
1009 rc_range_params_dword[5]);
1010 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
1011 rc_range_params_dword[6]);
1012 intel_de_write(dev_priv,
1013 DSCC_RC_RANGE_PARAMETERS_3_UDW,
1014 rc_range_params_dword[7]);
1015 }
1016 } else {
1017 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
1018 rc_range_params_dword[0]);
1019 intel_de_write(dev_priv,
1020 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
1021 rc_range_params_dword[1]);
1022 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
1023 rc_range_params_dword[2]);
1024 intel_de_write(dev_priv,
1025 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
1026 rc_range_params_dword[3]);
1027 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
1028 rc_range_params_dword[4]);
1029 intel_de_write(dev_priv,
1030 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
1031 rc_range_params_dword[5]);
1032 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
1033 rc_range_params_dword[6]);
1034 intel_de_write(dev_priv,
1035 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
1036 rc_range_params_dword[7]);
1037 if (crtc_state->dsc.dsc_split) {
1038 intel_de_write(dev_priv,
1039 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
1040 rc_range_params_dword[0]);
1041 intel_de_write(dev_priv,
1042 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
1043 rc_range_params_dword[1]);
1044 intel_de_write(dev_priv,
1045 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
1046 rc_range_params_dword[2]);
1047 intel_de_write(dev_priv,
1048 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
1049 rc_range_params_dword[3]);
1050 intel_de_write(dev_priv,
1051 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
1052 rc_range_params_dword[4]);
1053 intel_de_write(dev_priv,
1054 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
1055 rc_range_params_dword[5]);
1056 intel_de_write(dev_priv,
1057 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
1058 rc_range_params_dword[6]);
1059 intel_de_write(dev_priv,
1060 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
1061 rc_range_params_dword[7]);
1062 }
1063 }
1064 }
1065
intel_dsc_dsi_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1066 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
1067 const struct intel_crtc_state *crtc_state)
1068 {
1069 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1070 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1071 struct mipi_dsi_device *dsi;
1072 struct drm_dsc_picture_parameter_set pps;
1073 enum port port;
1074
1075 if (!crtc_state->dsc.compression_enable)
1076 return;
1077
1078 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
1079
1080 for_each_dsi_port(port, intel_dsi->ports) {
1081 dsi = intel_dsi->dsi_hosts[port]->device;
1082
1083 mipi_dsi_picture_parameter_set(dsi, &pps);
1084 mipi_dsi_compression_mode(dsi, true);
1085 }
1086 }
1087
intel_dsc_dp_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1088 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
1089 const struct intel_crtc_state *crtc_state)
1090 {
1091 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1092 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1093 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1094
1095 if (!crtc_state->dsc.compression_enable)
1096 return;
1097
1098 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1099 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1100
1101 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1102 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1103
1104 dig_port->write_infoframe(encoder, crtc_state,
1105 DP_SDP_PPS, &dp_dsc_pps_sdp,
1106 sizeof(dp_dsc_pps_sdp));
1107 }
1108
dss_ctl1_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)1109 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1110 {
1111 return is_pipe_dsc(crtc, cpu_transcoder) ?
1112 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
1113 }
1114
dss_ctl2_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)1115 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1116 {
1117 return is_pipe_dsc(crtc, cpu_transcoder) ?
1118 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
1119 }
1120
intel_uncompressed_joiner_enable(const struct intel_crtc_state * crtc_state)1121 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
1122 {
1123 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1124 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1125 u32 dss_ctl1_val = 0;
1126
1127 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) {
1128 if (intel_crtc_is_bigjoiner_slave(crtc_state))
1129 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
1130 else
1131 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
1132
1133 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1134 }
1135 }
1136
intel_dsc_enable(const struct intel_crtc_state * crtc_state)1137 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
1138 {
1139 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1141 u32 dss_ctl1_val = 0;
1142 u32 dss_ctl2_val = 0;
1143
1144 if (!crtc_state->dsc.compression_enable)
1145 return;
1146
1147 intel_dsc_pps_configure(crtc_state);
1148
1149 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1150 if (crtc_state->dsc.dsc_split) {
1151 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1152 dss_ctl1_val |= JOINER_ENABLE;
1153 }
1154 if (crtc_state->bigjoiner_pipes) {
1155 dss_ctl1_val |= BIG_JOINER_ENABLE;
1156 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
1157 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1158 }
1159 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1160 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
1161 }
1162
intel_dsc_disable(const struct intel_crtc_state * old_crtc_state)1163 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1164 {
1165 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1166 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1167
1168 /* Disable only if either of them is enabled */
1169 if (old_crtc_state->dsc.compression_enable ||
1170 old_crtc_state->bigjoiner_pipes) {
1171 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1172 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1173 }
1174 }
1175
intel_dsc_get_config(struct intel_crtc_state * crtc_state)1176 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1177 {
1178 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1180 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1181 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1182 enum pipe pipe = crtc->pipe;
1183 enum intel_display_power_domain power_domain;
1184 intel_wakeref_t wakeref;
1185 u32 dss_ctl1, dss_ctl2, val;
1186
1187 if (!intel_dsc_source_support(crtc_state))
1188 return;
1189
1190 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
1191
1192 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1193 if (!wakeref)
1194 return;
1195
1196 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
1197 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
1198
1199 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1200 if (!crtc_state->dsc.compression_enable)
1201 goto out;
1202
1203 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1204 (dss_ctl1 & JOINER_ENABLE);
1205
1206 /* FIXME: add more state readout as needed */
1207
1208 /* PPS1 */
1209 if (!is_pipe_dsc(crtc, cpu_transcoder))
1210 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1211 else
1212 val = intel_de_read(dev_priv,
1213 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1214 vdsc_cfg->bits_per_pixel = val;
1215 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1216 out:
1217 intel_display_power_put(dev_priv, power_domain, wakeref);
1218 }
1219