1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8 #include <linux/limits.h>
9
10 #include <drm/display/drm_dsc_helper.h>
11
12 #include "i915_drv.h"
13 #include "intel_crtc.h"
14 #include "intel_de.h"
15 #include "intel_display_types.h"
16 #include "intel_dsi.h"
17 #include "intel_qp_tables.h"
18 #include "intel_vdsc.h"
19
20 enum ROW_INDEX_BPP {
21 ROW_INDEX_6BPP = 0,
22 ROW_INDEX_8BPP,
23 ROW_INDEX_10BPP,
24 ROW_INDEX_12BPP,
25 ROW_INDEX_15BPP,
26 MAX_ROW_INDEX
27 };
28
29 enum COLUMN_INDEX_BPC {
30 COLUMN_INDEX_8BPC = 0,
31 COLUMN_INDEX_10BPC,
32 COLUMN_INDEX_12BPC,
33 COLUMN_INDEX_14BPC,
34 COLUMN_INDEX_16BPC,
35 MAX_COLUMN_INDEX
36 };
37
38 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
39 static const u16 rc_buf_thresh[] = {
40 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
41 7744, 7872, 8000, 8064
42 };
43
44 struct rc_parameters {
45 u16 initial_xmit_delay;
46 u8 first_line_bpg_offset;
47 u16 initial_offset;
48 u8 flatness_min_qp;
49 u8 flatness_max_qp;
50 u8 rc_quant_incr_limit0;
51 u8 rc_quant_incr_limit1;
52 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
53 };
54
55 /*
56 * Selected Rate Control Related Parameter Recommended Values
57 * from DSC_v1.11 spec & C Model release: DSC_model_20161212
58 */
59 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
60 {
61 /* 6BPP/8BPC */
62 { 768, 15, 6144, 3, 13, 11, 11, {
63 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
64 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
65 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
66 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
67 }
68 },
69 /* 6BPP/10BPC */
70 { 768, 15, 6144, 7, 17, 15, 15, {
71 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
72 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
73 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
74 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
75 { 17, 18, -12 }
76 }
77 },
78 /* 6BPP/12BPC */
79 { 768, 15, 6144, 11, 21, 19, 19, {
80 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
81 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
82 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
83 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
84 { 21, 22, -12 }
85 }
86 },
87 /* 6BPP/14BPC */
88 { 768, 15, 6144, 15, 25, 23, 27, {
89 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
90 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
91 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
92 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
93 { 25, 26, -12 }
94 }
95 },
96 /* 6BPP/16BPC */
97 { 768, 15, 6144, 19, 29, 27, 27, {
98 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
99 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
100 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
101 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
102 { 29, 30, -12 }
103 }
104 },
105 },
106 {
107 /* 8BPP/8BPC */
108 { 512, 12, 6144, 3, 12, 11, 11, {
109 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
110 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
111 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
112 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
113 }
114 },
115 /* 8BPP/10BPC */
116 { 512, 12, 6144, 7, 16, 15, 15, {
117 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
118 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
119 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
120 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
121 }
122 },
123 /* 8BPP/12BPC */
124 { 512, 12, 6144, 11, 20, 19, 19, {
125 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
126 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
127 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
128 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
129 { 21, 23, -12 }
130 }
131 },
132 /* 8BPP/14BPC */
133 { 512, 12, 6144, 15, 24, 23, 23, {
134 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
135 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
136 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
137 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
138 { 24, 25, -12 }
139 }
140 },
141 /* 8BPP/16BPC */
142 { 512, 12, 6144, 19, 28, 27, 27, {
143 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
144 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
145 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
146 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
147 { 28, 29, -12 }
148 }
149 },
150 },
151 {
152 /* 10BPP/8BPC */
153 { 410, 15, 5632, 3, 12, 11, 11, {
154 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
155 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
156 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
157 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
158 }
159 },
160 /* 10BPP/10BPC */
161 { 410, 15, 5632, 7, 16, 15, 15, {
162 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
163 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
164 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
165 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
166 }
167 },
168 /* 10BPP/12BPC */
169 { 410, 15, 5632, 11, 20, 19, 19, {
170 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
171 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
172 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
173 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
174 { 19, 20, -12 }
175 }
176 },
177 /* 10BPP/14BPC */
178 { 410, 15, 5632, 15, 24, 23, 23, {
179 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
180 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
181 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
182 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
183 { 23, 24, -12 }
184 }
185 },
186 /* 10BPP/16BPC */
187 { 410, 15, 5632, 19, 28, 27, 27, {
188 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
189 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
190 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
191 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
192 { 27, 28, -12 }
193 }
194 },
195 },
196 {
197 /* 12BPP/8BPC */
198 { 341, 15, 2048, 3, 12, 11, 11, {
199 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
200 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
201 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
202 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
203 }
204 },
205 /* 12BPP/10BPC */
206 { 341, 15, 2048, 7, 16, 15, 15, {
207 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
208 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
209 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
210 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
211 }
212 },
213 /* 12BPP/12BPC */
214 { 341, 15, 2048, 11, 20, 19, 19, {
215 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
216 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
217 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
218 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
219 { 21, 23, -12 }
220 }
221 },
222 /* 12BPP/14BPC */
223 { 341, 15, 2048, 15, 24, 23, 23, {
224 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
225 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
226 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
227 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
228 { 22, 23, -12 }
229 }
230 },
231 /* 12BPP/16BPC */
232 { 341, 15, 2048, 19, 28, 27, 27, {
233 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
234 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
235 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
236 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
237 { 26, 27, -12 }
238 }
239 },
240 },
241 {
242 /* 15BPP/8BPC */
243 { 273, 15, 2048, 3, 12, 11, 11, {
244 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
245 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
246 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
247 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
248 }
249 },
250 /* 15BPP/10BPC */
251 { 273, 15, 2048, 7, 16, 15, 15, {
252 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
253 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
254 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
255 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
256 }
257 },
258 /* 15BPP/12BPC */
259 { 273, 15, 2048, 11, 20, 19, 19, {
260 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
261 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
262 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
263 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
264 { 16, 17, -12 }
265 }
266 },
267 /* 15BPP/14BPC */
268 { 273, 15, 2048, 15, 24, 23, 23, {
269 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
270 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
271 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
272 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
273 { 20, 21, -12 }
274 }
275 },
276 /* 15BPP/16BPC */
277 { 273, 15, 2048, 19, 28, 27, 27, {
278 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
279 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
280 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
281 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
282 { 24, 25, -12 }
283 }
284 }
285 }
286
287 };
288
get_row_index_for_rc_params(u16 compressed_bpp)289 static int get_row_index_for_rc_params(u16 compressed_bpp)
290 {
291 switch (compressed_bpp) {
292 case 6:
293 return ROW_INDEX_6BPP;
294 case 8:
295 return ROW_INDEX_8BPP;
296 case 10:
297 return ROW_INDEX_10BPP;
298 case 12:
299 return ROW_INDEX_12BPP;
300 case 15:
301 return ROW_INDEX_15BPP;
302 default:
303 return -EINVAL;
304 }
305 }
306
get_column_index_for_rc_params(u8 bits_per_component)307 static int get_column_index_for_rc_params(u8 bits_per_component)
308 {
309 switch (bits_per_component) {
310 case 8:
311 return COLUMN_INDEX_8BPC;
312 case 10:
313 return COLUMN_INDEX_10BPC;
314 case 12:
315 return COLUMN_INDEX_12BPC;
316 case 14:
317 return COLUMN_INDEX_14BPC;
318 case 16:
319 return COLUMN_INDEX_16BPC;
320 default:
321 return -EINVAL;
322 }
323 }
324
get_rc_params(u16 compressed_bpp,u8 bits_per_component)325 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
326 u8 bits_per_component)
327 {
328 int row_index, column_index;
329
330 row_index = get_row_index_for_rc_params(compressed_bpp);
331 if (row_index < 0)
332 return NULL;
333
334 column_index = get_column_index_for_rc_params(bits_per_component);
335 if (column_index < 0)
336 return NULL;
337
338 return &rc_parameters[row_index][column_index];
339 }
340
intel_dsc_source_support(const struct intel_crtc_state * crtc_state)341 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
342 {
343 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
344 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
345 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
346
347 if (!INTEL_INFO(i915)->display.has_dsc)
348 return false;
349
350 if (DISPLAY_VER(i915) >= 12)
351 return true;
352
353 if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
354 return true;
355
356 return false;
357 }
358
is_pipe_dsc(struct intel_crtc * crtc,enum transcoder cpu_transcoder)359 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
360 {
361 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
362
363 if (DISPLAY_VER(i915) >= 12)
364 return true;
365
366 if (cpu_transcoder == TRANSCODER_EDP ||
367 cpu_transcoder == TRANSCODER_DSI_0 ||
368 cpu_transcoder == TRANSCODER_DSI_1)
369 return false;
370
371 /* There's no pipe A DSC engine on ICL */
372 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
373
374 return true;
375 }
376
377 static void
calculate_rc_params(struct rc_parameters * rc,struct drm_dsc_config * vdsc_cfg)378 calculate_rc_params(struct rc_parameters *rc,
379 struct drm_dsc_config *vdsc_cfg)
380 {
381 int bpc = vdsc_cfg->bits_per_component;
382 int bpp = vdsc_cfg->bits_per_pixel >> 4;
383 static const s8 ofs_und6[] = {
384 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
385 };
386 static const s8 ofs_und8[] = {
387 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
388 };
389 static const s8 ofs_und12[] = {
390 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
391 };
392 static const s8 ofs_und15[] = {
393 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
394 };
395 int qp_bpc_modifier = (bpc - 8) * 2;
396 u32 res, buf_i, bpp_i;
397
398 if (vdsc_cfg->slice_height >= 8)
399 rc->first_line_bpg_offset =
400 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
401 else
402 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
403
404 /* Our hw supports only 444 modes as of today */
405 if (bpp >= 12)
406 rc->initial_offset = 2048;
407 else if (bpp >= 10)
408 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
409 else if (bpp >= 8)
410 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
411 else
412 rc->initial_offset = 6144;
413
414 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
415 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
416
417 rc->flatness_min_qp = 3 + qp_bpc_modifier;
418 rc->flatness_max_qp = 12 + qp_bpc_modifier;
419
420 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
421 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
422
423 bpp_i = (2 * (bpp - 6));
424 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
425 /* Read range_minqp and range_max_qp from qp tables */
426 rc->rc_range_params[buf_i].range_min_qp =
427 intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
428 rc->rc_range_params[buf_i].range_max_qp =
429 intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
430
431 /* Calculate range_bgp_offset */
432 if (bpp <= 6) {
433 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
434 } else if (bpp <= 8) {
435 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
436 rc->rc_range_params[buf_i].range_bpg_offset =
437 ofs_und6[buf_i] + res;
438 } else if (bpp <= 12) {
439 rc->rc_range_params[buf_i].range_bpg_offset =
440 ofs_und8[buf_i];
441 } else if (bpp <= 15) {
442 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
443 rc->rc_range_params[buf_i].range_bpg_offset =
444 ofs_und12[buf_i] + res;
445 } else {
446 rc->rc_range_params[buf_i].range_bpg_offset =
447 ofs_und15[buf_i];
448 }
449 }
450 }
451
intel_dsc_compute_params(struct intel_crtc_state * pipe_config)452 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
453 {
454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
456 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
457 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
458 const struct rc_parameters *rc_params;
459 struct rc_parameters *rc = NULL;
460 u8 i = 0;
461
462 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
463 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
464 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
465 pipe_config->dsc.slice_count);
466
467 /* Gen 11 does not support YCbCr */
468 vdsc_cfg->simple_422 = false;
469 /* Gen 11 does not support VBR */
470 vdsc_cfg->vbr_enable = false;
471
472 /* Gen 11 only supports integral values of bpp */
473 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
474 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
475
476 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
477 /*
478 * six 0s are appended to the lsb of each threshold value
479 * internally in h/w.
480 * Only 8 bits are allowed for programming RcBufThreshold
481 */
482 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
483 }
484
485 /*
486 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
487 * as per C Model
488 */
489 if (compressed_bpp == 6) {
490 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
491 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
492 }
493
494 /*
495 * From XE_LPD onwards we supports compression bpps in steps of 1
496 * upto uncompressed bpp-1, hence add calculations for all the rc
497 * parameters
498 */
499 if (DISPLAY_VER(dev_priv) >= 13) {
500 rc = kmalloc(sizeof(*rc), GFP_KERNEL);
501 if (!rc)
502 return -ENOMEM;
503
504 calculate_rc_params(rc, vdsc_cfg);
505 rc_params = rc;
506 } else {
507 rc_params = get_rc_params(compressed_bpp,
508 vdsc_cfg->bits_per_component);
509 if (!rc_params)
510 return -EINVAL;
511 }
512
513 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
514 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
515 vdsc_cfg->initial_offset = rc_params->initial_offset;
516 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
517 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
518 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
519 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
520
521 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
522 vdsc_cfg->rc_range_params[i].range_min_qp =
523 rc_params->rc_range_params[i].range_min_qp;
524 vdsc_cfg->rc_range_params[i].range_max_qp =
525 rc_params->rc_range_params[i].range_max_qp;
526 /*
527 * Range BPG Offset uses 2's complement and is only a 6 bits. So
528 * mask it to get only 6 bits.
529 */
530 vdsc_cfg->rc_range_params[i].range_bpg_offset =
531 rc_params->rc_range_params[i].range_bpg_offset &
532 DSC_RANGE_BPG_OFFSET_MASK;
533 }
534
535 /*
536 * BitsPerComponent value determines mux_word_size:
537 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
538 * 48 bits otherwise 64
539 */
540 if (vdsc_cfg->bits_per_component <= 10)
541 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
542 else
543 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
544
545 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
546 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
547 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
548
549 kfree(rc);
550
551 return 0;
552 }
553
554 enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc * crtc,enum transcoder cpu_transcoder)555 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
556 {
557 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
558 enum pipe pipe = crtc->pipe;
559
560 /*
561 * VDSC/joining uses a separate power well, PW2, and requires
562 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
563 *
564 * - ICL eDP/DSI transcoder
565 * - Display version 12 (except RKL) pipe A
566 *
567 * For any other pipe, VDSC/joining uses the power well associated with
568 * the pipe in use. Hence another reference on the pipe power domain
569 * will suffice. (Except no VDSC/joining on ICL pipe A.)
570 */
571 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
572 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
573 else if (is_pipe_dsc(crtc, cpu_transcoder))
574 return POWER_DOMAIN_PIPE(pipe);
575 else
576 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
577 }
578
intel_dsc_pps_configure(const struct intel_crtc_state * crtc_state)579 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
580 {
581 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
582 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
583 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
584 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
585 enum pipe pipe = crtc->pipe;
586 u32 pps_val = 0;
587 u32 rc_buf_thresh_dword[4];
588 u32 rc_range_params_dword[8];
589 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
590 int i = 0;
591
592 if (crtc_state->bigjoiner_pipes)
593 num_vdsc_instances *= 2;
594
595 /* Populate PICTURE_PARAMETER_SET_0 registers */
596 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
597 DSC_VER_MIN_SHIFT |
598 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
599 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
600 if (vdsc_cfg->block_pred_enable)
601 pps_val |= DSC_BLOCK_PREDICTION;
602 if (vdsc_cfg->convert_rgb)
603 pps_val |= DSC_COLOR_SPACE_CONVERSION;
604 if (vdsc_cfg->simple_422)
605 pps_val |= DSC_422_ENABLE;
606 if (vdsc_cfg->vbr_enable)
607 pps_val |= DSC_VBR_ENABLE;
608 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
609 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
610 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
611 pps_val);
612 /*
613 * If 2 VDSC instances are needed, configure PPS for second
614 * VDSC
615 */
616 if (crtc_state->dsc.dsc_split)
617 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
618 pps_val);
619 } else {
620 intel_de_write(dev_priv,
621 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
622 pps_val);
623 if (crtc_state->dsc.dsc_split)
624 intel_de_write(dev_priv,
625 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
626 pps_val);
627 }
628
629 /* Populate PICTURE_PARAMETER_SET_1 registers */
630 pps_val = 0;
631 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
632 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
633 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
634 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
635 pps_val);
636 /*
637 * If 2 VDSC instances are needed, configure PPS for second
638 * VDSC
639 */
640 if (crtc_state->dsc.dsc_split)
641 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
642 pps_val);
643 } else {
644 intel_de_write(dev_priv,
645 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
646 pps_val);
647 if (crtc_state->dsc.dsc_split)
648 intel_de_write(dev_priv,
649 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
650 pps_val);
651 }
652
653 /* Populate PICTURE_PARAMETER_SET_2 registers */
654 pps_val = 0;
655 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
656 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
657 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
658 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
659 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
660 pps_val);
661 /*
662 * If 2 VDSC instances are needed, configure PPS for second
663 * VDSC
664 */
665 if (crtc_state->dsc.dsc_split)
666 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
667 pps_val);
668 } else {
669 intel_de_write(dev_priv,
670 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
671 pps_val);
672 if (crtc_state->dsc.dsc_split)
673 intel_de_write(dev_priv,
674 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
675 pps_val);
676 }
677
678 /* Populate PICTURE_PARAMETER_SET_3 registers */
679 pps_val = 0;
680 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
681 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
682 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
683 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
684 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
685 pps_val);
686 /*
687 * If 2 VDSC instances are needed, configure PPS for second
688 * VDSC
689 */
690 if (crtc_state->dsc.dsc_split)
691 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
692 pps_val);
693 } else {
694 intel_de_write(dev_priv,
695 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
696 pps_val);
697 if (crtc_state->dsc.dsc_split)
698 intel_de_write(dev_priv,
699 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
700 pps_val);
701 }
702
703 /* Populate PICTURE_PARAMETER_SET_4 registers */
704 pps_val = 0;
705 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
706 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
707 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
708 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
709 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
710 pps_val);
711 /*
712 * If 2 VDSC instances are needed, configure PPS for second
713 * VDSC
714 */
715 if (crtc_state->dsc.dsc_split)
716 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
717 pps_val);
718 } else {
719 intel_de_write(dev_priv,
720 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
721 pps_val);
722 if (crtc_state->dsc.dsc_split)
723 intel_de_write(dev_priv,
724 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
725 pps_val);
726 }
727
728 /* Populate PICTURE_PARAMETER_SET_5 registers */
729 pps_val = 0;
730 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
731 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
732 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
733 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
734 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
735 pps_val);
736 /*
737 * If 2 VDSC instances are needed, configure PPS for second
738 * VDSC
739 */
740 if (crtc_state->dsc.dsc_split)
741 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
742 pps_val);
743 } else {
744 intel_de_write(dev_priv,
745 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
746 pps_val);
747 if (crtc_state->dsc.dsc_split)
748 intel_de_write(dev_priv,
749 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
750 pps_val);
751 }
752
753 /* Populate PICTURE_PARAMETER_SET_6 registers */
754 pps_val = 0;
755 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
756 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
757 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
758 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
759 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
760 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
761 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
762 pps_val);
763 /*
764 * If 2 VDSC instances are needed, configure PPS for second
765 * VDSC
766 */
767 if (crtc_state->dsc.dsc_split)
768 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
769 pps_val);
770 } else {
771 intel_de_write(dev_priv,
772 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
773 pps_val);
774 if (crtc_state->dsc.dsc_split)
775 intel_de_write(dev_priv,
776 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
777 pps_val);
778 }
779
780 /* Populate PICTURE_PARAMETER_SET_7 registers */
781 pps_val = 0;
782 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
783 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
784 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
785 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
786 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
787 pps_val);
788 /*
789 * If 2 VDSC instances are needed, configure PPS for second
790 * VDSC
791 */
792 if (crtc_state->dsc.dsc_split)
793 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
794 pps_val);
795 } else {
796 intel_de_write(dev_priv,
797 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
798 pps_val);
799 if (crtc_state->dsc.dsc_split)
800 intel_de_write(dev_priv,
801 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
802 pps_val);
803 }
804
805 /* Populate PICTURE_PARAMETER_SET_8 registers */
806 pps_val = 0;
807 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
808 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
809 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
810 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
811 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
812 pps_val);
813 /*
814 * If 2 VDSC instances are needed, configure PPS for second
815 * VDSC
816 */
817 if (crtc_state->dsc.dsc_split)
818 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
819 pps_val);
820 } else {
821 intel_de_write(dev_priv,
822 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
823 pps_val);
824 if (crtc_state->dsc.dsc_split)
825 intel_de_write(dev_priv,
826 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
827 pps_val);
828 }
829
830 /* Populate PICTURE_PARAMETER_SET_9 registers */
831 pps_val = 0;
832 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
833 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
834 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
835 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
836 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
837 pps_val);
838 /*
839 * If 2 VDSC instances are needed, configure PPS for second
840 * VDSC
841 */
842 if (crtc_state->dsc.dsc_split)
843 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
844 pps_val);
845 } else {
846 intel_de_write(dev_priv,
847 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
848 pps_val);
849 if (crtc_state->dsc.dsc_split)
850 intel_de_write(dev_priv,
851 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
852 pps_val);
853 }
854
855 /* Populate PICTURE_PARAMETER_SET_10 registers */
856 pps_val = 0;
857 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
858 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
859 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
860 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
861 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
862 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
863 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
864 pps_val);
865 /*
866 * If 2 VDSC instances are needed, configure PPS for second
867 * VDSC
868 */
869 if (crtc_state->dsc.dsc_split)
870 intel_de_write(dev_priv,
871 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
872 } else {
873 intel_de_write(dev_priv,
874 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
875 pps_val);
876 if (crtc_state->dsc.dsc_split)
877 intel_de_write(dev_priv,
878 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
879 pps_val);
880 }
881
882 /* Populate Picture parameter set 16 */
883 pps_val = 0;
884 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
885 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
886 vdsc_cfg->slice_width) |
887 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
888 vdsc_cfg->slice_height);
889 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
890 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
891 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
892 pps_val);
893 /*
894 * If 2 VDSC instances are needed, configure PPS for second
895 * VDSC
896 */
897 if (crtc_state->dsc.dsc_split)
898 intel_de_write(dev_priv,
899 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
900 } else {
901 intel_de_write(dev_priv,
902 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
903 pps_val);
904 if (crtc_state->dsc.dsc_split)
905 intel_de_write(dev_priv,
906 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
907 pps_val);
908 }
909
910 /* Populate the RC_BUF_THRESH registers */
911 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
912 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
913 rc_buf_thresh_dword[i / 4] |=
914 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
915 BITS_PER_BYTE * (i % 4));
916 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
917 rc_buf_thresh_dword[i / 4]);
918 }
919 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
920 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
921 rc_buf_thresh_dword[0]);
922 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
923 rc_buf_thresh_dword[1]);
924 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
925 rc_buf_thresh_dword[2]);
926 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
927 rc_buf_thresh_dword[3]);
928 if (crtc_state->dsc.dsc_split) {
929 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
930 rc_buf_thresh_dword[0]);
931 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
932 rc_buf_thresh_dword[1]);
933 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
934 rc_buf_thresh_dword[2]);
935 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
936 rc_buf_thresh_dword[3]);
937 }
938 } else {
939 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
940 rc_buf_thresh_dword[0]);
941 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
942 rc_buf_thresh_dword[1]);
943 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
944 rc_buf_thresh_dword[2]);
945 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
946 rc_buf_thresh_dword[3]);
947 if (crtc_state->dsc.dsc_split) {
948 intel_de_write(dev_priv,
949 ICL_DSC1_RC_BUF_THRESH_0(pipe),
950 rc_buf_thresh_dword[0]);
951 intel_de_write(dev_priv,
952 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
953 rc_buf_thresh_dword[1]);
954 intel_de_write(dev_priv,
955 ICL_DSC1_RC_BUF_THRESH_1(pipe),
956 rc_buf_thresh_dword[2]);
957 intel_de_write(dev_priv,
958 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
959 rc_buf_thresh_dword[3]);
960 }
961 }
962
963 /* Populate the RC_RANGE_PARAMETERS registers */
964 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
965 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
966 rc_range_params_dword[i / 2] |=
967 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
968 RC_BPG_OFFSET_SHIFT) |
969 (vdsc_cfg->rc_range_params[i].range_max_qp <<
970 RC_MAX_QP_SHIFT) |
971 (vdsc_cfg->rc_range_params[i].range_min_qp <<
972 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
973 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
974 rc_range_params_dword[i / 2]);
975 }
976 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
977 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
978 rc_range_params_dword[0]);
979 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
980 rc_range_params_dword[1]);
981 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
982 rc_range_params_dword[2]);
983 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
984 rc_range_params_dword[3]);
985 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
986 rc_range_params_dword[4]);
987 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
988 rc_range_params_dword[5]);
989 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
990 rc_range_params_dword[6]);
991 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
992 rc_range_params_dword[7]);
993 if (crtc_state->dsc.dsc_split) {
994 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
995 rc_range_params_dword[0]);
996 intel_de_write(dev_priv,
997 DSCC_RC_RANGE_PARAMETERS_0_UDW,
998 rc_range_params_dword[1]);
999 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
1000 rc_range_params_dword[2]);
1001 intel_de_write(dev_priv,
1002 DSCC_RC_RANGE_PARAMETERS_1_UDW,
1003 rc_range_params_dword[3]);
1004 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
1005 rc_range_params_dword[4]);
1006 intel_de_write(dev_priv,
1007 DSCC_RC_RANGE_PARAMETERS_2_UDW,
1008 rc_range_params_dword[5]);
1009 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
1010 rc_range_params_dword[6]);
1011 intel_de_write(dev_priv,
1012 DSCC_RC_RANGE_PARAMETERS_3_UDW,
1013 rc_range_params_dword[7]);
1014 }
1015 } else {
1016 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
1017 rc_range_params_dword[0]);
1018 intel_de_write(dev_priv,
1019 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
1020 rc_range_params_dword[1]);
1021 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
1022 rc_range_params_dword[2]);
1023 intel_de_write(dev_priv,
1024 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
1025 rc_range_params_dword[3]);
1026 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
1027 rc_range_params_dword[4]);
1028 intel_de_write(dev_priv,
1029 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
1030 rc_range_params_dword[5]);
1031 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
1032 rc_range_params_dword[6]);
1033 intel_de_write(dev_priv,
1034 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
1035 rc_range_params_dword[7]);
1036 if (crtc_state->dsc.dsc_split) {
1037 intel_de_write(dev_priv,
1038 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
1039 rc_range_params_dword[0]);
1040 intel_de_write(dev_priv,
1041 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
1042 rc_range_params_dword[1]);
1043 intel_de_write(dev_priv,
1044 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
1045 rc_range_params_dword[2]);
1046 intel_de_write(dev_priv,
1047 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
1048 rc_range_params_dword[3]);
1049 intel_de_write(dev_priv,
1050 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
1051 rc_range_params_dword[4]);
1052 intel_de_write(dev_priv,
1053 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
1054 rc_range_params_dword[5]);
1055 intel_de_write(dev_priv,
1056 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
1057 rc_range_params_dword[6]);
1058 intel_de_write(dev_priv,
1059 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
1060 rc_range_params_dword[7]);
1061 }
1062 }
1063 }
1064
intel_dsc_dsi_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1065 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
1066 const struct intel_crtc_state *crtc_state)
1067 {
1068 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1069 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1070 struct mipi_dsi_device *dsi;
1071 struct drm_dsc_picture_parameter_set pps;
1072 enum port port;
1073
1074 if (!crtc_state->dsc.compression_enable)
1075 return;
1076
1077 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
1078
1079 for_each_dsi_port(port, intel_dsi->ports) {
1080 dsi = intel_dsi->dsi_hosts[port]->device;
1081
1082 mipi_dsi_picture_parameter_set(dsi, &pps);
1083 mipi_dsi_compression_mode(dsi, true);
1084 }
1085 }
1086
intel_dsc_dp_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1087 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
1088 const struct intel_crtc_state *crtc_state)
1089 {
1090 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1091 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1092 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1093
1094 if (!crtc_state->dsc.compression_enable)
1095 return;
1096
1097 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1098 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1099
1100 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1101 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1102
1103 dig_port->write_infoframe(encoder, crtc_state,
1104 DP_SDP_PPS, &dp_dsc_pps_sdp,
1105 sizeof(dp_dsc_pps_sdp));
1106 }
1107
dss_ctl1_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)1108 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1109 {
1110 return is_pipe_dsc(crtc, cpu_transcoder) ?
1111 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
1112 }
1113
dss_ctl2_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)1114 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1115 {
1116 return is_pipe_dsc(crtc, cpu_transcoder) ?
1117 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
1118 }
1119
intel_uncompressed_joiner_enable(const struct intel_crtc_state * crtc_state)1120 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
1121 {
1122 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1123 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1124 u32 dss_ctl1_val = 0;
1125
1126 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) {
1127 if (intel_crtc_is_bigjoiner_slave(crtc_state))
1128 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
1129 else
1130 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
1131
1132 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1133 }
1134 }
1135
intel_dsc_enable(const struct intel_crtc_state * crtc_state)1136 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
1137 {
1138 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1140 u32 dss_ctl1_val = 0;
1141 u32 dss_ctl2_val = 0;
1142
1143 if (!crtc_state->dsc.compression_enable)
1144 return;
1145
1146 intel_dsc_pps_configure(crtc_state);
1147
1148 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1149 if (crtc_state->dsc.dsc_split) {
1150 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1151 dss_ctl1_val |= JOINER_ENABLE;
1152 }
1153 if (crtc_state->bigjoiner_pipes) {
1154 dss_ctl1_val |= BIG_JOINER_ENABLE;
1155 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
1156 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1157 }
1158 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1159 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
1160 }
1161
intel_dsc_disable(const struct intel_crtc_state * old_crtc_state)1162 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1163 {
1164 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1165 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1166
1167 /* Disable only if either of them is enabled */
1168 if (old_crtc_state->dsc.compression_enable ||
1169 old_crtc_state->bigjoiner_pipes) {
1170 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1171 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1172 }
1173 }
1174
intel_dsc_get_config(struct intel_crtc_state * crtc_state)1175 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1176 {
1177 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1179 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1180 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1181 enum pipe pipe = crtc->pipe;
1182 enum intel_display_power_domain power_domain;
1183 intel_wakeref_t wakeref;
1184 u32 dss_ctl1, dss_ctl2, val;
1185
1186 if (!intel_dsc_source_support(crtc_state))
1187 return;
1188
1189 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
1190
1191 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1192 if (!wakeref)
1193 return;
1194
1195 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
1196 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
1197
1198 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1199 if (!crtc_state->dsc.compression_enable)
1200 goto out;
1201
1202 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1203 (dss_ctl1 & JOINER_ENABLE);
1204
1205 /* FIXME: add more state readout as needed */
1206
1207 /* PPS1 */
1208 if (!is_pipe_dsc(crtc, cpu_transcoder))
1209 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1210 else
1211 val = intel_de_read(dev_priv,
1212 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1213 vdsc_cfg->bits_per_pixel = val;
1214 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1215 out:
1216 intel_display_power_put(dev_priv, power_domain, wakeref);
1217 }
1218