1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright (C) 2020 Google, Inc.
4 *
5 * Authors:
6 * Sean Paul <seanpaul@chromium.org>
7 */
8
9 #include <drm/display/drm_dp_helper.h>
10 #include <drm/display/drm_dp_mst_helper.h>
11 #include <drm/display/drm_hdcp_helper.h>
12 #include <drm/drm_print.h>
13
14 #include "intel_ddi.h"
15 #include "intel_de.h"
16 #include "intel_display_types.h"
17 #include "intel_dp.h"
18 #include "intel_dp_hdcp.h"
19 #include "intel_hdcp.h"
20 #include "intel_hdcp_regs.h"
21
transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)22 static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
23 {
24 u32 stream_enc_mask;
25
26 switch (cpu_transcoder) {
27 case TRANSCODER_A:
28 stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
29 break;
30 case TRANSCODER_B:
31 stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
32 break;
33 case TRANSCODER_C:
34 stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
35 break;
36 case TRANSCODER_D:
37 stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
38 break;
39 default:
40 stream_enc_mask = 0;
41 }
42
43 return stream_enc_mask;
44 }
45
intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp * hdcp,int timeout)46 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
47 {
48 long ret;
49
50 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
51 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
52 msecs_to_jiffies(timeout));
53
54 if (!ret)
55 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
56 }
57
58 static
intel_dp_hdcp_write_an_aksv(struct intel_digital_port * dig_port,u8 * an)59 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
60 u8 *an)
61 {
62 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
63 u8 aksv[DRM_HDCP_KSV_LEN] = {};
64 ssize_t dpcd_ret;
65
66 /* Output An first, that's easy */
67 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
68 an, DRM_HDCP_AN_LEN);
69 if (dpcd_ret != DRM_HDCP_AN_LEN) {
70 drm_dbg_kms(&i915->drm,
71 "Failed to write An over DP/AUX (%zd)\n",
72 dpcd_ret);
73 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
74 }
75
76 /*
77 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
78 * send an empty buffer of the correct length through the DP helpers. On
79 * the other side, in the transfer hook, we'll generate a flag based on
80 * the destination address which will tickle the hardware to output the
81 * Aksv on our behalf after the header is sent.
82 */
83 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
84 aksv, DRM_HDCP_KSV_LEN);
85 if (dpcd_ret != DRM_HDCP_KSV_LEN) {
86 drm_dbg_kms(&i915->drm,
87 "Failed to write Aksv over DP/AUX (%zd)\n",
88 dpcd_ret);
89 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
90 }
91 return 0;
92 }
93
intel_dp_hdcp_read_bksv(struct intel_digital_port * dig_port,u8 * bksv)94 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
95 u8 *bksv)
96 {
97 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
98 ssize_t ret;
99
100 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
101 DRM_HDCP_KSV_LEN);
102 if (ret != DRM_HDCP_KSV_LEN) {
103 drm_dbg_kms(&i915->drm,
104 "Read Bksv from DP/AUX failed (%zd)\n", ret);
105 return ret >= 0 ? -EIO : ret;
106 }
107 return 0;
108 }
109
intel_dp_hdcp_read_bstatus(struct intel_digital_port * dig_port,u8 * bstatus)110 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
111 u8 *bstatus)
112 {
113 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
114 ssize_t ret;
115
116 /*
117 * For some reason the HDMI and DP HDCP specs call this register
118 * definition by different names. In the HDMI spec, it's called BSTATUS,
119 * but in DP it's called BINFO.
120 */
121 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
122 bstatus, DRM_HDCP_BSTATUS_LEN);
123 if (ret != DRM_HDCP_BSTATUS_LEN) {
124 drm_dbg_kms(&i915->drm,
125 "Read bstatus from DP/AUX failed (%zd)\n", ret);
126 return ret >= 0 ? -EIO : ret;
127 }
128 return 0;
129 }
130
131 static
intel_dp_hdcp_read_bcaps(struct intel_digital_port * dig_port,u8 * bcaps)132 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
133 u8 *bcaps)
134 {
135 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
136 ssize_t ret;
137
138 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
139 bcaps, 1);
140 if (ret != 1) {
141 drm_dbg_kms(&i915->drm,
142 "Read bcaps from DP/AUX failed (%zd)\n", ret);
143 return ret >= 0 ? -EIO : ret;
144 }
145
146 return 0;
147 }
148
149 static
intel_dp_hdcp_repeater_present(struct intel_digital_port * dig_port,bool * repeater_present)150 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
151 bool *repeater_present)
152 {
153 ssize_t ret;
154 u8 bcaps;
155
156 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
157 if (ret)
158 return ret;
159
160 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
161 return 0;
162 }
163
164 static
intel_dp_hdcp_read_ri_prime(struct intel_digital_port * dig_port,u8 * ri_prime)165 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
166 u8 *ri_prime)
167 {
168 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
169 ssize_t ret;
170
171 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
172 ri_prime, DRM_HDCP_RI_LEN);
173 if (ret != DRM_HDCP_RI_LEN) {
174 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
175 ret);
176 return ret >= 0 ? -EIO : ret;
177 }
178 return 0;
179 }
180
181 static
intel_dp_hdcp_read_ksv_ready(struct intel_digital_port * dig_port,bool * ksv_ready)182 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
183 bool *ksv_ready)
184 {
185 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
186 ssize_t ret;
187 u8 bstatus;
188
189 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
190 &bstatus, 1);
191 if (ret != 1) {
192 drm_dbg_kms(&i915->drm,
193 "Read bstatus from DP/AUX failed (%zd)\n", ret);
194 return ret >= 0 ? -EIO : ret;
195 }
196 *ksv_ready = bstatus & DP_BSTATUS_READY;
197 return 0;
198 }
199
200 static
intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port * dig_port,int num_downstream,u8 * ksv_fifo)201 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
202 int num_downstream, u8 *ksv_fifo)
203 {
204 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
205 ssize_t ret;
206 int i;
207
208 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
209 for (i = 0; i < num_downstream; i += 3) {
210 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
211 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
212 DP_AUX_HDCP_KSV_FIFO,
213 ksv_fifo + i * DRM_HDCP_KSV_LEN,
214 len);
215 if (ret != len) {
216 drm_dbg_kms(&i915->drm,
217 "Read ksv[%d] from DP/AUX failed (%zd)\n",
218 i, ret);
219 return ret >= 0 ? -EIO : ret;
220 }
221 }
222 return 0;
223 }
224
225 static
intel_dp_hdcp_read_v_prime_part(struct intel_digital_port * dig_port,int i,u32 * part)226 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
227 int i, u32 *part)
228 {
229 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
230 ssize_t ret;
231
232 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
233 return -EINVAL;
234
235 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
236 DP_AUX_HDCP_V_PRIME(i), part,
237 DRM_HDCP_V_PRIME_PART_LEN);
238 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
239 drm_dbg_kms(&i915->drm,
240 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
241 return ret >= 0 ? -EIO : ret;
242 }
243 return 0;
244 }
245
246 static
intel_dp_hdcp_toggle_signalling(struct intel_digital_port * dig_port,enum transcoder cpu_transcoder,bool enable)247 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
248 enum transcoder cpu_transcoder,
249 bool enable)
250 {
251 /* Not used for single stream DisplayPort setups */
252 return 0;
253 }
254
255 static
intel_dp_hdcp_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)256 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
257 struct intel_connector *connector)
258 {
259 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
260 ssize_t ret;
261 u8 bstatus;
262
263 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
264 &bstatus, 1);
265 if (ret != 1) {
266 drm_dbg_kms(&i915->drm,
267 "Read bstatus from DP/AUX failed (%zd)\n", ret);
268 return false;
269 }
270
271 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
272 }
273
274 static
intel_dp_hdcp_capable(struct intel_digital_port * dig_port,bool * hdcp_capable)275 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
276 bool *hdcp_capable)
277 {
278 ssize_t ret;
279 u8 bcaps;
280
281 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
282 if (ret)
283 return ret;
284
285 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
286 return 0;
287 }
288
289 struct hdcp2_dp_errata_stream_type {
290 u8 msg_id;
291 u8 stream_type;
292 } __packed;
293
294 struct hdcp2_dp_msg_data {
295 u8 msg_id;
296 u32 offset;
297 bool msg_detectable;
298 u32 timeout;
299 u32 timeout2; /* Added for non_paired situation */
300 /* Timeout to read entire msg */
301 u32 msg_read_timeout;
302 };
303
304 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
305 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
306 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
307 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
308 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
309 false, 0, 0, 0 },
310 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
311 false, 0, 0, 0 },
312 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
313 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
314 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
315 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
316 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
317 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
318 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
319 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
320 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
321 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
322 0, 0, 0 },
323 { HDCP_2_2_REP_SEND_RECVID_LIST,
324 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
325 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
326 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
327 0, 0, 0 },
328 { HDCP_2_2_REP_STREAM_MANAGE,
329 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
330 0, 0, 0},
331 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
332 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
333 /* local define to shovel this through the write_2_2 interface */
334 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
335 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
336 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
337 0, 0 },
338 };
339
340 static int
intel_dp_hdcp2_read_rx_status(struct intel_digital_port * dig_port,u8 * rx_status)341 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
342 u8 *rx_status)
343 {
344 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
345 ssize_t ret;
346
347 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
348 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
349 HDCP_2_2_DP_RXSTATUS_LEN);
350 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
351 drm_dbg_kms(&i915->drm,
352 "Read bstatus from DP/AUX failed (%zd)\n", ret);
353 return ret >= 0 ? -EIO : ret;
354 }
355
356 return 0;
357 }
358
359 static
hdcp2_detect_msg_availability(struct intel_digital_port * dig_port,u8 msg_id,bool * msg_ready)360 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
361 u8 msg_id, bool *msg_ready)
362 {
363 u8 rx_status;
364 int ret;
365
366 *msg_ready = false;
367 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
368 if (ret < 0)
369 return ret;
370
371 switch (msg_id) {
372 case HDCP_2_2_AKE_SEND_HPRIME:
373 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
374 *msg_ready = true;
375 break;
376 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
377 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
378 *msg_ready = true;
379 break;
380 case HDCP_2_2_REP_SEND_RECVID_LIST:
381 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
382 *msg_ready = true;
383 break;
384 default:
385 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
386 return -EINVAL;
387 }
388
389 return 0;
390 }
391
392 static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_digital_port * dig_port,const struct hdcp2_dp_msg_data * hdcp2_msg_data)393 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
394 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
395 {
396 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
397 struct intel_dp *dp = &dig_port->dp;
398 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
399 u8 msg_id = hdcp2_msg_data->msg_id;
400 int ret, timeout;
401 bool msg_ready = false;
402
403 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
404 timeout = hdcp2_msg_data->timeout2;
405 else
406 timeout = hdcp2_msg_data->timeout;
407
408 /*
409 * There is no way to detect the CERT, LPRIME and STREAM_READY
410 * availability. So Wait for timeout and read the msg.
411 */
412 if (!hdcp2_msg_data->msg_detectable) {
413 mdelay(timeout);
414 ret = 0;
415 } else {
416 /*
417 * As we want to check the msg availability at timeout, Ignoring
418 * the timeout at wait for CP_IRQ.
419 */
420 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
421 ret = hdcp2_detect_msg_availability(dig_port,
422 msg_id, &msg_ready);
423 if (!msg_ready)
424 ret = -ETIMEDOUT;
425 }
426
427 if (ret)
428 drm_dbg_kms(&i915->drm,
429 "msg_id %d, ret %d, timeout(mSec): %d\n",
430 hdcp2_msg_data->msg_id, ret, timeout);
431
432 return ret;
433 }
434
get_hdcp2_dp_msg_data(u8 msg_id)435 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
436 {
437 int i;
438
439 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
440 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
441 return &hdcp2_dp_msg_data[i];
442
443 return NULL;
444 }
445
446 static
intel_dp_hdcp2_write_msg(struct intel_digital_port * dig_port,void * buf,size_t size)447 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
448 void *buf, size_t size)
449 {
450 unsigned int offset;
451 u8 *byte = buf;
452 ssize_t ret, bytes_to_write, len;
453 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
454
455 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
456 if (!hdcp2_msg_data)
457 return -EINVAL;
458
459 offset = hdcp2_msg_data->offset;
460
461 /* No msg_id in DP HDCP2.2 msgs */
462 bytes_to_write = size - 1;
463 byte++;
464
465 while (bytes_to_write) {
466 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
467 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
468
469 ret = drm_dp_dpcd_write(&dig_port->dp.aux,
470 offset, (void *)byte, len);
471 if (ret < 0)
472 return ret;
473
474 bytes_to_write -= ret;
475 byte += ret;
476 offset += ret;
477 }
478
479 return size;
480 }
481
482 static
get_receiver_id_list_rx_info(struct intel_digital_port * dig_port,u32 * dev_cnt,u8 * byte)483 ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *dev_cnt, u8 *byte)
484 {
485 ssize_t ret;
486 u8 *rx_info = byte;
487
488 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
489 DP_HDCP_2_2_REG_RXINFO_OFFSET,
490 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
491 if (ret != HDCP_2_2_RXINFO_LEN)
492 return ret >= 0 ? -EIO : ret;
493
494 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
495 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
496
497 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
498 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
499
500 return ret;
501 }
502
503 static
intel_dp_hdcp2_read_msg(struct intel_digital_port * dig_port,u8 msg_id,void * buf,size_t size)504 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
505 u8 msg_id, void *buf, size_t size)
506 {
507 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
508 struct intel_dp *dp = &dig_port->dp;
509 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
510 unsigned int offset;
511 u8 *byte = buf;
512 ssize_t ret, bytes_to_recv, len;
513 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
514 ktime_t msg_end = ktime_set(0, 0);
515 bool msg_expired;
516 u32 dev_cnt;
517
518 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
519 if (!hdcp2_msg_data)
520 return -EINVAL;
521 offset = hdcp2_msg_data->offset;
522
523 ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
524 if (ret < 0)
525 return ret;
526
527 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
528
529 /* DP adaptation msgs has no msg_id */
530 byte++;
531
532 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
533 ret = get_receiver_id_list_rx_info(dig_port, &dev_cnt, byte);
534 if (ret < 0)
535 return ret;
536
537 byte += ret;
538 size = sizeof(struct hdcp2_rep_send_receiverid_list) -
539 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN +
540 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
541 offset += HDCP_2_2_RXINFO_LEN;
542 }
543
544 bytes_to_recv = size - 1;
545
546 while (bytes_to_recv) {
547 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
548 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
549
550 /* Entire msg read timeout since initiate of msg read */
551 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
552 msg_end = ktime_add_ms(ktime_get_raw(),
553 hdcp2_msg_data->msg_read_timeout);
554
555 ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
556 (void *)byte, len);
557 if (ret < 0) {
558 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
559 msg_id, ret);
560 return ret;
561 }
562
563 bytes_to_recv -= ret;
564 byte += ret;
565 offset += ret;
566 }
567
568 if (hdcp2_msg_data->msg_read_timeout > 0) {
569 msg_expired = ktime_after(ktime_get_raw(), msg_end);
570 if (msg_expired) {
571 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
572 msg_id, hdcp2_msg_data->msg_read_timeout);
573 return -ETIMEDOUT;
574 }
575 }
576
577 byte = buf;
578 *byte = msg_id;
579
580 return size;
581 }
582
583 static
intel_dp_hdcp2_config_stream_type(struct intel_digital_port * dig_port,bool is_repeater,u8 content_type)584 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
585 bool is_repeater, u8 content_type)
586 {
587 int ret;
588 struct hdcp2_dp_errata_stream_type stream_type_msg;
589
590 if (is_repeater)
591 return 0;
592
593 /*
594 * Errata for DP: As Stream type is used for encryption, Receiver
595 * should be communicated with stream type for the decryption of the
596 * content.
597 * Repeater will be communicated with stream type as a part of it's
598 * auth later in time.
599 */
600 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
601 stream_type_msg.stream_type = content_type;
602
603 ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
604 sizeof(stream_type_msg));
605
606 return ret < 0 ? ret : 0;
607
608 }
609
610 static
intel_dp_hdcp2_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)611 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
612 struct intel_connector *connector)
613 {
614 u8 rx_status;
615 int ret;
616
617 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
618 if (ret)
619 return ret;
620
621 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
622 ret = HDCP_REAUTH_REQUEST;
623 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
624 ret = HDCP_LINK_INTEGRITY_FAILURE;
625 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
626 ret = HDCP_TOPOLOGY_CHANGE;
627
628 return ret;
629 }
630
631 static
intel_dp_hdcp2_capable(struct intel_digital_port * dig_port,bool * capable)632 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
633 bool *capable)
634 {
635 u8 rx_caps[3];
636 int ret;
637
638 *capable = false;
639 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
640 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
641 rx_caps, HDCP_2_2_RXCAPS_LEN);
642 if (ret != HDCP_2_2_RXCAPS_LEN)
643 return ret >= 0 ? -EIO : ret;
644
645 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
646 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
647 *capable = true;
648
649 return 0;
650 }
651
652 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
653 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
654 .read_bksv = intel_dp_hdcp_read_bksv,
655 .read_bstatus = intel_dp_hdcp_read_bstatus,
656 .repeater_present = intel_dp_hdcp_repeater_present,
657 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
658 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
659 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
660 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
661 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
662 .check_link = intel_dp_hdcp_check_link,
663 .hdcp_capable = intel_dp_hdcp_capable,
664 .write_2_2_msg = intel_dp_hdcp2_write_msg,
665 .read_2_2_msg = intel_dp_hdcp2_read_msg,
666 .config_stream_type = intel_dp_hdcp2_config_stream_type,
667 .check_2_2_link = intel_dp_hdcp2_check_link,
668 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
669 .protocol = HDCP_PROTOCOL_DP,
670 };
671
672 static int
intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector * connector,bool enable)673 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
674 bool enable)
675 {
676 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
677 struct drm_i915_private *i915 = to_i915(connector->base.dev);
678 struct intel_hdcp *hdcp = &connector->hdcp;
679 int ret;
680
681 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
682 hdcp->stream_transcoder, enable,
683 TRANS_DDI_HDCP_SELECT);
684 if (ret)
685 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
686 enable ? "Enable" : "Disable", ret);
687 return ret;
688 }
689
690 static int
intel_dp_mst_hdcp_stream_encryption(struct intel_connector * connector,bool enable)691 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
692 bool enable)
693 {
694 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
695 struct drm_i915_private *i915 = to_i915(connector->base.dev);
696 struct intel_hdcp *hdcp = &connector->hdcp;
697 enum port port = dig_port->base.port;
698 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
699 u32 stream_enc_status;
700 int ret;
701
702 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
703 if (ret)
704 return ret;
705
706 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder);
707 if (!stream_enc_status)
708 return -EINVAL;
709
710 /* Wait for encryption confirmation */
711 if (intel_de_wait_for_register(i915,
712 HDCP_STATUS(i915, cpu_transcoder, port),
713 stream_enc_status,
714 enable ? stream_enc_status : 0,
715 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
716 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
717 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
718 return -ETIMEDOUT;
719 }
720
721 return 0;
722 }
723
724 static int
intel_dp_mst_hdcp2_stream_encryption(struct intel_connector * connector,bool enable)725 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
726 bool enable)
727 {
728 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
729 struct drm_i915_private *i915 = to_i915(connector->base.dev);
730 struct hdcp_port_data *data = &dig_port->hdcp_port_data;
731 struct intel_hdcp *hdcp = &connector->hdcp;
732 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
733 enum pipe pipe = (enum pipe)cpu_transcoder;
734 enum port port = dig_port->base.port;
735 int ret;
736
737 drm_WARN_ON(&i915->drm, enable &&
738 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
739 & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
740
741 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
742 if (ret)
743 return ret;
744
745 /* Wait for encryption confirmation */
746 if (intel_de_wait_for_register(i915,
747 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
748 STREAM_ENCRYPTION_STATUS,
749 enable ? STREAM_ENCRYPTION_STATUS : 0,
750 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
751 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
752 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
753 return -ETIMEDOUT;
754 }
755
756 return 0;
757 }
758
759 static
intel_dp_mst_hdcp2_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)760 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
761 struct intel_connector *connector)
762 {
763 struct intel_hdcp *hdcp = &connector->hdcp;
764 int ret;
765
766 /*
767 * We do need to do the Link Check only for the connector involved with
768 * HDCP port authentication and encryption.
769 * We can re-use the hdcp->is_repeater flag to know that the connector
770 * involved with HDCP port authentication and encryption.
771 */
772 if (hdcp->is_repeater) {
773 ret = intel_dp_hdcp2_check_link(dig_port, connector);
774 if (ret)
775 return ret;
776 }
777
778 return 0;
779 }
780
781 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
782 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
783 .read_bksv = intel_dp_hdcp_read_bksv,
784 .read_bstatus = intel_dp_hdcp_read_bstatus,
785 .repeater_present = intel_dp_hdcp_repeater_present,
786 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
787 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
788 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
789 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
790 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
791 .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
792 .check_link = intel_dp_hdcp_check_link,
793 .hdcp_capable = intel_dp_hdcp_capable,
794 .write_2_2_msg = intel_dp_hdcp2_write_msg,
795 .read_2_2_msg = intel_dp_hdcp2_read_msg,
796 .config_stream_type = intel_dp_hdcp2_config_stream_type,
797 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
798 .check_2_2_link = intel_dp_mst_hdcp2_check_link,
799 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
800 .protocol = HDCP_PROTOCOL_DP,
801 };
802
intel_dp_hdcp_init(struct intel_digital_port * dig_port,struct intel_connector * intel_connector)803 int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
804 struct intel_connector *intel_connector)
805 {
806 struct drm_device *dev = intel_connector->base.dev;
807 struct drm_i915_private *dev_priv = to_i915(dev);
808 struct intel_encoder *intel_encoder = &dig_port->base;
809 enum port port = intel_encoder->port;
810 struct intel_dp *intel_dp = &dig_port->dp;
811
812 if (!is_hdcp_supported(dev_priv, port))
813 return 0;
814
815 if (intel_connector->mst_port)
816 return intel_hdcp_init(intel_connector, dig_port,
817 &intel_dp_mst_hdcp_shim);
818 else if (!intel_dp_is_edp(intel_dp))
819 return intel_hdcp_init(intel_connector, dig_port,
820 &intel_dp_hdcp_shim);
821
822 return 0;
823 }
824