1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27 
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/string_helpers.h>
33 #include <linux/timekeeping.h>
34 #include <linux/types.h>
35 
36 #include <asm/byteorder.h>
37 
38 #include <drm/display/drm_dp_helper.h>
39 #include <drm/display/drm_dsc_helper.h>
40 #include <drm/display/drm_hdmi_helper.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_probe_helper.h>
45 
46 #include "g4x_dp.h"
47 #include "i915_debugfs.h"
48 #include "i915_drv.h"
49 #include "intel_atomic.h"
50 #include "intel_audio.h"
51 #include "intel_backlight.h"
52 #include "intel_combo_phy_regs.h"
53 #include "intel_connector.h"
54 #include "intel_crtc.h"
55 #include "intel_ddi.h"
56 #include "intel_de.h"
57 #include "intel_display_types.h"
58 #include "intel_dp.h"
59 #include "intel_dp_aux.h"
60 #include "intel_dp_hdcp.h"
61 #include "intel_dp_link_training.h"
62 #include "intel_dp_mst.h"
63 #include "intel_dpio_phy.h"
64 #include "intel_dpll.h"
65 #include "intel_fifo_underrun.h"
66 #include "intel_hdcp.h"
67 #include "intel_hdmi.h"
68 #include "intel_hotplug.h"
69 #include "intel_lspcon.h"
70 #include "intel_lvds.h"
71 #include "intel_panel.h"
72 #include "intel_pch_display.h"
73 #include "intel_pps.h"
74 #include "intel_psr.h"
75 #include "intel_tc.h"
76 #include "intel_vdsc.h"
77 #include "intel_vrr.h"
78 
79 /* DP DSC throughput values used for slice count calculations KPixels/s */
80 #define DP_DSC_PEAK_PIXEL_RATE			2720000
81 #define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
82 #define DP_DSC_MAX_ENC_THROUGHPUT_1		400000
83 
84 /* DP DSC FEC Overhead factor = 1/(0.972261) */
85 #define DP_DSC_FEC_OVERHEAD_FACTOR		972261
86 
87 /* Compliance test status bits  */
88 #define INTEL_DP_RESOLUTION_SHIFT_MASK	0
89 #define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
90 #define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
91 #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
92 
93 
94 /* Constants for DP DSC configurations */
95 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
96 
97 /* With Single pipe configuration, HW is capable of supporting maximum
98  * of 4 slices per line.
99  */
100 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
101 
102 /**
103  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104  * @intel_dp: DP struct
105  *
106  * If a CPU or PCH DP output is attached to an eDP panel, this function
107  * will return true, and false otherwise.
108  *
109  * This function is not safe to use prior to encoder type being set.
110  */
intel_dp_is_edp(struct intel_dp * intel_dp)111 bool intel_dp_is_edp(struct intel_dp *intel_dp)
112 {
113 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
114 
115 	return dig_port->base.type == INTEL_OUTPUT_EDP;
116 }
117 
118 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
119 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
120 
121 /* Is link rate UHBR and thus 128b/132b? */
intel_dp_is_uhbr(const struct intel_crtc_state * crtc_state)122 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
123 {
124 	return crtc_state->port_clock >= 1000000;
125 }
126 
intel_dp_set_default_sink_rates(struct intel_dp * intel_dp)127 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
128 {
129 	intel_dp->sink_rates[0] = 162000;
130 	intel_dp->num_sink_rates = 1;
131 }
132 
133 /* update sink rates from dpcd */
intel_dp_set_dpcd_sink_rates(struct intel_dp * intel_dp)134 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
135 {
136 	static const int dp_rates[] = {
137 		162000, 270000, 540000, 810000
138 	};
139 	int i, max_rate;
140 	int max_lttpr_rate;
141 
142 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
143 		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
144 		static const int quirk_rates[] = { 162000, 270000, 324000 };
145 
146 		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
147 		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
148 
149 		return;
150 	}
151 
152 	/*
153 	 * Sink rates for 8b/10b.
154 	 */
155 	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
156 	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
157 	if (max_lttpr_rate)
158 		max_rate = min(max_rate, max_lttpr_rate);
159 
160 	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
161 		if (dp_rates[i] > max_rate)
162 			break;
163 		intel_dp->sink_rates[i] = dp_rates[i];
164 	}
165 
166 	/*
167 	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
168 	 * rates and 10 Gbps.
169 	 */
170 	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
171 		u8 uhbr_rates = 0;
172 
173 		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
174 
175 		drm_dp_dpcd_readb(&intel_dp->aux,
176 				  DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
177 
178 		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
179 			/* We have a repeater */
180 			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
181 			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
182 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
183 			    DP_PHY_REPEATER_128B132B_SUPPORTED) {
184 				/* Repeater supports 128b/132b, valid UHBR rates */
185 				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
186 									  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
187 			} else {
188 				/* Does not support 128b/132b */
189 				uhbr_rates = 0;
190 			}
191 		}
192 
193 		if (uhbr_rates & DP_UHBR10)
194 			intel_dp->sink_rates[i++] = 1000000;
195 		if (uhbr_rates & DP_UHBR13_5)
196 			intel_dp->sink_rates[i++] = 1350000;
197 		if (uhbr_rates & DP_UHBR20)
198 			intel_dp->sink_rates[i++] = 2000000;
199 	}
200 
201 	intel_dp->num_sink_rates = i;
202 }
203 
intel_dp_set_sink_rates(struct intel_dp * intel_dp)204 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
205 {
206 	struct intel_connector *connector = intel_dp->attached_connector;
207 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
208 	struct intel_encoder *encoder = &intel_dig_port->base;
209 
210 	intel_dp_set_dpcd_sink_rates(intel_dp);
211 
212 	if (intel_dp->num_sink_rates)
213 		return;
214 
215 	drm_err(&dp_to_i915(intel_dp)->drm,
216 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
217 		connector->base.base.id, connector->base.name,
218 		encoder->base.base.id, encoder->base.name);
219 
220 	intel_dp_set_default_sink_rates(intel_dp);
221 }
222 
intel_dp_set_default_max_sink_lane_count(struct intel_dp * intel_dp)223 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
224 {
225 	intel_dp->max_sink_lane_count = 1;
226 }
227 
intel_dp_set_max_sink_lane_count(struct intel_dp * intel_dp)228 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
229 {
230 	struct intel_connector *connector = intel_dp->attached_connector;
231 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
232 	struct intel_encoder *encoder = &intel_dig_port->base;
233 
234 	intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
235 
236 	switch (intel_dp->max_sink_lane_count) {
237 	case 1:
238 	case 2:
239 	case 4:
240 		return;
241 	}
242 
243 	drm_err(&dp_to_i915(intel_dp)->drm,
244 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
245 		connector->base.base.id, connector->base.name,
246 		encoder->base.base.id, encoder->base.name,
247 		intel_dp->max_sink_lane_count);
248 
249 	intel_dp_set_default_max_sink_lane_count(intel_dp);
250 }
251 
252 /* Get length of rates array potentially limited by max_rate. */
intel_dp_rate_limit_len(const int * rates,int len,int max_rate)253 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
254 {
255 	int i;
256 
257 	/* Limit results by potentially reduced max rate */
258 	for (i = 0; i < len; i++) {
259 		if (rates[len - i - 1] <= max_rate)
260 			return len - i;
261 	}
262 
263 	return 0;
264 }
265 
266 /* Get length of common rates array potentially limited by max_rate. */
intel_dp_common_len_rate_limit(const struct intel_dp * intel_dp,int max_rate)267 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
268 					  int max_rate)
269 {
270 	return intel_dp_rate_limit_len(intel_dp->common_rates,
271 				       intel_dp->num_common_rates, max_rate);
272 }
273 
intel_dp_common_rate(struct intel_dp * intel_dp,int index)274 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
275 {
276 	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
277 			index < 0 || index >= intel_dp->num_common_rates))
278 		return 162000;
279 
280 	return intel_dp->common_rates[index];
281 }
282 
283 /* Theoretical max between source and sink */
intel_dp_max_common_rate(struct intel_dp * intel_dp)284 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
285 {
286 	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
287 }
288 
intel_dp_max_source_lane_count(struct intel_digital_port * dig_port)289 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
290 {
291 	int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
292 	int max_lanes = dig_port->max_lanes;
293 
294 	if (vbt_max_lanes)
295 		max_lanes = min(max_lanes, vbt_max_lanes);
296 
297 	return max_lanes;
298 }
299 
300 /* Theoretical max between source and sink */
intel_dp_max_common_lane_count(struct intel_dp * intel_dp)301 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
302 {
303 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
304 	int source_max = intel_dp_max_source_lane_count(dig_port);
305 	int sink_max = intel_dp->max_sink_lane_count;
306 	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
307 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
308 
309 	if (lttpr_max)
310 		sink_max = min(sink_max, lttpr_max);
311 
312 	return min3(source_max, sink_max, fia_max);
313 }
314 
intel_dp_max_lane_count(struct intel_dp * intel_dp)315 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
316 {
317 	switch (intel_dp->max_link_lane_count) {
318 	case 1:
319 	case 2:
320 	case 4:
321 		return intel_dp->max_link_lane_count;
322 	default:
323 		MISSING_CASE(intel_dp->max_link_lane_count);
324 		return 1;
325 	}
326 }
327 
328 /*
329  * The required data bandwidth for a mode with given pixel clock and bpp. This
330  * is the required net bandwidth independent of the data bandwidth efficiency.
331  */
332 int
intel_dp_link_required(int pixel_clock,int bpp)333 intel_dp_link_required(int pixel_clock, int bpp)
334 {
335 	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
336 	return DIV_ROUND_UP(pixel_clock * bpp, 8);
337 }
338 
339 /*
340  * Given a link rate and lanes, get the data bandwidth.
341  *
342  * Data bandwidth is the actual payload rate, which depends on the data
343  * bandwidth efficiency and the link rate.
344  *
345  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
346  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
347  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
348  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
349  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
350  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
351  *
352  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
353  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
354  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
355  * does not match the symbol clock, the port clock (not even if you think in
356  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
357  * rate in units of 10000 bps.
358  */
359 int
intel_dp_max_data_rate(int max_link_rate,int max_lanes)360 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
361 {
362 	if (max_link_rate >= 1000000) {
363 		/*
364 		 * UHBR rates always use 128b/132b channel encoding, and have
365 		 * 97.71% data bandwidth efficiency. Consider max_link_rate the
366 		 * link bit rate in units of 10000 bps.
367 		 */
368 		int max_link_rate_kbps = max_link_rate * 10;
369 
370 		max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
371 		max_link_rate = max_link_rate_kbps / 8;
372 	}
373 
374 	/*
375 	 * Lower than UHBR rates always use 8b/10b channel encoding, and have
376 	 * 80% data bandwidth efficiency for SST non-FEC. However, this turns
377 	 * out to be a nop by coincidence, and can be skipped:
378 	 *
379 	 *	int max_link_rate_kbps = max_link_rate * 10;
380 	 *	max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
381 	 *	max_link_rate = max_link_rate_kbps / 8;
382 	 */
383 
384 	return max_link_rate * max_lanes;
385 }
386 
intel_dp_can_bigjoiner(struct intel_dp * intel_dp)387 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
388 {
389 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
390 	struct intel_encoder *encoder = &intel_dig_port->base;
391 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
392 
393 	return DISPLAY_VER(dev_priv) >= 12 ||
394 		(DISPLAY_VER(dev_priv) == 11 &&
395 		 encoder->port != PORT_A);
396 }
397 
dg2_max_source_rate(struct intel_dp * intel_dp)398 static int dg2_max_source_rate(struct intel_dp *intel_dp)
399 {
400 	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
401 }
402 
icl_max_source_rate(struct intel_dp * intel_dp)403 static int icl_max_source_rate(struct intel_dp *intel_dp)
404 {
405 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
406 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
407 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
408 
409 	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
410 		return 540000;
411 
412 	return 810000;
413 }
414 
ehl_max_source_rate(struct intel_dp * intel_dp)415 static int ehl_max_source_rate(struct intel_dp *intel_dp)
416 {
417 	if (intel_dp_is_edp(intel_dp))
418 		return 540000;
419 
420 	return 810000;
421 }
422 
vbt_max_link_rate(struct intel_dp * intel_dp)423 static int vbt_max_link_rate(struct intel_dp *intel_dp)
424 {
425 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
426 	int max_rate;
427 
428 	max_rate = intel_bios_dp_max_link_rate(encoder);
429 
430 	if (intel_dp_is_edp(intel_dp)) {
431 		struct intel_connector *connector = intel_dp->attached_connector;
432 		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
433 
434 		if (max_rate && edp_max_rate)
435 			max_rate = min(max_rate, edp_max_rate);
436 		else if (edp_max_rate)
437 			max_rate = edp_max_rate;
438 	}
439 
440 	return max_rate;
441 }
442 
443 static void
intel_dp_set_source_rates(struct intel_dp * intel_dp)444 intel_dp_set_source_rates(struct intel_dp *intel_dp)
445 {
446 	/* The values must be in increasing order */
447 	static const int icl_rates[] = {
448 		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
449 		1000000, 1350000,
450 	};
451 	static const int bxt_rates[] = {
452 		162000, 216000, 243000, 270000, 324000, 432000, 540000
453 	};
454 	static const int skl_rates[] = {
455 		162000, 216000, 270000, 324000, 432000, 540000
456 	};
457 	static const int hsw_rates[] = {
458 		162000, 270000, 540000
459 	};
460 	static const int g4x_rates[] = {
461 		162000, 270000
462 	};
463 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
464 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
465 	const int *source_rates;
466 	int size, max_rate = 0, vbt_max_rate;
467 
468 	/* This should only be done once */
469 	drm_WARN_ON(&dev_priv->drm,
470 		    intel_dp->source_rates || intel_dp->num_source_rates);
471 
472 	if (DISPLAY_VER(dev_priv) >= 11) {
473 		source_rates = icl_rates;
474 		size = ARRAY_SIZE(icl_rates);
475 		if (IS_DG2(dev_priv))
476 			max_rate = dg2_max_source_rate(intel_dp);
477 		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
478 			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
479 			max_rate = 810000;
480 		else if (IS_JSL_EHL(dev_priv))
481 			max_rate = ehl_max_source_rate(intel_dp);
482 		else
483 			max_rate = icl_max_source_rate(intel_dp);
484 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
485 		source_rates = bxt_rates;
486 		size = ARRAY_SIZE(bxt_rates);
487 	} else if (DISPLAY_VER(dev_priv) == 9) {
488 		source_rates = skl_rates;
489 		size = ARRAY_SIZE(skl_rates);
490 	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
491 		   IS_BROADWELL(dev_priv)) {
492 		source_rates = hsw_rates;
493 		size = ARRAY_SIZE(hsw_rates);
494 	} else {
495 		source_rates = g4x_rates;
496 		size = ARRAY_SIZE(g4x_rates);
497 	}
498 
499 	vbt_max_rate = vbt_max_link_rate(intel_dp);
500 	if (max_rate && vbt_max_rate)
501 		max_rate = min(max_rate, vbt_max_rate);
502 	else if (vbt_max_rate)
503 		max_rate = vbt_max_rate;
504 
505 	if (max_rate)
506 		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
507 
508 	intel_dp->source_rates = source_rates;
509 	intel_dp->num_source_rates = size;
510 }
511 
intersect_rates(const int * source_rates,int source_len,const int * sink_rates,int sink_len,int * common_rates)512 static int intersect_rates(const int *source_rates, int source_len,
513 			   const int *sink_rates, int sink_len,
514 			   int *common_rates)
515 {
516 	int i = 0, j = 0, k = 0;
517 
518 	while (i < source_len && j < sink_len) {
519 		if (source_rates[i] == sink_rates[j]) {
520 			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
521 				return k;
522 			common_rates[k] = source_rates[i];
523 			++k;
524 			++i;
525 			++j;
526 		} else if (source_rates[i] < sink_rates[j]) {
527 			++i;
528 		} else {
529 			++j;
530 		}
531 	}
532 	return k;
533 }
534 
535 /* return index of rate in rates array, or -1 if not found */
intel_dp_rate_index(const int * rates,int len,int rate)536 static int intel_dp_rate_index(const int *rates, int len, int rate)
537 {
538 	int i;
539 
540 	for (i = 0; i < len; i++)
541 		if (rate == rates[i])
542 			return i;
543 
544 	return -1;
545 }
546 
intel_dp_set_common_rates(struct intel_dp * intel_dp)547 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
548 {
549 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
550 
551 	drm_WARN_ON(&i915->drm,
552 		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
553 
554 	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
555 						     intel_dp->num_source_rates,
556 						     intel_dp->sink_rates,
557 						     intel_dp->num_sink_rates,
558 						     intel_dp->common_rates);
559 
560 	/* Paranoia, there should always be something in common. */
561 	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
562 		intel_dp->common_rates[0] = 162000;
563 		intel_dp->num_common_rates = 1;
564 	}
565 }
566 
intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count)567 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
568 				       u8 lane_count)
569 {
570 	/*
571 	 * FIXME: we need to synchronize the current link parameters with
572 	 * hardware readout. Currently fast link training doesn't work on
573 	 * boot-up.
574 	 */
575 	if (link_rate == 0 ||
576 	    link_rate > intel_dp->max_link_rate)
577 		return false;
578 
579 	if (lane_count == 0 ||
580 	    lane_count > intel_dp_max_lane_count(intel_dp))
581 		return false;
582 
583 	return true;
584 }
585 
intel_dp_can_link_train_fallback_for_edp(struct intel_dp * intel_dp,int link_rate,u8 lane_count)586 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
587 						     int link_rate,
588 						     u8 lane_count)
589 {
590 	/* FIXME figure out what we actually want here */
591 	const struct drm_display_mode *fixed_mode =
592 		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
593 	int mode_rate, max_rate;
594 
595 	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
596 	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
597 	if (mode_rate > max_rate)
598 		return false;
599 
600 	return true;
601 }
602 
intel_dp_get_link_train_fallback_values(struct intel_dp * intel_dp,int link_rate,u8 lane_count)603 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
604 					    int link_rate, u8 lane_count)
605 {
606 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
607 	int index;
608 
609 	/*
610 	 * TODO: Enable fallback on MST links once MST link compute can handle
611 	 * the fallback params.
612 	 */
613 	if (intel_dp->is_mst) {
614 		drm_err(&i915->drm, "Link Training Unsuccessful\n");
615 		return -1;
616 	}
617 
618 	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
619 		drm_dbg_kms(&i915->drm,
620 			    "Retrying Link training for eDP with max parameters\n");
621 		intel_dp->use_max_params = true;
622 		return 0;
623 	}
624 
625 	index = intel_dp_rate_index(intel_dp->common_rates,
626 				    intel_dp->num_common_rates,
627 				    link_rate);
628 	if (index > 0) {
629 		if (intel_dp_is_edp(intel_dp) &&
630 		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
631 							      intel_dp_common_rate(intel_dp, index - 1),
632 							      lane_count)) {
633 			drm_dbg_kms(&i915->drm,
634 				    "Retrying Link training for eDP with same parameters\n");
635 			return 0;
636 		}
637 		intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
638 		intel_dp->max_link_lane_count = lane_count;
639 	} else if (lane_count > 1) {
640 		if (intel_dp_is_edp(intel_dp) &&
641 		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
642 							      intel_dp_max_common_rate(intel_dp),
643 							      lane_count >> 1)) {
644 			drm_dbg_kms(&i915->drm,
645 				    "Retrying Link training for eDP with same parameters\n");
646 			return 0;
647 		}
648 		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
649 		intel_dp->max_link_lane_count = lane_count >> 1;
650 	} else {
651 		drm_err(&i915->drm, "Link Training Unsuccessful\n");
652 		return -1;
653 	}
654 
655 	return 0;
656 }
657 
intel_dp_mode_to_fec_clock(u32 mode_clock)658 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
659 {
660 	return div_u64(mul_u32_u32(mode_clock, 1000000U),
661 		       DP_DSC_FEC_OVERHEAD_FACTOR);
662 }
663 
664 static int
small_joiner_ram_size_bits(struct drm_i915_private * i915)665 small_joiner_ram_size_bits(struct drm_i915_private *i915)
666 {
667 	if (DISPLAY_VER(i915) >= 13)
668 		return 17280 * 8;
669 	else if (DISPLAY_VER(i915) >= 11)
670 		return 7680 * 8;
671 	else
672 		return 6144 * 8;
673 }
674 
intel_dp_dsc_get_output_bpp(struct drm_i915_private * i915,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay,bool bigjoiner,u32 pipe_bpp)675 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
676 				       u32 link_clock, u32 lane_count,
677 				       u32 mode_clock, u32 mode_hdisplay,
678 				       bool bigjoiner,
679 				       u32 pipe_bpp)
680 {
681 	u32 bits_per_pixel, max_bpp_small_joiner_ram;
682 	int i;
683 
684 	/*
685 	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
686 	 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
687 	 * for SST -> TimeSlotsPerMTP is 1,
688 	 * for MST -> TimeSlotsPerMTP has to be calculated
689 	 */
690 	bits_per_pixel = (link_clock * lane_count * 8) /
691 			 intel_dp_mode_to_fec_clock(mode_clock);
692 
693 	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
694 	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
695 		mode_hdisplay;
696 
697 	if (bigjoiner)
698 		max_bpp_small_joiner_ram *= 2;
699 
700 	/*
701 	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
702 	 * check, output bpp from small joiner RAM check)
703 	 */
704 	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
705 
706 	if (bigjoiner) {
707 		u32 max_bpp_bigjoiner =
708 			i915->display.cdclk.max_cdclk_freq * 48 /
709 			intel_dp_mode_to_fec_clock(mode_clock);
710 
711 		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
712 	}
713 
714 	/* Error out if the max bpp is less than smallest allowed valid bpp */
715 	if (bits_per_pixel < valid_dsc_bpp[0]) {
716 		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
717 			    bits_per_pixel, valid_dsc_bpp[0]);
718 		return 0;
719 	}
720 
721 	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
722 	if (DISPLAY_VER(i915) >= 13) {
723 		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
724 	} else {
725 		/* Find the nearest match in the array of known BPPs from VESA */
726 		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
727 			if (bits_per_pixel < valid_dsc_bpp[i + 1])
728 				break;
729 		}
730 		bits_per_pixel = valid_dsc_bpp[i];
731 	}
732 
733 	/*
734 	 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
735 	 * fractional part is 0
736 	 */
737 	return bits_per_pixel << 4;
738 }
739 
intel_dp_dsc_get_slice_count(struct intel_dp * intel_dp,int mode_clock,int mode_hdisplay,bool bigjoiner)740 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
741 				       int mode_clock, int mode_hdisplay,
742 				       bool bigjoiner)
743 {
744 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
745 	u8 min_slice_count, i;
746 	int max_slice_width;
747 
748 	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
749 		min_slice_count = DIV_ROUND_UP(mode_clock,
750 					       DP_DSC_MAX_ENC_THROUGHPUT_0);
751 	else
752 		min_slice_count = DIV_ROUND_UP(mode_clock,
753 					       DP_DSC_MAX_ENC_THROUGHPUT_1);
754 
755 	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
756 	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
757 		drm_dbg_kms(&i915->drm,
758 			    "Unsupported slice width %d by DP DSC Sink device\n",
759 			    max_slice_width);
760 		return 0;
761 	}
762 	/* Also take into account max slice width */
763 	min_slice_count = max_t(u8, min_slice_count,
764 				DIV_ROUND_UP(mode_hdisplay,
765 					     max_slice_width));
766 
767 	/* Find the closest match to the valid slice count values */
768 	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
769 		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
770 
771 		if (test_slice_count >
772 		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
773 			break;
774 
775 		/* big joiner needs small joiner to be enabled */
776 		if (bigjoiner && test_slice_count < 4)
777 			continue;
778 
779 		if (min_slice_count <= test_slice_count)
780 			return test_slice_count;
781 	}
782 
783 	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
784 		    min_slice_count);
785 	return 0;
786 }
787 
788 static enum intel_output_format
intel_dp_output_format(struct intel_connector * connector,bool ycbcr_420_output)789 intel_dp_output_format(struct intel_connector *connector,
790 		       bool ycbcr_420_output)
791 {
792 	struct intel_dp *intel_dp = intel_attached_dp(connector);
793 
794 	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
795 		return INTEL_OUTPUT_FORMAT_RGB;
796 
797 	if (intel_dp->dfp.rgb_to_ycbcr &&
798 	    intel_dp->dfp.ycbcr_444_to_420)
799 		return INTEL_OUTPUT_FORMAT_RGB;
800 
801 	if (intel_dp->dfp.ycbcr_444_to_420)
802 		return INTEL_OUTPUT_FORMAT_YCBCR444;
803 	else
804 		return INTEL_OUTPUT_FORMAT_YCBCR420;
805 }
806 
intel_dp_min_bpp(enum intel_output_format output_format)807 int intel_dp_min_bpp(enum intel_output_format output_format)
808 {
809 	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
810 		return 6 * 3;
811 	else
812 		return 8 * 3;
813 }
814 
intel_dp_output_bpp(enum intel_output_format output_format,int bpp)815 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
816 {
817 	/*
818 	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
819 	 * format of the number of bytes per pixel will be half the number
820 	 * of bytes of RGB pixel.
821 	 */
822 	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
823 		bpp /= 2;
824 
825 	return bpp;
826 }
827 
828 static int
intel_dp_mode_min_output_bpp(struct intel_connector * connector,const struct drm_display_mode * mode)829 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
830 			     const struct drm_display_mode *mode)
831 {
832 	const struct drm_display_info *info = &connector->base.display_info;
833 	enum intel_output_format output_format =
834 		intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
835 
836 	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
837 }
838 
intel_dp_hdisplay_bad(struct drm_i915_private * dev_priv,int hdisplay)839 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
840 				  int hdisplay)
841 {
842 	/*
843 	 * Older platforms don't like hdisplay==4096 with DP.
844 	 *
845 	 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
846 	 * and frame counter increment), but we don't get vblank interrupts,
847 	 * and the pipe underruns immediately. The link also doesn't seem
848 	 * to get trained properly.
849 	 *
850 	 * On CHV the vblank interrupts don't seem to disappear but
851 	 * otherwise the symptoms are similar.
852 	 *
853 	 * TODO: confirm the behaviour on HSW+
854 	 */
855 	return hdisplay == 4096 && !HAS_DDI(dev_priv);
856 }
857 
intel_dp_max_tmds_clock(struct intel_dp * intel_dp)858 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
859 {
860 	struct intel_connector *connector = intel_dp->attached_connector;
861 	const struct drm_display_info *info = &connector->base.display_info;
862 	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
863 
864 	/* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
865 	if (max_tmds_clock && info->max_tmds_clock)
866 		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
867 
868 	return max_tmds_clock;
869 }
870 
871 static enum drm_mode_status
intel_dp_tmds_clock_valid(struct intel_dp * intel_dp,int clock,int bpc,bool ycbcr420_output,bool respect_downstream_limits)872 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
873 			  int clock, int bpc, bool ycbcr420_output,
874 			  bool respect_downstream_limits)
875 {
876 	int tmds_clock, min_tmds_clock, max_tmds_clock;
877 
878 	if (!respect_downstream_limits)
879 		return MODE_OK;
880 
881 	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
882 
883 	min_tmds_clock = intel_dp->dfp.min_tmds_clock;
884 	max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
885 
886 	if (min_tmds_clock && tmds_clock < min_tmds_clock)
887 		return MODE_CLOCK_LOW;
888 
889 	if (max_tmds_clock && tmds_clock > max_tmds_clock)
890 		return MODE_CLOCK_HIGH;
891 
892 	return MODE_OK;
893 }
894 
895 static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector * connector,const struct drm_display_mode * mode,int target_clock)896 intel_dp_mode_valid_downstream(struct intel_connector *connector,
897 			       const struct drm_display_mode *mode,
898 			       int target_clock)
899 {
900 	struct intel_dp *intel_dp = intel_attached_dp(connector);
901 	const struct drm_display_info *info = &connector->base.display_info;
902 	enum drm_mode_status status;
903 	bool ycbcr_420_only;
904 
905 	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
906 	if (intel_dp->dfp.pcon_max_frl_bw) {
907 		int target_bw;
908 		int max_frl_bw;
909 		int bpp = intel_dp_mode_min_output_bpp(connector, mode);
910 
911 		target_bw = bpp * target_clock;
912 
913 		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
914 
915 		/* converting bw from Gbps to Kbps*/
916 		max_frl_bw = max_frl_bw * 1000000;
917 
918 		if (target_bw > max_frl_bw)
919 			return MODE_CLOCK_HIGH;
920 
921 		return MODE_OK;
922 	}
923 
924 	if (intel_dp->dfp.max_dotclock &&
925 	    target_clock > intel_dp->dfp.max_dotclock)
926 		return MODE_CLOCK_HIGH;
927 
928 	ycbcr_420_only = drm_mode_is_420_only(info, mode);
929 
930 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
931 	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
932 					   8, ycbcr_420_only, true);
933 
934 	if (status != MODE_OK) {
935 		if (ycbcr_420_only ||
936 		    !connector->base.ycbcr_420_allowed ||
937 		    !drm_mode_is_420_also(info, mode))
938 			return status;
939 
940 		status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
941 						   8, true, true);
942 		if (status != MODE_OK)
943 			return status;
944 	}
945 
946 	return MODE_OK;
947 }
948 
intel_dp_need_bigjoiner(struct intel_dp * intel_dp,int hdisplay,int clock)949 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
950 				    int hdisplay, int clock)
951 {
952 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
953 
954 	if (!intel_dp_can_bigjoiner(intel_dp))
955 		return false;
956 
957 	return clock > i915->max_dotclk_freq || hdisplay > 5120;
958 }
959 
960 static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector * _connector,struct drm_display_mode * mode)961 intel_dp_mode_valid(struct drm_connector *_connector,
962 		    struct drm_display_mode *mode)
963 {
964 	struct intel_connector *connector = to_intel_connector(_connector);
965 	struct intel_dp *intel_dp = intel_attached_dp(connector);
966 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
967 	const struct drm_display_mode *fixed_mode;
968 	int target_clock = mode->clock;
969 	int max_rate, mode_rate, max_lanes, max_link_clock;
970 	int max_dotclk = dev_priv->max_dotclk_freq;
971 	u16 dsc_max_output_bpp = 0;
972 	u8 dsc_slice_count = 0;
973 	enum drm_mode_status status;
974 	bool dsc = false, bigjoiner = false;
975 
976 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
977 		return MODE_NO_DBLESCAN;
978 
979 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
980 		return MODE_H_ILLEGAL;
981 
982 	fixed_mode = intel_panel_fixed_mode(connector, mode);
983 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
984 		status = intel_panel_mode_valid(connector, mode);
985 		if (status != MODE_OK)
986 			return status;
987 
988 		target_clock = fixed_mode->clock;
989 	}
990 
991 	if (mode->clock < 10000)
992 		return MODE_CLOCK_LOW;
993 
994 	if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
995 		bigjoiner = true;
996 		max_dotclk *= 2;
997 	}
998 	if (target_clock > max_dotclk)
999 		return MODE_CLOCK_HIGH;
1000 
1001 	max_link_clock = intel_dp_max_link_rate(intel_dp);
1002 	max_lanes = intel_dp_max_lane_count(intel_dp);
1003 
1004 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1005 	mode_rate = intel_dp_link_required(target_clock,
1006 					   intel_dp_mode_min_output_bpp(connector, mode));
1007 
1008 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1009 		return MODE_H_ILLEGAL;
1010 
1011 	/*
1012 	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1013 	 * integer value since we support only integer values of bpp.
1014 	 */
1015 	if (DISPLAY_VER(dev_priv) >= 10 &&
1016 	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1017 		/*
1018 		 * TBD pass the connector BPC,
1019 		 * for now U8_MAX so that max BPC on that platform would be picked
1020 		 */
1021 		int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1022 
1023 		if (intel_dp_is_edp(intel_dp)) {
1024 			dsc_max_output_bpp =
1025 				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1026 			dsc_slice_count =
1027 				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1028 								true);
1029 		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1030 			dsc_max_output_bpp =
1031 				intel_dp_dsc_get_output_bpp(dev_priv,
1032 							    max_link_clock,
1033 							    max_lanes,
1034 							    target_clock,
1035 							    mode->hdisplay,
1036 							    bigjoiner,
1037 							    pipe_bpp) >> 4;
1038 			dsc_slice_count =
1039 				intel_dp_dsc_get_slice_count(intel_dp,
1040 							     target_clock,
1041 							     mode->hdisplay,
1042 							     bigjoiner);
1043 		}
1044 
1045 		dsc = dsc_max_output_bpp && dsc_slice_count;
1046 	}
1047 
1048 	/*
1049 	 * Big joiner configuration needs DSC for TGL which is not true for
1050 	 * XE_LPD where uncompressed joiner is supported.
1051 	 */
1052 	if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1053 		return MODE_CLOCK_HIGH;
1054 
1055 	if (mode_rate > max_rate && !dsc)
1056 		return MODE_CLOCK_HIGH;
1057 
1058 	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1059 	if (status != MODE_OK)
1060 		return status;
1061 
1062 	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1063 }
1064 
intel_dp_source_supports_tps3(struct drm_i915_private * i915)1065 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1066 {
1067 	return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1068 }
1069 
intel_dp_source_supports_tps4(struct drm_i915_private * i915)1070 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1071 {
1072 	return DISPLAY_VER(i915) >= 10;
1073 }
1074 
snprintf_int_array(char * str,size_t len,const int * array,int nelem)1075 static void snprintf_int_array(char *str, size_t len,
1076 			       const int *array, int nelem)
1077 {
1078 	int i;
1079 
1080 	str[0] = '\0';
1081 
1082 	for (i = 0; i < nelem; i++) {
1083 		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1084 		if (r >= len)
1085 			return;
1086 		str += r;
1087 		len -= r;
1088 	}
1089 }
1090 
intel_dp_print_rates(struct intel_dp * intel_dp)1091 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1092 {
1093 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1094 	char str[128]; /* FIXME: too big for stack? */
1095 
1096 	if (!drm_debug_enabled(DRM_UT_KMS))
1097 		return;
1098 
1099 	snprintf_int_array(str, sizeof(str),
1100 			   intel_dp->source_rates, intel_dp->num_source_rates);
1101 	drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1102 
1103 	snprintf_int_array(str, sizeof(str),
1104 			   intel_dp->sink_rates, intel_dp->num_sink_rates);
1105 	drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1106 
1107 	snprintf_int_array(str, sizeof(str),
1108 			   intel_dp->common_rates, intel_dp->num_common_rates);
1109 	drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1110 }
1111 
1112 int
intel_dp_max_link_rate(struct intel_dp * intel_dp)1113 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1114 {
1115 	int len;
1116 
1117 	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1118 
1119 	return intel_dp_common_rate(intel_dp, len - 1);
1120 }
1121 
intel_dp_rate_select(struct intel_dp * intel_dp,int rate)1122 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1123 {
1124 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1125 	int i = intel_dp_rate_index(intel_dp->sink_rates,
1126 				    intel_dp->num_sink_rates, rate);
1127 
1128 	if (drm_WARN_ON(&i915->drm, i < 0))
1129 		i = 0;
1130 
1131 	return i;
1132 }
1133 
intel_dp_compute_rate(struct intel_dp * intel_dp,int port_clock,u8 * link_bw,u8 * rate_select)1134 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1135 			   u8 *link_bw, u8 *rate_select)
1136 {
1137 	/* eDP 1.4 rate select method. */
1138 	if (intel_dp->use_rate_select) {
1139 		*link_bw = 0;
1140 		*rate_select =
1141 			intel_dp_rate_select(intel_dp, port_clock);
1142 	} else {
1143 		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1144 		*rate_select = 0;
1145 	}
1146 }
1147 
intel_dp_source_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1148 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1149 					 const struct intel_crtc_state *pipe_config)
1150 {
1151 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1152 
1153 	/* On TGL, FEC is supported on all Pipes */
1154 	if (DISPLAY_VER(dev_priv) >= 12)
1155 		return true;
1156 
1157 	if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1158 		return true;
1159 
1160 	return false;
1161 }
1162 
intel_dp_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1163 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1164 				  const struct intel_crtc_state *pipe_config)
1165 {
1166 	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1167 		drm_dp_sink_supports_fec(intel_dp->fec_capable);
1168 }
1169 
intel_dp_supports_dsc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1170 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1171 				  const struct intel_crtc_state *crtc_state)
1172 {
1173 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1174 		return false;
1175 
1176 	return intel_dsc_source_support(crtc_state) &&
1177 		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1178 }
1179 
intel_dp_is_ycbcr420(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1180 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1181 				 const struct intel_crtc_state *crtc_state)
1182 {
1183 	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1184 		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1185 		 intel_dp->dfp.ycbcr_444_to_420);
1186 }
1187 
intel_dp_hdmi_compute_bpc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc,bool respect_downstream_limits)1188 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1189 				     const struct intel_crtc_state *crtc_state,
1190 				     int bpc, bool respect_downstream_limits)
1191 {
1192 	bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1193 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1194 
1195 	/*
1196 	 * Current bpc could already be below 8bpc due to
1197 	 * FDI bandwidth constraints or other limits.
1198 	 * HDMI minimum is 8bpc however.
1199 	 */
1200 	bpc = max(bpc, 8);
1201 
1202 	/*
1203 	 * We will never exceed downstream TMDS clock limits while
1204 	 * attempting deep color. If the user insists on forcing an
1205 	 * out of spec mode they will have to be satisfied with 8bpc.
1206 	 */
1207 	if (!respect_downstream_limits)
1208 		bpc = 8;
1209 
1210 	for (; bpc >= 8; bpc -= 2) {
1211 		if (intel_hdmi_bpc_possible(crtc_state, bpc,
1212 					    intel_dp->has_hdmi_sink, ycbcr420_output) &&
1213 		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1214 					      respect_downstream_limits) == MODE_OK)
1215 			return bpc;
1216 	}
1217 
1218 	return -EINVAL;
1219 }
1220 
intel_dp_max_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool respect_downstream_limits)1221 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1222 			    const struct intel_crtc_state *crtc_state,
1223 			    bool respect_downstream_limits)
1224 {
1225 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1226 	struct intel_connector *intel_connector = intel_dp->attached_connector;
1227 	int bpp, bpc;
1228 
1229 	bpc = crtc_state->pipe_bpp / 3;
1230 
1231 	if (intel_dp->dfp.max_bpc)
1232 		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1233 
1234 	if (intel_dp->dfp.min_tmds_clock) {
1235 		int max_hdmi_bpc;
1236 
1237 		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1238 							 respect_downstream_limits);
1239 		if (max_hdmi_bpc < 0)
1240 			return 0;
1241 
1242 		bpc = min(bpc, max_hdmi_bpc);
1243 	}
1244 
1245 	bpp = bpc * 3;
1246 	if (intel_dp_is_edp(intel_dp)) {
1247 		/* Get bpp from vbt only for panels that dont have bpp in edid */
1248 		if (intel_connector->base.display_info.bpc == 0 &&
1249 		    intel_connector->panel.vbt.edp.bpp &&
1250 		    intel_connector->panel.vbt.edp.bpp < bpp) {
1251 			drm_dbg_kms(&dev_priv->drm,
1252 				    "clamping bpp for eDP panel to BIOS-provided %i\n",
1253 				    intel_connector->panel.vbt.edp.bpp);
1254 			bpp = intel_connector->panel.vbt.edp.bpp;
1255 		}
1256 	}
1257 
1258 	return bpp;
1259 }
1260 
1261 /* Adjust link config limits based on compliance test requests. */
1262 void
intel_dp_adjust_compliance_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct link_config_limits * limits)1263 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1264 				  struct intel_crtc_state *pipe_config,
1265 				  struct link_config_limits *limits)
1266 {
1267 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1268 
1269 	/* For DP Compliance we override the computed bpp for the pipe */
1270 	if (intel_dp->compliance.test_data.bpc != 0) {
1271 		int bpp = 3 * intel_dp->compliance.test_data.bpc;
1272 
1273 		limits->min_bpp = limits->max_bpp = bpp;
1274 		pipe_config->dither_force_disable = bpp == 6 * 3;
1275 
1276 		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1277 	}
1278 
1279 	/* Use values requested by Compliance Test Request */
1280 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1281 		int index;
1282 
1283 		/* Validate the compliance test data since max values
1284 		 * might have changed due to link train fallback.
1285 		 */
1286 		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1287 					       intel_dp->compliance.test_lane_count)) {
1288 			index = intel_dp_rate_index(intel_dp->common_rates,
1289 						    intel_dp->num_common_rates,
1290 						    intel_dp->compliance.test_link_rate);
1291 			if (index >= 0)
1292 				limits->min_rate = limits->max_rate =
1293 					intel_dp->compliance.test_link_rate;
1294 			limits->min_lane_count = limits->max_lane_count =
1295 				intel_dp->compliance.test_lane_count;
1296 		}
1297 	}
1298 }
1299 
has_seamless_m_n(struct intel_connector * connector)1300 static bool has_seamless_m_n(struct intel_connector *connector)
1301 {
1302 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1303 
1304 	/*
1305 	 * Seamless M/N reprogramming only implemented
1306 	 * for BDW+ double buffered M/N registers so far.
1307 	 */
1308 	return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1309 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1310 }
1311 
intel_dp_mode_clock(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1312 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1313 			       const struct drm_connector_state *conn_state)
1314 {
1315 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
1316 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1317 
1318 	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
1319 	if (has_seamless_m_n(connector))
1320 		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1321 	else
1322 		return adjusted_mode->crtc_clock;
1323 }
1324 
1325 /* Optimize link config in order: max bpp, min clock, min lanes */
1326 static int
intel_dp_compute_link_config_wide(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state,const struct link_config_limits * limits)1327 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1328 				  struct intel_crtc_state *pipe_config,
1329 				  const struct drm_connector_state *conn_state,
1330 				  const struct link_config_limits *limits)
1331 {
1332 	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1333 	int mode_rate, link_rate, link_avail;
1334 
1335 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1336 		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1337 
1338 		mode_rate = intel_dp_link_required(clock, output_bpp);
1339 
1340 		for (i = 0; i < intel_dp->num_common_rates; i++) {
1341 			link_rate = intel_dp_common_rate(intel_dp, i);
1342 			if (link_rate < limits->min_rate ||
1343 			    link_rate > limits->max_rate)
1344 				continue;
1345 
1346 			for (lane_count = limits->min_lane_count;
1347 			     lane_count <= limits->max_lane_count;
1348 			     lane_count <<= 1) {
1349 				link_avail = intel_dp_max_data_rate(link_rate,
1350 								    lane_count);
1351 
1352 				if (mode_rate <= link_avail) {
1353 					pipe_config->lane_count = lane_count;
1354 					pipe_config->pipe_bpp = bpp;
1355 					pipe_config->port_clock = link_rate;
1356 
1357 					return 0;
1358 				}
1359 			}
1360 		}
1361 	}
1362 
1363 	return -EINVAL;
1364 }
1365 
intel_dp_dsc_compute_bpp(struct intel_dp * intel_dp,u8 max_req_bpc)1366 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1367 {
1368 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1369 	int i, num_bpc;
1370 	u8 dsc_bpc[3] = {0};
1371 	u8 dsc_max_bpc;
1372 
1373 	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1374 	if (DISPLAY_VER(i915) >= 12)
1375 		dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1376 	else
1377 		dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1378 
1379 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1380 						       dsc_bpc);
1381 	for (i = 0; i < num_bpc; i++) {
1382 		if (dsc_max_bpc >= dsc_bpc[i])
1383 			return dsc_bpc[i] * 3;
1384 	}
1385 
1386 	return 0;
1387 }
1388 
intel_dp_source_dsc_version_minor(struct intel_dp * intel_dp)1389 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1390 {
1391 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1392 
1393 	return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1394 }
1395 
intel_dp_sink_dsc_version_minor(struct intel_dp * intel_dp)1396 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1397 {
1398 	return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1399 		DP_DSC_MINOR_SHIFT;
1400 }
1401 
intel_dp_dsc_compute_params(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1402 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1403 				       struct intel_crtc_state *crtc_state)
1404 {
1405 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1406 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1407 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1408 	u8 line_buf_depth;
1409 	int ret;
1410 
1411 	/*
1412 	 * RC_MODEL_SIZE is currently a constant across all configurations.
1413 	 *
1414 	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1415 	 * DP_DSC_RC_BUF_SIZE for this.
1416 	 */
1417 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1418 	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1419 
1420 	/*
1421 	 * Slice Height of 8 works for all currently available panels. So start
1422 	 * with that if pic_height is an integral multiple of 8. Eventually add
1423 	 * logic to try multiple slice heights.
1424 	 */
1425 	if (vdsc_cfg->pic_height % 8 == 0)
1426 		vdsc_cfg->slice_height = 8;
1427 	else if (vdsc_cfg->pic_height % 4 == 0)
1428 		vdsc_cfg->slice_height = 4;
1429 	else
1430 		vdsc_cfg->slice_height = 2;
1431 
1432 	ret = intel_dsc_compute_params(crtc_state);
1433 	if (ret)
1434 		return ret;
1435 
1436 	vdsc_cfg->dsc_version_major =
1437 		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1438 		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1439 	vdsc_cfg->dsc_version_minor =
1440 		min(intel_dp_source_dsc_version_minor(intel_dp),
1441 		    intel_dp_sink_dsc_version_minor(intel_dp));
1442 
1443 	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1444 		DP_DSC_RGB;
1445 
1446 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1447 	if (!line_buf_depth) {
1448 		drm_dbg_kms(&i915->drm,
1449 			    "DSC Sink Line Buffer Depth invalid\n");
1450 		return -EINVAL;
1451 	}
1452 
1453 	if (vdsc_cfg->dsc_version_minor == 2)
1454 		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1455 			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1456 	else
1457 		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1458 			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1459 
1460 	vdsc_cfg->block_pred_enable =
1461 		intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1462 		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1463 
1464 	return drm_dsc_compute_rc_parameters(vdsc_cfg);
1465 }
1466 
intel_dp_dsc_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits)1467 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1468 				       struct intel_crtc_state *pipe_config,
1469 				       struct drm_connector_state *conn_state,
1470 				       struct link_config_limits *limits)
1471 {
1472 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1473 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1474 	const struct drm_display_mode *adjusted_mode =
1475 		&pipe_config->hw.adjusted_mode;
1476 	int pipe_bpp;
1477 	int ret;
1478 
1479 	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1480 		intel_dp_supports_fec(intel_dp, pipe_config);
1481 
1482 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1483 		return -EINVAL;
1484 
1485 	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1486 
1487 	if (intel_dp->force_dsc_bpc) {
1488 		pipe_bpp = intel_dp->force_dsc_bpc * 3;
1489 		drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1490 	}
1491 
1492 	/* Min Input BPC for ICL+ is 8 */
1493 	if (pipe_bpp < 8 * 3) {
1494 		drm_dbg_kms(&dev_priv->drm,
1495 			    "No DSC support for less than 8bpc\n");
1496 		return -EINVAL;
1497 	}
1498 
1499 	/*
1500 	 * For now enable DSC for max bpp, max link rate, max lane count.
1501 	 * Optimize this later for the minimum possible link rate/lane count
1502 	 * with DSC enabled for the requested mode.
1503 	 */
1504 	pipe_config->pipe_bpp = pipe_bpp;
1505 	pipe_config->port_clock = limits->max_rate;
1506 	pipe_config->lane_count = limits->max_lane_count;
1507 
1508 	if (intel_dp_is_edp(intel_dp)) {
1509 		pipe_config->dsc.compressed_bpp =
1510 			min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1511 			      pipe_config->pipe_bpp);
1512 		pipe_config->dsc.slice_count =
1513 			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1514 							true);
1515 	} else {
1516 		u16 dsc_max_output_bpp;
1517 		u8 dsc_dp_slice_count;
1518 
1519 		dsc_max_output_bpp =
1520 			intel_dp_dsc_get_output_bpp(dev_priv,
1521 						    pipe_config->port_clock,
1522 						    pipe_config->lane_count,
1523 						    adjusted_mode->crtc_clock,
1524 						    adjusted_mode->crtc_hdisplay,
1525 						    pipe_config->bigjoiner_pipes,
1526 						    pipe_bpp);
1527 		dsc_dp_slice_count =
1528 			intel_dp_dsc_get_slice_count(intel_dp,
1529 						     adjusted_mode->crtc_clock,
1530 						     adjusted_mode->crtc_hdisplay,
1531 						     pipe_config->bigjoiner_pipes);
1532 		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1533 			drm_dbg_kms(&dev_priv->drm,
1534 				    "Compressed BPP/Slice Count not supported\n");
1535 			return -EINVAL;
1536 		}
1537 		pipe_config->dsc.compressed_bpp = min_t(u16,
1538 							       dsc_max_output_bpp >> 4,
1539 							       pipe_config->pipe_bpp);
1540 		pipe_config->dsc.slice_count = dsc_dp_slice_count;
1541 	}
1542 
1543 	/*
1544 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1545 	 * is greater than the maximum Cdclock and if slice count is even
1546 	 * then we need to use 2 VDSC instances.
1547 	 */
1548 	if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq ||
1549 	    pipe_config->bigjoiner_pipes) {
1550 		if (pipe_config->dsc.slice_count < 2) {
1551 			drm_dbg_kms(&dev_priv->drm,
1552 				    "Cannot split stream to use 2 VDSC instances\n");
1553 			return -EINVAL;
1554 		}
1555 
1556 		pipe_config->dsc.dsc_split = true;
1557 	}
1558 
1559 	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1560 	if (ret < 0) {
1561 		drm_dbg_kms(&dev_priv->drm,
1562 			    "Cannot compute valid DSC parameters for Input Bpp = %d "
1563 			    "Compressed BPP = %d\n",
1564 			    pipe_config->pipe_bpp,
1565 			    pipe_config->dsc.compressed_bpp);
1566 		return ret;
1567 	}
1568 
1569 	pipe_config->dsc.compression_enable = true;
1570 	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1571 		    "Compressed Bpp = %d Slice Count = %d\n",
1572 		    pipe_config->pipe_bpp,
1573 		    pipe_config->dsc.compressed_bpp,
1574 		    pipe_config->dsc.slice_count);
1575 
1576 	return 0;
1577 }
1578 
1579 static int
intel_dp_compute_link_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,bool respect_downstream_limits)1580 intel_dp_compute_link_config(struct intel_encoder *encoder,
1581 			     struct intel_crtc_state *pipe_config,
1582 			     struct drm_connector_state *conn_state,
1583 			     bool respect_downstream_limits)
1584 {
1585 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1586 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1587 	const struct drm_display_mode *adjusted_mode =
1588 		&pipe_config->hw.adjusted_mode;
1589 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1590 	struct link_config_limits limits;
1591 	bool joiner_needs_dsc = false;
1592 	int ret;
1593 
1594 	limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1595 	limits.max_rate = intel_dp_max_link_rate(intel_dp);
1596 
1597 	limits.min_lane_count = 1;
1598 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1599 
1600 	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1601 	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1602 
1603 	if (intel_dp->use_max_params) {
1604 		/*
1605 		 * Use the maximum clock and number of lanes the eDP panel
1606 		 * advertizes being capable of in case the initial fast
1607 		 * optimal params failed us. The panels are generally
1608 		 * designed to support only a single clock and lane
1609 		 * configuration, and typically on older panels these
1610 		 * values correspond to the native resolution of the panel.
1611 		 */
1612 		limits.min_lane_count = limits.max_lane_count;
1613 		limits.min_rate = limits.max_rate;
1614 	}
1615 
1616 	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1617 
1618 	drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1619 		    "max rate %d max bpp %d pixel clock %iKHz\n",
1620 		    limits.max_lane_count, limits.max_rate,
1621 		    limits.max_bpp, adjusted_mode->crtc_clock);
1622 
1623 	if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1624 				    adjusted_mode->crtc_clock))
1625 		pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1626 
1627 	/*
1628 	 * Pipe joiner needs compression up to display 12 due to bandwidth
1629 	 * limitation. DG2 onwards pipe joiner can be enabled without
1630 	 * compression.
1631 	 */
1632 	joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1633 
1634 	/*
1635 	 * Optimize for slow and wide for everything, because there are some
1636 	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1637 	 */
1638 	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1639 
1640 	if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1641 		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1642 			    str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1643 			    str_yes_no(intel_dp->force_dsc_en));
1644 		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1645 						  conn_state, &limits);
1646 		if (ret < 0)
1647 			return ret;
1648 	}
1649 
1650 	if (pipe_config->dsc.compression_enable) {
1651 		drm_dbg_kms(&i915->drm,
1652 			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1653 			    pipe_config->lane_count, pipe_config->port_clock,
1654 			    pipe_config->pipe_bpp,
1655 			    pipe_config->dsc.compressed_bpp);
1656 
1657 		drm_dbg_kms(&i915->drm,
1658 			    "DP link rate required %i available %i\n",
1659 			    intel_dp_link_required(adjusted_mode->crtc_clock,
1660 						   pipe_config->dsc.compressed_bpp),
1661 			    intel_dp_max_data_rate(pipe_config->port_clock,
1662 						   pipe_config->lane_count));
1663 	} else {
1664 		drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1665 			    pipe_config->lane_count, pipe_config->port_clock,
1666 			    pipe_config->pipe_bpp);
1667 
1668 		drm_dbg_kms(&i915->drm,
1669 			    "DP link rate required %i available %i\n",
1670 			    intel_dp_link_required(adjusted_mode->crtc_clock,
1671 						   pipe_config->pipe_bpp),
1672 			    intel_dp_max_data_rate(pipe_config->port_clock,
1673 						   pipe_config->lane_count));
1674 	}
1675 	return 0;
1676 }
1677 
intel_dp_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1678 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1679 				  const struct drm_connector_state *conn_state)
1680 {
1681 	const struct intel_digital_connector_state *intel_conn_state =
1682 		to_intel_digital_connector_state(conn_state);
1683 	const struct drm_display_mode *adjusted_mode =
1684 		&crtc_state->hw.adjusted_mode;
1685 
1686 	/*
1687 	 * Our YCbCr output is always limited range.
1688 	 * crtc_state->limited_color_range only applies to RGB,
1689 	 * and it must never be set for YCbCr or we risk setting
1690 	 * some conflicting bits in PIPECONF which will mess up
1691 	 * the colors on the monitor.
1692 	 */
1693 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1694 		return false;
1695 
1696 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1697 		/*
1698 		 * See:
1699 		 * CEA-861-E - 5.1 Default Encoding Parameters
1700 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1701 		 */
1702 		return crtc_state->pipe_bpp != 18 &&
1703 			drm_default_rgb_quant_range(adjusted_mode) ==
1704 			HDMI_QUANTIZATION_RANGE_LIMITED;
1705 	} else {
1706 		return intel_conn_state->broadcast_rgb ==
1707 			INTEL_BROADCAST_RGB_LIMITED;
1708 	}
1709 }
1710 
intel_dp_port_has_audio(struct drm_i915_private * dev_priv,enum port port)1711 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1712 				    enum port port)
1713 {
1714 	if (IS_G4X(dev_priv))
1715 		return false;
1716 	if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1717 		return false;
1718 
1719 	return true;
1720 }
1721 
intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)1722 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1723 					     const struct drm_connector_state *conn_state,
1724 					     struct drm_dp_vsc_sdp *vsc)
1725 {
1726 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1727 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1728 
1729 	/*
1730 	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1731 	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1732 	 * Colorimetry Format indication.
1733 	 */
1734 	vsc->revision = 0x5;
1735 	vsc->length = 0x13;
1736 
1737 	/* DP 1.4a spec, Table 2-120 */
1738 	switch (crtc_state->output_format) {
1739 	case INTEL_OUTPUT_FORMAT_YCBCR444:
1740 		vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1741 		break;
1742 	case INTEL_OUTPUT_FORMAT_YCBCR420:
1743 		vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1744 		break;
1745 	case INTEL_OUTPUT_FORMAT_RGB:
1746 	default:
1747 		vsc->pixelformat = DP_PIXELFORMAT_RGB;
1748 	}
1749 
1750 	switch (conn_state->colorspace) {
1751 	case DRM_MODE_COLORIMETRY_BT709_YCC:
1752 		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1753 		break;
1754 	case DRM_MODE_COLORIMETRY_XVYCC_601:
1755 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1756 		break;
1757 	case DRM_MODE_COLORIMETRY_XVYCC_709:
1758 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1759 		break;
1760 	case DRM_MODE_COLORIMETRY_SYCC_601:
1761 		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1762 		break;
1763 	case DRM_MODE_COLORIMETRY_OPYCC_601:
1764 		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1765 		break;
1766 	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1767 		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1768 		break;
1769 	case DRM_MODE_COLORIMETRY_BT2020_RGB:
1770 		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1771 		break;
1772 	case DRM_MODE_COLORIMETRY_BT2020_YCC:
1773 		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1774 		break;
1775 	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1776 	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1777 		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1778 		break;
1779 	default:
1780 		/*
1781 		 * RGB->YCBCR color conversion uses the BT.709
1782 		 * color space.
1783 		 */
1784 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1785 			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1786 		else
1787 			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1788 		break;
1789 	}
1790 
1791 	vsc->bpc = crtc_state->pipe_bpp / 3;
1792 
1793 	/* only RGB pixelformat supports 6 bpc */
1794 	drm_WARN_ON(&dev_priv->drm,
1795 		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1796 
1797 	/* all YCbCr are always limited range */
1798 	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1799 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1800 }
1801 
intel_dp_compute_vsc_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1802 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1803 				     struct intel_crtc_state *crtc_state,
1804 				     const struct drm_connector_state *conn_state)
1805 {
1806 	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1807 
1808 	/* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1809 	if (crtc_state->has_psr)
1810 		return;
1811 
1812 	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1813 		return;
1814 
1815 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1816 	vsc->sdp_type = DP_SDP_VSC;
1817 	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1818 					 &crtc_state->infoframes.vsc);
1819 }
1820 
intel_dp_compute_psr_vsc_sdp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)1821 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1822 				  const struct intel_crtc_state *crtc_state,
1823 				  const struct drm_connector_state *conn_state,
1824 				  struct drm_dp_vsc_sdp *vsc)
1825 {
1826 	vsc->sdp_type = DP_SDP_VSC;
1827 
1828 	if (crtc_state->has_psr2) {
1829 		if (intel_dp->psr.colorimetry_support &&
1830 		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1831 			/* [PSR2, +Colorimetry] */
1832 			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1833 							 vsc);
1834 		} else {
1835 			/*
1836 			 * [PSR2, -Colorimetry]
1837 			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1838 			 * 3D stereo + PSR/PSR2 + Y-coordinate.
1839 			 */
1840 			vsc->revision = 0x4;
1841 			vsc->length = 0xe;
1842 		}
1843 	} else {
1844 		/*
1845 		 * [PSR1]
1846 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1847 		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1848 		 * higher).
1849 		 */
1850 		vsc->revision = 0x2;
1851 		vsc->length = 0x8;
1852 	}
1853 }
1854 
1855 static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1856 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1857 					    struct intel_crtc_state *crtc_state,
1858 					    const struct drm_connector_state *conn_state)
1859 {
1860 	int ret;
1861 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1862 	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1863 
1864 	if (!conn_state->hdr_output_metadata)
1865 		return;
1866 
1867 	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1868 
1869 	if (ret) {
1870 		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1871 		return;
1872 	}
1873 
1874 	crtc_state->infoframes.enable |=
1875 		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1876 }
1877 
cpu_transcoder_has_drrs(struct drm_i915_private * i915,enum transcoder cpu_transcoder)1878 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1879 				    enum transcoder cpu_transcoder)
1880 {
1881 	if (HAS_DOUBLE_BUFFERED_M_N(i915))
1882 		return true;
1883 
1884 	return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1885 }
1886 
can_enable_drrs(struct intel_connector * connector,const struct intel_crtc_state * pipe_config,const struct drm_display_mode * downclock_mode)1887 static bool can_enable_drrs(struct intel_connector *connector,
1888 			    const struct intel_crtc_state *pipe_config,
1889 			    const struct drm_display_mode *downclock_mode)
1890 {
1891 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1892 
1893 	if (pipe_config->vrr.enable)
1894 		return false;
1895 
1896 	/*
1897 	 * DRRS and PSR can't be enable together, so giving preference to PSR
1898 	 * as it allows more power-savings by complete shutting down display,
1899 	 * so to guarantee this, intel_drrs_compute_config() must be called
1900 	 * after intel_psr_compute_config().
1901 	 */
1902 	if (pipe_config->has_psr)
1903 		return false;
1904 
1905 	/* FIXME missing FDI M2/N2 etc. */
1906 	if (pipe_config->has_pch_encoder)
1907 		return false;
1908 
1909 	if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
1910 		return false;
1911 
1912 	return downclock_mode &&
1913 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1914 }
1915 
1916 static void
intel_dp_drrs_compute_config(struct intel_connector * connector,struct intel_crtc_state * pipe_config,int output_bpp)1917 intel_dp_drrs_compute_config(struct intel_connector *connector,
1918 			     struct intel_crtc_state *pipe_config,
1919 			     int output_bpp)
1920 {
1921 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1922 	const struct drm_display_mode *downclock_mode =
1923 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
1924 	int pixel_clock;
1925 
1926 	if (has_seamless_m_n(connector))
1927 		pipe_config->seamless_m_n = true;
1928 
1929 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
1930 		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
1931 			intel_zero_m_n(&pipe_config->dp_m2_n2);
1932 		return;
1933 	}
1934 
1935 	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
1936 		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
1937 
1938 	pipe_config->has_drrs = true;
1939 
1940 	pixel_clock = downclock_mode->clock;
1941 	if (pipe_config->splitter.enable)
1942 		pixel_clock /= pipe_config->splitter.link_count;
1943 
1944 	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1945 			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
1946 			       pipe_config->fec_enable);
1947 
1948 	/* FIXME: abstract this better */
1949 	if (pipe_config->splitter.enable)
1950 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
1951 }
1952 
intel_dp_has_audio(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1953 static bool intel_dp_has_audio(struct intel_encoder *encoder,
1954 			       const struct intel_crtc_state *crtc_state,
1955 			       const struct drm_connector_state *conn_state)
1956 {
1957 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1958 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1959 	const struct intel_digital_connector_state *intel_conn_state =
1960 		to_intel_digital_connector_state(conn_state);
1961 
1962 	if (!intel_dp_port_has_audio(i915, encoder->port))
1963 		return false;
1964 
1965 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1966 		return intel_dp->has_audio;
1967 	else
1968 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1969 }
1970 
1971 static int
intel_dp_compute_output_format(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state,bool respect_downstream_limits)1972 intel_dp_compute_output_format(struct intel_encoder *encoder,
1973 			       struct intel_crtc_state *crtc_state,
1974 			       struct drm_connector_state *conn_state,
1975 			       bool respect_downstream_limits)
1976 {
1977 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1978 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1979 	struct intel_connector *connector = intel_dp->attached_connector;
1980 	const struct drm_display_info *info = &connector->base.display_info;
1981 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1982 	bool ycbcr_420_only;
1983 	int ret;
1984 
1985 	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
1986 
1987 	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
1988 
1989 	if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
1990 		drm_dbg_kms(&i915->drm,
1991 			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
1992 		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
1993 	}
1994 
1995 	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1996 					   respect_downstream_limits);
1997 	if (ret) {
1998 		if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
1999 		    !connector->base.ycbcr_420_allowed ||
2000 		    !drm_mode_is_420_also(info, adjusted_mode))
2001 			return ret;
2002 
2003 		crtc_state->output_format = intel_dp_output_format(connector, true);
2004 		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2005 						   respect_downstream_limits);
2006 	}
2007 
2008 	return ret;
2009 }
2010 
2011 int
intel_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)2012 intel_dp_compute_config(struct intel_encoder *encoder,
2013 			struct intel_crtc_state *pipe_config,
2014 			struct drm_connector_state *conn_state)
2015 {
2016 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2017 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2018 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2019 	const struct drm_display_mode *fixed_mode;
2020 	struct intel_connector *connector = intel_dp->attached_connector;
2021 	int ret = 0, output_bpp;
2022 
2023 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2024 		pipe_config->has_pch_encoder = true;
2025 
2026 	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
2027 
2028 	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2029 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2030 		ret = intel_panel_compute_config(connector, adjusted_mode);
2031 		if (ret)
2032 			return ret;
2033 	}
2034 
2035 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2036 		return -EINVAL;
2037 
2038 	if (HAS_GMCH(dev_priv) &&
2039 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2040 		return -EINVAL;
2041 
2042 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2043 		return -EINVAL;
2044 
2045 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2046 		return -EINVAL;
2047 
2048 	/*
2049 	 * Try to respect downstream TMDS clock limits first, if
2050 	 * that fails assume the user might know something we don't.
2051 	 */
2052 	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2053 	if (ret)
2054 		ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2055 	if (ret)
2056 		return ret;
2057 
2058 	if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2059 	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2060 		ret = intel_panel_fitting(pipe_config, conn_state);
2061 		if (ret)
2062 			return ret;
2063 	}
2064 
2065 	pipe_config->limited_color_range =
2066 		intel_dp_limited_color_range(pipe_config, conn_state);
2067 
2068 	if (pipe_config->dsc.compression_enable)
2069 		output_bpp = pipe_config->dsc.compressed_bpp;
2070 	else
2071 		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2072 						 pipe_config->pipe_bpp);
2073 
2074 	if (intel_dp->mso_link_count) {
2075 		int n = intel_dp->mso_link_count;
2076 		int overlap = intel_dp->mso_pixel_overlap;
2077 
2078 		pipe_config->splitter.enable = true;
2079 		pipe_config->splitter.link_count = n;
2080 		pipe_config->splitter.pixel_overlap = overlap;
2081 
2082 		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2083 			    n, overlap);
2084 
2085 		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2086 		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2087 		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2088 		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2089 		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2090 		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2091 		adjusted_mode->crtc_clock /= n;
2092 	}
2093 
2094 	intel_link_compute_m_n(output_bpp,
2095 			       pipe_config->lane_count,
2096 			       adjusted_mode->crtc_clock,
2097 			       pipe_config->port_clock,
2098 			       &pipe_config->dp_m_n,
2099 			       pipe_config->fec_enable);
2100 
2101 	/* FIXME: abstract this better */
2102 	if (pipe_config->splitter.enable)
2103 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2104 
2105 	if (!HAS_DDI(dev_priv))
2106 		g4x_dp_set_clock(encoder, pipe_config);
2107 
2108 	intel_vrr_compute_config(pipe_config, conn_state);
2109 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2110 	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2111 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2112 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2113 
2114 	return 0;
2115 }
2116 
intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count)2117 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2118 			      int link_rate, int lane_count)
2119 {
2120 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2121 	intel_dp->link_trained = false;
2122 	intel_dp->link_rate = link_rate;
2123 	intel_dp->lane_count = lane_count;
2124 }
2125 
intel_dp_reset_max_link_params(struct intel_dp * intel_dp)2126 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2127 {
2128 	intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2129 	intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2130 }
2131 
2132 /* Enable backlight PWM and backlight PP control. */
intel_edp_backlight_on(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2133 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2134 			    const struct drm_connector_state *conn_state)
2135 {
2136 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2137 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2138 
2139 	if (!intel_dp_is_edp(intel_dp))
2140 		return;
2141 
2142 	drm_dbg_kms(&i915->drm, "\n");
2143 
2144 	intel_backlight_enable(crtc_state, conn_state);
2145 	intel_pps_backlight_on(intel_dp);
2146 }
2147 
2148 /* Disable backlight PP control and backlight PWM. */
intel_edp_backlight_off(const struct drm_connector_state * old_conn_state)2149 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2150 {
2151 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2152 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2153 
2154 	if (!intel_dp_is_edp(intel_dp))
2155 		return;
2156 
2157 	drm_dbg_kms(&i915->drm, "\n");
2158 
2159 	intel_pps_backlight_off(intel_dp);
2160 	intel_backlight_disable(old_conn_state);
2161 }
2162 
downstream_hpd_needs_d0(struct intel_dp * intel_dp)2163 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2164 {
2165 	/*
2166 	 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2167 	 * be capable of signalling downstream hpd with a long pulse.
2168 	 * Whether or not that means D3 is safe to use is not clear,
2169 	 * but let's assume so until proven otherwise.
2170 	 *
2171 	 * FIXME should really check all downstream ports...
2172 	 */
2173 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2174 		drm_dp_is_branch(intel_dp->dpcd) &&
2175 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2176 }
2177 
intel_dp_sink_set_decompression_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)2178 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2179 					   const struct intel_crtc_state *crtc_state,
2180 					   bool enable)
2181 {
2182 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2183 	int ret;
2184 
2185 	if (!crtc_state->dsc.compression_enable)
2186 		return;
2187 
2188 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2189 				 enable ? DP_DECOMPRESSION_EN : 0);
2190 	if (ret < 0)
2191 		drm_dbg_kms(&i915->drm,
2192 			    "Failed to %s sink decompression state\n",
2193 			    str_enable_disable(enable));
2194 }
2195 
2196 static void
intel_edp_init_source_oui(struct intel_dp * intel_dp,bool careful)2197 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2198 {
2199 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2200 	u8 oui[] = { 0x00, 0xaa, 0x01 };
2201 	u8 buf[3] = { 0 };
2202 
2203 	/*
2204 	 * During driver init, we want to be careful and avoid changing the source OUI if it's
2205 	 * already set to what we want, so as to avoid clearing any state by accident
2206 	 */
2207 	if (careful) {
2208 		if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2209 			drm_err(&i915->drm, "Failed to read source OUI\n");
2210 
2211 		if (memcmp(oui, buf, sizeof(oui)) == 0)
2212 			return;
2213 	}
2214 
2215 	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2216 		drm_err(&i915->drm, "Failed to write source OUI\n");
2217 
2218 	intel_dp->last_oui_write = jiffies;
2219 }
2220 
intel_dp_wait_source_oui(struct intel_dp * intel_dp)2221 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2222 {
2223 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2224 
2225 	drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2226 	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2227 }
2228 
2229 /* If the device supports it, try to set the power state appropriately */
intel_dp_set_power(struct intel_dp * intel_dp,u8 mode)2230 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2231 {
2232 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2233 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2234 	int ret, i;
2235 
2236 	/* Should have a valid DPCD by this point */
2237 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2238 		return;
2239 
2240 	if (mode != DP_SET_POWER_D0) {
2241 		if (downstream_hpd_needs_d0(intel_dp))
2242 			return;
2243 
2244 		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2245 	} else {
2246 		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2247 
2248 		lspcon_resume(dp_to_dig_port(intel_dp));
2249 
2250 		/* Write the source OUI as early as possible */
2251 		if (intel_dp_is_edp(intel_dp))
2252 			intel_edp_init_source_oui(intel_dp, false);
2253 
2254 		/*
2255 		 * When turning on, we need to retry for 1ms to give the sink
2256 		 * time to wake up.
2257 		 */
2258 		for (i = 0; i < 3; i++) {
2259 			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2260 			if (ret == 1)
2261 				break;
2262 			msleep(1);
2263 		}
2264 
2265 		if (ret == 1 && lspcon->active)
2266 			lspcon_wait_pcon_mode(lspcon);
2267 	}
2268 
2269 	if (ret != 1)
2270 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2271 			    encoder->base.base.id, encoder->base.name,
2272 			    mode == DP_SET_POWER_D0 ? "D0" : "D3");
2273 }
2274 
2275 static bool
2276 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2277 
2278 /**
2279  * intel_dp_sync_state - sync the encoder state during init/resume
2280  * @encoder: intel encoder to sync
2281  * @crtc_state: state for the CRTC connected to the encoder
2282  *
2283  * Sync any state stored in the encoder wrt. HW state during driver init
2284  * and system resume.
2285  */
intel_dp_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2286 void intel_dp_sync_state(struct intel_encoder *encoder,
2287 			 const struct intel_crtc_state *crtc_state)
2288 {
2289 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2290 
2291 	if (!crtc_state)
2292 		return;
2293 
2294 	/*
2295 	 * Don't clobber DPCD if it's been already read out during output
2296 	 * setup (eDP) or detect.
2297 	 */
2298 	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2299 		intel_dp_get_dpcd(intel_dp);
2300 
2301 	intel_dp_reset_max_link_params(intel_dp);
2302 }
2303 
intel_dp_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)2304 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2305 				    struct intel_crtc_state *crtc_state)
2306 {
2307 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2308 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2309 
2310 	/*
2311 	 * If BIOS has set an unsupported or non-standard link rate for some
2312 	 * reason force an encoder recompute and full modeset.
2313 	 */
2314 	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2315 				crtc_state->port_clock) < 0) {
2316 		drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
2317 		crtc_state->uapi.connectors_changed = true;
2318 		return false;
2319 	}
2320 
2321 	/*
2322 	 * FIXME hack to force full modeset when DSC is being used.
2323 	 *
2324 	 * As long as we do not have full state readout and config comparison
2325 	 * of crtc_state->dsc, we have no way to ensure reliable fastset.
2326 	 * Remove once we have readout for DSC.
2327 	 */
2328 	if (crtc_state->dsc.compression_enable) {
2329 		drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
2330 		crtc_state->uapi.mode_changed = true;
2331 		return false;
2332 	}
2333 
2334 	if (CAN_PSR(intel_dp)) {
2335 		drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
2336 		crtc_state->uapi.mode_changed = true;
2337 		return false;
2338 	}
2339 
2340 	return true;
2341 }
2342 
intel_dp_get_pcon_dsc_cap(struct intel_dp * intel_dp)2343 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2344 {
2345 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2346 
2347 	/* Clear the cached register set to avoid using stale values */
2348 
2349 	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2350 
2351 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2352 			     intel_dp->pcon_dsc_dpcd,
2353 			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2354 		drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2355 			DP_PCON_DSC_ENCODER);
2356 
2357 	drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2358 		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2359 }
2360 
intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)2361 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2362 {
2363 	int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2364 	int i;
2365 
2366 	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2367 		if (frl_bw_mask & (1 << i))
2368 			return bw_gbps[i];
2369 	}
2370 	return 0;
2371 }
2372 
intel_dp_pcon_set_frl_mask(int max_frl)2373 static int intel_dp_pcon_set_frl_mask(int max_frl)
2374 {
2375 	switch (max_frl) {
2376 	case 48:
2377 		return DP_PCON_FRL_BW_MASK_48GBPS;
2378 	case 40:
2379 		return DP_PCON_FRL_BW_MASK_40GBPS;
2380 	case 32:
2381 		return DP_PCON_FRL_BW_MASK_32GBPS;
2382 	case 24:
2383 		return DP_PCON_FRL_BW_MASK_24GBPS;
2384 	case 18:
2385 		return DP_PCON_FRL_BW_MASK_18GBPS;
2386 	case 9:
2387 		return DP_PCON_FRL_BW_MASK_9GBPS;
2388 	}
2389 
2390 	return 0;
2391 }
2392 
intel_dp_hdmi_sink_max_frl(struct intel_dp * intel_dp)2393 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2394 {
2395 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2396 	struct drm_connector *connector = &intel_connector->base;
2397 	int max_frl_rate;
2398 	int max_lanes, rate_per_lane;
2399 	int max_dsc_lanes, dsc_rate_per_lane;
2400 
2401 	max_lanes = connector->display_info.hdmi.max_lanes;
2402 	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2403 	max_frl_rate = max_lanes * rate_per_lane;
2404 
2405 	if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2406 		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2407 		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2408 		if (max_dsc_lanes && dsc_rate_per_lane)
2409 			max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2410 	}
2411 
2412 	return max_frl_rate;
2413 }
2414 
2415 static bool
intel_dp_pcon_is_frl_trained(struct intel_dp * intel_dp,u8 max_frl_bw_mask,u8 * frl_trained_mask)2416 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2417 			     u8 max_frl_bw_mask, u8 *frl_trained_mask)
2418 {
2419 	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2420 	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2421 	    *frl_trained_mask >= max_frl_bw_mask)
2422 		return true;
2423 
2424 	return false;
2425 }
2426 
intel_dp_pcon_start_frl_training(struct intel_dp * intel_dp)2427 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2428 {
2429 #define TIMEOUT_FRL_READY_MS 500
2430 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2431 
2432 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2433 	int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2434 	u8 max_frl_bw_mask = 0, frl_trained_mask;
2435 	bool is_active;
2436 
2437 	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2438 	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2439 
2440 	max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2441 	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2442 
2443 	max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2444 
2445 	if (max_frl_bw <= 0)
2446 		return -EINVAL;
2447 
2448 	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2449 	drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2450 
2451 	if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2452 		goto frl_trained;
2453 
2454 	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2455 	if (ret < 0)
2456 		return ret;
2457 	/* Wait for PCON to be FRL Ready */
2458 	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2459 
2460 	if (!is_active)
2461 		return -ETIMEDOUT;
2462 
2463 	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2464 					  DP_PCON_ENABLE_SEQUENTIAL_LINK);
2465 	if (ret < 0)
2466 		return ret;
2467 	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2468 					  DP_PCON_FRL_LINK_TRAIN_NORMAL);
2469 	if (ret < 0)
2470 		return ret;
2471 	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2472 	if (ret < 0)
2473 		return ret;
2474 	/*
2475 	 * Wait for FRL to be completed
2476 	 * Check if the HDMI Link is up and active.
2477 	 */
2478 	wait_for(is_active =
2479 		 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2480 		 TIMEOUT_HDMI_LINK_ACTIVE_MS);
2481 
2482 	if (!is_active)
2483 		return -ETIMEDOUT;
2484 
2485 frl_trained:
2486 	drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2487 	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2488 	intel_dp->frl.is_trained = true;
2489 	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2490 
2491 	return 0;
2492 }
2493 
intel_dp_is_hdmi_2_1_sink(struct intel_dp * intel_dp)2494 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2495 {
2496 	if (drm_dp_is_branch(intel_dp->dpcd) &&
2497 	    intel_dp->has_hdmi_sink &&
2498 	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2499 		return true;
2500 
2501 	return false;
2502 }
2503 
2504 static
intel_dp_pcon_set_tmds_mode(struct intel_dp * intel_dp)2505 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2506 {
2507 	int ret;
2508 	u8 buf = 0;
2509 
2510 	/* Set PCON source control mode */
2511 	buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2512 
2513 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2514 	if (ret < 0)
2515 		return ret;
2516 
2517 	/* Set HDMI LINK ENABLE */
2518 	buf |= DP_PCON_ENABLE_HDMI_LINK;
2519 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2520 	if (ret < 0)
2521 		return ret;
2522 
2523 	return 0;
2524 }
2525 
intel_dp_check_frl_training(struct intel_dp * intel_dp)2526 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2527 {
2528 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2529 
2530 	/*
2531 	 * Always go for FRL training if:
2532 	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2533 	 * -sink is HDMI2.1
2534 	 */
2535 	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2536 	    !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2537 	    intel_dp->frl.is_trained)
2538 		return;
2539 
2540 	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2541 		int ret, mode;
2542 
2543 		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2544 		ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2545 		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2546 
2547 		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2548 			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2549 	} else {
2550 		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2551 	}
2552 }
2553 
2554 static int
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state * crtc_state)2555 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2556 {
2557 	int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2558 
2559 	return intel_hdmi_dsc_get_slice_height(vactive);
2560 }
2561 
2562 static int
intel_dp_pcon_dsc_enc_slices(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2563 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2564 			     const struct intel_crtc_state *crtc_state)
2565 {
2566 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2567 	struct drm_connector *connector = &intel_connector->base;
2568 	int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2569 	int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2570 	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2571 	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2572 
2573 	return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2574 					     pcon_max_slice_width,
2575 					     hdmi_max_slices, hdmi_throughput);
2576 }
2577 
2578 static int
intel_dp_pcon_dsc_enc_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int num_slices,int slice_width)2579 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2580 			  const struct intel_crtc_state *crtc_state,
2581 			  int num_slices, int slice_width)
2582 {
2583 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2584 	struct drm_connector *connector = &intel_connector->base;
2585 	int output_format = crtc_state->output_format;
2586 	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2587 	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2588 	int hdmi_max_chunk_bytes =
2589 		connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2590 
2591 	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2592 				      num_slices, output_format, hdmi_all_bpp,
2593 				      hdmi_max_chunk_bytes);
2594 }
2595 
2596 void
intel_dp_pcon_dsc_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2597 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2598 			    const struct intel_crtc_state *crtc_state)
2599 {
2600 	u8 pps_param[6];
2601 	int slice_height;
2602 	int slice_width;
2603 	int num_slices;
2604 	int bits_per_pixel;
2605 	int ret;
2606 	struct intel_connector *intel_connector = intel_dp->attached_connector;
2607 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2608 	struct drm_connector *connector;
2609 	bool hdmi_is_dsc_1_2;
2610 
2611 	if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2612 		return;
2613 
2614 	if (!intel_connector)
2615 		return;
2616 	connector = &intel_connector->base;
2617 	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2618 
2619 	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2620 	    !hdmi_is_dsc_1_2)
2621 		return;
2622 
2623 	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2624 	if (!slice_height)
2625 		return;
2626 
2627 	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2628 	if (!num_slices)
2629 		return;
2630 
2631 	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2632 				   num_slices);
2633 
2634 	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2635 						   num_slices, slice_width);
2636 	if (!bits_per_pixel)
2637 		return;
2638 
2639 	pps_param[0] = slice_height & 0xFF;
2640 	pps_param[1] = slice_height >> 8;
2641 	pps_param[2] = slice_width & 0xFF;
2642 	pps_param[3] = slice_width >> 8;
2643 	pps_param[4] = bits_per_pixel & 0xFF;
2644 	pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2645 
2646 	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2647 	if (ret < 0)
2648 		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2649 }
2650 
intel_dp_configure_protocol_converter(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2651 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2652 					   const struct intel_crtc_state *crtc_state)
2653 {
2654 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2655 	u8 tmp;
2656 
2657 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2658 		return;
2659 
2660 	if (!drm_dp_is_branch(intel_dp->dpcd))
2661 		return;
2662 
2663 	tmp = intel_dp->has_hdmi_sink ?
2664 		DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2665 
2666 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2667 			       DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2668 		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2669 			    str_enable_disable(intel_dp->has_hdmi_sink));
2670 
2671 	tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2672 		intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2673 
2674 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2675 			       DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2676 		drm_dbg_kms(&i915->drm,
2677 			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2678 			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2679 
2680 	tmp = intel_dp->dfp.rgb_to_ycbcr ?
2681 		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2682 
2683 	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2684 		drm_dbg_kms(&i915->drm,
2685 			   "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2686 			   str_enable_disable(tmp));
2687 }
2688 
2689 
intel_dp_get_colorimetry_status(struct intel_dp * intel_dp)2690 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2691 {
2692 	u8 dprx = 0;
2693 
2694 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2695 			      &dprx) != 1)
2696 		return false;
2697 	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2698 }
2699 
intel_dp_get_dsc_sink_cap(struct intel_dp * intel_dp)2700 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2701 {
2702 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2703 
2704 	/*
2705 	 * Clear the cached register set to avoid using stale values
2706 	 * for the sinks that do not support DSC.
2707 	 */
2708 	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2709 
2710 	/* Clear fec_capable to avoid using stale values */
2711 	intel_dp->fec_capable = 0;
2712 
2713 	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2714 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2715 	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2716 		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2717 				     intel_dp->dsc_dpcd,
2718 				     sizeof(intel_dp->dsc_dpcd)) < 0)
2719 			drm_err(&i915->drm,
2720 				"Failed to read DPCD register 0x%x\n",
2721 				DP_DSC_SUPPORT);
2722 
2723 		drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2724 			    (int)sizeof(intel_dp->dsc_dpcd),
2725 			    intel_dp->dsc_dpcd);
2726 
2727 		/* FEC is supported only on DP 1.4 */
2728 		if (!intel_dp_is_edp(intel_dp) &&
2729 		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2730 				      &intel_dp->fec_capable) < 0)
2731 			drm_err(&i915->drm,
2732 				"Failed to read FEC DPCD register\n");
2733 
2734 		drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2735 			    intel_dp->fec_capable);
2736 	}
2737 }
2738 
intel_edp_mso_mode_fixup(struct intel_connector * connector,struct drm_display_mode * mode)2739 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2740 				     struct drm_display_mode *mode)
2741 {
2742 	struct intel_dp *intel_dp = intel_attached_dp(connector);
2743 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2744 	int n = intel_dp->mso_link_count;
2745 	int overlap = intel_dp->mso_pixel_overlap;
2746 
2747 	if (!mode || !n)
2748 		return;
2749 
2750 	mode->hdisplay = (mode->hdisplay - overlap) * n;
2751 	mode->hsync_start = (mode->hsync_start - overlap) * n;
2752 	mode->hsync_end = (mode->hsync_end - overlap) * n;
2753 	mode->htotal = (mode->htotal - overlap) * n;
2754 	mode->clock *= n;
2755 
2756 	drm_mode_set_name(mode);
2757 
2758 	drm_dbg_kms(&i915->drm,
2759 		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2760 		    connector->base.base.id, connector->base.name,
2761 		    DRM_MODE_ARG(mode));
2762 }
2763 
intel_edp_fixup_vbt_bpp(struct intel_encoder * encoder,int pipe_bpp)2764 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
2765 {
2766 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2767 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2768 	struct intel_connector *connector = intel_dp->attached_connector;
2769 
2770 	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
2771 		/*
2772 		 * This is a big fat ugly hack.
2773 		 *
2774 		 * Some machines in UEFI boot mode provide us a VBT that has 18
2775 		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2776 		 * unknown we fail to light up. Yet the same BIOS boots up with
2777 		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2778 		 * max, not what it tells us to use.
2779 		 *
2780 		 * Note: This will still be broken if the eDP panel is not lit
2781 		 * up by the BIOS, and thus we can't get the mode at module
2782 		 * load.
2783 		 */
2784 		drm_dbg_kms(&dev_priv->drm,
2785 			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2786 			    pipe_bpp, connector->panel.vbt.edp.bpp);
2787 		connector->panel.vbt.edp.bpp = pipe_bpp;
2788 	}
2789 }
2790 
intel_edp_mso_init(struct intel_dp * intel_dp)2791 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2792 {
2793 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2794 	struct intel_connector *connector = intel_dp->attached_connector;
2795 	struct drm_display_info *info = &connector->base.display_info;
2796 	u8 mso;
2797 
2798 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2799 		return;
2800 
2801 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2802 		drm_err(&i915->drm, "Failed to read MSO cap\n");
2803 		return;
2804 	}
2805 
2806 	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2807 	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2808 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2809 		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2810 		mso = 0;
2811 	}
2812 
2813 	if (mso) {
2814 		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2815 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2816 			    info->mso_pixel_overlap);
2817 		if (!HAS_MSO(i915)) {
2818 			drm_err(&i915->drm, "No source MSO support, disabling\n");
2819 			mso = 0;
2820 		}
2821 	}
2822 
2823 	intel_dp->mso_link_count = mso;
2824 	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2825 }
2826 
2827 static bool
intel_edp_init_dpcd(struct intel_dp * intel_dp)2828 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2829 {
2830 	struct drm_i915_private *dev_priv =
2831 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2832 
2833 	/* this function is meant to be called only once */
2834 	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2835 
2836 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2837 		return false;
2838 
2839 	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2840 			 drm_dp_is_branch(intel_dp->dpcd));
2841 
2842 	/*
2843 	 * Read the eDP display control registers.
2844 	 *
2845 	 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2846 	 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2847 	 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2848 	 * method). The display control registers should read zero if they're
2849 	 * not supported anyway.
2850 	 */
2851 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2852 			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2853 			     sizeof(intel_dp->edp_dpcd)) {
2854 		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2855 			    (int)sizeof(intel_dp->edp_dpcd),
2856 			    intel_dp->edp_dpcd);
2857 
2858 		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2859 	}
2860 
2861 	/*
2862 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2863 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2864 	 */
2865 	intel_psr_init_dpcd(intel_dp);
2866 
2867 	/* Clear the default sink rates */
2868 	intel_dp->num_sink_rates = 0;
2869 
2870 	/* Read the eDP 1.4+ supported link rates. */
2871 	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2872 		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2873 		int i;
2874 
2875 		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2876 				sink_rates, sizeof(sink_rates));
2877 
2878 		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2879 			int val = le16_to_cpu(sink_rates[i]);
2880 
2881 			if (val == 0)
2882 				break;
2883 
2884 			/* Value read multiplied by 200kHz gives the per-lane
2885 			 * link rate in kHz. The source rates are, however,
2886 			 * stored in terms of LS_Clk kHz. The full conversion
2887 			 * back to symbols is
2888 			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2889 			 */
2890 			intel_dp->sink_rates[i] = (val * 200) / 10;
2891 		}
2892 		intel_dp->num_sink_rates = i;
2893 	}
2894 
2895 	/*
2896 	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2897 	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2898 	 */
2899 	if (intel_dp->num_sink_rates)
2900 		intel_dp->use_rate_select = true;
2901 	else
2902 		intel_dp_set_sink_rates(intel_dp);
2903 	intel_dp_set_max_sink_lane_count(intel_dp);
2904 
2905 	/* Read the eDP DSC DPCD registers */
2906 	if (DISPLAY_VER(dev_priv) >= 10)
2907 		intel_dp_get_dsc_sink_cap(intel_dp);
2908 
2909 	/*
2910 	 * If needed, program our source OUI so we can make various Intel-specific AUX services
2911 	 * available (such as HDR backlight controls)
2912 	 */
2913 	intel_edp_init_source_oui(intel_dp, true);
2914 
2915 	return true;
2916 }
2917 
2918 static bool
intel_dp_has_sink_count(struct intel_dp * intel_dp)2919 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2920 {
2921 	if (!intel_dp->attached_connector)
2922 		return false;
2923 
2924 	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2925 					  intel_dp->dpcd,
2926 					  &intel_dp->desc);
2927 }
2928 
2929 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)2930 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2931 {
2932 	int ret;
2933 
2934 	if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2935 		return false;
2936 
2937 	/*
2938 	 * Don't clobber cached eDP rates. Also skip re-reading
2939 	 * the OUI/ID since we know it won't change.
2940 	 */
2941 	if (!intel_dp_is_edp(intel_dp)) {
2942 		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2943 				 drm_dp_is_branch(intel_dp->dpcd));
2944 
2945 		intel_dp_set_sink_rates(intel_dp);
2946 		intel_dp_set_max_sink_lane_count(intel_dp);
2947 		intel_dp_set_common_rates(intel_dp);
2948 	}
2949 
2950 	if (intel_dp_has_sink_count(intel_dp)) {
2951 		ret = drm_dp_read_sink_count(&intel_dp->aux);
2952 		if (ret < 0)
2953 			return false;
2954 
2955 		/*
2956 		 * Sink count can change between short pulse hpd hence
2957 		 * a member variable in intel_dp will track any changes
2958 		 * between short pulse interrupts.
2959 		 */
2960 		intel_dp->sink_count = ret;
2961 
2962 		/*
2963 		 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2964 		 * a dongle is present but no display. Unless we require to know
2965 		 * if a dongle is present or not, we don't need to update
2966 		 * downstream port information. So, an early return here saves
2967 		 * time from performing other operations which are not required.
2968 		 */
2969 		if (!intel_dp->sink_count)
2970 			return false;
2971 	}
2972 
2973 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2974 					   intel_dp->downstream_ports) == 0;
2975 }
2976 
2977 static bool
intel_dp_can_mst(struct intel_dp * intel_dp)2978 intel_dp_can_mst(struct intel_dp *intel_dp)
2979 {
2980 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2981 
2982 	return i915->params.enable_dp_mst &&
2983 		intel_dp_mst_source_support(intel_dp) &&
2984 		drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2985 }
2986 
2987 static void
intel_dp_configure_mst(struct intel_dp * intel_dp)2988 intel_dp_configure_mst(struct intel_dp *intel_dp)
2989 {
2990 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2991 	struct intel_encoder *encoder =
2992 		&dp_to_dig_port(intel_dp)->base;
2993 	bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2994 
2995 	drm_dbg_kms(&i915->drm,
2996 		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2997 		    encoder->base.base.id, encoder->base.name,
2998 		    str_yes_no(intel_dp_mst_source_support(intel_dp)),
2999 		    str_yes_no(sink_can_mst),
3000 		    str_yes_no(i915->params.enable_dp_mst));
3001 
3002 	if (!intel_dp_mst_source_support(intel_dp))
3003 		return;
3004 
3005 	intel_dp->is_mst = sink_can_mst &&
3006 		i915->params.enable_dp_mst;
3007 
3008 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3009 					intel_dp->is_mst);
3010 }
3011 
3012 static bool
intel_dp_get_sink_irq_esi(struct intel_dp * intel_dp,u8 * esi)3013 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3014 {
3015 	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3016 }
3017 
intel_dp_ack_sink_irq_esi(struct intel_dp * intel_dp,u8 esi[4])3018 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3019 {
3020 	int retry;
3021 
3022 	for (retry = 0; retry < 3; retry++) {
3023 		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3024 				      &esi[1], 3) == 3)
3025 			return true;
3026 	}
3027 
3028 	return false;
3029 }
3030 
3031 bool
intel_dp_needs_vsc_sdp(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3032 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3033 		       const struct drm_connector_state *conn_state)
3034 {
3035 	/*
3036 	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3037 	 * of Color Encoding Format and Content Color Gamut], in order to
3038 	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3039 	 */
3040 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3041 		return true;
3042 
3043 	switch (conn_state->colorspace) {
3044 	case DRM_MODE_COLORIMETRY_SYCC_601:
3045 	case DRM_MODE_COLORIMETRY_OPYCC_601:
3046 	case DRM_MODE_COLORIMETRY_BT2020_YCC:
3047 	case DRM_MODE_COLORIMETRY_BT2020_RGB:
3048 	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3049 		return true;
3050 	default:
3051 		break;
3052 	}
3053 
3054 	return false;
3055 }
3056 
intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp * vsc,struct dp_sdp * sdp,size_t size)3057 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3058 				     struct dp_sdp *sdp, size_t size)
3059 {
3060 	size_t length = sizeof(struct dp_sdp);
3061 
3062 	if (size < length)
3063 		return -ENOSPC;
3064 
3065 	memset(sdp, 0, size);
3066 
3067 	/*
3068 	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3069 	 * VSC SDP Header Bytes
3070 	 */
3071 	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3072 	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3073 	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3074 	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3075 
3076 	/*
3077 	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3078 	 * per DP 1.4a spec.
3079 	 */
3080 	if (vsc->revision != 0x5)
3081 		goto out;
3082 
3083 	/* VSC SDP Payload for DB16 through DB18 */
3084 	/* Pixel Encoding and Colorimetry Formats  */
3085 	sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3086 	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3087 
3088 	switch (vsc->bpc) {
3089 	case 6:
3090 		/* 6bpc: 0x0 */
3091 		break;
3092 	case 8:
3093 		sdp->db[17] = 0x1; /* DB17[3:0] */
3094 		break;
3095 	case 10:
3096 		sdp->db[17] = 0x2;
3097 		break;
3098 	case 12:
3099 		sdp->db[17] = 0x3;
3100 		break;
3101 	case 16:
3102 		sdp->db[17] = 0x4;
3103 		break;
3104 	default:
3105 		MISSING_CASE(vsc->bpc);
3106 		break;
3107 	}
3108 	/* Dynamic Range and Component Bit Depth */
3109 	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3110 		sdp->db[17] |= 0x80;  /* DB17[7] */
3111 
3112 	/* Content Type */
3113 	sdp->db[18] = vsc->content_type & 0x7;
3114 
3115 out:
3116 	return length;
3117 }
3118 
3119 static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private * i915,const struct hdmi_drm_infoframe * drm_infoframe,struct dp_sdp * sdp,size_t size)3120 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3121 					 const struct hdmi_drm_infoframe *drm_infoframe,
3122 					 struct dp_sdp *sdp,
3123 					 size_t size)
3124 {
3125 	size_t length = sizeof(struct dp_sdp);
3126 	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3127 	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3128 	ssize_t len;
3129 
3130 	if (size < length)
3131 		return -ENOSPC;
3132 
3133 	memset(sdp, 0, size);
3134 
3135 	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3136 	if (len < 0) {
3137 		drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3138 		return -ENOSPC;
3139 	}
3140 
3141 	if (len != infoframe_size) {
3142 		drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3143 		return -ENOSPC;
3144 	}
3145 
3146 	/*
3147 	 * Set up the infoframe sdp packet for HDR static metadata.
3148 	 * Prepare VSC Header for SU as per DP 1.4a spec,
3149 	 * Table 2-100 and Table 2-101
3150 	 */
3151 
3152 	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3153 	sdp->sdp_header.HB0 = 0;
3154 	/*
3155 	 * Packet Type 80h + Non-audio INFOFRAME Type value
3156 	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
3157 	 * - 80h + Non-audio INFOFRAME Type value
3158 	 * - InfoFrame Type: 0x07
3159 	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3160 	 */
3161 	sdp->sdp_header.HB1 = drm_infoframe->type;
3162 	/*
3163 	 * Least Significant Eight Bits of (Data Byte Count – 1)
3164 	 * infoframe_size - 1
3165 	 */
3166 	sdp->sdp_header.HB2 = 0x1D;
3167 	/* INFOFRAME SDP Version Number */
3168 	sdp->sdp_header.HB3 = (0x13 << 2);
3169 	/* CTA Header Byte 2 (INFOFRAME Version Number) */
3170 	sdp->db[0] = drm_infoframe->version;
3171 	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3172 	sdp->db[1] = drm_infoframe->length;
3173 	/*
3174 	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3175 	 * HDMI_INFOFRAME_HEADER_SIZE
3176 	 */
3177 	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3178 	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3179 	       HDMI_DRM_INFOFRAME_SIZE);
3180 
3181 	/*
3182 	 * Size of DP infoframe sdp packet for HDR static metadata consists of
3183 	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
3184 	 * - Two Data Blocks: 2 bytes
3185 	 *    CTA Header Byte2 (INFOFRAME Version Number)
3186 	 *    CTA Header Byte3 (Length of INFOFRAME)
3187 	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3188 	 *
3189 	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3190 	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
3191 	 * will pad rest of the size.
3192 	 */
3193 	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3194 }
3195 
intel_write_dp_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type)3196 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3197 			       const struct intel_crtc_state *crtc_state,
3198 			       unsigned int type)
3199 {
3200 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3201 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3202 	struct dp_sdp sdp = {};
3203 	ssize_t len;
3204 
3205 	if ((crtc_state->infoframes.enable &
3206 	     intel_hdmi_infoframe_enable(type)) == 0)
3207 		return;
3208 
3209 	switch (type) {
3210 	case DP_SDP_VSC:
3211 		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3212 					    sizeof(sdp));
3213 		break;
3214 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3215 		len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3216 							       &crtc_state->infoframes.drm.drm,
3217 							       &sdp, sizeof(sdp));
3218 		break;
3219 	default:
3220 		MISSING_CASE(type);
3221 		return;
3222 	}
3223 
3224 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
3225 		return;
3226 
3227 	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3228 }
3229 
intel_write_dp_vsc_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_dp_vsc_sdp * vsc)3230 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3231 			    const struct intel_crtc_state *crtc_state,
3232 			    const struct drm_dp_vsc_sdp *vsc)
3233 {
3234 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3235 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3236 	struct dp_sdp sdp = {};
3237 	ssize_t len;
3238 
3239 	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3240 
3241 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
3242 		return;
3243 
3244 	dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3245 					&sdp, len);
3246 }
3247 
intel_dp_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3248 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3249 			     bool enable,
3250 			     const struct intel_crtc_state *crtc_state,
3251 			     const struct drm_connector_state *conn_state)
3252 {
3253 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3254 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3255 	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3256 			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3257 			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3258 	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3259 
3260 	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
3261 	/* When PSR is enabled, this routine doesn't disable VSC DIP */
3262 	if (!crtc_state->has_psr)
3263 		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3264 
3265 	intel_de_write(dev_priv, reg, val);
3266 	intel_de_posting_read(dev_priv, reg);
3267 
3268 	if (!enable)
3269 		return;
3270 
3271 	/* When PSR is enabled, VSC SDP is handled by PSR routine */
3272 	if (!crtc_state->has_psr)
3273 		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3274 
3275 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3276 }
3277 
intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp * vsc,const void * buffer,size_t size)3278 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3279 				   const void *buffer, size_t size)
3280 {
3281 	const struct dp_sdp *sdp = buffer;
3282 
3283 	if (size < sizeof(struct dp_sdp))
3284 		return -EINVAL;
3285 
3286 	memset(vsc, 0, sizeof(*vsc));
3287 
3288 	if (sdp->sdp_header.HB0 != 0)
3289 		return -EINVAL;
3290 
3291 	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3292 		return -EINVAL;
3293 
3294 	vsc->sdp_type = sdp->sdp_header.HB1;
3295 	vsc->revision = sdp->sdp_header.HB2;
3296 	vsc->length = sdp->sdp_header.HB3;
3297 
3298 	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3299 	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3300 		/*
3301 		 * - HB2 = 0x2, HB3 = 0x8
3302 		 *   VSC SDP supporting 3D stereo + PSR
3303 		 * - HB2 = 0x4, HB3 = 0xe
3304 		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3305 		 *   first scan line of the SU region (applies to eDP v1.4b
3306 		 *   and higher).
3307 		 */
3308 		return 0;
3309 	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3310 		/*
3311 		 * - HB2 = 0x5, HB3 = 0x13
3312 		 *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3313 		 *   Format.
3314 		 */
3315 		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3316 		vsc->colorimetry = sdp->db[16] & 0xf;
3317 		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3318 
3319 		switch (sdp->db[17] & 0x7) {
3320 		case 0x0:
3321 			vsc->bpc = 6;
3322 			break;
3323 		case 0x1:
3324 			vsc->bpc = 8;
3325 			break;
3326 		case 0x2:
3327 			vsc->bpc = 10;
3328 			break;
3329 		case 0x3:
3330 			vsc->bpc = 12;
3331 			break;
3332 		case 0x4:
3333 			vsc->bpc = 16;
3334 			break;
3335 		default:
3336 			MISSING_CASE(sdp->db[17] & 0x7);
3337 			return -EINVAL;
3338 		}
3339 
3340 		vsc->content_type = sdp->db[18] & 0x7;
3341 	} else {
3342 		return -EINVAL;
3343 	}
3344 
3345 	return 0;
3346 }
3347 
3348 static int
intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe * drm_infoframe,const void * buffer,size_t size)3349 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3350 					   const void *buffer, size_t size)
3351 {
3352 	int ret;
3353 
3354 	const struct dp_sdp *sdp = buffer;
3355 
3356 	if (size < sizeof(struct dp_sdp))
3357 		return -EINVAL;
3358 
3359 	if (sdp->sdp_header.HB0 != 0)
3360 		return -EINVAL;
3361 
3362 	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3363 		return -EINVAL;
3364 
3365 	/*
3366 	 * Least Significant Eight Bits of (Data Byte Count – 1)
3367 	 * 1Dh (i.e., Data Byte Count = 30 bytes).
3368 	 */
3369 	if (sdp->sdp_header.HB2 != 0x1D)
3370 		return -EINVAL;
3371 
3372 	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3373 	if ((sdp->sdp_header.HB3 & 0x3) != 0)
3374 		return -EINVAL;
3375 
3376 	/* INFOFRAME SDP Version Number */
3377 	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3378 		return -EINVAL;
3379 
3380 	/* CTA Header Byte 2 (INFOFRAME Version Number) */
3381 	if (sdp->db[0] != 1)
3382 		return -EINVAL;
3383 
3384 	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3385 	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3386 		return -EINVAL;
3387 
3388 	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3389 					     HDMI_DRM_INFOFRAME_SIZE);
3390 
3391 	return ret;
3392 }
3393 
intel_read_dp_vsc_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_vsc_sdp * vsc)3394 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3395 				  struct intel_crtc_state *crtc_state,
3396 				  struct drm_dp_vsc_sdp *vsc)
3397 {
3398 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3399 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3400 	unsigned int type = DP_SDP_VSC;
3401 	struct dp_sdp sdp = {};
3402 	int ret;
3403 
3404 	/* When PSR is enabled, VSC SDP is handled by PSR routine */
3405 	if (crtc_state->has_psr)
3406 		return;
3407 
3408 	if ((crtc_state->infoframes.enable &
3409 	     intel_hdmi_infoframe_enable(type)) == 0)
3410 		return;
3411 
3412 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3413 
3414 	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3415 
3416 	if (ret)
3417 		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3418 }
3419 
intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct hdmi_drm_infoframe * drm_infoframe)3420 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3421 						     struct intel_crtc_state *crtc_state,
3422 						     struct hdmi_drm_infoframe *drm_infoframe)
3423 {
3424 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3425 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3426 	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3427 	struct dp_sdp sdp = {};
3428 	int ret;
3429 
3430 	if ((crtc_state->infoframes.enable &
3431 	    intel_hdmi_infoframe_enable(type)) == 0)
3432 		return;
3433 
3434 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3435 				 sizeof(sdp));
3436 
3437 	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3438 							 sizeof(sdp));
3439 
3440 	if (ret)
3441 		drm_dbg_kms(&dev_priv->drm,
3442 			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3443 }
3444 
intel_read_dp_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,unsigned int type)3445 void intel_read_dp_sdp(struct intel_encoder *encoder,
3446 		       struct intel_crtc_state *crtc_state,
3447 		       unsigned int type)
3448 {
3449 	switch (type) {
3450 	case DP_SDP_VSC:
3451 		intel_read_dp_vsc_sdp(encoder, crtc_state,
3452 				      &crtc_state->infoframes.vsc);
3453 		break;
3454 	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3455 		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3456 							 &crtc_state->infoframes.drm.drm);
3457 		break;
3458 	default:
3459 		MISSING_CASE(type);
3460 		break;
3461 	}
3462 }
3463 
intel_dp_autotest_link_training(struct intel_dp * intel_dp)3464 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3465 {
3466 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3467 	int status = 0;
3468 	int test_link_rate;
3469 	u8 test_lane_count, test_link_bw;
3470 	/* (DP CTS 1.2)
3471 	 * 4.3.1.11
3472 	 */
3473 	/* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3474 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3475 				   &test_lane_count);
3476 
3477 	if (status <= 0) {
3478 		drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3479 		return DP_TEST_NAK;
3480 	}
3481 	test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3482 
3483 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3484 				   &test_link_bw);
3485 	if (status <= 0) {
3486 		drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3487 		return DP_TEST_NAK;
3488 	}
3489 	test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3490 
3491 	/* Validate the requested link rate and lane count */
3492 	if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3493 					test_lane_count))
3494 		return DP_TEST_NAK;
3495 
3496 	intel_dp->compliance.test_lane_count = test_lane_count;
3497 	intel_dp->compliance.test_link_rate = test_link_rate;
3498 
3499 	return DP_TEST_ACK;
3500 }
3501 
intel_dp_autotest_video_pattern(struct intel_dp * intel_dp)3502 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3503 {
3504 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3505 	u8 test_pattern;
3506 	u8 test_misc;
3507 	__be16 h_width, v_height;
3508 	int status = 0;
3509 
3510 	/* Read the TEST_PATTERN (DP CTS 3.1.5) */
3511 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3512 				   &test_pattern);
3513 	if (status <= 0) {
3514 		drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3515 		return DP_TEST_NAK;
3516 	}
3517 	if (test_pattern != DP_COLOR_RAMP)
3518 		return DP_TEST_NAK;
3519 
3520 	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3521 				  &h_width, 2);
3522 	if (status <= 0) {
3523 		drm_dbg_kms(&i915->drm, "H Width read failed\n");
3524 		return DP_TEST_NAK;
3525 	}
3526 
3527 	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3528 				  &v_height, 2);
3529 	if (status <= 0) {
3530 		drm_dbg_kms(&i915->drm, "V Height read failed\n");
3531 		return DP_TEST_NAK;
3532 	}
3533 
3534 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3535 				   &test_misc);
3536 	if (status <= 0) {
3537 		drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3538 		return DP_TEST_NAK;
3539 	}
3540 	if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3541 		return DP_TEST_NAK;
3542 	if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3543 		return DP_TEST_NAK;
3544 	switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3545 	case DP_TEST_BIT_DEPTH_6:
3546 		intel_dp->compliance.test_data.bpc = 6;
3547 		break;
3548 	case DP_TEST_BIT_DEPTH_8:
3549 		intel_dp->compliance.test_data.bpc = 8;
3550 		break;
3551 	default:
3552 		return DP_TEST_NAK;
3553 	}
3554 
3555 	intel_dp->compliance.test_data.video_pattern = test_pattern;
3556 	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3557 	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3558 	/* Set test active flag here so userspace doesn't interrupt things */
3559 	intel_dp->compliance.test_active = true;
3560 
3561 	return DP_TEST_ACK;
3562 }
3563 
intel_dp_autotest_edid(struct intel_dp * intel_dp)3564 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3565 {
3566 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3567 	u8 test_result = DP_TEST_ACK;
3568 	struct intel_connector *intel_connector = intel_dp->attached_connector;
3569 	struct drm_connector *connector = &intel_connector->base;
3570 
3571 	if (intel_connector->detect_edid == NULL ||
3572 	    connector->edid_corrupt ||
3573 	    intel_dp->aux.i2c_defer_count > 6) {
3574 		/* Check EDID read for NACKs, DEFERs and corruption
3575 		 * (DP CTS 1.2 Core r1.1)
3576 		 *    4.2.2.4 : Failed EDID read, I2C_NAK
3577 		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
3578 		 *    4.2.2.6 : EDID corruption detected
3579 		 * Use failsafe mode for all cases
3580 		 */
3581 		if (intel_dp->aux.i2c_nack_count > 0 ||
3582 			intel_dp->aux.i2c_defer_count > 0)
3583 			drm_dbg_kms(&i915->drm,
3584 				    "EDID read had %d NACKs, %d DEFERs\n",
3585 				    intel_dp->aux.i2c_nack_count,
3586 				    intel_dp->aux.i2c_defer_count);
3587 		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3588 	} else {
3589 		struct edid *block = intel_connector->detect_edid;
3590 
3591 		/* We have to write the checksum
3592 		 * of the last block read
3593 		 */
3594 		block += intel_connector->detect_edid->extensions;
3595 
3596 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3597 				       block->checksum) <= 0)
3598 			drm_dbg_kms(&i915->drm,
3599 				    "Failed to write EDID checksum\n");
3600 
3601 		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3602 		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3603 	}
3604 
3605 	/* Set test active flag here so userspace doesn't interrupt things */
3606 	intel_dp->compliance.test_active = true;
3607 
3608 	return test_result;
3609 }
3610 
intel_dp_phy_pattern_update(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3611 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3612 					const struct intel_crtc_state *crtc_state)
3613 {
3614 	struct drm_i915_private *dev_priv =
3615 			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3616 	struct drm_dp_phy_test_params *data =
3617 			&intel_dp->compliance.test_data.phytest;
3618 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3619 	enum pipe pipe = crtc->pipe;
3620 	u32 pattern_val;
3621 
3622 	switch (data->phy_pattern) {
3623 	case DP_PHY_TEST_PATTERN_NONE:
3624 		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3625 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3626 		break;
3627 	case DP_PHY_TEST_PATTERN_D10_2:
3628 		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3629 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3630 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3631 		break;
3632 	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3633 		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3634 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3635 			       DDI_DP_COMP_CTL_ENABLE |
3636 			       DDI_DP_COMP_CTL_SCRAMBLED_0);
3637 		break;
3638 	case DP_PHY_TEST_PATTERN_PRBS7:
3639 		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3640 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3641 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3642 		break;
3643 	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3644 		/*
3645 		 * FIXME: Ideally pattern should come from DPCD 0x250. As
3646 		 * current firmware of DPR-100 could not set it, so hardcoding
3647 		 * now for complaince test.
3648 		 */
3649 		drm_dbg_kms(&dev_priv->drm,
3650 			    "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3651 		pattern_val = 0x3e0f83e0;
3652 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3653 		pattern_val = 0x0f83e0f8;
3654 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3655 		pattern_val = 0x0000f83e;
3656 		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3657 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3658 			       DDI_DP_COMP_CTL_ENABLE |
3659 			       DDI_DP_COMP_CTL_CUSTOM80);
3660 		break;
3661 	case DP_PHY_TEST_PATTERN_CP2520:
3662 		/*
3663 		 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3664 		 * current firmware of DPR-100 could not set it, so hardcoding
3665 		 * now for complaince test.
3666 		 */
3667 		drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3668 		pattern_val = 0xFB;
3669 		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3670 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3671 			       pattern_val);
3672 		break;
3673 	default:
3674 		WARN(1, "Invalid Phy Test Pattern\n");
3675 	}
3676 }
3677 
intel_dp_process_phy_request(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3678 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3679 					 const struct intel_crtc_state *crtc_state)
3680 {
3681 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3682 	struct drm_dp_phy_test_params *data =
3683 		&intel_dp->compliance.test_data.phytest;
3684 	u8 link_status[DP_LINK_STATUS_SIZE];
3685 
3686 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3687 					     link_status) < 0) {
3688 		drm_dbg_kms(&i915->drm, "failed to get link status\n");
3689 		return;
3690 	}
3691 
3692 	/* retrieve vswing & pre-emphasis setting */
3693 	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3694 				  link_status);
3695 
3696 	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3697 
3698 	intel_dp_phy_pattern_update(intel_dp, crtc_state);
3699 
3700 	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3701 			  intel_dp->train_set, crtc_state->lane_count);
3702 
3703 	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3704 				    link_status[DP_DPCD_REV]);
3705 }
3706 
intel_dp_autotest_phy_pattern(struct intel_dp * intel_dp)3707 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3708 {
3709 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3710 	struct drm_dp_phy_test_params *data =
3711 		&intel_dp->compliance.test_data.phytest;
3712 
3713 	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3714 		drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3715 		return DP_TEST_NAK;
3716 	}
3717 
3718 	/* Set test active flag here so userspace doesn't interrupt things */
3719 	intel_dp->compliance.test_active = true;
3720 
3721 	return DP_TEST_ACK;
3722 }
3723 
intel_dp_handle_test_request(struct intel_dp * intel_dp)3724 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3725 {
3726 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3727 	u8 response = DP_TEST_NAK;
3728 	u8 request = 0;
3729 	int status;
3730 
3731 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3732 	if (status <= 0) {
3733 		drm_dbg_kms(&i915->drm,
3734 			    "Could not read test request from sink\n");
3735 		goto update_status;
3736 	}
3737 
3738 	switch (request) {
3739 	case DP_TEST_LINK_TRAINING:
3740 		drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3741 		response = intel_dp_autotest_link_training(intel_dp);
3742 		break;
3743 	case DP_TEST_LINK_VIDEO_PATTERN:
3744 		drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3745 		response = intel_dp_autotest_video_pattern(intel_dp);
3746 		break;
3747 	case DP_TEST_LINK_EDID_READ:
3748 		drm_dbg_kms(&i915->drm, "EDID test requested\n");
3749 		response = intel_dp_autotest_edid(intel_dp);
3750 		break;
3751 	case DP_TEST_LINK_PHY_TEST_PATTERN:
3752 		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3753 		response = intel_dp_autotest_phy_pattern(intel_dp);
3754 		break;
3755 	default:
3756 		drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3757 			    request);
3758 		break;
3759 	}
3760 
3761 	if (response & DP_TEST_ACK)
3762 		intel_dp->compliance.test_type = request;
3763 
3764 update_status:
3765 	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3766 	if (status <= 0)
3767 		drm_dbg_kms(&i915->drm,
3768 			    "Could not write test response to sink\n");
3769 }
3770 
intel_dp_link_ok(struct intel_dp * intel_dp,u8 link_status[DP_LINK_STATUS_SIZE])3771 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3772 			     u8 link_status[DP_LINK_STATUS_SIZE])
3773 {
3774 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3775 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3776 	bool uhbr = intel_dp->link_rate >= 1000000;
3777 	bool ok;
3778 
3779 	if (uhbr)
3780 		ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3781 							  intel_dp->lane_count);
3782 	else
3783 		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3784 
3785 	if (ok)
3786 		return true;
3787 
3788 	intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3789 	drm_dbg_kms(&i915->drm,
3790 		    "[ENCODER:%d:%s] %s link not ok, retraining\n",
3791 		    encoder->base.base.id, encoder->base.name,
3792 		    uhbr ? "128b/132b" : "8b/10b");
3793 
3794 	return false;
3795 }
3796 
3797 static void
intel_dp_mst_hpd_irq(struct intel_dp * intel_dp,u8 * esi,u8 * ack)3798 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3799 {
3800 	bool handled = false;
3801 
3802 	drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3803 	if (handled)
3804 		ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3805 
3806 	if (esi[1] & DP_CP_IRQ) {
3807 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3808 		ack[1] |= DP_CP_IRQ;
3809 	}
3810 }
3811 
intel_dp_mst_link_status(struct intel_dp * intel_dp)3812 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3813 {
3814 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3815 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3816 	u8 link_status[DP_LINK_STATUS_SIZE] = {};
3817 	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3818 
3819 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3820 			     esi_link_status_size) != esi_link_status_size) {
3821 		drm_err(&i915->drm,
3822 			"[ENCODER:%d:%s] Failed to read link status\n",
3823 			encoder->base.base.id, encoder->base.name);
3824 		return false;
3825 	}
3826 
3827 	return intel_dp_link_ok(intel_dp, link_status);
3828 }
3829 
3830 /**
3831  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3832  * @intel_dp: Intel DP struct
3833  *
3834  * Read any pending MST interrupts, call MST core to handle these and ack the
3835  * interrupts. Check if the main and AUX link state is ok.
3836  *
3837  * Returns:
3838  * - %true if pending interrupts were serviced (or no interrupts were
3839  *   pending) w/o detecting an error condition.
3840  * - %false if an error condition - like AUX failure or a loss of link - is
3841  *   detected, which needs servicing from the hotplug work.
3842  */
3843 static bool
intel_dp_check_mst_status(struct intel_dp * intel_dp)3844 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3845 {
3846 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3847 	bool link_ok = true;
3848 
3849 	drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3850 
3851 	for (;;) {
3852 		u8 esi[4] = {};
3853 		u8 ack[4] = {};
3854 
3855 		if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3856 			drm_dbg_kms(&i915->drm,
3857 				    "failed to get ESI - device may have failed\n");
3858 			link_ok = false;
3859 
3860 			break;
3861 		}
3862 
3863 		drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3864 
3865 		if (intel_dp->active_mst_links > 0 && link_ok &&
3866 		    esi[3] & LINK_STATUS_CHANGED) {
3867 			if (!intel_dp_mst_link_status(intel_dp))
3868 				link_ok = false;
3869 			ack[3] |= LINK_STATUS_CHANGED;
3870 		}
3871 
3872 		intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3873 
3874 		if (!memchr_inv(ack, 0, sizeof(ack)))
3875 			break;
3876 
3877 		if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3878 			drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3879 	}
3880 
3881 	return link_ok;
3882 }
3883 
3884 static void
intel_dp_handle_hdmi_link_status_change(struct intel_dp * intel_dp)3885 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3886 {
3887 	bool is_active;
3888 	u8 buf = 0;
3889 
3890 	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3891 	if (intel_dp->frl.is_trained && !is_active) {
3892 		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3893 			return;
3894 
3895 		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3896 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3897 			return;
3898 
3899 		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3900 
3901 		intel_dp->frl.is_trained = false;
3902 
3903 		/* Restart FRL training or fall back to TMDS mode */
3904 		intel_dp_check_frl_training(intel_dp);
3905 	}
3906 }
3907 
3908 static bool
intel_dp_needs_link_retrain(struct intel_dp * intel_dp)3909 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3910 {
3911 	u8 link_status[DP_LINK_STATUS_SIZE];
3912 
3913 	if (!intel_dp->link_trained)
3914 		return false;
3915 
3916 	/*
3917 	 * While PSR source HW is enabled, it will control main-link sending
3918 	 * frames, enabling and disabling it so trying to do a retrain will fail
3919 	 * as the link would or not be on or it could mix training patterns
3920 	 * and frame data at the same time causing retrain to fail.
3921 	 * Also when exiting PSR, HW will retrain the link anyways fixing
3922 	 * any link status error.
3923 	 */
3924 	if (intel_psr_enabled(intel_dp))
3925 		return false;
3926 
3927 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3928 					     link_status) < 0)
3929 		return false;
3930 
3931 	/*
3932 	 * Validate the cached values of intel_dp->link_rate and
3933 	 * intel_dp->lane_count before attempting to retrain.
3934 	 *
3935 	 * FIXME would be nice to user the crtc state here, but since
3936 	 * we need to call this from the short HPD handler that seems
3937 	 * a bit hard.
3938 	 */
3939 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3940 					intel_dp->lane_count))
3941 		return false;
3942 
3943 	/* Retrain if link not ok */
3944 	return !intel_dp_link_ok(intel_dp, link_status);
3945 }
3946 
intel_dp_has_connector(struct intel_dp * intel_dp,const struct drm_connector_state * conn_state)3947 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3948 				   const struct drm_connector_state *conn_state)
3949 {
3950 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3951 	struct intel_encoder *encoder;
3952 	enum pipe pipe;
3953 
3954 	if (!conn_state->best_encoder)
3955 		return false;
3956 
3957 	/* SST */
3958 	encoder = &dp_to_dig_port(intel_dp)->base;
3959 	if (conn_state->best_encoder == &encoder->base)
3960 		return true;
3961 
3962 	/* MST */
3963 	for_each_pipe(i915, pipe) {
3964 		encoder = &intel_dp->mst_encoders[pipe]->base;
3965 		if (conn_state->best_encoder == &encoder->base)
3966 			return true;
3967 	}
3968 
3969 	return false;
3970 }
3971 
intel_dp_prep_link_retrain(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask)3972 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3973 				      struct drm_modeset_acquire_ctx *ctx,
3974 				      u8 *pipe_mask)
3975 {
3976 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3977 	struct drm_connector_list_iter conn_iter;
3978 	struct intel_connector *connector;
3979 	int ret = 0;
3980 
3981 	*pipe_mask = 0;
3982 
3983 	if (!intel_dp_needs_link_retrain(intel_dp))
3984 		return 0;
3985 
3986 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3987 	for_each_intel_connector_iter(connector, &conn_iter) {
3988 		struct drm_connector_state *conn_state =
3989 			connector->base.state;
3990 		struct intel_crtc_state *crtc_state;
3991 		struct intel_crtc *crtc;
3992 
3993 		if (!intel_dp_has_connector(intel_dp, conn_state))
3994 			continue;
3995 
3996 		crtc = to_intel_crtc(conn_state->crtc);
3997 		if (!crtc)
3998 			continue;
3999 
4000 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4001 		if (ret)
4002 			break;
4003 
4004 		crtc_state = to_intel_crtc_state(crtc->base.state);
4005 
4006 		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4007 
4008 		if (!crtc_state->hw.active)
4009 			continue;
4010 
4011 		if (conn_state->commit &&
4012 		    !try_wait_for_completion(&conn_state->commit->hw_done))
4013 			continue;
4014 
4015 		*pipe_mask |= BIT(crtc->pipe);
4016 	}
4017 	drm_connector_list_iter_end(&conn_iter);
4018 
4019 	if (!intel_dp_needs_link_retrain(intel_dp))
4020 		*pipe_mask = 0;
4021 
4022 	return ret;
4023 }
4024 
intel_dp_is_connected(struct intel_dp * intel_dp)4025 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4026 {
4027 	struct intel_connector *connector = intel_dp->attached_connector;
4028 
4029 	return connector->base.status == connector_status_connected ||
4030 		intel_dp->is_mst;
4031 }
4032 
intel_dp_retrain_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4033 int intel_dp_retrain_link(struct intel_encoder *encoder,
4034 			  struct drm_modeset_acquire_ctx *ctx)
4035 {
4036 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4037 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4038 	struct intel_crtc *crtc;
4039 	u8 pipe_mask;
4040 	int ret;
4041 
4042 	if (!intel_dp_is_connected(intel_dp))
4043 		return 0;
4044 
4045 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4046 			       ctx);
4047 	if (ret)
4048 		return ret;
4049 
4050 	ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4051 	if (ret)
4052 		return ret;
4053 
4054 	if (pipe_mask == 0)
4055 		return 0;
4056 
4057 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4058 		    encoder->base.base.id, encoder->base.name);
4059 
4060 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4061 		const struct intel_crtc_state *crtc_state =
4062 			to_intel_crtc_state(crtc->base.state);
4063 
4064 		/* Suppress underruns caused by re-training */
4065 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4066 		if (crtc_state->has_pch_encoder)
4067 			intel_set_pch_fifo_underrun_reporting(dev_priv,
4068 							      intel_crtc_pch_transcoder(crtc), false);
4069 	}
4070 
4071 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4072 		const struct intel_crtc_state *crtc_state =
4073 			to_intel_crtc_state(crtc->base.state);
4074 
4075 		/* retrain on the MST master transcoder */
4076 		if (DISPLAY_VER(dev_priv) >= 12 &&
4077 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4078 		    !intel_dp_mst_is_master_trans(crtc_state))
4079 			continue;
4080 
4081 		intel_dp_check_frl_training(intel_dp);
4082 		intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4083 		intel_dp_start_link_train(intel_dp, crtc_state);
4084 		intel_dp_stop_link_train(intel_dp, crtc_state);
4085 		break;
4086 	}
4087 
4088 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4089 		const struct intel_crtc_state *crtc_state =
4090 			to_intel_crtc_state(crtc->base.state);
4091 
4092 		/* Keep underrun reporting disabled until things are stable */
4093 		intel_crtc_wait_for_next_vblank(crtc);
4094 
4095 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4096 		if (crtc_state->has_pch_encoder)
4097 			intel_set_pch_fifo_underrun_reporting(dev_priv,
4098 							      intel_crtc_pch_transcoder(crtc), true);
4099 	}
4100 
4101 	return 0;
4102 }
4103 
intel_dp_prep_phy_test(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask)4104 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4105 				  struct drm_modeset_acquire_ctx *ctx,
4106 				  u8 *pipe_mask)
4107 {
4108 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4109 	struct drm_connector_list_iter conn_iter;
4110 	struct intel_connector *connector;
4111 	int ret = 0;
4112 
4113 	*pipe_mask = 0;
4114 
4115 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4116 	for_each_intel_connector_iter(connector, &conn_iter) {
4117 		struct drm_connector_state *conn_state =
4118 			connector->base.state;
4119 		struct intel_crtc_state *crtc_state;
4120 		struct intel_crtc *crtc;
4121 
4122 		if (!intel_dp_has_connector(intel_dp, conn_state))
4123 			continue;
4124 
4125 		crtc = to_intel_crtc(conn_state->crtc);
4126 		if (!crtc)
4127 			continue;
4128 
4129 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4130 		if (ret)
4131 			break;
4132 
4133 		crtc_state = to_intel_crtc_state(crtc->base.state);
4134 
4135 		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4136 
4137 		if (!crtc_state->hw.active)
4138 			continue;
4139 
4140 		if (conn_state->commit &&
4141 		    !try_wait_for_completion(&conn_state->commit->hw_done))
4142 			continue;
4143 
4144 		*pipe_mask |= BIT(crtc->pipe);
4145 	}
4146 	drm_connector_list_iter_end(&conn_iter);
4147 
4148 	return ret;
4149 }
4150 
intel_dp_do_phy_test(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4151 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4152 				struct drm_modeset_acquire_ctx *ctx)
4153 {
4154 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4155 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4156 	struct intel_crtc *crtc;
4157 	u8 pipe_mask;
4158 	int ret;
4159 
4160 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4161 			       ctx);
4162 	if (ret)
4163 		return ret;
4164 
4165 	ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4166 	if (ret)
4167 		return ret;
4168 
4169 	if (pipe_mask == 0)
4170 		return 0;
4171 
4172 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4173 		    encoder->base.base.id, encoder->base.name);
4174 
4175 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4176 		const struct intel_crtc_state *crtc_state =
4177 			to_intel_crtc_state(crtc->base.state);
4178 
4179 		/* test on the MST master transcoder */
4180 		if (DISPLAY_VER(dev_priv) >= 12 &&
4181 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4182 		    !intel_dp_mst_is_master_trans(crtc_state))
4183 			continue;
4184 
4185 		intel_dp_process_phy_request(intel_dp, crtc_state);
4186 		break;
4187 	}
4188 
4189 	return 0;
4190 }
4191 
intel_dp_phy_test(struct intel_encoder * encoder)4192 void intel_dp_phy_test(struct intel_encoder *encoder)
4193 {
4194 	struct drm_modeset_acquire_ctx ctx;
4195 	int ret;
4196 
4197 	drm_modeset_acquire_init(&ctx, 0);
4198 
4199 	for (;;) {
4200 		ret = intel_dp_do_phy_test(encoder, &ctx);
4201 
4202 		if (ret == -EDEADLK) {
4203 			drm_modeset_backoff(&ctx);
4204 			continue;
4205 		}
4206 
4207 		break;
4208 	}
4209 
4210 	drm_modeset_drop_locks(&ctx);
4211 	drm_modeset_acquire_fini(&ctx);
4212 	drm_WARN(encoder->base.dev, ret,
4213 		 "Acquiring modeset locks failed with %i\n", ret);
4214 }
4215 
intel_dp_check_device_service_irq(struct intel_dp * intel_dp)4216 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4217 {
4218 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4219 	u8 val;
4220 
4221 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4222 		return;
4223 
4224 	if (drm_dp_dpcd_readb(&intel_dp->aux,
4225 			      DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4226 		return;
4227 
4228 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4229 
4230 	if (val & DP_AUTOMATED_TEST_REQUEST)
4231 		intel_dp_handle_test_request(intel_dp);
4232 
4233 	if (val & DP_CP_IRQ)
4234 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4235 
4236 	if (val & DP_SINK_SPECIFIC_IRQ)
4237 		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4238 }
4239 
intel_dp_check_link_service_irq(struct intel_dp * intel_dp)4240 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4241 {
4242 	u8 val;
4243 
4244 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4245 		return;
4246 
4247 	if (drm_dp_dpcd_readb(&intel_dp->aux,
4248 			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4249 		return;
4250 
4251 	if (drm_dp_dpcd_writeb(&intel_dp->aux,
4252 			       DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4253 		return;
4254 
4255 	if (val & HDMI_LINK_STATUS_CHANGED)
4256 		intel_dp_handle_hdmi_link_status_change(intel_dp);
4257 }
4258 
4259 /*
4260  * According to DP spec
4261  * 5.1.2:
4262  *  1. Read DPCD
4263  *  2. Configure link according to Receiver Capabilities
4264  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4265  *  4. Check link status on receipt of hot-plug interrupt
4266  *
4267  * intel_dp_short_pulse -  handles short pulse interrupts
4268  * when full detection is not required.
4269  * Returns %true if short pulse is handled and full detection
4270  * is NOT required and %false otherwise.
4271  */
4272 static bool
intel_dp_short_pulse(struct intel_dp * intel_dp)4273 intel_dp_short_pulse(struct intel_dp *intel_dp)
4274 {
4275 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4276 	u8 old_sink_count = intel_dp->sink_count;
4277 	bool ret;
4278 
4279 	/*
4280 	 * Clearing compliance test variables to allow capturing
4281 	 * of values for next automated test request.
4282 	 */
4283 	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4284 
4285 	/*
4286 	 * Now read the DPCD to see if it's actually running
4287 	 * If the current value of sink count doesn't match with
4288 	 * the value that was stored earlier or dpcd read failed
4289 	 * we need to do full detection
4290 	 */
4291 	ret = intel_dp_get_dpcd(intel_dp);
4292 
4293 	if ((old_sink_count != intel_dp->sink_count) || !ret) {
4294 		/* No need to proceed if we are going to do full detect */
4295 		return false;
4296 	}
4297 
4298 	intel_dp_check_device_service_irq(intel_dp);
4299 	intel_dp_check_link_service_irq(intel_dp);
4300 
4301 	/* Handle CEC interrupts, if any */
4302 	drm_dp_cec_irq(&intel_dp->aux);
4303 
4304 	/* defer to the hotplug work for link retraining if needed */
4305 	if (intel_dp_needs_link_retrain(intel_dp))
4306 		return false;
4307 
4308 	intel_psr_short_pulse(intel_dp);
4309 
4310 	switch (intel_dp->compliance.test_type) {
4311 	case DP_TEST_LINK_TRAINING:
4312 		drm_dbg_kms(&dev_priv->drm,
4313 			    "Link Training Compliance Test requested\n");
4314 		/* Send a Hotplug Uevent to userspace to start modeset */
4315 		drm_kms_helper_hotplug_event(&dev_priv->drm);
4316 		break;
4317 	case DP_TEST_LINK_PHY_TEST_PATTERN:
4318 		drm_dbg_kms(&dev_priv->drm,
4319 			    "PHY test pattern Compliance Test requested\n");
4320 		/*
4321 		 * Schedule long hpd to do the test
4322 		 *
4323 		 * FIXME get rid of the ad-hoc phy test modeset code
4324 		 * and properly incorporate it into the normal modeset.
4325 		 */
4326 		return false;
4327 	}
4328 
4329 	return true;
4330 }
4331 
4332 /* XXX this is probably wrong for multiple downstream ports */
4333 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)4334 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4335 {
4336 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4337 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4338 	u8 *dpcd = intel_dp->dpcd;
4339 	u8 type;
4340 
4341 	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4342 		return connector_status_connected;
4343 
4344 	lspcon_resume(dig_port);
4345 
4346 	if (!intel_dp_get_dpcd(intel_dp))
4347 		return connector_status_disconnected;
4348 
4349 	/* if there's no downstream port, we're done */
4350 	if (!drm_dp_is_branch(dpcd))
4351 		return connector_status_connected;
4352 
4353 	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4354 	if (intel_dp_has_sink_count(intel_dp) &&
4355 	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4356 		return intel_dp->sink_count ?
4357 		connector_status_connected : connector_status_disconnected;
4358 	}
4359 
4360 	if (intel_dp_can_mst(intel_dp))
4361 		return connector_status_connected;
4362 
4363 	/* If no HPD, poke DDC gently */
4364 	if (drm_probe_ddc(&intel_dp->aux.ddc))
4365 		return connector_status_connected;
4366 
4367 	/* Well we tried, say unknown for unreliable port types */
4368 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4369 		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4370 		if (type == DP_DS_PORT_TYPE_VGA ||
4371 		    type == DP_DS_PORT_TYPE_NON_EDID)
4372 			return connector_status_unknown;
4373 	} else {
4374 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4375 			DP_DWN_STRM_PORT_TYPE_MASK;
4376 		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4377 		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
4378 			return connector_status_unknown;
4379 	}
4380 
4381 	/* Anything else is out of spec, warn and ignore */
4382 	drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4383 	return connector_status_disconnected;
4384 }
4385 
4386 static enum drm_connector_status
edp_detect(struct intel_dp * intel_dp)4387 edp_detect(struct intel_dp *intel_dp)
4388 {
4389 	return connector_status_connected;
4390 }
4391 
4392 /*
4393  * intel_digital_port_connected - is the specified port connected?
4394  * @encoder: intel_encoder
4395  *
4396  * In cases where there's a connector physically connected but it can't be used
4397  * by our hardware we also return false, since the rest of the driver should
4398  * pretty much treat the port as disconnected. This is relevant for type-C
4399  * (starting on ICL) where there's ownership involved.
4400  *
4401  * Return %true if port is connected, %false otherwise.
4402  */
intel_digital_port_connected(struct intel_encoder * encoder)4403 bool intel_digital_port_connected(struct intel_encoder *encoder)
4404 {
4405 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4406 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4407 	bool is_connected = false;
4408 	intel_wakeref_t wakeref;
4409 
4410 	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4411 		is_connected = dig_port->connected(encoder);
4412 
4413 	return is_connected;
4414 }
4415 
4416 static struct edid *
intel_dp_get_edid(struct intel_dp * intel_dp)4417 intel_dp_get_edid(struct intel_dp *intel_dp)
4418 {
4419 	struct intel_connector *intel_connector = intel_dp->attached_connector;
4420 
4421 	/* use cached edid if we have one */
4422 	if (intel_connector->edid) {
4423 		/* invalid edid */
4424 		if (IS_ERR(intel_connector->edid))
4425 			return NULL;
4426 
4427 		return drm_edid_duplicate(intel_connector->edid);
4428 	} else
4429 		return drm_get_edid(&intel_connector->base,
4430 				    &intel_dp->aux.ddc);
4431 }
4432 
4433 static void
intel_dp_update_dfp(struct intel_dp * intel_dp,const struct edid * edid)4434 intel_dp_update_dfp(struct intel_dp *intel_dp,
4435 		    const struct edid *edid)
4436 {
4437 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4438 	struct intel_connector *connector = intel_dp->attached_connector;
4439 
4440 	intel_dp->dfp.max_bpc =
4441 		drm_dp_downstream_max_bpc(intel_dp->dpcd,
4442 					  intel_dp->downstream_ports, edid);
4443 
4444 	intel_dp->dfp.max_dotclock =
4445 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4446 					       intel_dp->downstream_ports);
4447 
4448 	intel_dp->dfp.min_tmds_clock =
4449 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4450 						 intel_dp->downstream_ports,
4451 						 edid);
4452 	intel_dp->dfp.max_tmds_clock =
4453 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4454 						 intel_dp->downstream_ports,
4455 						 edid);
4456 
4457 	intel_dp->dfp.pcon_max_frl_bw =
4458 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4459 					   intel_dp->downstream_ports);
4460 
4461 	drm_dbg_kms(&i915->drm,
4462 		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4463 		    connector->base.base.id, connector->base.name,
4464 		    intel_dp->dfp.max_bpc,
4465 		    intel_dp->dfp.max_dotclock,
4466 		    intel_dp->dfp.min_tmds_clock,
4467 		    intel_dp->dfp.max_tmds_clock,
4468 		    intel_dp->dfp.pcon_max_frl_bw);
4469 
4470 	intel_dp_get_pcon_dsc_cap(intel_dp);
4471 }
4472 
4473 static void
intel_dp_update_420(struct intel_dp * intel_dp)4474 intel_dp_update_420(struct intel_dp *intel_dp)
4475 {
4476 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4477 	struct intel_connector *connector = intel_dp->attached_connector;
4478 	bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4479 
4480 	/* No YCbCr output support on gmch platforms */
4481 	if (HAS_GMCH(i915))
4482 		return;
4483 
4484 	/*
4485 	 * ILK doesn't seem capable of DP YCbCr output. The
4486 	 * displayed image is severly corrupted. SNB+ is fine.
4487 	 */
4488 	if (IS_IRONLAKE(i915))
4489 		return;
4490 
4491 	is_branch = drm_dp_is_branch(intel_dp->dpcd);
4492 	ycbcr_420_passthrough =
4493 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4494 						  intel_dp->downstream_ports);
4495 	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4496 	ycbcr_444_to_420 =
4497 		dp_to_dig_port(intel_dp)->lspcon.active ||
4498 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4499 							intel_dp->downstream_ports);
4500 	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4501 								 intel_dp->downstream_ports,
4502 								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4503 
4504 	if (DISPLAY_VER(i915) >= 11) {
4505 		/* Let PCON convert from RGB->YCbCr if possible */
4506 		if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4507 			intel_dp->dfp.rgb_to_ycbcr = true;
4508 			intel_dp->dfp.ycbcr_444_to_420 = true;
4509 			connector->base.ycbcr_420_allowed = true;
4510 		} else {
4511 		/* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4512 			intel_dp->dfp.ycbcr_444_to_420 =
4513 				ycbcr_444_to_420 && !ycbcr_420_passthrough;
4514 
4515 			connector->base.ycbcr_420_allowed =
4516 				!is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4517 		}
4518 	} else {
4519 		/* 4:4:4->4:2:0 conversion is the only way */
4520 		intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4521 
4522 		connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4523 	}
4524 
4525 	drm_dbg_kms(&i915->drm,
4526 		    "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4527 		    connector->base.base.id, connector->base.name,
4528 		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4529 		    str_yes_no(connector->base.ycbcr_420_allowed),
4530 		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4531 }
4532 
4533 static void
intel_dp_set_edid(struct intel_dp * intel_dp)4534 intel_dp_set_edid(struct intel_dp *intel_dp)
4535 {
4536 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4537 	struct intel_connector *connector = intel_dp->attached_connector;
4538 	struct edid *edid;
4539 	bool vrr_capable;
4540 
4541 	intel_dp_unset_edid(intel_dp);
4542 	edid = intel_dp_get_edid(intel_dp);
4543 	connector->detect_edid = edid;
4544 
4545 	vrr_capable = intel_vrr_is_capable(connector);
4546 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4547 		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4548 	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4549 
4550 	intel_dp_update_dfp(intel_dp, edid);
4551 	intel_dp_update_420(intel_dp);
4552 
4553 	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4554 		intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4555 		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4556 	}
4557 
4558 	drm_dp_cec_set_edid(&intel_dp->aux, edid);
4559 }
4560 
4561 static void
intel_dp_unset_edid(struct intel_dp * intel_dp)4562 intel_dp_unset_edid(struct intel_dp *intel_dp)
4563 {
4564 	struct intel_connector *connector = intel_dp->attached_connector;
4565 
4566 	drm_dp_cec_unset_edid(&intel_dp->aux);
4567 	kfree(connector->detect_edid);
4568 	connector->detect_edid = NULL;
4569 
4570 	intel_dp->has_hdmi_sink = false;
4571 	intel_dp->has_audio = false;
4572 
4573 	intel_dp->dfp.max_bpc = 0;
4574 	intel_dp->dfp.max_dotclock = 0;
4575 	intel_dp->dfp.min_tmds_clock = 0;
4576 	intel_dp->dfp.max_tmds_clock = 0;
4577 
4578 	intel_dp->dfp.pcon_max_frl_bw = 0;
4579 
4580 	intel_dp->dfp.ycbcr_444_to_420 = false;
4581 	connector->base.ycbcr_420_allowed = false;
4582 
4583 	drm_connector_set_vrr_capable_property(&connector->base,
4584 					       false);
4585 }
4586 
4587 static int
intel_dp_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)4588 intel_dp_detect(struct drm_connector *connector,
4589 		struct drm_modeset_acquire_ctx *ctx,
4590 		bool force)
4591 {
4592 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
4593 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4594 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4595 	struct intel_encoder *encoder = &dig_port->base;
4596 	enum drm_connector_status status;
4597 
4598 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4599 		    connector->base.id, connector->name);
4600 	drm_WARN_ON(&dev_priv->drm,
4601 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4602 
4603 	if (!INTEL_DISPLAY_ENABLED(dev_priv))
4604 		return connector_status_disconnected;
4605 
4606 	/* Can't disconnect eDP */
4607 	if (intel_dp_is_edp(intel_dp))
4608 		status = edp_detect(intel_dp);
4609 	else if (intel_digital_port_connected(encoder))
4610 		status = intel_dp_detect_dpcd(intel_dp);
4611 	else
4612 		status = connector_status_disconnected;
4613 
4614 	if (status == connector_status_disconnected) {
4615 		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4616 		memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4617 
4618 		if (intel_dp->is_mst) {
4619 			drm_dbg_kms(&dev_priv->drm,
4620 				    "MST device may have disappeared %d vs %d\n",
4621 				    intel_dp->is_mst,
4622 				    intel_dp->mst_mgr.mst_state);
4623 			intel_dp->is_mst = false;
4624 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4625 							intel_dp->is_mst);
4626 		}
4627 
4628 		goto out;
4629 	}
4630 
4631 	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4632 	if (DISPLAY_VER(dev_priv) >= 11)
4633 		intel_dp_get_dsc_sink_cap(intel_dp);
4634 
4635 	intel_dp_configure_mst(intel_dp);
4636 
4637 	/*
4638 	 * TODO: Reset link params when switching to MST mode, until MST
4639 	 * supports link training fallback params.
4640 	 */
4641 	if (intel_dp->reset_link_params || intel_dp->is_mst) {
4642 		intel_dp_reset_max_link_params(intel_dp);
4643 		intel_dp->reset_link_params = false;
4644 	}
4645 
4646 	intel_dp_print_rates(intel_dp);
4647 
4648 	if (intel_dp->is_mst) {
4649 		/*
4650 		 * If we are in MST mode then this connector
4651 		 * won't appear connected or have anything
4652 		 * with EDID on it
4653 		 */
4654 		status = connector_status_disconnected;
4655 		goto out;
4656 	}
4657 
4658 	/*
4659 	 * Some external monitors do not signal loss of link synchronization
4660 	 * with an IRQ_HPD, so force a link status check.
4661 	 */
4662 	if (!intel_dp_is_edp(intel_dp)) {
4663 		int ret;
4664 
4665 		ret = intel_dp_retrain_link(encoder, ctx);
4666 		if (ret)
4667 			return ret;
4668 	}
4669 
4670 	/*
4671 	 * Clearing NACK and defer counts to get their exact values
4672 	 * while reading EDID which are required by Compliance tests
4673 	 * 4.2.2.4 and 4.2.2.5
4674 	 */
4675 	intel_dp->aux.i2c_nack_count = 0;
4676 	intel_dp->aux.i2c_defer_count = 0;
4677 
4678 	intel_dp_set_edid(intel_dp);
4679 	if (intel_dp_is_edp(intel_dp) ||
4680 	    to_intel_connector(connector)->detect_edid)
4681 		status = connector_status_connected;
4682 
4683 	intel_dp_check_device_service_irq(intel_dp);
4684 
4685 out:
4686 	if (status != connector_status_connected && !intel_dp->is_mst)
4687 		intel_dp_unset_edid(intel_dp);
4688 
4689 	/*
4690 	 * Make sure the refs for power wells enabled during detect are
4691 	 * dropped to avoid a new detect cycle triggered by HPD polling.
4692 	 */
4693 	intel_display_power_flush_work(dev_priv);
4694 
4695 	if (!intel_dp_is_edp(intel_dp))
4696 		drm_dp_set_subconnector_property(connector,
4697 						 status,
4698 						 intel_dp->dpcd,
4699 						 intel_dp->downstream_ports);
4700 	return status;
4701 }
4702 
4703 static void
intel_dp_force(struct drm_connector * connector)4704 intel_dp_force(struct drm_connector *connector)
4705 {
4706 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4707 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4708 	struct intel_encoder *intel_encoder = &dig_port->base;
4709 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4710 	enum intel_display_power_domain aux_domain =
4711 		intel_aux_power_domain(dig_port);
4712 	intel_wakeref_t wakeref;
4713 
4714 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4715 		    connector->base.id, connector->name);
4716 	intel_dp_unset_edid(intel_dp);
4717 
4718 	if (connector->status != connector_status_connected)
4719 		return;
4720 
4721 	wakeref = intel_display_power_get(dev_priv, aux_domain);
4722 
4723 	intel_dp_set_edid(intel_dp);
4724 
4725 	intel_display_power_put(dev_priv, aux_domain, wakeref);
4726 }
4727 
intel_dp_get_modes(struct drm_connector * connector)4728 static int intel_dp_get_modes(struct drm_connector *connector)
4729 {
4730 	struct intel_connector *intel_connector = to_intel_connector(connector);
4731 	struct edid *edid;
4732 	int num_modes = 0;
4733 
4734 	edid = intel_connector->detect_edid;
4735 	if (edid)
4736 		num_modes = intel_connector_update_modes(connector, edid);
4737 
4738 	/* Also add fixed mode, which may or may not be present in EDID */
4739 	if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4740 		num_modes += intel_panel_get_modes(intel_connector);
4741 
4742 	if (num_modes)
4743 		return num_modes;
4744 
4745 	if (!edid) {
4746 		struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4747 		struct drm_display_mode *mode;
4748 
4749 		mode = drm_dp_downstream_mode(connector->dev,
4750 					      intel_dp->dpcd,
4751 					      intel_dp->downstream_ports);
4752 		if (mode) {
4753 			drm_mode_probed_add(connector, mode);
4754 			num_modes++;
4755 		}
4756 	}
4757 
4758 	return num_modes;
4759 }
4760 
4761 static int
intel_dp_connector_register(struct drm_connector * connector)4762 intel_dp_connector_register(struct drm_connector *connector)
4763 {
4764 	struct drm_i915_private *i915 = to_i915(connector->dev);
4765 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4766 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4767 	struct intel_lspcon *lspcon = &dig_port->lspcon;
4768 	int ret;
4769 
4770 	ret = intel_connector_register(connector);
4771 	if (ret)
4772 		return ret;
4773 
4774 	drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4775 		    intel_dp->aux.name, connector->kdev->kobj.name);
4776 
4777 	intel_dp->aux.dev = connector->kdev;
4778 	ret = drm_dp_aux_register(&intel_dp->aux);
4779 	if (!ret)
4780 		drm_dp_cec_register_connector(&intel_dp->aux, connector);
4781 
4782 	if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4783 		return ret;
4784 
4785 	/*
4786 	 * ToDo: Clean this up to handle lspcon init and resume more
4787 	 * efficiently and streamlined.
4788 	 */
4789 	if (lspcon_init(dig_port)) {
4790 		lspcon_detect_hdr_capability(lspcon);
4791 		if (lspcon->hdr_supported)
4792 			drm_connector_attach_hdr_output_metadata_property(connector);
4793 	}
4794 
4795 	return ret;
4796 }
4797 
4798 static void
intel_dp_connector_unregister(struct drm_connector * connector)4799 intel_dp_connector_unregister(struct drm_connector *connector)
4800 {
4801 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4802 
4803 	drm_dp_cec_unregister_connector(&intel_dp->aux);
4804 	drm_dp_aux_unregister(&intel_dp->aux);
4805 	intel_connector_unregister(connector);
4806 }
4807 
intel_dp_encoder_flush_work(struct drm_encoder * encoder)4808 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4809 {
4810 	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4811 	struct intel_dp *intel_dp = &dig_port->dp;
4812 
4813 	intel_dp_mst_encoder_cleanup(dig_port);
4814 
4815 	intel_pps_vdd_off_sync(intel_dp);
4816 
4817 	intel_dp_aux_fini(intel_dp);
4818 }
4819 
intel_dp_encoder_suspend(struct intel_encoder * intel_encoder)4820 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4821 {
4822 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4823 
4824 	intel_pps_vdd_off_sync(intel_dp);
4825 }
4826 
intel_dp_encoder_shutdown(struct intel_encoder * intel_encoder)4827 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4828 {
4829 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4830 
4831 	intel_pps_wait_power_cycle(intel_dp);
4832 }
4833 
intel_modeset_tile_group(struct intel_atomic_state * state,int tile_group_id)4834 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4835 				    int tile_group_id)
4836 {
4837 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4838 	struct drm_connector_list_iter conn_iter;
4839 	struct drm_connector *connector;
4840 	int ret = 0;
4841 
4842 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4843 	drm_for_each_connector_iter(connector, &conn_iter) {
4844 		struct drm_connector_state *conn_state;
4845 		struct intel_crtc_state *crtc_state;
4846 		struct intel_crtc *crtc;
4847 
4848 		if (!connector->has_tile ||
4849 		    connector->tile_group->id != tile_group_id)
4850 			continue;
4851 
4852 		conn_state = drm_atomic_get_connector_state(&state->base,
4853 							    connector);
4854 		if (IS_ERR(conn_state)) {
4855 			ret = PTR_ERR(conn_state);
4856 			break;
4857 		}
4858 
4859 		crtc = to_intel_crtc(conn_state->crtc);
4860 
4861 		if (!crtc)
4862 			continue;
4863 
4864 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4865 		crtc_state->uapi.mode_changed = true;
4866 
4867 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4868 		if (ret)
4869 			break;
4870 	}
4871 	drm_connector_list_iter_end(&conn_iter);
4872 
4873 	return ret;
4874 }
4875 
intel_modeset_affected_transcoders(struct intel_atomic_state * state,u8 transcoders)4876 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4877 {
4878 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4879 	struct intel_crtc *crtc;
4880 
4881 	if (transcoders == 0)
4882 		return 0;
4883 
4884 	for_each_intel_crtc(&dev_priv->drm, crtc) {
4885 		struct intel_crtc_state *crtc_state;
4886 		int ret;
4887 
4888 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4889 		if (IS_ERR(crtc_state))
4890 			return PTR_ERR(crtc_state);
4891 
4892 		if (!crtc_state->hw.enable)
4893 			continue;
4894 
4895 		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4896 			continue;
4897 
4898 		crtc_state->uapi.mode_changed = true;
4899 
4900 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4901 		if (ret)
4902 			return ret;
4903 
4904 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4905 		if (ret)
4906 			return ret;
4907 
4908 		transcoders &= ~BIT(crtc_state->cpu_transcoder);
4909 	}
4910 
4911 	drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4912 
4913 	return 0;
4914 }
4915 
intel_modeset_synced_crtcs(struct intel_atomic_state * state,struct drm_connector * connector)4916 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4917 				      struct drm_connector *connector)
4918 {
4919 	const struct drm_connector_state *old_conn_state =
4920 		drm_atomic_get_old_connector_state(&state->base, connector);
4921 	const struct intel_crtc_state *old_crtc_state;
4922 	struct intel_crtc *crtc;
4923 	u8 transcoders;
4924 
4925 	crtc = to_intel_crtc(old_conn_state->crtc);
4926 	if (!crtc)
4927 		return 0;
4928 
4929 	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4930 
4931 	if (!old_crtc_state->hw.active)
4932 		return 0;
4933 
4934 	transcoders = old_crtc_state->sync_mode_slaves_mask;
4935 	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4936 		transcoders |= BIT(old_crtc_state->master_transcoder);
4937 
4938 	return intel_modeset_affected_transcoders(state,
4939 						  transcoders);
4940 }
4941 
intel_dp_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * _state)4942 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4943 					   struct drm_atomic_state *_state)
4944 {
4945 	struct drm_i915_private *dev_priv = to_i915(conn->dev);
4946 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
4947 	struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
4948 	struct intel_connector *intel_conn = to_intel_connector(conn);
4949 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
4950 	int ret;
4951 
4952 	ret = intel_digital_connector_atomic_check(conn, &state->base);
4953 	if (ret)
4954 		return ret;
4955 
4956 	if (intel_dp_mst_source_support(intel_dp)) {
4957 		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
4958 		if (ret)
4959 			return ret;
4960 	}
4961 
4962 	/*
4963 	 * We don't enable port sync on BDW due to missing w/as and
4964 	 * due to not having adjusted the modeset sequence appropriately.
4965 	 */
4966 	if (DISPLAY_VER(dev_priv) < 9)
4967 		return 0;
4968 
4969 	if (!intel_connector_needs_modeset(state, conn))
4970 		return 0;
4971 
4972 	if (conn->has_tile) {
4973 		ret = intel_modeset_tile_group(state, conn->tile_group->id);
4974 		if (ret)
4975 			return ret;
4976 	}
4977 
4978 	return intel_modeset_synced_crtcs(state, conn);
4979 }
4980 
intel_dp_oob_hotplug_event(struct drm_connector * connector)4981 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
4982 {
4983 	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
4984 	struct drm_i915_private *i915 = to_i915(connector->dev);
4985 
4986 	spin_lock_irq(&i915->irq_lock);
4987 	i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
4988 	spin_unlock_irq(&i915->irq_lock);
4989 	queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
4990 }
4991 
4992 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4993 	.force = intel_dp_force,
4994 	.fill_modes = drm_helper_probe_single_connector_modes,
4995 	.atomic_get_property = intel_digital_connector_atomic_get_property,
4996 	.atomic_set_property = intel_digital_connector_atomic_set_property,
4997 	.late_register = intel_dp_connector_register,
4998 	.early_unregister = intel_dp_connector_unregister,
4999 	.destroy = intel_connector_destroy,
5000 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5001 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
5002 	.oob_hotplug_event = intel_dp_oob_hotplug_event,
5003 };
5004 
5005 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5006 	.detect_ctx = intel_dp_detect,
5007 	.get_modes = intel_dp_get_modes,
5008 	.mode_valid = intel_dp_mode_valid,
5009 	.atomic_check = intel_dp_connector_atomic_check,
5010 };
5011 
5012 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port * dig_port,bool long_hpd)5013 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5014 {
5015 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5016 	struct intel_dp *intel_dp = &dig_port->dp;
5017 
5018 	if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5019 	    (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5020 		/*
5021 		 * vdd off can generate a long/short pulse on eDP which
5022 		 * would require vdd on to handle it, and thus we
5023 		 * would end up in an endless cycle of
5024 		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5025 		 */
5026 		drm_dbg_kms(&i915->drm,
5027 			    "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5028 			    long_hpd ? "long" : "short",
5029 			    dig_port->base.base.base.id,
5030 			    dig_port->base.base.name);
5031 		return IRQ_HANDLED;
5032 	}
5033 
5034 	drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5035 		    dig_port->base.base.base.id,
5036 		    dig_port->base.base.name,
5037 		    long_hpd ? "long" : "short");
5038 
5039 	if (long_hpd) {
5040 		intel_dp->reset_link_params = true;
5041 		return IRQ_NONE;
5042 	}
5043 
5044 	if (intel_dp->is_mst) {
5045 		if (!intel_dp_check_mst_status(intel_dp))
5046 			return IRQ_NONE;
5047 	} else if (!intel_dp_short_pulse(intel_dp)) {
5048 		return IRQ_NONE;
5049 	}
5050 
5051 	return IRQ_HANDLED;
5052 }
5053 
5054 /* check the VBT to see whether the eDP is on another port */
intel_dp_is_port_edp(struct drm_i915_private * dev_priv,enum port port)5055 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5056 {
5057 	/*
5058 	 * eDP not supported on g4x. so bail out early just
5059 	 * for a bit extra safety in case the VBT is bonkers.
5060 	 */
5061 	if (DISPLAY_VER(dev_priv) < 5)
5062 		return false;
5063 
5064 	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5065 		return true;
5066 
5067 	return intel_bios_is_port_edp(dev_priv, port);
5068 }
5069 
5070 static bool
has_gamut_metadata_dip(struct drm_i915_private * i915,enum port port)5071 has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
5072 {
5073 	if (intel_bios_is_lspcon_present(i915, port))
5074 		return false;
5075 
5076 	if (DISPLAY_VER(i915) >= 11)
5077 		return true;
5078 
5079 	if (port == PORT_A)
5080 		return false;
5081 
5082 	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5083 	    DISPLAY_VER(i915) >= 9)
5084 		return true;
5085 
5086 	return false;
5087 }
5088 
5089 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)5090 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5091 {
5092 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
5093 	enum port port = dp_to_dig_port(intel_dp)->base.port;
5094 
5095 	if (!intel_dp_is_edp(intel_dp))
5096 		drm_connector_attach_dp_subconnector_property(connector);
5097 
5098 	if (!IS_G4X(dev_priv) && port != PORT_A)
5099 		intel_attach_force_audio_property(connector);
5100 
5101 	intel_attach_broadcast_rgb_property(connector);
5102 	if (HAS_GMCH(dev_priv))
5103 		drm_connector_attach_max_bpc_property(connector, 6, 10);
5104 	else if (DISPLAY_VER(dev_priv) >= 5)
5105 		drm_connector_attach_max_bpc_property(connector, 6, 12);
5106 
5107 	/* Register HDMI colorspace for case of lspcon */
5108 	if (intel_bios_is_lspcon_present(dev_priv, port)) {
5109 		drm_connector_attach_content_type_property(connector);
5110 		intel_attach_hdmi_colorspace_property(connector);
5111 	} else {
5112 		intel_attach_dp_colorspace_property(connector);
5113 	}
5114 
5115 	if (has_gamut_metadata_dip(dev_priv, port))
5116 		drm_connector_attach_hdr_output_metadata_property(connector);
5117 
5118 	if (intel_dp_is_edp(intel_dp)) {
5119 		u32 allowed_scalers;
5120 
5121 		allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5122 		if (!HAS_GMCH(dev_priv))
5123 			allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5124 
5125 		drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5126 
5127 		connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5128 
5129 	}
5130 
5131 	if (HAS_VRR(dev_priv))
5132 		drm_connector_attach_vrr_capable_property(connector);
5133 }
5134 
5135 static void
intel_edp_add_properties(struct intel_dp * intel_dp)5136 intel_edp_add_properties(struct intel_dp *intel_dp)
5137 {
5138 	struct intel_connector *connector = intel_dp->attached_connector;
5139 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
5140 	const struct drm_display_mode *fixed_mode =
5141 		intel_panel_preferred_fixed_mode(connector);
5142 
5143 	if (!fixed_mode)
5144 		return;
5145 
5146 	drm_connector_set_panel_orientation_with_quirk(&connector->base,
5147 						       i915->display.vbt.orientation,
5148 						       fixed_mode->hdisplay,
5149 						       fixed_mode->vdisplay);
5150 }
5151 
intel_edp_init_connector(struct intel_dp * intel_dp,struct intel_connector * intel_connector)5152 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5153 				     struct intel_connector *intel_connector)
5154 {
5155 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5156 	struct drm_device *dev = &dev_priv->drm;
5157 	struct drm_connector *connector = &intel_connector->base;
5158 	struct drm_display_mode *fixed_mode;
5159 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5160 	bool has_dpcd;
5161 	enum pipe pipe = INVALID_PIPE;
5162 	struct edid *edid;
5163 
5164 	if (!intel_dp_is_edp(intel_dp))
5165 		return true;
5166 
5167 	/*
5168 	 * On IBX/CPT we may get here with LVDS already registered. Since the
5169 	 * driver uses the only internal power sequencer available for both
5170 	 * eDP and LVDS bail out early in this case to prevent interfering
5171 	 * with an already powered-on LVDS power sequencer.
5172 	 */
5173 	if (intel_get_lvds_encoder(dev_priv)) {
5174 		drm_WARN_ON(dev,
5175 			    !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5176 		drm_info(&dev_priv->drm,
5177 			 "LVDS was detected, not registering eDP\n");
5178 
5179 		return false;
5180 	}
5181 
5182 	intel_pps_init(intel_dp);
5183 
5184 	/* Cache DPCD and EDID for edp. */
5185 	has_dpcd = intel_edp_init_dpcd(intel_dp);
5186 
5187 	if (!has_dpcd) {
5188 		/* if this fails, presume the device is a ghost */
5189 		drm_info(&dev_priv->drm,
5190 			 "failed to retrieve link info, disabling eDP\n");
5191 		goto out_vdd_off;
5192 	}
5193 
5194 	mutex_lock(&dev->mode_config.mutex);
5195 	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5196 	if (!edid) {
5197 		/* Fallback to EDID from ACPI OpRegion, if any */
5198 		edid = intel_opregion_get_edid(intel_connector);
5199 		if (edid)
5200 			drm_dbg_kms(&dev_priv->drm,
5201 				    "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5202 				    connector->base.id, connector->name);
5203 	}
5204 	if (edid) {
5205 		if (drm_add_edid_modes(connector, edid)) {
5206 			drm_connector_update_edid_property(connector, edid);
5207 		} else {
5208 			kfree(edid);
5209 			edid = ERR_PTR(-EINVAL);
5210 		}
5211 	} else {
5212 		edid = ERR_PTR(-ENOENT);
5213 	}
5214 	intel_connector->edid = edid;
5215 
5216 	intel_bios_init_panel(dev_priv, &intel_connector->panel,
5217 			      encoder->devdata, IS_ERR(edid) ? NULL : edid);
5218 
5219 	intel_panel_add_edid_fixed_modes(intel_connector, true);
5220 
5221 	/* MSO requires information from the EDID */
5222 	intel_edp_mso_init(intel_dp);
5223 
5224 	/* multiply the mode clock and horizontal timings for MSO */
5225 	list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5226 		intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5227 
5228 	/* fallback to VBT if available for eDP */
5229 	if (!intel_panel_preferred_fixed_mode(intel_connector))
5230 		intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5231 
5232 	mutex_unlock(&dev->mode_config.mutex);
5233 
5234 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5235 		/*
5236 		 * Figure out the current pipe for the initial backlight setup.
5237 		 * If the current pipe isn't valid, try the PPS pipe, and if that
5238 		 * fails just assume pipe A.
5239 		 */
5240 		pipe = vlv_active_pipe(intel_dp);
5241 
5242 		if (pipe != PIPE_A && pipe != PIPE_B)
5243 			pipe = intel_dp->pps.pps_pipe;
5244 
5245 		if (pipe != PIPE_A && pipe != PIPE_B)
5246 			pipe = PIPE_A;
5247 
5248 		drm_dbg_kms(&dev_priv->drm,
5249 			    "using pipe %c for initial backlight setup\n",
5250 			    pipe_name(pipe));
5251 	}
5252 
5253 	intel_panel_init(intel_connector);
5254 
5255 	intel_backlight_setup(intel_connector, pipe);
5256 
5257 	intel_edp_add_properties(intel_dp);
5258 
5259 	intel_pps_init_late(intel_dp);
5260 
5261 	return true;
5262 
5263 out_vdd_off:
5264 	intel_pps_vdd_off_sync(intel_dp);
5265 
5266 	return false;
5267 }
5268 
intel_dp_modeset_retry_work_fn(struct work_struct * work)5269 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5270 {
5271 	struct intel_connector *intel_connector;
5272 	struct drm_connector *connector;
5273 
5274 	intel_connector = container_of(work, typeof(*intel_connector),
5275 				       modeset_retry_work);
5276 	connector = &intel_connector->base;
5277 	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5278 		    connector->name);
5279 
5280 	/* Grab the locks before changing connector property*/
5281 	mutex_lock(&connector->dev->mode_config.mutex);
5282 	/* Set connector link status to BAD and send a Uevent to notify
5283 	 * userspace to do a modeset.
5284 	 */
5285 	drm_connector_set_link_status_property(connector,
5286 					       DRM_MODE_LINK_STATUS_BAD);
5287 	mutex_unlock(&connector->dev->mode_config.mutex);
5288 	/* Send Hotplug uevent so userspace can reprobe */
5289 	drm_kms_helper_connector_hotplug_event(connector);
5290 }
5291 
5292 bool
intel_dp_init_connector(struct intel_digital_port * dig_port,struct intel_connector * intel_connector)5293 intel_dp_init_connector(struct intel_digital_port *dig_port,
5294 			struct intel_connector *intel_connector)
5295 {
5296 	struct drm_connector *connector = &intel_connector->base;
5297 	struct intel_dp *intel_dp = &dig_port->dp;
5298 	struct intel_encoder *intel_encoder = &dig_port->base;
5299 	struct drm_device *dev = intel_encoder->base.dev;
5300 	struct drm_i915_private *dev_priv = to_i915(dev);
5301 	enum port port = intel_encoder->port;
5302 	enum phy phy = intel_port_to_phy(dev_priv, port);
5303 	int type;
5304 
5305 	/* Initialize the work for modeset in case of link train failure */
5306 	INIT_WORK(&intel_connector->modeset_retry_work,
5307 		  intel_dp_modeset_retry_work_fn);
5308 
5309 	if (drm_WARN(dev, dig_port->max_lanes < 1,
5310 		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5311 		     dig_port->max_lanes, intel_encoder->base.base.id,
5312 		     intel_encoder->base.name))
5313 		return false;
5314 
5315 	intel_dp->reset_link_params = true;
5316 	intel_dp->pps.pps_pipe = INVALID_PIPE;
5317 	intel_dp->pps.active_pipe = INVALID_PIPE;
5318 
5319 	/* Preserve the current hw state. */
5320 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5321 	intel_dp->attached_connector = intel_connector;
5322 
5323 	if (intel_dp_is_port_edp(dev_priv, port)) {
5324 		/*
5325 		 * Currently we don't support eDP on TypeC ports, although in
5326 		 * theory it could work on TypeC legacy ports.
5327 		 */
5328 		drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5329 		type = DRM_MODE_CONNECTOR_eDP;
5330 		intel_encoder->type = INTEL_OUTPUT_EDP;
5331 
5332 		/* eDP only on port B and/or C on vlv/chv */
5333 		if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5334 				      IS_CHERRYVIEW(dev_priv)) &&
5335 				port != PORT_B && port != PORT_C))
5336 			return false;
5337 	} else {
5338 		type = DRM_MODE_CONNECTOR_DisplayPort;
5339 	}
5340 
5341 	intel_dp_set_default_sink_rates(intel_dp);
5342 	intel_dp_set_default_max_sink_lane_count(intel_dp);
5343 
5344 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5345 		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5346 
5347 	drm_dbg_kms(&dev_priv->drm,
5348 		    "Adding %s connector on [ENCODER:%d:%s]\n",
5349 		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5350 		    intel_encoder->base.base.id, intel_encoder->base.name);
5351 
5352 	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5353 	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5354 
5355 	if (!HAS_GMCH(dev_priv))
5356 		connector->interlace_allowed = true;
5357 	connector->doublescan_allowed = 0;
5358 
5359 	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5360 
5361 	intel_dp_aux_init(intel_dp);
5362 
5363 	intel_connector_attach_encoder(intel_connector, intel_encoder);
5364 
5365 	if (HAS_DDI(dev_priv))
5366 		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5367 	else
5368 		intel_connector->get_hw_state = intel_connector_get_hw_state;
5369 
5370 	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5371 		intel_dp_aux_fini(intel_dp);
5372 		goto fail;
5373 	}
5374 
5375 	intel_dp_set_source_rates(intel_dp);
5376 	intel_dp_set_common_rates(intel_dp);
5377 	intel_dp_reset_max_link_params(intel_dp);
5378 
5379 	/* init MST on ports that can support it */
5380 	intel_dp_mst_encoder_init(dig_port,
5381 				  intel_connector->base.base.id);
5382 
5383 	intel_dp_add_properties(intel_dp, connector);
5384 
5385 	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5386 		int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5387 		if (ret)
5388 			drm_dbg_kms(&dev_priv->drm,
5389 				    "HDCP init failed, skipping.\n");
5390 	}
5391 
5392 	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5393 	 * 0xd.  Failure to do so will result in spurious interrupts being
5394 	 * generated on the port when a cable is not attached.
5395 	 */
5396 	if (IS_G45(dev_priv)) {
5397 		u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5398 		intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5399 			       (temp & ~0xf) | 0xd);
5400 	}
5401 
5402 	intel_dp->frl.is_trained = false;
5403 	intel_dp->frl.trained_rate_gbps = 0;
5404 
5405 	intel_psr_init(intel_dp);
5406 
5407 	return true;
5408 
5409 fail:
5410 	drm_connector_cleanup(connector);
5411 
5412 	return false;
5413 }
5414 
intel_dp_mst_suspend(struct drm_i915_private * dev_priv)5415 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5416 {
5417 	struct intel_encoder *encoder;
5418 
5419 	if (!HAS_DISPLAY(dev_priv))
5420 		return;
5421 
5422 	for_each_intel_encoder(&dev_priv->drm, encoder) {
5423 		struct intel_dp *intel_dp;
5424 
5425 		if (encoder->type != INTEL_OUTPUT_DDI)
5426 			continue;
5427 
5428 		intel_dp = enc_to_intel_dp(encoder);
5429 
5430 		if (!intel_dp_mst_source_support(intel_dp))
5431 			continue;
5432 
5433 		if (intel_dp->is_mst)
5434 			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5435 	}
5436 }
5437 
intel_dp_mst_resume(struct drm_i915_private * dev_priv)5438 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5439 {
5440 	struct intel_encoder *encoder;
5441 
5442 	if (!HAS_DISPLAY(dev_priv))
5443 		return;
5444 
5445 	for_each_intel_encoder(&dev_priv->drm, encoder) {
5446 		struct intel_dp *intel_dp;
5447 		int ret;
5448 
5449 		if (encoder->type != INTEL_OUTPUT_DDI)
5450 			continue;
5451 
5452 		intel_dp = enc_to_intel_dp(encoder);
5453 
5454 		if (!intel_dp_mst_source_support(intel_dp))
5455 			continue;
5456 
5457 		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5458 						     true);
5459 		if (ret) {
5460 			intel_dp->is_mst = false;
5461 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5462 							false);
5463 		}
5464 	}
5465 }
5466