1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/firmware.h>
26 
27 #include "i915_drv.h"
28 #include "i915_reg.h"
29 #include "intel_de.h"
30 #include "intel_dmc.h"
31 #include "intel_dmc_regs.h"
32 
33 /**
34  * DOC: DMC Firmware Support
35  *
36  * From gen9 onwards we have newly added DMC (Display microcontroller) in display
37  * engine to save and restore the state of display engine when it enter into
38  * low-power state and comes back to normal.
39  */
40 
41 #define DMC_VERSION(major, minor)	((major) << 16 | (minor))
42 #define DMC_VERSION_MAJOR(version)	((version) >> 16)
43 #define DMC_VERSION_MINOR(version)	((version) & 0xffff)
44 
45 #define DMC_PATH(platform, major, minor) \
46 	"i915/"				 \
47 	__stringify(platform) "_dmc_ver" \
48 	__stringify(major) "_"		 \
49 	__stringify(minor) ".bin"
50 
51 #define DISPLAY_VER13_DMC_MAX_FW_SIZE	0x20000
52 
53 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
54 
55 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
56 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
57 MODULE_FIRMWARE(ADLP_DMC_PATH);
58 
59 #define ADLS_DMC_PATH			DMC_PATH(adls, 2, 01)
60 #define ADLS_DMC_VERSION_REQUIRED	DMC_VERSION(2, 1)
61 MODULE_FIRMWARE(ADLS_DMC_PATH);
62 
63 #define DG1_DMC_PATH			DMC_PATH(dg1, 2, 02)
64 #define DG1_DMC_VERSION_REQUIRED	DMC_VERSION(2, 2)
65 MODULE_FIRMWARE(DG1_DMC_PATH);
66 
67 #define RKL_DMC_PATH			DMC_PATH(rkl, 2, 03)
68 #define RKL_DMC_VERSION_REQUIRED	DMC_VERSION(2, 3)
69 MODULE_FIRMWARE(RKL_DMC_PATH);
70 
71 #define TGL_DMC_PATH			DMC_PATH(tgl, 2, 12)
72 #define TGL_DMC_VERSION_REQUIRED	DMC_VERSION(2, 12)
73 MODULE_FIRMWARE(TGL_DMC_PATH);
74 
75 #define ICL_DMC_PATH			DMC_PATH(icl, 1, 09)
76 #define ICL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 9)
77 #define ICL_DMC_MAX_FW_SIZE		0x6000
78 MODULE_FIRMWARE(ICL_DMC_PATH);
79 
80 #define GLK_DMC_PATH			DMC_PATH(glk, 1, 04)
81 #define GLK_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
82 #define GLK_DMC_MAX_FW_SIZE		0x4000
83 MODULE_FIRMWARE(GLK_DMC_PATH);
84 
85 #define KBL_DMC_PATH			DMC_PATH(kbl, 1, 04)
86 #define KBL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
87 #define KBL_DMC_MAX_FW_SIZE		BXT_DMC_MAX_FW_SIZE
88 MODULE_FIRMWARE(KBL_DMC_PATH);
89 
90 #define SKL_DMC_PATH			DMC_PATH(skl, 1, 27)
91 #define SKL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 27)
92 #define SKL_DMC_MAX_FW_SIZE		BXT_DMC_MAX_FW_SIZE
93 MODULE_FIRMWARE(SKL_DMC_PATH);
94 
95 #define BXT_DMC_PATH			DMC_PATH(bxt, 1, 07)
96 #define BXT_DMC_VERSION_REQUIRED	DMC_VERSION(1, 7)
97 #define BXT_DMC_MAX_FW_SIZE		0x3000
98 MODULE_FIRMWARE(BXT_DMC_PATH);
99 
100 #define DMC_DEFAULT_FW_OFFSET		0xFFFFFFFF
101 #define PACKAGE_MAX_FW_INFO_ENTRIES	20
102 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES	32
103 #define DMC_V1_MAX_MMIO_COUNT		8
104 #define DMC_V3_MAX_MMIO_COUNT		20
105 #define DMC_V1_MMIO_START_RANGE		0x80000
106 
107 struct intel_css_header {
108 	/* 0x09 for DMC */
109 	u32 module_type;
110 
111 	/* Includes the DMC specific header in dwords */
112 	u32 header_len;
113 
114 	/* always value would be 0x10000 */
115 	u32 header_ver;
116 
117 	/* Not used */
118 	u32 module_id;
119 
120 	/* Not used */
121 	u32 module_vendor;
122 
123 	/* in YYYYMMDD format */
124 	u32 date;
125 
126 	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
127 	u32 size;
128 
129 	/* Not used */
130 	u32 key_size;
131 
132 	/* Not used */
133 	u32 modulus_size;
134 
135 	/* Not used */
136 	u32 exponent_size;
137 
138 	/* Not used */
139 	u32 reserved1[12];
140 
141 	/* Major Minor */
142 	u32 version;
143 
144 	/* Not used */
145 	u32 reserved2[8];
146 
147 	/* Not used */
148 	u32 kernel_header_info;
149 } __packed;
150 
151 struct intel_fw_info {
152 	u8 reserved1;
153 
154 	/* reserved on package_header version 1, must be 0 on version 2 */
155 	u8 dmc_id;
156 
157 	/* Stepping (A, B, C, ..., *). * is a wildcard */
158 	char stepping;
159 
160 	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
161 	char substepping;
162 
163 	u32 offset;
164 	u32 reserved2;
165 } __packed;
166 
167 struct intel_package_header {
168 	/* DMC container header length in dwords */
169 	u8 header_len;
170 
171 	/* 0x01, 0x02 */
172 	u8 header_ver;
173 
174 	u8 reserved[10];
175 
176 	/* Number of valid entries in the FWInfo array below */
177 	u32 num_entries;
178 } __packed;
179 
180 struct intel_dmc_header_base {
181 	/* always value would be 0x40403E3E */
182 	u32 signature;
183 
184 	/* DMC binary header length */
185 	u8 header_len;
186 
187 	/* 0x01 */
188 	u8 header_ver;
189 
190 	/* Reserved */
191 	u16 dmcc_ver;
192 
193 	/* Major, Minor */
194 	u32 project;
195 
196 	/* Firmware program size (excluding header) in dwords */
197 	u32 fw_size;
198 
199 	/* Major Minor version */
200 	u32 fw_version;
201 } __packed;
202 
203 struct intel_dmc_header_v1 {
204 	struct intel_dmc_header_base base;
205 
206 	/* Number of valid MMIO cycles present. */
207 	u32 mmio_count;
208 
209 	/* MMIO address */
210 	u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
211 
212 	/* MMIO data */
213 	u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
214 
215 	/* FW filename  */
216 	char dfile[32];
217 
218 	u32 reserved1[2];
219 } __packed;
220 
221 struct intel_dmc_header_v3 {
222 	struct intel_dmc_header_base base;
223 
224 	/* DMC RAM start MMIO address */
225 	u32 start_mmioaddr;
226 
227 	u32 reserved[9];
228 
229 	/* FW filename */
230 	char dfile[32];
231 
232 	/* Number of valid MMIO cycles present. */
233 	u32 mmio_count;
234 
235 	/* MMIO address */
236 	u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
237 
238 	/* MMIO data */
239 	u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
240 } __packed;
241 
242 struct stepping_info {
243 	char stepping;
244 	char substepping;
245 };
246 
intel_dmc_has_payload(struct drm_i915_private * i915)247 bool intel_dmc_has_payload(struct drm_i915_private *i915)
248 {
249 	return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
250 }
251 
252 static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private * i915,struct stepping_info * si)253 intel_get_stepping_info(struct drm_i915_private *i915,
254 			struct stepping_info *si)
255 {
256 	const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step);
257 
258 	si->stepping = step_name[0];
259 	si->substepping = step_name[1];
260 	return si;
261 }
262 
gen9_set_dc_state_debugmask(struct drm_i915_private * dev_priv)263 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
264 {
265 	/* The below bit doesn't need to be cleared ever afterwards */
266 	intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
267 		     DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
268 	intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
269 }
270 
271 /**
272  * intel_dmc_load_program() - write the firmware from memory to register.
273  * @dev_priv: i915 drm device.
274  *
275  * DMC firmware is read from a .bin file and kept in internal memory one time.
276  * Everytime display comes back from low power state this function is called to
277  * copy the firmware from internal memory to registers.
278  */
intel_dmc_load_program(struct drm_i915_private * dev_priv)279 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
280 {
281 	struct intel_dmc *dmc = &dev_priv->dmc;
282 	u32 id, i;
283 
284 	if (!intel_dmc_has_payload(dev_priv))
285 		return;
286 
287 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
288 
289 	preempt_disable();
290 
291 	for (id = 0; id < DMC_FW_MAX; id++) {
292 		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
293 			intel_uncore_write_fw(&dev_priv->uncore,
294 					      DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
295 					      dmc->dmc_info[id].payload[i]);
296 		}
297 	}
298 
299 	preempt_enable();
300 
301 	for (id = 0; id < DMC_FW_MAX; id++) {
302 		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
303 			intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
304 				       dmc->dmc_info[id].mmiodata[i]);
305 		}
306 	}
307 
308 	dev_priv->dmc.dc_state = 0;
309 
310 	gen9_set_dc_state_debugmask(dev_priv);
311 }
312 
assert_dmc_loaded(struct drm_i915_private * i915)313 void assert_dmc_loaded(struct drm_i915_private *i915)
314 {
315 	drm_WARN_ONCE(&i915->drm,
316 		      !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
317 		      "DMC program storage start is NULL\n");
318 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
319 		      "DMC SSP Base Not fine\n");
320 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
321 		      "DMC HTP Not fine\n");
322 }
323 
fw_info_matches_stepping(const struct intel_fw_info * fw_info,const struct stepping_info * si)324 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
325 				     const struct stepping_info *si)
326 {
327 	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
328 	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
329 	    /*
330 	     * If we don't find a more specific one from above two checks, we
331 	     * then check for the generic one to be sure to work even with
332 	     * "broken firmware"
333 	     */
334 	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||
335 	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
336 		return true;
337 
338 	return false;
339 }
340 
341 /*
342  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
343  * already sanitized.
344  */
dmc_set_fw_offset(struct intel_dmc * dmc,const struct intel_fw_info * fw_info,unsigned int num_entries,const struct stepping_info * si,u8 package_ver)345 static void dmc_set_fw_offset(struct intel_dmc *dmc,
346 			      const struct intel_fw_info *fw_info,
347 			      unsigned int num_entries,
348 			      const struct stepping_info *si,
349 			      u8 package_ver)
350 {
351 	unsigned int i, id;
352 
353 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
354 
355 	for (i = 0; i < num_entries; i++) {
356 		id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
357 
358 		if (id >= DMC_FW_MAX) {
359 			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id);
360 			continue;
361 		}
362 
363 		/* More specific versions come first, so we don't even have to
364 		 * check for the stepping since we already found a previous FW
365 		 * for this id.
366 		 */
367 		if (dmc->dmc_info[id].present)
368 			continue;
369 
370 		if (fw_info_matches_stepping(&fw_info[i], si)) {
371 			dmc->dmc_info[id].present = true;
372 			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
373 		}
374 	}
375 }
376 
dmc_mmio_addr_sanity_check(struct intel_dmc * dmc,const u32 * mmioaddr,u32 mmio_count,int header_ver,u8 dmc_id)377 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
378 				       const u32 *mmioaddr, u32 mmio_count,
379 				       int header_ver, u8 dmc_id)
380 {
381 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
382 	u32 start_range, end_range;
383 	int i;
384 
385 	if (dmc_id >= DMC_FW_MAX) {
386 		drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);
387 		return false;
388 	}
389 
390 	if (header_ver == 1) {
391 		start_range = DMC_MMIO_START_RANGE;
392 		end_range = DMC_MMIO_END_RANGE;
393 	} else if (dmc_id == DMC_FW_MAIN) {
394 		start_range = TGL_MAIN_MMIO_START;
395 		end_range = TGL_MAIN_MMIO_END;
396 	} else if (DISPLAY_VER(i915) >= 13) {
397 		start_range = ADLP_PIPE_MMIO_START;
398 		end_range = ADLP_PIPE_MMIO_END;
399 	} else if (DISPLAY_VER(i915) >= 12) {
400 		start_range = TGL_PIPE_MMIO_START(dmc_id);
401 		end_range = TGL_PIPE_MMIO_END(dmc_id);
402 	} else {
403 		drm_warn(&i915->drm, "Unknown mmio range for sanity check");
404 		return false;
405 	}
406 
407 	for (i = 0; i < mmio_count; i++) {
408 		if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
409 			return false;
410 	}
411 
412 	return true;
413 }
414 
parse_dmc_fw_header(struct intel_dmc * dmc,const struct intel_dmc_header_base * dmc_header,size_t rem_size,u8 dmc_id)415 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
416 			       const struct intel_dmc_header_base *dmc_header,
417 			       size_t rem_size, u8 dmc_id)
418 {
419 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
420 	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
421 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
422 	const u32 *mmioaddr, *mmiodata;
423 	u32 mmio_count, mmio_count_max, start_mmioaddr;
424 	u8 *payload;
425 
426 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
427 		     ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
428 
429 	/*
430 	 * Check if we can access common fields, we will checkc again below
431 	 * after we have read the version
432 	 */
433 	if (rem_size < sizeof(struct intel_dmc_header_base))
434 		goto error_truncated;
435 
436 	/* Cope with small differences between v1 and v3 */
437 	if (dmc_header->header_ver == 3) {
438 		const struct intel_dmc_header_v3 *v3 =
439 			(const struct intel_dmc_header_v3 *)dmc_header;
440 
441 		if (rem_size < sizeof(struct intel_dmc_header_v3))
442 			goto error_truncated;
443 
444 		mmioaddr = v3->mmioaddr;
445 		mmiodata = v3->mmiodata;
446 		mmio_count = v3->mmio_count;
447 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
448 		/* header_len is in dwords */
449 		header_len_bytes = dmc_header->header_len * 4;
450 		start_mmioaddr = v3->start_mmioaddr;
451 		dmc_header_size = sizeof(*v3);
452 	} else if (dmc_header->header_ver == 1) {
453 		const struct intel_dmc_header_v1 *v1 =
454 			(const struct intel_dmc_header_v1 *)dmc_header;
455 
456 		if (rem_size < sizeof(struct intel_dmc_header_v1))
457 			goto error_truncated;
458 
459 		mmioaddr = v1->mmioaddr;
460 		mmiodata = v1->mmiodata;
461 		mmio_count = v1->mmio_count;
462 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
463 		header_len_bytes = dmc_header->header_len;
464 		start_mmioaddr = DMC_V1_MMIO_START_RANGE;
465 		dmc_header_size = sizeof(*v1);
466 	} else {
467 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
468 			dmc_header->header_ver);
469 		return 0;
470 	}
471 
472 	if (header_len_bytes != dmc_header_size) {
473 		drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
474 			"(%u bytes)\n", header_len_bytes);
475 		return 0;
476 	}
477 
478 	/* Cache the dmc header info. */
479 	if (mmio_count > mmio_count_max) {
480 		drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
481 		return 0;
482 	}
483 
484 	if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
485 					dmc_header->header_ver, dmc_id)) {
486 		drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
487 		return 0;
488 	}
489 
490 	for (i = 0; i < mmio_count; i++) {
491 		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
492 		dmc_info->mmiodata[i] = mmiodata[i];
493 	}
494 	dmc_info->mmio_count = mmio_count;
495 	dmc_info->start_mmioaddr = start_mmioaddr;
496 
497 	rem_size -= header_len_bytes;
498 
499 	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
500 	payload_size = dmc_header->fw_size * 4;
501 	if (rem_size < payload_size)
502 		goto error_truncated;
503 
504 	if (payload_size > dmc->max_fw_size) {
505 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
506 		return 0;
507 	}
508 	dmc_info->dmc_fw_size = dmc_header->fw_size;
509 
510 	dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
511 	if (!dmc_info->payload)
512 		return 0;
513 
514 	payload = (u8 *)(dmc_header) + header_len_bytes;
515 	memcpy(dmc_info->payload, payload, payload_size);
516 
517 	return header_len_bytes + payload_size;
518 
519 error_truncated:
520 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
521 	return 0;
522 }
523 
524 static u32
parse_dmc_fw_package(struct intel_dmc * dmc,const struct intel_package_header * package_header,const struct stepping_info * si,size_t rem_size)525 parse_dmc_fw_package(struct intel_dmc *dmc,
526 		     const struct intel_package_header *package_header,
527 		     const struct stepping_info *si,
528 		     size_t rem_size)
529 {
530 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
531 	u32 package_size = sizeof(struct intel_package_header);
532 	u32 num_entries, max_entries;
533 	const struct intel_fw_info *fw_info;
534 
535 	if (rem_size < package_size)
536 		goto error_truncated;
537 
538 	if (package_header->header_ver == 1) {
539 		max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
540 	} else if (package_header->header_ver == 2) {
541 		max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
542 	} else {
543 		drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",
544 			package_header->header_ver);
545 		return 0;
546 	}
547 
548 	/*
549 	 * We should always have space for max_entries,
550 	 * even if not all are used
551 	 */
552 	package_size += max_entries * sizeof(struct intel_fw_info);
553 	if (rem_size < package_size)
554 		goto error_truncated;
555 
556 	if (package_header->header_len * 4 != package_size) {
557 		drm_err(&i915->drm, "DMC firmware has wrong package header length "
558 			"(%u bytes)\n", package_size);
559 		return 0;
560 	}
561 
562 	num_entries = package_header->num_entries;
563 	if (WARN_ON(package_header->num_entries > max_entries))
564 		num_entries = max_entries;
565 
566 	fw_info = (const struct intel_fw_info *)
567 		((u8 *)package_header + sizeof(*package_header));
568 	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
569 			  package_header->header_ver);
570 
571 	/* dmc_offset is in dwords */
572 	return package_size;
573 
574 error_truncated:
575 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
576 	return 0;
577 }
578 
579 /* Return number of bytes parsed or 0 on error */
parse_dmc_fw_css(struct intel_dmc * dmc,struct intel_css_header * css_header,size_t rem_size)580 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
581 			    struct intel_css_header *css_header,
582 			    size_t rem_size)
583 {
584 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
585 
586 	if (rem_size < sizeof(struct intel_css_header)) {
587 		drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
588 		return 0;
589 	}
590 
591 	if (sizeof(struct intel_css_header) !=
592 	    (css_header->header_len * 4)) {
593 		drm_err(&i915->drm, "DMC firmware has wrong CSS header length "
594 			"(%u bytes)\n",
595 			(css_header->header_len * 4));
596 		return 0;
597 	}
598 
599 	if (dmc->required_version &&
600 	    css_header->version != dmc->required_version) {
601 		drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u,"
602 			 " please use v%u.%u\n",
603 			 DMC_VERSION_MAJOR(css_header->version),
604 			 DMC_VERSION_MINOR(css_header->version),
605 			 DMC_VERSION_MAJOR(dmc->required_version),
606 			 DMC_VERSION_MINOR(dmc->required_version));
607 		return 0;
608 	}
609 
610 	dmc->version = css_header->version;
611 
612 	return sizeof(struct intel_css_header);
613 }
614 
parse_dmc_fw(struct drm_i915_private * dev_priv,const struct firmware * fw)615 static void parse_dmc_fw(struct drm_i915_private *dev_priv,
616 			 const struct firmware *fw)
617 {
618 	struct intel_css_header *css_header;
619 	struct intel_package_header *package_header;
620 	struct intel_dmc_header_base *dmc_header;
621 	struct intel_dmc *dmc = &dev_priv->dmc;
622 	struct stepping_info display_info = { '*', '*'};
623 	const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
624 	u32 readcount = 0;
625 	u32 r, offset;
626 	int id;
627 
628 	if (!fw)
629 		return;
630 
631 	/* Extract CSS Header information */
632 	css_header = (struct intel_css_header *)fw->data;
633 	r = parse_dmc_fw_css(dmc, css_header, fw->size);
634 	if (!r)
635 		return;
636 
637 	readcount += r;
638 
639 	/* Extract Package Header information */
640 	package_header = (struct intel_package_header *)&fw->data[readcount];
641 	r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
642 	if (!r)
643 		return;
644 
645 	readcount += r;
646 
647 	for (id = 0; id < DMC_FW_MAX; id++) {
648 		if (!dev_priv->dmc.dmc_info[id].present)
649 			continue;
650 
651 		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
652 		if (offset > fw->size) {
653 			drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
654 			continue;
655 		}
656 
657 		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
658 		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
659 	}
660 }
661 
intel_dmc_runtime_pm_get(struct drm_i915_private * dev_priv)662 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
663 {
664 	drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
665 	dev_priv->dmc.wakeref =
666 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
667 }
668 
intel_dmc_runtime_pm_put(struct drm_i915_private * dev_priv)669 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
670 {
671 	intel_wakeref_t wakeref __maybe_unused =
672 		fetch_and_zero(&dev_priv->dmc.wakeref);
673 
674 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
675 }
676 
dmc_load_work_fn(struct work_struct * work)677 static void dmc_load_work_fn(struct work_struct *work)
678 {
679 	struct drm_i915_private *dev_priv;
680 	struct intel_dmc *dmc;
681 	const struct firmware *fw = NULL;
682 
683 	dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
684 	dmc = &dev_priv->dmc;
685 
686 	request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
687 	parse_dmc_fw(dev_priv, fw);
688 
689 	if (intel_dmc_has_payload(dev_priv)) {
690 		intel_dmc_load_program(dev_priv);
691 		intel_dmc_runtime_pm_put(dev_priv);
692 
693 		drm_info(&dev_priv->drm,
694 			 "Finished loading DMC firmware %s (v%u.%u)\n",
695 			 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
696 			 DMC_VERSION_MINOR(dmc->version));
697 	} else {
698 		drm_notice(&dev_priv->drm,
699 			   "Failed to load DMC firmware %s."
700 			   " Disabling runtime power management.\n",
701 			   dmc->fw_path);
702 		drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
703 			   INTEL_UC_FIRMWARE_URL);
704 	}
705 
706 	release_firmware(fw);
707 }
708 
709 /**
710  * intel_dmc_ucode_init() - initialize the firmware loading.
711  * @dev_priv: i915 drm device.
712  *
713  * This function is called at the time of loading the display driver to read
714  * firmware from a .bin file and copied into a internal memory.
715  */
intel_dmc_ucode_init(struct drm_i915_private * dev_priv)716 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
717 {
718 	struct intel_dmc *dmc = &dev_priv->dmc;
719 
720 	INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
721 
722 	if (!HAS_DMC(dev_priv))
723 		return;
724 
725 	/*
726 	 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
727 	 * runtime-suspend.
728 	 *
729 	 * On error, we return with the rpm wakeref held to prevent runtime
730 	 * suspend as runtime suspend *requires* a working DMC for whatever
731 	 * reason.
732 	 */
733 	intel_dmc_runtime_pm_get(dev_priv);
734 
735 	if (IS_ALDERLAKE_P(dev_priv)) {
736 		dmc->fw_path = ADLP_DMC_PATH;
737 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
738 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
739 	} else if (IS_ALDERLAKE_S(dev_priv)) {
740 		dmc->fw_path = ADLS_DMC_PATH;
741 		dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
742 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
743 	} else if (IS_DG1(dev_priv)) {
744 		dmc->fw_path = DG1_DMC_PATH;
745 		dmc->required_version = DG1_DMC_VERSION_REQUIRED;
746 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
747 	} else if (IS_ROCKETLAKE(dev_priv)) {
748 		dmc->fw_path = RKL_DMC_PATH;
749 		dmc->required_version = RKL_DMC_VERSION_REQUIRED;
750 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
751 	} else if (IS_TIGERLAKE(dev_priv)) {
752 		dmc->fw_path = TGL_DMC_PATH;
753 		dmc->required_version = TGL_DMC_VERSION_REQUIRED;
754 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
755 	} else if (DISPLAY_VER(dev_priv) == 11) {
756 		dmc->fw_path = ICL_DMC_PATH;
757 		dmc->required_version = ICL_DMC_VERSION_REQUIRED;
758 		dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
759 	} else if (IS_GEMINILAKE(dev_priv)) {
760 		dmc->fw_path = GLK_DMC_PATH;
761 		dmc->required_version = GLK_DMC_VERSION_REQUIRED;
762 		dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
763 	} else if (IS_KABYLAKE(dev_priv) ||
764 		   IS_COFFEELAKE(dev_priv) ||
765 		   IS_COMETLAKE(dev_priv)) {
766 		dmc->fw_path = KBL_DMC_PATH;
767 		dmc->required_version = KBL_DMC_VERSION_REQUIRED;
768 		dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
769 	} else if (IS_SKYLAKE(dev_priv)) {
770 		dmc->fw_path = SKL_DMC_PATH;
771 		dmc->required_version = SKL_DMC_VERSION_REQUIRED;
772 		dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
773 	} else if (IS_BROXTON(dev_priv)) {
774 		dmc->fw_path = BXT_DMC_PATH;
775 		dmc->required_version = BXT_DMC_VERSION_REQUIRED;
776 		dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
777 	}
778 
779 	if (dev_priv->params.dmc_firmware_path) {
780 		if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
781 			dmc->fw_path = NULL;
782 			drm_info(&dev_priv->drm,
783 				 "Disabling DMC firmware and runtime PM\n");
784 			return;
785 		}
786 
787 		dmc->fw_path = dev_priv->params.dmc_firmware_path;
788 		/* Bypass version check for firmware override. */
789 		dmc->required_version = 0;
790 	}
791 
792 	if (!dmc->fw_path) {
793 		drm_dbg_kms(&dev_priv->drm,
794 			    "No known DMC firmware for platform, disabling runtime PM\n");
795 		return;
796 	}
797 
798 	drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
799 	schedule_work(&dev_priv->dmc.work);
800 }
801 
802 /**
803  * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend
804  * @dev_priv: i915 drm device
805  *
806  * Prepare the DMC firmware before entering system suspend. This includes
807  * flushing pending work items and releasing any resources acquired during
808  * init.
809  */
intel_dmc_ucode_suspend(struct drm_i915_private * dev_priv)810 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
811 {
812 	if (!HAS_DMC(dev_priv))
813 		return;
814 
815 	flush_work(&dev_priv->dmc.work);
816 
817 	/* Drop the reference held in case DMC isn't loaded. */
818 	if (!intel_dmc_has_payload(dev_priv))
819 		intel_dmc_runtime_pm_put(dev_priv);
820 }
821 
822 /**
823  * intel_dmc_ucode_resume() - init DMC firmware during system resume
824  * @dev_priv: i915 drm device
825  *
826  * Reinitialize the DMC firmware during system resume, reacquiring any
827  * resources released in intel_dmc_ucode_suspend().
828  */
intel_dmc_ucode_resume(struct drm_i915_private * dev_priv)829 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
830 {
831 	if (!HAS_DMC(dev_priv))
832 		return;
833 
834 	/*
835 	 * Reacquire the reference to keep RPM disabled in case DMC isn't
836 	 * loaded.
837 	 */
838 	if (!intel_dmc_has_payload(dev_priv))
839 		intel_dmc_runtime_pm_get(dev_priv);
840 }
841 
842 /**
843  * intel_dmc_ucode_fini() - unload the DMC firmware.
844  * @dev_priv: i915 drm device.
845  *
846  * Firmmware unloading includes freeing the internal memory and reset the
847  * firmware loading status.
848  */
intel_dmc_ucode_fini(struct drm_i915_private * dev_priv)849 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
850 {
851 	int id;
852 
853 	if (!HAS_DMC(dev_priv))
854 		return;
855 
856 	intel_dmc_ucode_suspend(dev_priv);
857 	drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
858 
859 	for (id = 0; id < DMC_FW_MAX; id++)
860 		kfree(dev_priv->dmc.dmc_info[id].payload);
861 }
862 
intel_dmc_print_error_state(struct drm_i915_error_state_buf * m,struct drm_i915_private * i915)863 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
864 				 struct drm_i915_private *i915)
865 {
866 	struct intel_dmc *dmc = &i915->dmc;
867 
868 	if (!HAS_DMC(i915))
869 		return;
870 
871 	i915_error_printf(m, "DMC loaded: %s\n",
872 			  str_yes_no(intel_dmc_has_payload(i915)));
873 	i915_error_printf(m, "DMC fw version: %d.%d\n",
874 			  DMC_VERSION_MAJOR(dmc->version),
875 			  DMC_VERSION_MINOR(dmc->version));
876 }
877 
intel_dmc_debugfs_status_show(struct seq_file * m,void * unused)878 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
879 {
880 	struct drm_i915_private *i915 = m->private;
881 	intel_wakeref_t wakeref;
882 	struct intel_dmc *dmc;
883 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
884 
885 	if (!HAS_DMC(i915))
886 		return -ENODEV;
887 
888 	dmc = &i915->dmc;
889 
890 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
891 
892 	seq_printf(m, "fw loaded: %s\n",
893 		   str_yes_no(intel_dmc_has_payload(i915)));
894 	seq_printf(m, "path: %s\n", dmc->fw_path);
895 	seq_printf(m, "Pipe A fw support: %s\n",
896 		   str_yes_no(GRAPHICS_VER(i915) >= 12));
897 	seq_printf(m, "Pipe A fw loaded: %s\n",
898 		   str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
899 	seq_printf(m, "Pipe B fw support: %s\n",
900 		   str_yes_no(IS_ALDERLAKE_P(i915)));
901 	seq_printf(m, "Pipe B fw loaded: %s\n",
902 		   str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
903 
904 	if (!intel_dmc_has_payload(i915))
905 		goto out;
906 
907 	seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
908 		   DMC_VERSION_MINOR(dmc->version));
909 
910 	if (DISPLAY_VER(i915) >= 12) {
911 		if (IS_DGFX(i915)) {
912 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
913 		} else {
914 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
915 			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
916 		}
917 
918 		/*
919 		 * NOTE: DMC_DEBUG3 is a general purpose reg.
920 		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
921 		 * reg for DC3CO debugging and validation,
922 		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
923 		 */
924 		seq_printf(m, "DC3CO count: %d\n",
925 			   intel_de_read(i915, IS_DGFX(i915) ?
926 					 DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
927 	} else {
928 		dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
929 			SKL_DMC_DC3_DC5_COUNT;
930 		if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))
931 			dc6_reg = SKL_DMC_DC5_DC6_COUNT;
932 	}
933 
934 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
935 	if (i915_mmio_reg_valid(dc6_reg))
936 		seq_printf(m, "DC5 -> DC6 count: %d\n",
937 			   intel_de_read(i915, dc6_reg));
938 
939 out:
940 	seq_printf(m, "program base: 0x%08x\n",
941 		   intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
942 	seq_printf(m, "ssp base: 0x%08x\n",
943 		   intel_de_read(i915, DMC_SSP_BASE));
944 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL));
945 
946 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
947 
948 	return 0;
949 }
950 
951 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
952 
intel_dmc_debugfs_register(struct drm_i915_private * i915)953 void intel_dmc_debugfs_register(struct drm_i915_private *i915)
954 {
955 	struct drm_minor *minor = i915->drm.primary;
956 
957 	debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
958 			    i915, &intel_dmc_debugfs_status_fops);
959 }
960