1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/string_helpers.h>
29
30 #include <drm/display/drm_scdc_helper.h>
31 #include <drm/drm_privacy_screen_consumer.h>
32
33 #include "i915_drv.h"
34 #include "intel_audio.h"
35 #include "intel_audio_regs.h"
36 #include "intel_backlight.h"
37 #include "intel_combo_phy.h"
38 #include "intel_combo_phy_regs.h"
39 #include "intel_connector.h"
40 #include "intel_crtc.h"
41 #include "intel_ddi.h"
42 #include "intel_ddi_buf_trans.h"
43 #include "intel_de.h"
44 #include "intel_display_power.h"
45 #include "intel_display_types.h"
46 #include "intel_dkl_phy.h"
47 #include "intel_dp.h"
48 #include "intel_dp_link_training.h"
49 #include "intel_dp_mst.h"
50 #include "intel_dpio_phy.h"
51 #include "intel_dsi.h"
52 #include "intel_fdi.h"
53 #include "intel_fifo_underrun.h"
54 #include "intel_gmbus.h"
55 #include "intel_hdcp.h"
56 #include "intel_hdmi.h"
57 #include "intel_hotplug.h"
58 #include "intel_lspcon.h"
59 #include "intel_pps.h"
60 #include "intel_psr.h"
61 #include "intel_quirks.h"
62 #include "intel_snps_phy.h"
63 #include "intel_sprite.h"
64 #include "intel_tc.h"
65 #include "intel_tc_phy_regs.h"
66 #include "intel_vdsc.h"
67 #include "intel_vrr.h"
68 #include "skl_scaler.h"
69 #include "skl_universal_plane.h"
70
71 static const u8 index_to_dp_signal_levels[] = {
72 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
73 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
74 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
75 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
76 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
77 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
78 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
79 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
80 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
81 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
82 };
83
intel_ddi_hdmi_level(struct intel_encoder * encoder,const struct intel_ddi_buf_trans * trans)84 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
85 const struct intel_ddi_buf_trans *trans)
86 {
87 int level;
88
89 level = intel_bios_hdmi_level_shift(encoder);
90 if (level < 0)
91 level = trans->hdmi_default_entry;
92
93 return level;
94 }
95
has_buf_trans_select(struct drm_i915_private * i915)96 static bool has_buf_trans_select(struct drm_i915_private *i915)
97 {
98 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
99 }
100
has_iboost(struct drm_i915_private * i915)101 static bool has_iboost(struct drm_i915_private *i915)
102 {
103 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
104 }
105
106 /*
107 * Starting with Haswell, DDI port buffers must be programmed with correct
108 * values in advance. This function programs the correct values for
109 * DP/eDP/FDI use cases.
110 */
hsw_prepare_dp_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)111 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
112 const struct intel_crtc_state *crtc_state)
113 {
114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
115 u32 iboost_bit = 0;
116 int i, n_entries;
117 enum port port = encoder->port;
118 const struct intel_ddi_buf_trans *trans;
119
120 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
121 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
122 return;
123
124 /* If we're boosting the current, set bit 31 of trans1 */
125 if (has_iboost(dev_priv) &&
126 intel_bios_encoder_dp_boost_level(encoder->devdata))
127 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
128
129 for (i = 0; i < n_entries; i++) {
130 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
131 trans->entries[i].hsw.trans1 | iboost_bit);
132 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
133 trans->entries[i].hsw.trans2);
134 }
135 }
136
137 /*
138 * Starting with Haswell, DDI port buffers must be programmed with correct
139 * values in advance. This function programs the correct values for
140 * HDMI/DVI use cases.
141 */
hsw_prepare_hdmi_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)142 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
143 const struct intel_crtc_state *crtc_state)
144 {
145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
146 int level = intel_ddi_level(encoder, crtc_state, 0);
147 u32 iboost_bit = 0;
148 int n_entries;
149 enum port port = encoder->port;
150 const struct intel_ddi_buf_trans *trans;
151
152 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
153 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
154 return;
155
156 /* If we're boosting the current, set bit 31 of trans1 */
157 if (has_iboost(dev_priv) &&
158 intel_bios_encoder_hdmi_boost_level(encoder->devdata))
159 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
160
161 /* Entry 9 is for HDMI: */
162 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
163 trans->entries[level].hsw.trans1 | iboost_bit);
164 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
165 trans->entries[level].hsw.trans2);
166 }
167
intel_wait_ddi_buf_idle(struct drm_i915_private * dev_priv,enum port port)168 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
169 enum port port)
170 {
171 if (IS_BROXTON(dev_priv)) {
172 udelay(16);
173 return;
174 }
175
176 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
177 DDI_BUF_IS_IDLE), 8))
178 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
179 port_name(port));
180 }
181
intel_wait_ddi_buf_active(struct drm_i915_private * dev_priv,enum port port)182 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
183 enum port port)
184 {
185 int ret;
186
187 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
188 if (DISPLAY_VER(dev_priv) < 10) {
189 usleep_range(518, 1000);
190 return;
191 }
192
193 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
194 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
195
196 if (ret)
197 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
198 port_name(port));
199 }
200
hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll * pll)201 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
202 {
203 switch (pll->info->id) {
204 case DPLL_ID_WRPLL1:
205 return PORT_CLK_SEL_WRPLL1;
206 case DPLL_ID_WRPLL2:
207 return PORT_CLK_SEL_WRPLL2;
208 case DPLL_ID_SPLL:
209 return PORT_CLK_SEL_SPLL;
210 case DPLL_ID_LCPLL_810:
211 return PORT_CLK_SEL_LCPLL_810;
212 case DPLL_ID_LCPLL_1350:
213 return PORT_CLK_SEL_LCPLL_1350;
214 case DPLL_ID_LCPLL_2700:
215 return PORT_CLK_SEL_LCPLL_2700;
216 default:
217 MISSING_CASE(pll->info->id);
218 return PORT_CLK_SEL_NONE;
219 }
220 }
221
icl_pll_to_ddi_clk_sel(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)222 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
223 const struct intel_crtc_state *crtc_state)
224 {
225 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
226 int clock = crtc_state->port_clock;
227 const enum intel_dpll_id id = pll->info->id;
228
229 switch (id) {
230 default:
231 /*
232 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
233 * here, so do warn if this get passed in
234 */
235 MISSING_CASE(id);
236 return DDI_CLK_SEL_NONE;
237 case DPLL_ID_ICL_TBTPLL:
238 switch (clock) {
239 case 162000:
240 return DDI_CLK_SEL_TBT_162;
241 case 270000:
242 return DDI_CLK_SEL_TBT_270;
243 case 540000:
244 return DDI_CLK_SEL_TBT_540;
245 case 810000:
246 return DDI_CLK_SEL_TBT_810;
247 default:
248 MISSING_CASE(clock);
249 return DDI_CLK_SEL_NONE;
250 }
251 case DPLL_ID_ICL_MGPLL1:
252 case DPLL_ID_ICL_MGPLL2:
253 case DPLL_ID_ICL_MGPLL3:
254 case DPLL_ID_ICL_MGPLL4:
255 case DPLL_ID_TGL_MGPLL5:
256 case DPLL_ID_TGL_MGPLL6:
257 return DDI_CLK_SEL_MG;
258 }
259 }
260
ddi_buf_phy_link_rate(int port_clock)261 static u32 ddi_buf_phy_link_rate(int port_clock)
262 {
263 switch (port_clock) {
264 case 162000:
265 return DDI_BUF_PHY_LINK_RATE(0);
266 case 216000:
267 return DDI_BUF_PHY_LINK_RATE(4);
268 case 243000:
269 return DDI_BUF_PHY_LINK_RATE(5);
270 case 270000:
271 return DDI_BUF_PHY_LINK_RATE(1);
272 case 324000:
273 return DDI_BUF_PHY_LINK_RATE(6);
274 case 432000:
275 return DDI_BUF_PHY_LINK_RATE(7);
276 case 540000:
277 return DDI_BUF_PHY_LINK_RATE(2);
278 case 810000:
279 return DDI_BUF_PHY_LINK_RATE(3);
280 default:
281 MISSING_CASE(port_clock);
282 return DDI_BUF_PHY_LINK_RATE(0);
283 }
284 }
285
intel_ddi_init_dp_buf_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)286 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
287 const struct intel_crtc_state *crtc_state)
288 {
289 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
290 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
291 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
292 enum phy phy = intel_port_to_phy(i915, encoder->port);
293
294 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
295 intel_dp->DP = dig_port->saved_port_bits |
296 DDI_PORT_WIDTH(crtc_state->lane_count) |
297 DDI_BUF_TRANS_SELECT(0);
298
299 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
300 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
301 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
302 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
303 }
304 }
305
icl_calc_tbt_pll_link(struct drm_i915_private * dev_priv,enum port port)306 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
307 enum port port)
308 {
309 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
310
311 switch (val) {
312 case DDI_CLK_SEL_NONE:
313 return 0;
314 case DDI_CLK_SEL_TBT_162:
315 return 162000;
316 case DDI_CLK_SEL_TBT_270:
317 return 270000;
318 case DDI_CLK_SEL_TBT_540:
319 return 540000;
320 case DDI_CLK_SEL_TBT_810:
321 return 810000;
322 default:
323 MISSING_CASE(val);
324 return 0;
325 }
326 }
327
ddi_dotclock_get(struct intel_crtc_state * pipe_config)328 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
329 {
330 /* CRT dotclock is determined via other means */
331 if (pipe_config->has_pch_encoder)
332 return;
333
334 pipe_config->hw.adjusted_mode.crtc_clock =
335 intel_crtc_dotclock(pipe_config);
336 }
337
intel_ddi_set_dp_msa(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)338 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
339 const struct drm_connector_state *conn_state)
340 {
341 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
342 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
343 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
344 u32 temp;
345
346 if (!intel_crtc_has_dp_encoder(crtc_state))
347 return;
348
349 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
350
351 temp = DP_MSA_MISC_SYNC_CLOCK;
352
353 switch (crtc_state->pipe_bpp) {
354 case 18:
355 temp |= DP_MSA_MISC_6_BPC;
356 break;
357 case 24:
358 temp |= DP_MSA_MISC_8_BPC;
359 break;
360 case 30:
361 temp |= DP_MSA_MISC_10_BPC;
362 break;
363 case 36:
364 temp |= DP_MSA_MISC_12_BPC;
365 break;
366 default:
367 MISSING_CASE(crtc_state->pipe_bpp);
368 break;
369 }
370
371 /* nonsense combination */
372 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
373 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
374
375 if (crtc_state->limited_color_range)
376 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
377
378 /*
379 * As per DP 1.2 spec section 2.3.4.3 while sending
380 * YCBCR 444 signals we should program MSA MISC1/0 fields with
381 * colorspace information.
382 */
383 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
384 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
385
386 /*
387 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
388 * of Color Encoding Format and Content Color Gamut] while sending
389 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
390 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
391 */
392 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
393 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
394
395 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
396 }
397
bdw_trans_port_sync_master_select(enum transcoder master_transcoder)398 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
399 {
400 if (master_transcoder == TRANSCODER_EDP)
401 return 0;
402 else
403 return master_transcoder + 1;
404 }
405
406 static void
intel_ddi_config_transcoder_dp2(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)407 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
408 const struct intel_crtc_state *crtc_state)
409 {
410 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
411 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
412 u32 val = 0;
413
414 if (intel_dp_is_uhbr(crtc_state))
415 val = TRANS_DP2_128B132B_CHANNEL_CODING;
416
417 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
418 }
419
420 /*
421 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
422 *
423 * Only intended to be used by intel_ddi_enable_transcoder_func() and
424 * intel_ddi_config_transcoder_func().
425 */
426 static u32
intel_ddi_transcoder_func_reg_val_get(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)427 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
428 const struct intel_crtc_state *crtc_state)
429 {
430 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
432 enum pipe pipe = crtc->pipe;
433 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
434 enum port port = encoder->port;
435 u32 temp;
436
437 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
438 temp = TRANS_DDI_FUNC_ENABLE;
439 if (DISPLAY_VER(dev_priv) >= 12)
440 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
441 else
442 temp |= TRANS_DDI_SELECT_PORT(port);
443
444 switch (crtc_state->pipe_bpp) {
445 default:
446 MISSING_CASE(crtc_state->pipe_bpp);
447 fallthrough;
448 case 18:
449 temp |= TRANS_DDI_BPC_6;
450 break;
451 case 24:
452 temp |= TRANS_DDI_BPC_8;
453 break;
454 case 30:
455 temp |= TRANS_DDI_BPC_10;
456 break;
457 case 36:
458 temp |= TRANS_DDI_BPC_12;
459 break;
460 }
461
462 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
463 temp |= TRANS_DDI_PVSYNC;
464 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
465 temp |= TRANS_DDI_PHSYNC;
466
467 if (cpu_transcoder == TRANSCODER_EDP) {
468 switch (pipe) {
469 default:
470 MISSING_CASE(pipe);
471 fallthrough;
472 case PIPE_A:
473 /* On Haswell, can only use the always-on power well for
474 * eDP when not using the panel fitter, and when not
475 * using motion blur mitigation (which we don't
476 * support). */
477 if (crtc_state->pch_pfit.force_thru)
478 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
479 else
480 temp |= TRANS_DDI_EDP_INPUT_A_ON;
481 break;
482 case PIPE_B:
483 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
484 break;
485 case PIPE_C:
486 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
487 break;
488 }
489 }
490
491 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
492 if (crtc_state->has_hdmi_sink)
493 temp |= TRANS_DDI_MODE_SELECT_HDMI;
494 else
495 temp |= TRANS_DDI_MODE_SELECT_DVI;
496
497 if (crtc_state->hdmi_scrambling)
498 temp |= TRANS_DDI_HDMI_SCRAMBLING;
499 if (crtc_state->hdmi_high_tmds_clock_ratio)
500 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
501 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
503 temp |= (crtc_state->fdi_lanes - 1) << 1;
504 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
505 if (intel_dp_is_uhbr(crtc_state))
506 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
507 else
508 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
509 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
510
511 if (DISPLAY_VER(dev_priv) >= 12) {
512 enum transcoder master;
513
514 master = crtc_state->mst_master_transcoder;
515 drm_WARN_ON(&dev_priv->drm,
516 master == INVALID_TRANSCODER);
517 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
518 }
519 } else {
520 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
521 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
522 }
523
524 if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
525 crtc_state->master_transcoder != INVALID_TRANSCODER) {
526 u8 master_select =
527 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
528
529 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
530 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
531 }
532
533 return temp;
534 }
535
intel_ddi_enable_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)536 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
537 const struct intel_crtc_state *crtc_state)
538 {
539 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
541 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
542
543 if (DISPLAY_VER(dev_priv) >= 11) {
544 enum transcoder master_transcoder = crtc_state->master_transcoder;
545 u32 ctl2 = 0;
546
547 if (master_transcoder != INVALID_TRANSCODER) {
548 u8 master_select =
549 bdw_trans_port_sync_master_select(master_transcoder);
550
551 ctl2 |= PORT_SYNC_MODE_ENABLE |
552 PORT_SYNC_MODE_MASTER_SELECT(master_select);
553 }
554
555 intel_de_write(dev_priv,
556 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
557 }
558
559 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
560 intel_ddi_transcoder_func_reg_val_get(encoder,
561 crtc_state));
562 }
563
564 /*
565 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
566 * bit.
567 */
568 static void
intel_ddi_config_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)569 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
570 const struct intel_crtc_state *crtc_state)
571 {
572 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
574 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
575 u32 ctl;
576
577 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
578 ctl &= ~TRANS_DDI_FUNC_ENABLE;
579 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
580 }
581
intel_ddi_disable_transcoder_func(const struct intel_crtc_state * crtc_state)582 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
583 {
584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
586 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
587 u32 ctl;
588
589 if (DISPLAY_VER(dev_priv) >= 11)
590 intel_de_write(dev_priv,
591 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
592
593 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
594
595 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
596
597 ctl &= ~TRANS_DDI_FUNC_ENABLE;
598
599 if (IS_DISPLAY_VER(dev_priv, 8, 10))
600 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
601 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
602
603 if (DISPLAY_VER(dev_priv) >= 12) {
604 if (!intel_dp_mst_is_master_trans(crtc_state)) {
605 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
606 TRANS_DDI_MODE_SELECT_MASK);
607 }
608 } else {
609 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
610 }
611
612 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
613
614 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
615 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
616 drm_dbg_kms(&dev_priv->drm,
617 "Quirk Increase DDI disabled time\n");
618 /* Quirk time at 100ms for reliable operation */
619 msleep(100);
620 }
621 }
622
intel_ddi_toggle_hdcp_bits(struct intel_encoder * intel_encoder,enum transcoder cpu_transcoder,bool enable,u32 hdcp_mask)623 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
624 enum transcoder cpu_transcoder,
625 bool enable, u32 hdcp_mask)
626 {
627 struct drm_device *dev = intel_encoder->base.dev;
628 struct drm_i915_private *dev_priv = to_i915(dev);
629 intel_wakeref_t wakeref;
630 int ret = 0;
631 u32 tmp;
632
633 wakeref = intel_display_power_get_if_enabled(dev_priv,
634 intel_encoder->power_domain);
635 if (drm_WARN_ON(dev, !wakeref))
636 return -ENXIO;
637
638 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
639 if (enable)
640 tmp |= hdcp_mask;
641 else
642 tmp &= ~hdcp_mask;
643 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
644 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
645 return ret;
646 }
647
intel_ddi_connector_get_hw_state(struct intel_connector * intel_connector)648 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
649 {
650 struct drm_device *dev = intel_connector->base.dev;
651 struct drm_i915_private *dev_priv = to_i915(dev);
652 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
653 int type = intel_connector->base.connector_type;
654 enum port port = encoder->port;
655 enum transcoder cpu_transcoder;
656 intel_wakeref_t wakeref;
657 enum pipe pipe = 0;
658 u32 tmp;
659 bool ret;
660
661 wakeref = intel_display_power_get_if_enabled(dev_priv,
662 encoder->power_domain);
663 if (!wakeref)
664 return false;
665
666 if (!encoder->get_hw_state(encoder, &pipe)) {
667 ret = false;
668 goto out;
669 }
670
671 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
672 cpu_transcoder = TRANSCODER_EDP;
673 else
674 cpu_transcoder = (enum transcoder) pipe;
675
676 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
677
678 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
679 case TRANS_DDI_MODE_SELECT_HDMI:
680 case TRANS_DDI_MODE_SELECT_DVI:
681 ret = type == DRM_MODE_CONNECTOR_HDMIA;
682 break;
683
684 case TRANS_DDI_MODE_SELECT_DP_SST:
685 ret = type == DRM_MODE_CONNECTOR_eDP ||
686 type == DRM_MODE_CONNECTOR_DisplayPort;
687 break;
688
689 case TRANS_DDI_MODE_SELECT_DP_MST:
690 /* if the transcoder is in MST state then
691 * connector isn't connected */
692 ret = false;
693 break;
694
695 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
696 if (HAS_DP20(dev_priv))
697 /* 128b/132b */
698 ret = false;
699 else
700 /* FDI */
701 ret = type == DRM_MODE_CONNECTOR_VGA;
702 break;
703
704 default:
705 ret = false;
706 break;
707 }
708
709 out:
710 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
711
712 return ret;
713 }
714
intel_ddi_get_encoder_pipes(struct intel_encoder * encoder,u8 * pipe_mask,bool * is_dp_mst)715 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
716 u8 *pipe_mask, bool *is_dp_mst)
717 {
718 struct drm_device *dev = encoder->base.dev;
719 struct drm_i915_private *dev_priv = to_i915(dev);
720 enum port port = encoder->port;
721 intel_wakeref_t wakeref;
722 enum pipe p;
723 u32 tmp;
724 u8 mst_pipe_mask;
725
726 *pipe_mask = 0;
727 *is_dp_mst = false;
728
729 wakeref = intel_display_power_get_if_enabled(dev_priv,
730 encoder->power_domain);
731 if (!wakeref)
732 return;
733
734 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
735 if (!(tmp & DDI_BUF_CTL_ENABLE))
736 goto out;
737
738 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
739 tmp = intel_de_read(dev_priv,
740 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
741
742 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
743 default:
744 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
745 fallthrough;
746 case TRANS_DDI_EDP_INPUT_A_ON:
747 case TRANS_DDI_EDP_INPUT_A_ONOFF:
748 *pipe_mask = BIT(PIPE_A);
749 break;
750 case TRANS_DDI_EDP_INPUT_B_ONOFF:
751 *pipe_mask = BIT(PIPE_B);
752 break;
753 case TRANS_DDI_EDP_INPUT_C_ONOFF:
754 *pipe_mask = BIT(PIPE_C);
755 break;
756 }
757
758 goto out;
759 }
760
761 mst_pipe_mask = 0;
762 for_each_pipe(dev_priv, p) {
763 enum transcoder cpu_transcoder = (enum transcoder)p;
764 unsigned int port_mask, ddi_select;
765 intel_wakeref_t trans_wakeref;
766
767 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
768 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
769 if (!trans_wakeref)
770 continue;
771
772 if (DISPLAY_VER(dev_priv) >= 12) {
773 port_mask = TGL_TRANS_DDI_PORT_MASK;
774 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
775 } else {
776 port_mask = TRANS_DDI_PORT_MASK;
777 ddi_select = TRANS_DDI_SELECT_PORT(port);
778 }
779
780 tmp = intel_de_read(dev_priv,
781 TRANS_DDI_FUNC_CTL(cpu_transcoder));
782 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
783 trans_wakeref);
784
785 if ((tmp & port_mask) != ddi_select)
786 continue;
787
788 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
789 (HAS_DP20(dev_priv) &&
790 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
791 mst_pipe_mask |= BIT(p);
792
793 *pipe_mask |= BIT(p);
794 }
795
796 if (!*pipe_mask)
797 drm_dbg_kms(&dev_priv->drm,
798 "No pipe for [ENCODER:%d:%s] found\n",
799 encoder->base.base.id, encoder->base.name);
800
801 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
802 drm_dbg_kms(&dev_priv->drm,
803 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
804 encoder->base.base.id, encoder->base.name,
805 *pipe_mask);
806 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
807 }
808
809 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
810 drm_dbg_kms(&dev_priv->drm,
811 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
812 encoder->base.base.id, encoder->base.name,
813 *pipe_mask, mst_pipe_mask);
814 else
815 *is_dp_mst = mst_pipe_mask;
816
817 out:
818 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
819 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
820 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
821 BXT_PHY_LANE_POWERDOWN_ACK |
822 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
823 drm_err(&dev_priv->drm,
824 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
825 encoder->base.base.id, encoder->base.name, tmp);
826 }
827
828 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
829 }
830
intel_ddi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)831 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
832 enum pipe *pipe)
833 {
834 u8 pipe_mask;
835 bool is_mst;
836
837 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
838
839 if (is_mst || !pipe_mask)
840 return false;
841
842 *pipe = ffs(pipe_mask) - 1;
843
844 return true;
845 }
846
847 static enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_digital_port * dig_port)848 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
849 {
850 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
851 * DC states enabled at the same time, while for driver initiated AUX
852 * transfers we need the same AUX IOs to be powered but with DC states
853 * disabled. Accordingly use the AUX power domain here which leaves DC
854 * states enabled.
855 * However, for non-A AUX ports the corresponding non-EDP transcoders
856 * would have already enabled power well 2 and DC_OFF. This means we can
857 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
858 * specific AUX_IO reference without powering up any extra wells.
859 * Note that PSR is enabled only on Port A even though this function
860 * returns the correct domain for other ports too.
861 */
862 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
863 intel_aux_power_domain(dig_port);
864 }
865
intel_ddi_get_power_domains(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)866 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
867 struct intel_crtc_state *crtc_state)
868 {
869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
870 struct intel_digital_port *dig_port;
871 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
872
873 /*
874 * TODO: Add support for MST encoders. Atm, the following should never
875 * happen since fake-MST encoders don't set their get_power_domains()
876 * hook.
877 */
878 if (drm_WARN_ON(&dev_priv->drm,
879 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
880 return;
881
882 dig_port = enc_to_dig_port(encoder);
883
884 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
885 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
886 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
887 dig_port->ddi_io_power_domain);
888 }
889
890 /*
891 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
892 * ports.
893 */
894 if (intel_crtc_has_dp_encoder(crtc_state) ||
895 intel_phy_is_tc(dev_priv, phy)) {
896 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
897 dig_port->aux_wakeref =
898 intel_display_power_get(dev_priv,
899 intel_ddi_main_link_aux_domain(dig_port));
900 }
901 }
902
intel_ddi_enable_pipe_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)903 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
904 const struct intel_crtc_state *crtc_state)
905 {
906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
907 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
908 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
909 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
910 u32 val;
911
912 if (cpu_transcoder != TRANSCODER_EDP) {
913 if (DISPLAY_VER(dev_priv) >= 13)
914 val = TGL_TRANS_CLK_SEL_PORT(phy);
915 else if (DISPLAY_VER(dev_priv) >= 12)
916 val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
917 else
918 val = TRANS_CLK_SEL_PORT(encoder->port);
919
920 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
921 }
922 }
923
intel_ddi_disable_pipe_clock(const struct intel_crtc_state * crtc_state)924 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
925 {
926 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
927 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
928
929 if (cpu_transcoder != TRANSCODER_EDP) {
930 if (DISPLAY_VER(dev_priv) >= 12)
931 intel_de_write(dev_priv,
932 TRANS_CLK_SEL(cpu_transcoder),
933 TGL_TRANS_CLK_SEL_DISABLED);
934 else
935 intel_de_write(dev_priv,
936 TRANS_CLK_SEL(cpu_transcoder),
937 TRANS_CLK_SEL_DISABLED);
938 }
939 }
940
_skl_ddi_set_iboost(struct drm_i915_private * dev_priv,enum port port,u8 iboost)941 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
942 enum port port, u8 iboost)
943 {
944 u32 tmp;
945
946 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
947 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
948 if (iboost)
949 tmp |= iboost << BALANCE_LEG_SHIFT(port);
950 else
951 tmp |= BALANCE_LEG_DISABLE(port);
952 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
953 }
954
skl_ddi_set_iboost(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int level)955 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
956 const struct intel_crtc_state *crtc_state,
957 int level)
958 {
959 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
960 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
961 u8 iboost;
962
963 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
964 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
965 else
966 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
967
968 if (iboost == 0) {
969 const struct intel_ddi_buf_trans *trans;
970 int n_entries;
971
972 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
973 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
974 return;
975
976 iboost = trans->entries[level].hsw.i_boost;
977 }
978
979 /* Make sure that the requested I_boost is valid */
980 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
981 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
982 return;
983 }
984
985 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
986
987 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
988 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
989 }
990
intel_ddi_dp_voltage_max(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)991 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
992 const struct intel_crtc_state *crtc_state)
993 {
994 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
996 int n_entries;
997
998 encoder->get_buf_trans(encoder, crtc_state, &n_entries);
999
1000 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1001 n_entries = 1;
1002 if (drm_WARN_ON(&dev_priv->drm,
1003 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1004 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1005
1006 return index_to_dp_signal_levels[n_entries - 1] &
1007 DP_TRAIN_VOLTAGE_SWING_MASK;
1008 }
1009
1010 /*
1011 * We assume that the full set of pre-emphasis values can be
1012 * used on all DDI platforms. Should that change we need to
1013 * rethink this code.
1014 */
intel_ddi_dp_preemph_max(struct intel_dp * intel_dp)1015 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1016 {
1017 return DP_TRAIN_PRE_EMPH_LEVEL_3;
1018 }
1019
icl_combo_phy_loadgen_select(const struct intel_crtc_state * crtc_state,int lane)1020 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1021 int lane)
1022 {
1023 if (crtc_state->port_clock > 600000)
1024 return 0;
1025
1026 if (crtc_state->lane_count == 4)
1027 return lane >= 1 ? LOADGEN_SELECT : 0;
1028 else
1029 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1030 }
1031
icl_ddi_combo_vswing_program(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1032 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1033 const struct intel_crtc_state *crtc_state)
1034 {
1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1036 const struct intel_ddi_buf_trans *trans;
1037 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1038 int n_entries, ln;
1039 u32 val;
1040
1041 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1042 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1043 return;
1044
1045 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1046 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1047
1048 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1049 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1050 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1051 intel_dp->hobl_active ? val : 0);
1052 }
1053
1054 /* Set PORT_TX_DW5 */
1055 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1056 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1057 TAP2_DISABLE | TAP3_DISABLE);
1058 val |= SCALING_MODE_SEL(0x2);
1059 val |= RTERM_SELECT(0x6);
1060 val |= TAP3_DISABLE;
1061 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1062
1063 /* Program PORT_TX_DW2 */
1064 for (ln = 0; ln < 4; ln++) {
1065 int level = intel_ddi_level(encoder, crtc_state, ln);
1066
1067 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1068 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1069 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1070 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1071 RCOMP_SCALAR(0x98));
1072 }
1073
1074 /* Program PORT_TX_DW4 */
1075 /* We cannot write to GRP. It would overwrite individual loadgen. */
1076 for (ln = 0; ln < 4; ln++) {
1077 int level = intel_ddi_level(encoder, crtc_state, ln);
1078
1079 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1080 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1081 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1082 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1083 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1084 }
1085
1086 /* Program PORT_TX_DW7 */
1087 for (ln = 0; ln < 4; ln++) {
1088 int level = intel_ddi_level(encoder, crtc_state, ln);
1089
1090 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1091 N_SCALAR_MASK,
1092 N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1093 }
1094 }
1095
icl_combo_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1096 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1097 const struct intel_crtc_state *crtc_state)
1098 {
1099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1100 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1101 u32 val;
1102 int ln;
1103
1104 /*
1105 * 1. If port type is eDP or DP,
1106 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1107 * else clear to 0b.
1108 */
1109 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1110 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1111 val &= ~COMMON_KEEPER_EN;
1112 else
1113 val |= COMMON_KEEPER_EN;
1114 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1115
1116 /* 2. Program loadgen select */
1117 /*
1118 * Program PORT_TX_DW4 depending on Bit rate and used lanes
1119 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1120 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1121 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1122 */
1123 for (ln = 0; ln < 4; ln++) {
1124 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1125 LOADGEN_SELECT,
1126 icl_combo_phy_loadgen_select(crtc_state, ln));
1127 }
1128
1129 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1130 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
1131 0, SUS_CLOCK_CONFIG);
1132
1133 /* 4. Clear training enable to change swing values */
1134 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1135 val &= ~TX_TRAINING_EN;
1136 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1137
1138 /* 5. Program swing and de-emphasis */
1139 icl_ddi_combo_vswing_program(encoder, crtc_state);
1140
1141 /* 6. Set training enable to trigger update */
1142 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1143 val |= TX_TRAINING_EN;
1144 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1145 }
1146
icl_mg_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1147 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1148 const struct intel_crtc_state *crtc_state)
1149 {
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1151 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1152 const struct intel_ddi_buf_trans *trans;
1153 int n_entries, ln;
1154
1155 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1156 return;
1157
1158 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1159 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1160 return;
1161
1162 for (ln = 0; ln < 2; ln++) {
1163 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1164 CRI_USE_FS32, 0);
1165 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1166 CRI_USE_FS32, 0);
1167 }
1168
1169 /* Program MG_TX_SWINGCTRL with values from vswing table */
1170 for (ln = 0; ln < 2; ln++) {
1171 int level;
1172
1173 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1174
1175 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1176 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1177 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1178
1179 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1180
1181 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1182 CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1183 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1184 }
1185
1186 /* Program MG_TX_DRVCTRL with values from vswing table */
1187 for (ln = 0; ln < 2; ln++) {
1188 int level;
1189
1190 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1191
1192 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1193 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1194 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1195 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1196 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1197 CRI_TXDEEMPH_OVERRIDE_EN);
1198
1199 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1200
1201 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1202 CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1203 CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1204 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1205 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1206 CRI_TXDEEMPH_OVERRIDE_EN);
1207
1208 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1209 }
1210
1211 /*
1212 * Program MG_CLKHUB<LN, port being used> with value from frequency table
1213 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1214 * values from table for which TX1 and TX2 enabled.
1215 */
1216 for (ln = 0; ln < 2; ln++) {
1217 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1218 CFG_LOW_RATE_LKREN_EN,
1219 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1220 }
1221
1222 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1223 for (ln = 0; ln < 2; ln++) {
1224 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1225 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1226 CFG_AMI_CK_DIV_OVERRIDE_EN,
1227 crtc_state->port_clock > 500000 ?
1228 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1229 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1230
1231 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1232 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1233 CFG_AMI_CK_DIV_OVERRIDE_EN,
1234 crtc_state->port_clock > 500000 ?
1235 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1236 CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1237 }
1238
1239 /* Program MG_TX_PISO_READLOAD with values from vswing table */
1240 for (ln = 0; ln < 2; ln++) {
1241 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1242 0, CRI_CALCINIT);
1243 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1244 0, CRI_CALCINIT);
1245 }
1246 }
1247
tgl_dkl_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1248 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1249 const struct intel_crtc_state *crtc_state)
1250 {
1251 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1252 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1253 const struct intel_ddi_buf_trans *trans;
1254 int n_entries, ln;
1255
1256 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1257 return;
1258
1259 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1260 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1261 return;
1262
1263 for (ln = 0; ln < 2; ln++) {
1264 int level;
1265
1266 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 0);
1267
1268 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1269
1270 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
1271 DKL_TX_PRESHOOT_COEFF_MASK |
1272 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1273 DKL_TX_VSWING_CONTROL_MASK,
1274 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1275 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1276 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1277
1278 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1279
1280 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
1281 DKL_TX_PRESHOOT_COEFF_MASK |
1282 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1283 DKL_TX_VSWING_CONTROL_MASK,
1284 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1285 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1286 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1287
1288 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
1289 DKL_TX_DP20BITMODE, 0);
1290
1291 if (IS_ALDERLAKE_P(dev_priv)) {
1292 u32 val;
1293
1294 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1295 if (ln == 0) {
1296 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1297 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1298 } else {
1299 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1300 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1301 }
1302 } else {
1303 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1304 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1305 }
1306
1307 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
1308 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1309 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1310 val);
1311 }
1312 }
1313 }
1314
translate_signal_level(struct intel_dp * intel_dp,u8 signal_levels)1315 static int translate_signal_level(struct intel_dp *intel_dp,
1316 u8 signal_levels)
1317 {
1318 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1319 int i;
1320
1321 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1322 if (index_to_dp_signal_levels[i] == signal_levels)
1323 return i;
1324 }
1325
1326 drm_WARN(&i915->drm, 1,
1327 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1328 signal_levels);
1329
1330 return 0;
1331 }
1332
intel_ddi_dp_level(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int lane)1333 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1334 const struct intel_crtc_state *crtc_state,
1335 int lane)
1336 {
1337 u8 train_set = intel_dp->train_set[lane];
1338
1339 if (intel_dp_is_uhbr(crtc_state)) {
1340 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1341 } else {
1342 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1343 DP_TRAIN_PRE_EMPHASIS_MASK);
1344
1345 return translate_signal_level(intel_dp, signal_levels);
1346 }
1347 }
1348
intel_ddi_level(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int lane)1349 int intel_ddi_level(struct intel_encoder *encoder,
1350 const struct intel_crtc_state *crtc_state,
1351 int lane)
1352 {
1353 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1354 const struct intel_ddi_buf_trans *trans;
1355 int level, n_entries;
1356
1357 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1358 if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1359 return 0;
1360
1361 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1362 level = intel_ddi_hdmi_level(encoder, trans);
1363 else
1364 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1365 lane);
1366
1367 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1368 level = n_entries - 1;
1369
1370 return level;
1371 }
1372
1373 static void
hsw_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1374 hsw_set_signal_levels(struct intel_encoder *encoder,
1375 const struct intel_crtc_state *crtc_state)
1376 {
1377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1378 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1379 int level = intel_ddi_level(encoder, crtc_state, 0);
1380 enum port port = encoder->port;
1381 u32 signal_levels;
1382
1383 if (has_iboost(dev_priv))
1384 skl_ddi_set_iboost(encoder, crtc_state, level);
1385
1386 /* HDMI ignores the rest */
1387 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1388 return;
1389
1390 signal_levels = DDI_BUF_TRANS_SELECT(level);
1391
1392 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1393 signal_levels);
1394
1395 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1396 intel_dp->DP |= signal_levels;
1397
1398 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1399 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1400 }
1401
_icl_ddi_enable_clock(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_sel_mask,u32 clk_sel,u32 clk_off)1402 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1403 u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1404 {
1405 mutex_lock(&i915->display.dpll.lock);
1406
1407 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1408
1409 /*
1410 * "This step and the step before must be
1411 * done with separate register writes."
1412 */
1413 intel_de_rmw(i915, reg, clk_off, 0);
1414
1415 mutex_unlock(&i915->display.dpll.lock);
1416 }
1417
_icl_ddi_disable_clock(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_off)1418 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1419 u32 clk_off)
1420 {
1421 mutex_lock(&i915->display.dpll.lock);
1422
1423 intel_de_rmw(i915, reg, 0, clk_off);
1424
1425 mutex_unlock(&i915->display.dpll.lock);
1426 }
1427
_icl_ddi_is_clock_enabled(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_off)1428 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1429 u32 clk_off)
1430 {
1431 return !(intel_de_read(i915, reg) & clk_off);
1432 }
1433
1434 static struct intel_shared_dpll *
_icl_ddi_get_pll(struct drm_i915_private * i915,i915_reg_t reg,u32 clk_sel_mask,u32 clk_sel_shift)1435 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1436 u32 clk_sel_mask, u32 clk_sel_shift)
1437 {
1438 enum intel_dpll_id id;
1439
1440 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1441
1442 return intel_get_shared_dpll_by_id(i915, id);
1443 }
1444
adls_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1445 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1446 const struct intel_crtc_state *crtc_state)
1447 {
1448 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1449 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1450 enum phy phy = intel_port_to_phy(i915, encoder->port);
1451
1452 if (drm_WARN_ON(&i915->drm, !pll))
1453 return;
1454
1455 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1456 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1457 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1458 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1459 }
1460
adls_ddi_disable_clock(struct intel_encoder * encoder)1461 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1462 {
1463 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1464 enum phy phy = intel_port_to_phy(i915, encoder->port);
1465
1466 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1467 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1468 }
1469
adls_ddi_is_clock_enabled(struct intel_encoder * encoder)1470 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1471 {
1472 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1473 enum phy phy = intel_port_to_phy(i915, encoder->port);
1474
1475 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1476 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1477 }
1478
adls_ddi_get_pll(struct intel_encoder * encoder)1479 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1480 {
1481 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1482 enum phy phy = intel_port_to_phy(i915, encoder->port);
1483
1484 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1485 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1486 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1487 }
1488
rkl_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1489 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1490 const struct intel_crtc_state *crtc_state)
1491 {
1492 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1493 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1494 enum phy phy = intel_port_to_phy(i915, encoder->port);
1495
1496 if (drm_WARN_ON(&i915->drm, !pll))
1497 return;
1498
1499 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1500 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1501 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1502 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1503 }
1504
rkl_ddi_disable_clock(struct intel_encoder * encoder)1505 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1506 {
1507 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1508 enum phy phy = intel_port_to_phy(i915, encoder->port);
1509
1510 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1511 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1512 }
1513
rkl_ddi_is_clock_enabled(struct intel_encoder * encoder)1514 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1515 {
1516 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1517 enum phy phy = intel_port_to_phy(i915, encoder->port);
1518
1519 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1520 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1521 }
1522
rkl_ddi_get_pll(struct intel_encoder * encoder)1523 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1524 {
1525 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1526 enum phy phy = intel_port_to_phy(i915, encoder->port);
1527
1528 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1529 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1530 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1531 }
1532
dg1_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1533 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1534 const struct intel_crtc_state *crtc_state)
1535 {
1536 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1537 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1538 enum phy phy = intel_port_to_phy(i915, encoder->port);
1539
1540 if (drm_WARN_ON(&i915->drm, !pll))
1541 return;
1542
1543 /*
1544 * If we fail this, something went very wrong: first 2 PLLs should be
1545 * used by first 2 phys and last 2 PLLs by last phys
1546 */
1547 if (drm_WARN_ON(&i915->drm,
1548 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1549 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1550 return;
1551
1552 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1553 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1554 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1555 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1556 }
1557
dg1_ddi_disable_clock(struct intel_encoder * encoder)1558 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1559 {
1560 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1561 enum phy phy = intel_port_to_phy(i915, encoder->port);
1562
1563 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1564 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1565 }
1566
dg1_ddi_is_clock_enabled(struct intel_encoder * encoder)1567 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1568 {
1569 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1570 enum phy phy = intel_port_to_phy(i915, encoder->port);
1571
1572 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1573 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1574 }
1575
dg1_ddi_get_pll(struct intel_encoder * encoder)1576 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1577 {
1578 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1579 enum phy phy = intel_port_to_phy(i915, encoder->port);
1580 enum intel_dpll_id id;
1581 u32 val;
1582
1583 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1584 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1585 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1586 id = val;
1587
1588 /*
1589 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1590 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1591 * bit for phy C and D.
1592 */
1593 if (phy >= PHY_C)
1594 id += DPLL_ID_DG1_DPLL2;
1595
1596 return intel_get_shared_dpll_by_id(i915, id);
1597 }
1598
icl_ddi_combo_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1599 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1600 const struct intel_crtc_state *crtc_state)
1601 {
1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1603 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1604 enum phy phy = intel_port_to_phy(i915, encoder->port);
1605
1606 if (drm_WARN_ON(&i915->drm, !pll))
1607 return;
1608
1609 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1610 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1611 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1612 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1613 }
1614
icl_ddi_combo_disable_clock(struct intel_encoder * encoder)1615 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1616 {
1617 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1618 enum phy phy = intel_port_to_phy(i915, encoder->port);
1619
1620 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1621 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1622 }
1623
icl_ddi_combo_is_clock_enabled(struct intel_encoder * encoder)1624 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1625 {
1626 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1627 enum phy phy = intel_port_to_phy(i915, encoder->port);
1628
1629 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1630 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1631 }
1632
icl_ddi_combo_get_pll(struct intel_encoder * encoder)1633 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1634 {
1635 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1636 enum phy phy = intel_port_to_phy(i915, encoder->port);
1637
1638 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1639 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1640 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1641 }
1642
jsl_ddi_tc_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1643 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1644 const struct intel_crtc_state *crtc_state)
1645 {
1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1647 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1648 enum port port = encoder->port;
1649
1650 if (drm_WARN_ON(&i915->drm, !pll))
1651 return;
1652
1653 /*
1654 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1655 * MG does not exist, but the programming is required to ungate DDIC and DDID."
1656 */
1657 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1658
1659 icl_ddi_combo_enable_clock(encoder, crtc_state);
1660 }
1661
jsl_ddi_tc_disable_clock(struct intel_encoder * encoder)1662 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1663 {
1664 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1665 enum port port = encoder->port;
1666
1667 icl_ddi_combo_disable_clock(encoder);
1668
1669 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1670 }
1671
jsl_ddi_tc_is_clock_enabled(struct intel_encoder * encoder)1672 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1673 {
1674 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1675 enum port port = encoder->port;
1676 u32 tmp;
1677
1678 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1679
1680 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1681 return false;
1682
1683 return icl_ddi_combo_is_clock_enabled(encoder);
1684 }
1685
icl_ddi_tc_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1686 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1687 const struct intel_crtc_state *crtc_state)
1688 {
1689 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1690 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1691 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1692 enum port port = encoder->port;
1693
1694 if (drm_WARN_ON(&i915->drm, !pll))
1695 return;
1696
1697 intel_de_write(i915, DDI_CLK_SEL(port),
1698 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1699
1700 mutex_lock(&i915->display.dpll.lock);
1701
1702 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1703 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1704
1705 mutex_unlock(&i915->display.dpll.lock);
1706 }
1707
icl_ddi_tc_disable_clock(struct intel_encoder * encoder)1708 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1709 {
1710 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1711 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1712 enum port port = encoder->port;
1713
1714 mutex_lock(&i915->display.dpll.lock);
1715
1716 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1717 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1718
1719 mutex_unlock(&i915->display.dpll.lock);
1720
1721 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1722 }
1723
icl_ddi_tc_is_clock_enabled(struct intel_encoder * encoder)1724 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1725 {
1726 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1727 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1728 enum port port = encoder->port;
1729 u32 tmp;
1730
1731 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1732
1733 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1734 return false;
1735
1736 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1737
1738 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1739 }
1740
icl_ddi_tc_get_pll(struct intel_encoder * encoder)1741 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1742 {
1743 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1744 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1745 enum port port = encoder->port;
1746 enum intel_dpll_id id;
1747 u32 tmp;
1748
1749 tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1750
1751 switch (tmp & DDI_CLK_SEL_MASK) {
1752 case DDI_CLK_SEL_TBT_162:
1753 case DDI_CLK_SEL_TBT_270:
1754 case DDI_CLK_SEL_TBT_540:
1755 case DDI_CLK_SEL_TBT_810:
1756 id = DPLL_ID_ICL_TBTPLL;
1757 break;
1758 case DDI_CLK_SEL_MG:
1759 id = icl_tc_port_to_pll_id(tc_port);
1760 break;
1761 default:
1762 MISSING_CASE(tmp);
1763 fallthrough;
1764 case DDI_CLK_SEL_NONE:
1765 return NULL;
1766 }
1767
1768 return intel_get_shared_dpll_by_id(i915, id);
1769 }
1770
bxt_ddi_get_pll(struct intel_encoder * encoder)1771 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1772 {
1773 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1774 enum intel_dpll_id id;
1775
1776 switch (encoder->port) {
1777 case PORT_A:
1778 id = DPLL_ID_SKL_DPLL0;
1779 break;
1780 case PORT_B:
1781 id = DPLL_ID_SKL_DPLL1;
1782 break;
1783 case PORT_C:
1784 id = DPLL_ID_SKL_DPLL2;
1785 break;
1786 default:
1787 MISSING_CASE(encoder->port);
1788 return NULL;
1789 }
1790
1791 return intel_get_shared_dpll_by_id(i915, id);
1792 }
1793
skl_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1794 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1795 const struct intel_crtc_state *crtc_state)
1796 {
1797 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1798 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1799 enum port port = encoder->port;
1800
1801 if (drm_WARN_ON(&i915->drm, !pll))
1802 return;
1803
1804 mutex_lock(&i915->display.dpll.lock);
1805
1806 intel_de_rmw(i915, DPLL_CTRL2,
1807 DPLL_CTRL2_DDI_CLK_OFF(port) |
1808 DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1809 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1810 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1811
1812 mutex_unlock(&i915->display.dpll.lock);
1813 }
1814
skl_ddi_disable_clock(struct intel_encoder * encoder)1815 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1816 {
1817 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1818 enum port port = encoder->port;
1819
1820 mutex_lock(&i915->display.dpll.lock);
1821
1822 intel_de_rmw(i915, DPLL_CTRL2,
1823 0, DPLL_CTRL2_DDI_CLK_OFF(port));
1824
1825 mutex_unlock(&i915->display.dpll.lock);
1826 }
1827
skl_ddi_is_clock_enabled(struct intel_encoder * encoder)1828 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1829 {
1830 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1831 enum port port = encoder->port;
1832
1833 /*
1834 * FIXME Not sure if the override affects both
1835 * the PLL selection and the CLK_OFF bit.
1836 */
1837 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1838 }
1839
skl_ddi_get_pll(struct intel_encoder * encoder)1840 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1841 {
1842 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1843 enum port port = encoder->port;
1844 enum intel_dpll_id id;
1845 u32 tmp;
1846
1847 tmp = intel_de_read(i915, DPLL_CTRL2);
1848
1849 /*
1850 * FIXME Not sure if the override affects both
1851 * the PLL selection and the CLK_OFF bit.
1852 */
1853 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1854 return NULL;
1855
1856 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1857 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1858
1859 return intel_get_shared_dpll_by_id(i915, id);
1860 }
1861
hsw_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1862 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1863 const struct intel_crtc_state *crtc_state)
1864 {
1865 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1866 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1867 enum port port = encoder->port;
1868
1869 if (drm_WARN_ON(&i915->drm, !pll))
1870 return;
1871
1872 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1873 }
1874
hsw_ddi_disable_clock(struct intel_encoder * encoder)1875 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1876 {
1877 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1878 enum port port = encoder->port;
1879
1880 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1881 }
1882
hsw_ddi_is_clock_enabled(struct intel_encoder * encoder)1883 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1884 {
1885 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1886 enum port port = encoder->port;
1887
1888 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1889 }
1890
hsw_ddi_get_pll(struct intel_encoder * encoder)1891 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1892 {
1893 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1894 enum port port = encoder->port;
1895 enum intel_dpll_id id;
1896 u32 tmp;
1897
1898 tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1899
1900 switch (tmp & PORT_CLK_SEL_MASK) {
1901 case PORT_CLK_SEL_WRPLL1:
1902 id = DPLL_ID_WRPLL1;
1903 break;
1904 case PORT_CLK_SEL_WRPLL2:
1905 id = DPLL_ID_WRPLL2;
1906 break;
1907 case PORT_CLK_SEL_SPLL:
1908 id = DPLL_ID_SPLL;
1909 break;
1910 case PORT_CLK_SEL_LCPLL_810:
1911 id = DPLL_ID_LCPLL_810;
1912 break;
1913 case PORT_CLK_SEL_LCPLL_1350:
1914 id = DPLL_ID_LCPLL_1350;
1915 break;
1916 case PORT_CLK_SEL_LCPLL_2700:
1917 id = DPLL_ID_LCPLL_2700;
1918 break;
1919 default:
1920 MISSING_CASE(tmp);
1921 fallthrough;
1922 case PORT_CLK_SEL_NONE:
1923 return NULL;
1924 }
1925
1926 return intel_get_shared_dpll_by_id(i915, id);
1927 }
1928
intel_ddi_enable_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1929 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1930 const struct intel_crtc_state *crtc_state)
1931 {
1932 if (encoder->enable_clock)
1933 encoder->enable_clock(encoder, crtc_state);
1934 }
1935
intel_ddi_disable_clock(struct intel_encoder * encoder)1936 void intel_ddi_disable_clock(struct intel_encoder *encoder)
1937 {
1938 if (encoder->disable_clock)
1939 encoder->disable_clock(encoder);
1940 }
1941
intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder * encoder)1942 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1943 {
1944 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1945 u32 port_mask;
1946 bool ddi_clk_needed;
1947
1948 /*
1949 * In case of DP MST, we sanitize the primary encoder only, not the
1950 * virtual ones.
1951 */
1952 if (encoder->type == INTEL_OUTPUT_DP_MST)
1953 return;
1954
1955 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
1956 u8 pipe_mask;
1957 bool is_mst;
1958
1959 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1960 /*
1961 * In the unlikely case that BIOS enables DP in MST mode, just
1962 * warn since our MST HW readout is incomplete.
1963 */
1964 if (drm_WARN_ON(&i915->drm, is_mst))
1965 return;
1966 }
1967
1968 port_mask = BIT(encoder->port);
1969 ddi_clk_needed = encoder->base.crtc;
1970
1971 if (encoder->type == INTEL_OUTPUT_DSI) {
1972 struct intel_encoder *other_encoder;
1973
1974 port_mask = intel_dsi_encoder_ports(encoder);
1975 /*
1976 * Sanity check that we haven't incorrectly registered another
1977 * encoder using any of the ports of this DSI encoder.
1978 */
1979 for_each_intel_encoder(&i915->drm, other_encoder) {
1980 if (other_encoder == encoder)
1981 continue;
1982
1983 if (drm_WARN_ON(&i915->drm,
1984 port_mask & BIT(other_encoder->port)))
1985 return;
1986 }
1987 /*
1988 * For DSI we keep the ddi clocks gated
1989 * except during enable/disable sequence.
1990 */
1991 ddi_clk_needed = false;
1992 }
1993
1994 if (ddi_clk_needed || !encoder->is_clock_enabled ||
1995 !encoder->is_clock_enabled(encoder))
1996 return;
1997
1998 drm_notice(&i915->drm,
1999 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2000 encoder->base.base.id, encoder->base.name);
2001
2002 encoder->disable_clock(encoder);
2003 }
2004
2005 static void
icl_program_mg_dp_mode(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)2006 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2007 const struct intel_crtc_state *crtc_state)
2008 {
2009 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2010 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2011 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2012 u32 ln0, ln1, pin_assignment;
2013 u8 width;
2014
2015 if (!intel_phy_is_tc(dev_priv, phy) ||
2016 intel_tc_port_in_tbt_alt_mode(dig_port))
2017 return;
2018
2019 if (DISPLAY_VER(dev_priv) >= 12) {
2020 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0);
2021 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1);
2022 } else {
2023 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2024 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2025 }
2026
2027 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2028 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2029
2030 /* DPPATC */
2031 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2032 width = crtc_state->lane_count;
2033
2034 switch (pin_assignment) {
2035 case 0x0:
2036 drm_WARN_ON(&dev_priv->drm,
2037 !intel_tc_port_in_legacy_mode(dig_port));
2038 if (width == 1) {
2039 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2040 } else {
2041 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2042 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2043 }
2044 break;
2045 case 0x1:
2046 if (width == 4) {
2047 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2048 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2049 }
2050 break;
2051 case 0x2:
2052 if (width == 2) {
2053 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2054 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2055 }
2056 break;
2057 case 0x3:
2058 case 0x5:
2059 if (width == 1) {
2060 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2061 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2062 } else {
2063 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2064 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2065 }
2066 break;
2067 case 0x4:
2068 case 0x6:
2069 if (width == 1) {
2070 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2071 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2072 } else {
2073 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2074 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2075 }
2076 break;
2077 default:
2078 MISSING_CASE(pin_assignment);
2079 }
2080
2081 if (DISPLAY_VER(dev_priv) >= 12) {
2082 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0);
2083 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1);
2084 } else {
2085 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2086 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2087 }
2088 }
2089
2090 static enum transcoder
tgl_dp_tp_transcoder(const struct intel_crtc_state * crtc_state)2091 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2092 {
2093 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2094 return crtc_state->mst_master_transcoder;
2095 else
2096 return crtc_state->cpu_transcoder;
2097 }
2098
dp_tp_ctl_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2099 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2100 const struct intel_crtc_state *crtc_state)
2101 {
2102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2103
2104 if (DISPLAY_VER(dev_priv) >= 12)
2105 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2106 else
2107 return DP_TP_CTL(encoder->port);
2108 }
2109
dp_tp_status_reg(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2110 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2111 const struct intel_crtc_state *crtc_state)
2112 {
2113 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2114
2115 if (DISPLAY_VER(dev_priv) >= 12)
2116 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2117 else
2118 return DP_TP_STATUS(encoder->port);
2119 }
2120
intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)2121 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2122 const struct intel_crtc_state *crtc_state,
2123 bool enable)
2124 {
2125 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2126
2127 if (!crtc_state->vrr.enable)
2128 return;
2129
2130 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2131 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2132 drm_dbg_kms(&i915->drm,
2133 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2134 str_enable_disable(enable));
2135 }
2136
intel_dp_sink_set_fec_ready(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2137 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2138 const struct intel_crtc_state *crtc_state)
2139 {
2140 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2141
2142 if (!crtc_state->fec_enable)
2143 return;
2144
2145 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2146 drm_dbg_kms(&i915->drm,
2147 "Failed to set FEC_READY in the sink\n");
2148 }
2149
intel_ddi_enable_fec(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2150 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2151 const struct intel_crtc_state *crtc_state)
2152 {
2153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2154 struct intel_dp *intel_dp;
2155 u32 val;
2156
2157 if (!crtc_state->fec_enable)
2158 return;
2159
2160 intel_dp = enc_to_intel_dp(encoder);
2161 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2162 val |= DP_TP_CTL_FEC_ENABLE;
2163 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2164 }
2165
intel_ddi_disable_fec_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2166 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2167 const struct intel_crtc_state *crtc_state)
2168 {
2169 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2170 struct intel_dp *intel_dp;
2171 u32 val;
2172
2173 if (!crtc_state->fec_enable)
2174 return;
2175
2176 intel_dp = enc_to_intel_dp(encoder);
2177 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2178 val &= ~DP_TP_CTL_FEC_ENABLE;
2179 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2180 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2181 }
2182
intel_ddi_power_up_lanes(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2183 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2184 const struct intel_crtc_state *crtc_state)
2185 {
2186 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2187 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2188 enum phy phy = intel_port_to_phy(i915, encoder->port);
2189
2190 if (intel_phy_is_combo(i915, phy)) {
2191 bool lane_reversal =
2192 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2193
2194 intel_combo_phy_power_up_lanes(i915, phy, false,
2195 crtc_state->lane_count,
2196 lane_reversal);
2197 }
2198 }
2199
2200 /* Splitter enable for eDP MSO is limited to certain pipes. */
intel_ddi_splitter_pipe_mask(struct drm_i915_private * i915)2201 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2202 {
2203 if (IS_ALDERLAKE_P(i915))
2204 return BIT(PIPE_A) | BIT(PIPE_B);
2205 else
2206 return BIT(PIPE_A);
2207 }
2208
intel_ddi_mso_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)2209 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2210 struct intel_crtc_state *pipe_config)
2211 {
2212 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2213 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2214 enum pipe pipe = crtc->pipe;
2215 u32 dss1;
2216
2217 if (!HAS_MSO(i915))
2218 return;
2219
2220 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2221
2222 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2223 if (!pipe_config->splitter.enable)
2224 return;
2225
2226 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2227 pipe_config->splitter.enable = false;
2228 return;
2229 }
2230
2231 switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2232 default:
2233 drm_WARN(&i915->drm, true,
2234 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2235 fallthrough;
2236 case SPLITTER_CONFIGURATION_2_SEGMENT:
2237 pipe_config->splitter.link_count = 2;
2238 break;
2239 case SPLITTER_CONFIGURATION_4_SEGMENT:
2240 pipe_config->splitter.link_count = 4;
2241 break;
2242 }
2243
2244 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2245 }
2246
intel_ddi_mso_configure(const struct intel_crtc_state * crtc_state)2247 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2248 {
2249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2250 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2251 enum pipe pipe = crtc->pipe;
2252 u32 dss1 = 0;
2253
2254 if (!HAS_MSO(i915))
2255 return;
2256
2257 if (crtc_state->splitter.enable) {
2258 dss1 |= SPLITTER_ENABLE;
2259 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2260 if (crtc_state->splitter.link_count == 2)
2261 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2262 else
2263 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2264 }
2265
2266 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2267 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2268 OVERLAP_PIXELS_MASK, dss1);
2269 }
2270
tgl_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2271 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2272 struct intel_encoder *encoder,
2273 const struct intel_crtc_state *crtc_state,
2274 const struct drm_connector_state *conn_state)
2275 {
2276 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2278 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2279 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2280
2281 intel_dp_set_link_params(intel_dp,
2282 crtc_state->port_clock,
2283 crtc_state->lane_count);
2284
2285 /*
2286 * We only configure what the register value will be here. Actual
2287 * enabling happens during link training farther down.
2288 */
2289 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2290
2291 /*
2292 * 1. Enable Power Wells
2293 *
2294 * This was handled at the beginning of intel_atomic_commit_tail(),
2295 * before we called down into this function.
2296 */
2297
2298 /* 2. Enable Panel Power if PPS is required */
2299 intel_pps_on(intel_dp);
2300
2301 /*
2302 * 3. For non-TBT Type-C ports, set FIA lane count
2303 * (DFLEXDPSP.DPX4TXLATC)
2304 *
2305 * This was done before tgl_ddi_pre_enable_dp by
2306 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2307 */
2308
2309 /*
2310 * 4. Enable the port PLL.
2311 *
2312 * The PLL enabling itself was already done before this function by
2313 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
2314 * configure the PLL to port mapping here.
2315 */
2316 intel_ddi_enable_clock(encoder, crtc_state);
2317
2318 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2319 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2320 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2321 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2322 dig_port->ddi_io_power_domain);
2323 }
2324
2325 /* 6. Program DP_MODE */
2326 icl_program_mg_dp_mode(dig_port, crtc_state);
2327
2328 /*
2329 * 7. The rest of the below are substeps under the bspec's "Enable and
2330 * Train Display Port" step. Note that steps that are specific to
2331 * MST will be handled by intel_mst_pre_enable_dp() before/after it
2332 * calls into this function. Also intel_mst_pre_enable_dp() only calls
2333 * us when active_mst_links==0, so any steps designated for "single
2334 * stream or multi-stream master transcoder" can just be performed
2335 * unconditionally here.
2336 */
2337
2338 /*
2339 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2340 * Transcoder.
2341 */
2342 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2343
2344 if (HAS_DP20(dev_priv))
2345 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2346
2347 /*
2348 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2349 * Transport Select
2350 */
2351 intel_ddi_config_transcoder_func(encoder, crtc_state);
2352
2353 /*
2354 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2355 * selected
2356 *
2357 * This will be handled by the intel_dp_start_link_train() farther
2358 * down this function.
2359 */
2360
2361 /* 7.e Configure voltage swing and related IO settings */
2362 encoder->set_signal_levels(encoder, crtc_state);
2363
2364 /*
2365 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2366 * the used lanes of the DDI.
2367 */
2368 intel_ddi_power_up_lanes(encoder, crtc_state);
2369
2370 /*
2371 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2372 */
2373 intel_ddi_mso_configure(crtc_state);
2374
2375 if (!is_mst)
2376 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2377
2378 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2379 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2380 /*
2381 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2382 * in the FEC_CONFIGURATION register to 1 before initiating link
2383 * training
2384 */
2385 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2386
2387 intel_dp_check_frl_training(intel_dp);
2388 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2389
2390 /*
2391 * 7.i Follow DisplayPort specification training sequence (see notes for
2392 * failure handling)
2393 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2394 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2395 * (timeout after 800 us)
2396 */
2397 intel_dp_start_link_train(intel_dp, crtc_state);
2398
2399 /* 7.k Set DP_TP_CTL link training to Normal */
2400 if (!is_trans_port_sync_mode(crtc_state))
2401 intel_dp_stop_link_train(intel_dp, crtc_state);
2402
2403 /* 7.l Configure and enable FEC if needed */
2404 intel_ddi_enable_fec(encoder, crtc_state);
2405
2406 intel_dsc_dp_pps_write(encoder, crtc_state);
2407 }
2408
hsw_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2409 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2410 struct intel_encoder *encoder,
2411 const struct intel_crtc_state *crtc_state,
2412 const struct drm_connector_state *conn_state)
2413 {
2414 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2415 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2416 enum port port = encoder->port;
2417 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2418 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2419
2420 if (DISPLAY_VER(dev_priv) < 11)
2421 drm_WARN_ON(&dev_priv->drm,
2422 is_mst && (port == PORT_A || port == PORT_E));
2423 else
2424 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2425
2426 intel_dp_set_link_params(intel_dp,
2427 crtc_state->port_clock,
2428 crtc_state->lane_count);
2429
2430 /*
2431 * We only configure what the register value will be here. Actual
2432 * enabling happens during link training farther down.
2433 */
2434 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2435
2436 intel_pps_on(intel_dp);
2437
2438 intel_ddi_enable_clock(encoder, crtc_state);
2439
2440 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2441 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2442 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2443 dig_port->ddi_io_power_domain);
2444 }
2445
2446 icl_program_mg_dp_mode(dig_port, crtc_state);
2447
2448 if (has_buf_trans_select(dev_priv))
2449 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2450
2451 encoder->set_signal_levels(encoder, crtc_state);
2452
2453 intel_ddi_power_up_lanes(encoder, crtc_state);
2454
2455 if (!is_mst)
2456 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2457 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2458 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2459 true);
2460 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2461 intel_dp_start_link_train(intel_dp, crtc_state);
2462 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2463 !is_trans_port_sync_mode(crtc_state))
2464 intel_dp_stop_link_train(intel_dp, crtc_state);
2465
2466 intel_ddi_enable_fec(encoder, crtc_state);
2467
2468 if (!is_mst)
2469 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2470
2471 intel_dsc_dp_pps_write(encoder, crtc_state);
2472 }
2473
intel_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2474 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2475 struct intel_encoder *encoder,
2476 const struct intel_crtc_state *crtc_state,
2477 const struct drm_connector_state *conn_state)
2478 {
2479 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2480
2481 if (DISPLAY_VER(dev_priv) >= 12)
2482 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2483 else
2484 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2485
2486 /* MST will call a setting of MSA after an allocating of Virtual Channel
2487 * from MST encoder pre_enable callback.
2488 */
2489 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2490 intel_ddi_set_dp_msa(crtc_state, conn_state);
2491 }
2492
intel_ddi_pre_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2493 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2494 struct intel_encoder *encoder,
2495 const struct intel_crtc_state *crtc_state,
2496 const struct drm_connector_state *conn_state)
2497 {
2498 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2499 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2501
2502 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2503 intel_ddi_enable_clock(encoder, crtc_state);
2504
2505 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2506 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2507 dig_port->ddi_io_power_domain);
2508
2509 icl_program_mg_dp_mode(dig_port, crtc_state);
2510
2511 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2512
2513 dig_port->set_infoframes(encoder,
2514 crtc_state->has_infoframe,
2515 crtc_state, conn_state);
2516 }
2517
intel_ddi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2518 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2519 struct intel_encoder *encoder,
2520 const struct intel_crtc_state *crtc_state,
2521 const struct drm_connector_state *conn_state)
2522 {
2523 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2525 enum pipe pipe = crtc->pipe;
2526
2527 /*
2528 * When called from DP MST code:
2529 * - conn_state will be NULL
2530 * - encoder will be the main encoder (ie. mst->primary)
2531 * - the main connector associated with this port
2532 * won't be active or linked to a crtc
2533 * - crtc_state will be the state of the first stream to
2534 * be activated on this port, and it may not be the same
2535 * stream that will be deactivated last, but each stream
2536 * should have a state that is identical when it comes to
2537 * the DP link parameteres
2538 */
2539
2540 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2541
2542 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2543
2544 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2545 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2546 conn_state);
2547 } else {
2548 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2549
2550 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2551 conn_state);
2552
2553 /* FIXME precompute everything properly */
2554 /* FIXME how do we turn infoframes off again? */
2555 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2556 dig_port->set_infoframes(encoder,
2557 crtc_state->has_infoframe,
2558 crtc_state, conn_state);
2559 }
2560 }
2561
intel_disable_ddi_buf(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2562 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2563 const struct intel_crtc_state *crtc_state)
2564 {
2565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2566 enum port port = encoder->port;
2567 bool wait = false;
2568 u32 val;
2569
2570 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2571 if (val & DDI_BUF_CTL_ENABLE) {
2572 val &= ~DDI_BUF_CTL_ENABLE;
2573 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2574 wait = true;
2575 }
2576
2577 if (intel_crtc_has_dp_encoder(crtc_state)) {
2578 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2579 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2580 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2581 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2582 }
2583
2584 /* Disable FEC in DP Sink */
2585 intel_ddi_disable_fec_state(encoder, crtc_state);
2586
2587 if (wait)
2588 intel_wait_ddi_buf_idle(dev_priv, port);
2589 }
2590
intel_ddi_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2591 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2592 struct intel_encoder *encoder,
2593 const struct intel_crtc_state *old_crtc_state,
2594 const struct drm_connector_state *old_conn_state)
2595 {
2596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2597 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2598 struct intel_dp *intel_dp = &dig_port->dp;
2599 bool is_mst = intel_crtc_has_type(old_crtc_state,
2600 INTEL_OUTPUT_DP_MST);
2601
2602 if (!is_mst)
2603 intel_dp_set_infoframes(encoder, false,
2604 old_crtc_state, old_conn_state);
2605
2606 /*
2607 * Power down sink before disabling the port, otherwise we end
2608 * up getting interrupts from the sink on detecting link loss.
2609 */
2610 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2611
2612 if (DISPLAY_VER(dev_priv) >= 12) {
2613 if (is_mst) {
2614 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2615 u32 val;
2616
2617 val = intel_de_read(dev_priv,
2618 TRANS_DDI_FUNC_CTL(cpu_transcoder));
2619 val &= ~(TGL_TRANS_DDI_PORT_MASK |
2620 TRANS_DDI_MODE_SELECT_MASK);
2621 intel_de_write(dev_priv,
2622 TRANS_DDI_FUNC_CTL(cpu_transcoder),
2623 val);
2624 }
2625 } else {
2626 if (!is_mst)
2627 intel_ddi_disable_pipe_clock(old_crtc_state);
2628 }
2629
2630 intel_disable_ddi_buf(encoder, old_crtc_state);
2631
2632 /*
2633 * From TGL spec: "If single stream or multi-stream master transcoder:
2634 * Configure Transcoder Clock select to direct no clock to the
2635 * transcoder"
2636 */
2637 if (DISPLAY_VER(dev_priv) >= 12)
2638 intel_ddi_disable_pipe_clock(old_crtc_state);
2639
2640 intel_pps_vdd_on(intel_dp);
2641 intel_pps_off(intel_dp);
2642
2643 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
2644 intel_display_power_put(dev_priv,
2645 dig_port->ddi_io_power_domain,
2646 fetch_and_zero(&dig_port->ddi_io_wakeref));
2647
2648 intel_ddi_disable_clock(encoder);
2649 }
2650
intel_ddi_post_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2651 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2652 struct intel_encoder *encoder,
2653 const struct intel_crtc_state *old_crtc_state,
2654 const struct drm_connector_state *old_conn_state)
2655 {
2656 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2657 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2658 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2659
2660 dig_port->set_infoframes(encoder, false,
2661 old_crtc_state, old_conn_state);
2662
2663 if (DISPLAY_VER(dev_priv) < 12)
2664 intel_ddi_disable_pipe_clock(old_crtc_state);
2665
2666 intel_disable_ddi_buf(encoder, old_crtc_state);
2667
2668 if (DISPLAY_VER(dev_priv) >= 12)
2669 intel_ddi_disable_pipe_clock(old_crtc_state);
2670
2671 intel_display_power_put(dev_priv,
2672 dig_port->ddi_io_power_domain,
2673 fetch_and_zero(&dig_port->ddi_io_wakeref));
2674
2675 intel_ddi_disable_clock(encoder);
2676
2677 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2678 }
2679
intel_ddi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2680 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2681 struct intel_encoder *encoder,
2682 const struct intel_crtc_state *old_crtc_state,
2683 const struct drm_connector_state *old_conn_state)
2684 {
2685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2686 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2687 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2688 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2689 struct intel_crtc *slave_crtc;
2690
2691 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2692 intel_crtc_vblank_off(old_crtc_state);
2693
2694 intel_disable_transcoder(old_crtc_state);
2695
2696 intel_vrr_disable(old_crtc_state);
2697
2698 intel_ddi_disable_transcoder_func(old_crtc_state);
2699
2700 intel_dsc_disable(old_crtc_state);
2701
2702 if (DISPLAY_VER(dev_priv) >= 9)
2703 skl_scaler_disable(old_crtc_state);
2704 else
2705 ilk_pfit_disable(old_crtc_state);
2706 }
2707
2708 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
2709 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
2710 const struct intel_crtc_state *old_slave_crtc_state =
2711 intel_atomic_get_old_crtc_state(state, slave_crtc);
2712
2713 intel_crtc_vblank_off(old_slave_crtc_state);
2714
2715 intel_dsc_disable(old_slave_crtc_state);
2716 skl_scaler_disable(old_slave_crtc_state);
2717 }
2718
2719 /*
2720 * When called from DP MST code:
2721 * - old_conn_state will be NULL
2722 * - encoder will be the main encoder (ie. mst->primary)
2723 * - the main connector associated with this port
2724 * won't be active or linked to a crtc
2725 * - old_crtc_state will be the state of the last stream to
2726 * be deactivated on this port, and it may not be the same
2727 * stream that was activated last, but each stream
2728 * should have a state that is identical when it comes to
2729 * the DP link parameteres
2730 */
2731
2732 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2733 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2734 old_conn_state);
2735 else
2736 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2737 old_conn_state);
2738
2739 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2740 intel_display_power_put(dev_priv,
2741 intel_ddi_main_link_aux_domain(dig_port),
2742 fetch_and_zero(&dig_port->aux_wakeref));
2743
2744 if (is_tc_port)
2745 intel_tc_port_put_link(dig_port);
2746 }
2747
trans_port_sync_stop_link_train(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2748 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2749 struct intel_encoder *encoder,
2750 const struct intel_crtc_state *crtc_state)
2751 {
2752 const struct drm_connector_state *conn_state;
2753 struct drm_connector *conn;
2754 int i;
2755
2756 if (!crtc_state->sync_mode_slaves_mask)
2757 return;
2758
2759 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2760 struct intel_encoder *slave_encoder =
2761 to_intel_encoder(conn_state->best_encoder);
2762 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2763 const struct intel_crtc_state *slave_crtc_state;
2764
2765 if (!slave_crtc)
2766 continue;
2767
2768 slave_crtc_state =
2769 intel_atomic_get_new_crtc_state(state, slave_crtc);
2770
2771 if (slave_crtc_state->master_transcoder !=
2772 crtc_state->cpu_transcoder)
2773 continue;
2774
2775 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2776 slave_crtc_state);
2777 }
2778
2779 usleep_range(200, 400);
2780
2781 intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2782 crtc_state);
2783 }
2784
intel_enable_ddi_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2785 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
2786 struct intel_encoder *encoder,
2787 const struct intel_crtc_state *crtc_state,
2788 const struct drm_connector_state *conn_state)
2789 {
2790 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2791 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2792 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2793 enum port port = encoder->port;
2794
2795 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
2796 intel_dp_stop_link_train(intel_dp, crtc_state);
2797
2798 drm_connector_update_privacy_screen(conn_state);
2799 intel_edp_backlight_on(crtc_state, conn_state);
2800
2801 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
2802 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2803
2804 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2805
2806 trans_port_sync_stop_link_train(state, encoder, crtc_state);
2807 }
2808
2809 static i915_reg_t
gen9_chicken_trans_reg_by_port(struct drm_i915_private * dev_priv,enum port port)2810 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
2811 enum port port)
2812 {
2813 static const enum transcoder trans[] = {
2814 [PORT_A] = TRANSCODER_EDP,
2815 [PORT_B] = TRANSCODER_A,
2816 [PORT_C] = TRANSCODER_B,
2817 [PORT_D] = TRANSCODER_C,
2818 [PORT_E] = TRANSCODER_A,
2819 };
2820
2821 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
2822
2823 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
2824 port = PORT_A;
2825
2826 return CHICKEN_TRANS(trans[port]);
2827 }
2828
intel_enable_ddi_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2829 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
2830 struct intel_encoder *encoder,
2831 const struct intel_crtc_state *crtc_state,
2832 const struct drm_connector_state *conn_state)
2833 {
2834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2835 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2836 struct drm_connector *connector = conn_state->connector;
2837 enum port port = encoder->port;
2838 enum phy phy = intel_port_to_phy(dev_priv, port);
2839 u32 buf_ctl;
2840
2841 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2842 crtc_state->hdmi_high_tmds_clock_ratio,
2843 crtc_state->hdmi_scrambling))
2844 drm_dbg_kms(&dev_priv->drm,
2845 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2846 connector->base.id, connector->name);
2847
2848 if (has_buf_trans_select(dev_priv))
2849 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
2850
2851 encoder->set_signal_levels(encoder, crtc_state);
2852
2853 /* Display WA #1143: skl,kbl,cfl */
2854 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
2855 /*
2856 * For some reason these chicken bits have been
2857 * stuffed into a transcoder register, event though
2858 * the bits affect a specific DDI port rather than
2859 * a specific transcoder.
2860 */
2861 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
2862 u32 val;
2863
2864 val = intel_de_read(dev_priv, reg);
2865
2866 if (port == PORT_E)
2867 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2868 DDIE_TRAINING_OVERRIDE_VALUE;
2869 else
2870 val |= DDI_TRAINING_OVERRIDE_ENABLE |
2871 DDI_TRAINING_OVERRIDE_VALUE;
2872
2873 intel_de_write(dev_priv, reg, val);
2874 intel_de_posting_read(dev_priv, reg);
2875
2876 udelay(1);
2877
2878 if (port == PORT_E)
2879 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2880 DDIE_TRAINING_OVERRIDE_VALUE);
2881 else
2882 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2883 DDI_TRAINING_OVERRIDE_VALUE);
2884
2885 intel_de_write(dev_priv, reg, val);
2886 }
2887
2888 intel_ddi_power_up_lanes(encoder, crtc_state);
2889
2890 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2891 * are ignored so nothing special needs to be done besides
2892 * enabling the port.
2893 *
2894 * On ADL_P the PHY link rate and lane count must be programmed but
2895 * these are both 0 for HDMI.
2896 */
2897 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
2898 if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
2899 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
2900 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
2901 }
2902 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
2903
2904 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2905 }
2906
intel_enable_ddi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2907 static void intel_enable_ddi(struct intel_atomic_state *state,
2908 struct intel_encoder *encoder,
2909 const struct intel_crtc_state *crtc_state,
2910 const struct drm_connector_state *conn_state)
2911 {
2912 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
2913
2914 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
2915 intel_ddi_enable_transcoder_func(encoder, crtc_state);
2916
2917 intel_vrr_enable(encoder, crtc_state);
2918
2919 intel_enable_transcoder(crtc_state);
2920
2921 intel_crtc_vblank_on(crtc_state);
2922
2923 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2924 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
2925 else
2926 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
2927
2928 /* Enable hdcp if it's desired */
2929 if (conn_state->content_protection ==
2930 DRM_MODE_CONTENT_PROTECTION_DESIRED)
2931 intel_hdcp_enable(to_intel_connector(conn_state->connector),
2932 crtc_state,
2933 (u8)conn_state->hdcp_content_type);
2934 }
2935
intel_disable_ddi_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2936 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
2937 struct intel_encoder *encoder,
2938 const struct intel_crtc_state *old_crtc_state,
2939 const struct drm_connector_state *old_conn_state)
2940 {
2941 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2942
2943 intel_dp->link_trained = false;
2944
2945 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
2946
2947 intel_psr_disable(intel_dp, old_crtc_state);
2948 intel_edp_backlight_off(old_conn_state);
2949 /* Disable the decompression in DP Sink */
2950 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
2951 false);
2952 /* Disable Ignore_MSA bit in DP Sink */
2953 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
2954 false);
2955 }
2956
intel_disable_ddi_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2957 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
2958 struct intel_encoder *encoder,
2959 const struct intel_crtc_state *old_crtc_state,
2960 const struct drm_connector_state *old_conn_state)
2961 {
2962 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2963 struct drm_connector *connector = old_conn_state->connector;
2964
2965 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
2966
2967 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2968 false, false))
2969 drm_dbg_kms(&i915->drm,
2970 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
2971 connector->base.id, connector->name);
2972 }
2973
intel_disable_ddi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2974 static void intel_disable_ddi(struct intel_atomic_state *state,
2975 struct intel_encoder *encoder,
2976 const struct intel_crtc_state *old_crtc_state,
2977 const struct drm_connector_state *old_conn_state)
2978 {
2979 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2980
2981 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2982 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
2983 old_conn_state);
2984 else
2985 intel_disable_ddi_dp(state, encoder, old_crtc_state,
2986 old_conn_state);
2987 }
2988
intel_ddi_update_pipe_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2989 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
2990 struct intel_encoder *encoder,
2991 const struct intel_crtc_state *crtc_state,
2992 const struct drm_connector_state *conn_state)
2993 {
2994 intel_ddi_set_dp_msa(crtc_state, conn_state);
2995
2996 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2997
2998 intel_backlight_update(state, encoder, crtc_state, conn_state);
2999 drm_connector_update_privacy_screen(conn_state);
3000 }
3001
intel_ddi_update_pipe(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3002 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3003 struct intel_encoder *encoder,
3004 const struct intel_crtc_state *crtc_state,
3005 const struct drm_connector_state *conn_state)
3006 {
3007
3008 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3009 !intel_encoder_is_mst(encoder))
3010 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3011 conn_state);
3012
3013 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3014 }
3015
3016 static void
intel_ddi_update_prepare(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)3017 intel_ddi_update_prepare(struct intel_atomic_state *state,
3018 struct intel_encoder *encoder,
3019 struct intel_crtc *crtc)
3020 {
3021 struct drm_i915_private *i915 = to_i915(state->base.dev);
3022 struct intel_crtc_state *crtc_state =
3023 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3024 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3025
3026 drm_WARN_ON(state->base.dev, crtc && crtc->active);
3027
3028 intel_tc_port_get_link(enc_to_dig_port(encoder),
3029 required_lanes);
3030 if (crtc_state && crtc_state->hw.active) {
3031 struct intel_crtc *slave_crtc;
3032
3033 intel_update_active_dpll(state, crtc, encoder);
3034
3035 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
3036 intel_crtc_bigjoiner_slave_pipes(crtc_state))
3037 intel_update_active_dpll(state, slave_crtc, encoder);
3038 }
3039 }
3040
3041 static void
intel_ddi_update_complete(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)3042 intel_ddi_update_complete(struct intel_atomic_state *state,
3043 struct intel_encoder *encoder,
3044 struct intel_crtc *crtc)
3045 {
3046 intel_tc_port_put_link(enc_to_dig_port(encoder));
3047 }
3048
3049 static void
intel_ddi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3050 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3051 struct intel_encoder *encoder,
3052 const struct intel_crtc_state *crtc_state,
3053 const struct drm_connector_state *conn_state)
3054 {
3055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3056 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3057 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3058 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3059
3060 if (is_tc_port)
3061 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3062
3063 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3064 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3065 dig_port->aux_wakeref =
3066 intel_display_power_get(dev_priv,
3067 intel_ddi_main_link_aux_domain(dig_port));
3068 }
3069
3070 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3071 /*
3072 * Program the lane count for static/dynamic connections on
3073 * Type-C ports. Skip this step for TBT.
3074 */
3075 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3076 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3077 bxt_ddi_phy_set_lane_optim_mask(encoder,
3078 crtc_state->lane_lat_optim_mask);
3079 }
3080
adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder * encoder)3081 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3082 {
3083 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3084 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
3085 int ln;
3086
3087 for (ln = 0; ln < 2; ln++)
3088 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port), ln, DKL_PCS_DW5_CORE_SOFTRESET, 0);
3089 }
3090
intel_ddi_prepare_link_retrain(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3091 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3092 const struct intel_crtc_state *crtc_state)
3093 {
3094 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3095 struct intel_encoder *encoder = &dig_port->base;
3096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3097 enum port port = encoder->port;
3098 u32 dp_tp_ctl, ddi_buf_ctl;
3099 bool wait = false;
3100
3101 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3102
3103 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3104 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3105 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3106 intel_de_write(dev_priv, DDI_BUF_CTL(port),
3107 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3108 wait = true;
3109 }
3110
3111 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3112 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3113 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3114 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3115
3116 if (wait)
3117 intel_wait_ddi_buf_idle(dev_priv, port);
3118 }
3119
3120 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3121 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3122 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3123 } else {
3124 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3125 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3126 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3127 }
3128 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3129 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3130
3131 if (IS_ALDERLAKE_P(dev_priv) &&
3132 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3133 adlp_tbt_to_dp_alt_switch_wa(encoder);
3134
3135 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3136 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3137 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3138
3139 intel_wait_ddi_buf_active(dev_priv, port);
3140 }
3141
intel_ddi_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)3142 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3143 const struct intel_crtc_state *crtc_state,
3144 u8 dp_train_pat)
3145 {
3146 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3147 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3148 u32 temp;
3149
3150 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3151
3152 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3153 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3154 case DP_TRAINING_PATTERN_DISABLE:
3155 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3156 break;
3157 case DP_TRAINING_PATTERN_1:
3158 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3159 break;
3160 case DP_TRAINING_PATTERN_2:
3161 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3162 break;
3163 case DP_TRAINING_PATTERN_3:
3164 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3165 break;
3166 case DP_TRAINING_PATTERN_4:
3167 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3168 break;
3169 }
3170
3171 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3172 }
3173
intel_ddi_set_idle_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3174 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3175 const struct intel_crtc_state *crtc_state)
3176 {
3177 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3179 enum port port = encoder->port;
3180 u32 val;
3181
3182 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3183 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3184 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3185 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3186
3187 /*
3188 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3189 * reason we need to set idle transmission mode is to work around a HW
3190 * issue where we enable the pipe while not in idle link-training mode.
3191 * In this case there is requirement to wait for a minimum number of
3192 * idle patterns to be sent.
3193 */
3194 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3195 return;
3196
3197 if (intel_de_wait_for_set(dev_priv,
3198 dp_tp_status_reg(encoder, crtc_state),
3199 DP_TP_STATUS_IDLE_DONE, 1))
3200 drm_err(&dev_priv->drm,
3201 "Timed out waiting for DP idle patterns\n");
3202 }
3203
intel_ddi_is_audio_enabled(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)3204 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3205 enum transcoder cpu_transcoder)
3206 {
3207 if (cpu_transcoder == TRANSCODER_EDP)
3208 return false;
3209
3210 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3211 return false;
3212
3213 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3214 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3215 }
3216
intel_ddi_compute_min_voltage_level(struct drm_i915_private * dev_priv,struct intel_crtc_state * crtc_state)3217 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3218 struct intel_crtc_state *crtc_state)
3219 {
3220 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3221 crtc_state->min_voltage_level = 2;
3222 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3223 crtc_state->min_voltage_level = 3;
3224 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3225 crtc_state->min_voltage_level = 1;
3226 }
3227
bdw_transcoder_master_readout(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)3228 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3229 enum transcoder cpu_transcoder)
3230 {
3231 u32 master_select;
3232
3233 if (DISPLAY_VER(dev_priv) >= 11) {
3234 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3235
3236 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3237 return INVALID_TRANSCODER;
3238
3239 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3240 } else {
3241 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3242
3243 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3244 return INVALID_TRANSCODER;
3245
3246 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3247 }
3248
3249 if (master_select == 0)
3250 return TRANSCODER_EDP;
3251 else
3252 return master_select - 1;
3253 }
3254
bdw_get_trans_port_sync_config(struct intel_crtc_state * crtc_state)3255 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3256 {
3257 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3258 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3259 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3260 enum transcoder cpu_transcoder;
3261
3262 crtc_state->master_transcoder =
3263 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3264
3265 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3266 enum intel_display_power_domain power_domain;
3267 intel_wakeref_t trans_wakeref;
3268
3269 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3270 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3271 power_domain);
3272
3273 if (!trans_wakeref)
3274 continue;
3275
3276 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3277 crtc_state->cpu_transcoder)
3278 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3279
3280 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3281 }
3282
3283 drm_WARN_ON(&dev_priv->drm,
3284 crtc_state->master_transcoder != INVALID_TRANSCODER &&
3285 crtc_state->sync_mode_slaves_mask);
3286 }
3287
intel_ddi_read_func_ctl(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)3288 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3289 struct intel_crtc_state *pipe_config)
3290 {
3291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3292 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3293 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3294 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3295 u32 temp, flags = 0;
3296
3297 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3298 if (temp & TRANS_DDI_PHSYNC)
3299 flags |= DRM_MODE_FLAG_PHSYNC;
3300 else
3301 flags |= DRM_MODE_FLAG_NHSYNC;
3302 if (temp & TRANS_DDI_PVSYNC)
3303 flags |= DRM_MODE_FLAG_PVSYNC;
3304 else
3305 flags |= DRM_MODE_FLAG_NVSYNC;
3306
3307 pipe_config->hw.adjusted_mode.flags |= flags;
3308
3309 switch (temp & TRANS_DDI_BPC_MASK) {
3310 case TRANS_DDI_BPC_6:
3311 pipe_config->pipe_bpp = 18;
3312 break;
3313 case TRANS_DDI_BPC_8:
3314 pipe_config->pipe_bpp = 24;
3315 break;
3316 case TRANS_DDI_BPC_10:
3317 pipe_config->pipe_bpp = 30;
3318 break;
3319 case TRANS_DDI_BPC_12:
3320 pipe_config->pipe_bpp = 36;
3321 break;
3322 default:
3323 break;
3324 }
3325
3326 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3327 case TRANS_DDI_MODE_SELECT_HDMI:
3328 pipe_config->has_hdmi_sink = true;
3329
3330 pipe_config->infoframes.enable |=
3331 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3332
3333 if (pipe_config->infoframes.enable)
3334 pipe_config->has_infoframe = true;
3335
3336 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3337 pipe_config->hdmi_scrambling = true;
3338 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3339 pipe_config->hdmi_high_tmds_clock_ratio = true;
3340 fallthrough;
3341 case TRANS_DDI_MODE_SELECT_DVI:
3342 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3343 pipe_config->lane_count = 4;
3344 break;
3345 case TRANS_DDI_MODE_SELECT_DP_SST:
3346 if (encoder->type == INTEL_OUTPUT_EDP)
3347 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3348 else
3349 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3350 pipe_config->lane_count =
3351 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3352
3353 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3354 &pipe_config->dp_m_n);
3355 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3356 &pipe_config->dp_m2_n2);
3357
3358 if (DISPLAY_VER(dev_priv) >= 11) {
3359 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3360
3361 pipe_config->fec_enable =
3362 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3363
3364 drm_dbg_kms(&dev_priv->drm,
3365 "[ENCODER:%d:%s] Fec status: %u\n",
3366 encoder->base.base.id, encoder->base.name,
3367 pipe_config->fec_enable);
3368 }
3369
3370 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3371 pipe_config->infoframes.enable |=
3372 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3373 else
3374 pipe_config->infoframes.enable |=
3375 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3376 break;
3377 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3378 if (!HAS_DP20(dev_priv)) {
3379 /* FDI */
3380 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3381 break;
3382 }
3383 fallthrough; /* 128b/132b */
3384 case TRANS_DDI_MODE_SELECT_DP_MST:
3385 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3386 pipe_config->lane_count =
3387 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3388
3389 if (DISPLAY_VER(dev_priv) >= 12)
3390 pipe_config->mst_master_transcoder =
3391 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3392
3393 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3394 &pipe_config->dp_m_n);
3395
3396 pipe_config->infoframes.enable |=
3397 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3398 break;
3399 default:
3400 break;
3401 }
3402 }
3403
intel_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)3404 static void intel_ddi_get_config(struct intel_encoder *encoder,
3405 struct intel_crtc_state *pipe_config)
3406 {
3407 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3408 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3409
3410 /* XXX: DSI transcoder paranoia */
3411 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3412 return;
3413
3414 intel_ddi_read_func_ctl(encoder, pipe_config);
3415
3416 intel_ddi_mso_get_config(encoder, pipe_config);
3417
3418 pipe_config->has_audio =
3419 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3420
3421 if (encoder->type == INTEL_OUTPUT_EDP)
3422 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
3423
3424 ddi_dotclock_get(pipe_config);
3425
3426 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3427 pipe_config->lane_lat_optim_mask =
3428 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3429
3430 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3431
3432 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3433
3434 intel_read_infoframe(encoder, pipe_config,
3435 HDMI_INFOFRAME_TYPE_AVI,
3436 &pipe_config->infoframes.avi);
3437 intel_read_infoframe(encoder, pipe_config,
3438 HDMI_INFOFRAME_TYPE_SPD,
3439 &pipe_config->infoframes.spd);
3440 intel_read_infoframe(encoder, pipe_config,
3441 HDMI_INFOFRAME_TYPE_VENDOR,
3442 &pipe_config->infoframes.hdmi);
3443 intel_read_infoframe(encoder, pipe_config,
3444 HDMI_INFOFRAME_TYPE_DRM,
3445 &pipe_config->infoframes.drm);
3446
3447 if (DISPLAY_VER(dev_priv) >= 8)
3448 bdw_get_trans_port_sync_config(pipe_config);
3449
3450 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3451 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3452
3453 intel_psr_get_config(encoder, pipe_config);
3454 }
3455
intel_ddi_get_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct intel_shared_dpll * pll)3456 void intel_ddi_get_clock(struct intel_encoder *encoder,
3457 struct intel_crtc_state *crtc_state,
3458 struct intel_shared_dpll *pll)
3459 {
3460 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3461 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3462 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3463 bool pll_active;
3464
3465 if (drm_WARN_ON(&i915->drm, !pll))
3466 return;
3467
3468 port_dpll->pll = pll;
3469 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3470 drm_WARN_ON(&i915->drm, !pll_active);
3471
3472 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3473
3474 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3475 &crtc_state->dpll_hw_state);
3476 }
3477
dg2_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3478 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3479 struct intel_crtc_state *crtc_state)
3480 {
3481 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3482 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3483
3484 intel_ddi_get_config(encoder, crtc_state);
3485 }
3486
adls_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3487 static void adls_ddi_get_config(struct intel_encoder *encoder,
3488 struct intel_crtc_state *crtc_state)
3489 {
3490 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3491 intel_ddi_get_config(encoder, crtc_state);
3492 }
3493
rkl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3494 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3495 struct intel_crtc_state *crtc_state)
3496 {
3497 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3498 intel_ddi_get_config(encoder, crtc_state);
3499 }
3500
dg1_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3501 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3502 struct intel_crtc_state *crtc_state)
3503 {
3504 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3505 intel_ddi_get_config(encoder, crtc_state);
3506 }
3507
icl_ddi_combo_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3508 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3509 struct intel_crtc_state *crtc_state)
3510 {
3511 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3512 intel_ddi_get_config(encoder, crtc_state);
3513 }
3514
icl_ddi_tc_get_clock(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct intel_shared_dpll * pll)3515 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3516 struct intel_crtc_state *crtc_state,
3517 struct intel_shared_dpll *pll)
3518 {
3519 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3520 enum icl_port_dpll_id port_dpll_id;
3521 struct icl_port_dpll *port_dpll;
3522 bool pll_active;
3523
3524 if (drm_WARN_ON(&i915->drm, !pll))
3525 return;
3526
3527 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3528 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3529 else
3530 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3531
3532 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3533
3534 port_dpll->pll = pll;
3535 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3536 drm_WARN_ON(&i915->drm, !pll_active);
3537
3538 icl_set_active_port_dpll(crtc_state, port_dpll_id);
3539
3540 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3541 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3542 else
3543 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3544 &crtc_state->dpll_hw_state);
3545 }
3546
icl_ddi_tc_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3547 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3548 struct intel_crtc_state *crtc_state)
3549 {
3550 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3551 intel_ddi_get_config(encoder, crtc_state);
3552 }
3553
bxt_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3554 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3555 struct intel_crtc_state *crtc_state)
3556 {
3557 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3558 intel_ddi_get_config(encoder, crtc_state);
3559 }
3560
skl_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3561 static void skl_ddi_get_config(struct intel_encoder *encoder,
3562 struct intel_crtc_state *crtc_state)
3563 {
3564 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3565 intel_ddi_get_config(encoder, crtc_state);
3566 }
3567
hsw_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3568 void hsw_ddi_get_config(struct intel_encoder *encoder,
3569 struct intel_crtc_state *crtc_state)
3570 {
3571 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3572 intel_ddi_get_config(encoder, crtc_state);
3573 }
3574
intel_ddi_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3575 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3576 const struct intel_crtc_state *crtc_state)
3577 {
3578 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3579 enum phy phy = intel_port_to_phy(i915, encoder->port);
3580
3581 if (intel_phy_is_tc(i915, phy))
3582 intel_tc_port_sanitize(enc_to_dig_port(encoder));
3583
3584 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
3585 intel_dp_sync_state(encoder, crtc_state);
3586 }
3587
intel_ddi_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3588 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3589 struct intel_crtc_state *crtc_state)
3590 {
3591 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3592 enum phy phy = intel_port_to_phy(i915, encoder->port);
3593 bool fastset = true;
3594
3595 if (intel_phy_is_tc(i915, phy)) {
3596 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
3597 encoder->base.base.id, encoder->base.name);
3598 crtc_state->uapi.mode_changed = true;
3599 fastset = false;
3600 }
3601
3602 if (intel_crtc_has_dp_encoder(crtc_state) &&
3603 !intel_dp_initial_fastset_check(encoder, crtc_state))
3604 fastset = false;
3605
3606 return fastset;
3607 }
3608
3609 static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)3610 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3611 struct intel_crtc_state *crtc_state,
3612 struct drm_connector_state *conn_state)
3613 {
3614 switch (conn_state->connector->connector_type) {
3615 case DRM_MODE_CONNECTOR_HDMIA:
3616 return INTEL_OUTPUT_HDMI;
3617 case DRM_MODE_CONNECTOR_eDP:
3618 return INTEL_OUTPUT_EDP;
3619 case DRM_MODE_CONNECTOR_DisplayPort:
3620 return INTEL_OUTPUT_DP;
3621 default:
3622 MISSING_CASE(conn_state->connector->connector_type);
3623 return INTEL_OUTPUT_UNUSED;
3624 }
3625 }
3626
intel_ddi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)3627 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3628 struct intel_crtc_state *pipe_config,
3629 struct drm_connector_state *conn_state)
3630 {
3631 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3632 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3633 enum port port = encoder->port;
3634 int ret;
3635
3636 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3637 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3638
3639 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3640 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3641 } else {
3642 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3643 }
3644
3645 if (ret)
3646 return ret;
3647
3648 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3649 pipe_config->cpu_transcoder == TRANSCODER_EDP)
3650 pipe_config->pch_pfit.force_thru =
3651 pipe_config->pch_pfit.enabled ||
3652 pipe_config->crc_enabled;
3653
3654 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3655 pipe_config->lane_lat_optim_mask =
3656 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3657
3658 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3659
3660 return 0;
3661 }
3662
mode_equal(const struct drm_display_mode * mode1,const struct drm_display_mode * mode2)3663 static bool mode_equal(const struct drm_display_mode *mode1,
3664 const struct drm_display_mode *mode2)
3665 {
3666 return drm_mode_match(mode1, mode2,
3667 DRM_MODE_MATCH_TIMINGS |
3668 DRM_MODE_MATCH_FLAGS |
3669 DRM_MODE_MATCH_3D_FLAGS) &&
3670 mode1->clock == mode2->clock; /* we want an exact match */
3671 }
3672
m_n_equal(const struct intel_link_m_n * m_n_1,const struct intel_link_m_n * m_n_2)3673 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3674 const struct intel_link_m_n *m_n_2)
3675 {
3676 return m_n_1->tu == m_n_2->tu &&
3677 m_n_1->data_m == m_n_2->data_m &&
3678 m_n_1->data_n == m_n_2->data_n &&
3679 m_n_1->link_m == m_n_2->link_m &&
3680 m_n_1->link_n == m_n_2->link_n;
3681 }
3682
crtcs_port_sync_compatible(const struct intel_crtc_state * crtc_state1,const struct intel_crtc_state * crtc_state2)3683 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3684 const struct intel_crtc_state *crtc_state2)
3685 {
3686 return crtc_state1->hw.active && crtc_state2->hw.active &&
3687 crtc_state1->output_types == crtc_state2->output_types &&
3688 crtc_state1->output_format == crtc_state2->output_format &&
3689 crtc_state1->lane_count == crtc_state2->lane_count &&
3690 crtc_state1->port_clock == crtc_state2->port_clock &&
3691 mode_equal(&crtc_state1->hw.adjusted_mode,
3692 &crtc_state2->hw.adjusted_mode) &&
3693 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3694 }
3695
3696 static u8
intel_ddi_port_sync_transcoders(const struct intel_crtc_state * ref_crtc_state,int tile_group_id)3697 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3698 int tile_group_id)
3699 {
3700 struct drm_connector *connector;
3701 const struct drm_connector_state *conn_state;
3702 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3703 struct intel_atomic_state *state =
3704 to_intel_atomic_state(ref_crtc_state->uapi.state);
3705 u8 transcoders = 0;
3706 int i;
3707
3708 /*
3709 * We don't enable port sync on BDW due to missing w/as and
3710 * due to not having adjusted the modeset sequence appropriately.
3711 */
3712 if (DISPLAY_VER(dev_priv) < 9)
3713 return 0;
3714
3715 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3716 return 0;
3717
3718 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3719 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3720 const struct intel_crtc_state *crtc_state;
3721
3722 if (!crtc)
3723 continue;
3724
3725 if (!connector->has_tile ||
3726 connector->tile_group->id !=
3727 tile_group_id)
3728 continue;
3729 crtc_state = intel_atomic_get_new_crtc_state(state,
3730 crtc);
3731 if (!crtcs_port_sync_compatible(ref_crtc_state,
3732 crtc_state))
3733 continue;
3734 transcoders |= BIT(crtc_state->cpu_transcoder);
3735 }
3736
3737 return transcoders;
3738 }
3739
intel_ddi_compute_config_late(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)3740 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3741 struct intel_crtc_state *crtc_state,
3742 struct drm_connector_state *conn_state)
3743 {
3744 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3745 struct drm_connector *connector = conn_state->connector;
3746 u8 port_sync_transcoders = 0;
3747
3748 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3749 encoder->base.base.id, encoder->base.name,
3750 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3751
3752 if (connector->has_tile)
3753 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3754 connector->tile_group->id);
3755
3756 /*
3757 * EDP Transcoders cannot be ensalved
3758 * make them a master always when present
3759 */
3760 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3761 crtc_state->master_transcoder = TRANSCODER_EDP;
3762 else
3763 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3764
3765 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3766 crtc_state->master_transcoder = INVALID_TRANSCODER;
3767 crtc_state->sync_mode_slaves_mask =
3768 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3769 }
3770
3771 return 0;
3772 }
3773
intel_ddi_encoder_destroy(struct drm_encoder * encoder)3774 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3775 {
3776 struct drm_i915_private *i915 = to_i915(encoder->dev);
3777 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3778 enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
3779
3780 intel_dp_encoder_flush_work(encoder);
3781 if (intel_phy_is_tc(i915, phy))
3782 intel_tc_port_flush_work(dig_port);
3783 intel_display_power_flush_work(i915);
3784
3785 drm_encoder_cleanup(encoder);
3786 kfree(dig_port->hdcp_port_data.streams);
3787 kfree(dig_port);
3788 }
3789
intel_ddi_encoder_reset(struct drm_encoder * encoder)3790 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
3791 {
3792 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
3793
3794 intel_dp->reset_link_params = true;
3795
3796 intel_pps_encoder_reset(intel_dp);
3797 }
3798
3799 static const struct drm_encoder_funcs intel_ddi_funcs = {
3800 .reset = intel_ddi_encoder_reset,
3801 .destroy = intel_ddi_encoder_destroy,
3802 };
3803
3804 static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port * dig_port)3805 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
3806 {
3807 struct intel_connector *connector;
3808 enum port port = dig_port->base.port;
3809
3810 connector = intel_connector_alloc();
3811 if (!connector)
3812 return NULL;
3813
3814 dig_port->dp.output_reg = DDI_BUF_CTL(port);
3815 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
3816 dig_port->dp.set_link_train = intel_ddi_set_link_train;
3817 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
3818
3819 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
3820 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
3821
3822 if (!intel_dp_init_connector(dig_port, connector)) {
3823 kfree(connector);
3824 return NULL;
3825 }
3826
3827 if (dig_port->base.type == INTEL_OUTPUT_EDP) {
3828 struct drm_device *dev = dig_port->base.base.dev;
3829 struct drm_privacy_screen *privacy_screen;
3830
3831 privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
3832 if (!IS_ERR(privacy_screen)) {
3833 drm_connector_attach_privacy_screen_provider(&connector->base,
3834 privacy_screen);
3835 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
3836 drm_warn(dev, "Error getting privacy-screen\n");
3837 }
3838 }
3839
3840 return connector;
3841 }
3842
modeset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)3843 static int modeset_pipe(struct drm_crtc *crtc,
3844 struct drm_modeset_acquire_ctx *ctx)
3845 {
3846 struct drm_atomic_state *state;
3847 struct drm_crtc_state *crtc_state;
3848 int ret;
3849
3850 state = drm_atomic_state_alloc(crtc->dev);
3851 if (!state)
3852 return -ENOMEM;
3853
3854 state->acquire_ctx = ctx;
3855
3856 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3857 if (IS_ERR(crtc_state)) {
3858 ret = PTR_ERR(crtc_state);
3859 goto out;
3860 }
3861
3862 crtc_state->connectors_changed = true;
3863
3864 ret = drm_atomic_commit(state);
3865 out:
3866 drm_atomic_state_put(state);
3867
3868 return ret;
3869 }
3870
intel_hdmi_reset_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)3871 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3872 struct drm_modeset_acquire_ctx *ctx)
3873 {
3874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3875 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
3876 struct intel_connector *connector = hdmi->attached_connector;
3877 struct i2c_adapter *adapter =
3878 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3879 struct drm_connector_state *conn_state;
3880 struct intel_crtc_state *crtc_state;
3881 struct intel_crtc *crtc;
3882 u8 config;
3883 int ret;
3884
3885 if (!connector || connector->base.status != connector_status_connected)
3886 return 0;
3887
3888 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3889 ctx);
3890 if (ret)
3891 return ret;
3892
3893 conn_state = connector->base.state;
3894
3895 crtc = to_intel_crtc(conn_state->crtc);
3896 if (!crtc)
3897 return 0;
3898
3899 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3900 if (ret)
3901 return ret;
3902
3903 crtc_state = to_intel_crtc_state(crtc->base.state);
3904
3905 drm_WARN_ON(&dev_priv->drm,
3906 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3907
3908 if (!crtc_state->hw.active)
3909 return 0;
3910
3911 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3912 !crtc_state->hdmi_scrambling)
3913 return 0;
3914
3915 if (conn_state->commit &&
3916 !try_wait_for_completion(&conn_state->commit->hw_done))
3917 return 0;
3918
3919 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3920 if (ret < 0) {
3921 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
3922 ret);
3923 return 0;
3924 }
3925
3926 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3927 crtc_state->hdmi_high_tmds_clock_ratio &&
3928 !!(config & SCDC_SCRAMBLING_ENABLE) ==
3929 crtc_state->hdmi_scrambling)
3930 return 0;
3931
3932 /*
3933 * HDMI 2.0 says that one should not send scrambled data
3934 * prior to configuring the sink scrambling, and that
3935 * TMDS clock/data transmission should be suspended when
3936 * changing the TMDS clock rate in the sink. So let's
3937 * just do a full modeset here, even though some sinks
3938 * would be perfectly happy if were to just reconfigure
3939 * the SCDC settings on the fly.
3940 */
3941 return modeset_pipe(&crtc->base, ctx);
3942 }
3943
3944 static enum intel_hotplug_state
intel_ddi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)3945 intel_ddi_hotplug(struct intel_encoder *encoder,
3946 struct intel_connector *connector)
3947 {
3948 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3949 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3950 struct intel_dp *intel_dp = &dig_port->dp;
3951 enum phy phy = intel_port_to_phy(i915, encoder->port);
3952 bool is_tc = intel_phy_is_tc(i915, phy);
3953 struct drm_modeset_acquire_ctx ctx;
3954 enum intel_hotplug_state state;
3955 int ret;
3956
3957 if (intel_dp->compliance.test_active &&
3958 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
3959 intel_dp_phy_test(encoder);
3960 /* just do the PHY test and nothing else */
3961 return INTEL_HOTPLUG_UNCHANGED;
3962 }
3963
3964 state = intel_encoder_hotplug(encoder, connector);
3965
3966 drm_modeset_acquire_init(&ctx, 0);
3967
3968 for (;;) {
3969 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3970 ret = intel_hdmi_reset_link(encoder, &ctx);
3971 else
3972 ret = intel_dp_retrain_link(encoder, &ctx);
3973
3974 if (ret == -EDEADLK) {
3975 drm_modeset_backoff(&ctx);
3976 continue;
3977 }
3978
3979 break;
3980 }
3981
3982 drm_modeset_drop_locks(&ctx);
3983 drm_modeset_acquire_fini(&ctx);
3984 drm_WARN(encoder->base.dev, ret,
3985 "Acquiring modeset locks failed with %i\n", ret);
3986
3987 /*
3988 * Unpowered type-c dongles can take some time to boot and be
3989 * responsible, so here giving some time to those dongles to power up
3990 * and then retrying the probe.
3991 *
3992 * On many platforms the HDMI live state signal is known to be
3993 * unreliable, so we can't use it to detect if a sink is connected or
3994 * not. Instead we detect if it's connected based on whether we can
3995 * read the EDID or not. That in turn has a problem during disconnect,
3996 * since the HPD interrupt may be raised before the DDC lines get
3997 * disconnected (due to how the required length of DDC vs. HPD
3998 * connector pins are specified) and so we'll still be able to get a
3999 * valid EDID. To solve this schedule another detection cycle if this
4000 * time around we didn't detect any change in the sink's connection
4001 * status.
4002 *
4003 * Type-c connectors which get their HPD signal deasserted then
4004 * reasserted, without unplugging/replugging the sink from the
4005 * connector, introduce a delay until the AUX channel communication
4006 * becomes functional. Retry the detection for 5 seconds on type-c
4007 * connectors to account for this delay.
4008 */
4009 if (state == INTEL_HOTPLUG_UNCHANGED &&
4010 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4011 !dig_port->dp.is_mst)
4012 state = INTEL_HOTPLUG_RETRY;
4013
4014 return state;
4015 }
4016
lpt_digital_port_connected(struct intel_encoder * encoder)4017 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4018 {
4019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4020 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
4021
4022 return intel_de_read(dev_priv, SDEISR) & bit;
4023 }
4024
hsw_digital_port_connected(struct intel_encoder * encoder)4025 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4026 {
4027 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4028 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4029
4030 return intel_de_read(dev_priv, DEISR) & bit;
4031 }
4032
bdw_digital_port_connected(struct intel_encoder * encoder)4033 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4034 {
4035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4036 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
4037
4038 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4039 }
4040
4041 static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port * dig_port)4042 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4043 {
4044 struct intel_connector *connector;
4045 enum port port = dig_port->base.port;
4046
4047 connector = intel_connector_alloc();
4048 if (!connector)
4049 return NULL;
4050
4051 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4052 intel_hdmi_init_connector(dig_port, connector);
4053
4054 return connector;
4055 }
4056
intel_ddi_a_force_4_lanes(struct intel_digital_port * dig_port)4057 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4058 {
4059 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4060
4061 if (dig_port->base.port != PORT_A)
4062 return false;
4063
4064 if (dig_port->saved_port_bits & DDI_A_4_LANES)
4065 return false;
4066
4067 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4068 * supported configuration
4069 */
4070 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4071 return true;
4072
4073 return false;
4074 }
4075
4076 static int
intel_ddi_max_lanes(struct intel_digital_port * dig_port)4077 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4078 {
4079 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4080 enum port port = dig_port->base.port;
4081 int max_lanes = 4;
4082
4083 if (DISPLAY_VER(dev_priv) >= 11)
4084 return max_lanes;
4085
4086 if (port == PORT_A || port == PORT_E) {
4087 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4088 max_lanes = port == PORT_A ? 4 : 0;
4089 else
4090 /* Both A and E share 2 lanes */
4091 max_lanes = 2;
4092 }
4093
4094 /*
4095 * Some BIOS might fail to set this bit on port A if eDP
4096 * wasn't lit up at boot. Force this bit set when needed
4097 * so we use the proper lane count for our calculations.
4098 */
4099 if (intel_ddi_a_force_4_lanes(dig_port)) {
4100 drm_dbg_kms(&dev_priv->drm,
4101 "Forcing DDI_A_4_LANES for port A\n");
4102 dig_port->saved_port_bits |= DDI_A_4_LANES;
4103 max_lanes = 4;
4104 }
4105
4106 return max_lanes;
4107 }
4108
hti_uses_phy(struct drm_i915_private * i915,enum phy phy)4109 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4110 {
4111 return i915->hti_state & HDPORT_ENABLED &&
4112 i915->hti_state & HDPORT_DDI_USED(phy);
4113 }
4114
xelpd_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4115 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4116 enum port port)
4117 {
4118 if (port >= PORT_D_XELPD)
4119 return HPD_PORT_D + port - PORT_D_XELPD;
4120 else if (port >= PORT_TC1)
4121 return HPD_PORT_TC1 + port - PORT_TC1;
4122 else
4123 return HPD_PORT_A + port - PORT_A;
4124 }
4125
dg1_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4126 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4127 enum port port)
4128 {
4129 if (port >= PORT_TC1)
4130 return HPD_PORT_C + port - PORT_TC1;
4131 else
4132 return HPD_PORT_A + port - PORT_A;
4133 }
4134
tgl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4135 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4136 enum port port)
4137 {
4138 if (port >= PORT_TC1)
4139 return HPD_PORT_TC1 + port - PORT_TC1;
4140 else
4141 return HPD_PORT_A + port - PORT_A;
4142 }
4143
rkl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4144 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4145 enum port port)
4146 {
4147 if (HAS_PCH_TGP(dev_priv))
4148 return tgl_hpd_pin(dev_priv, port);
4149
4150 if (port >= PORT_TC1)
4151 return HPD_PORT_C + port - PORT_TC1;
4152 else
4153 return HPD_PORT_A + port - PORT_A;
4154 }
4155
icl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4156 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4157 enum port port)
4158 {
4159 if (port >= PORT_C)
4160 return HPD_PORT_TC1 + port - PORT_C;
4161 else
4162 return HPD_PORT_A + port - PORT_A;
4163 }
4164
ehl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4165 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4166 enum port port)
4167 {
4168 if (port == PORT_D)
4169 return HPD_PORT_A;
4170
4171 if (HAS_PCH_TGP(dev_priv))
4172 return icl_hpd_pin(dev_priv, port);
4173
4174 return HPD_PORT_A + port - PORT_A;
4175 }
4176
skl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4177 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4178 {
4179 if (HAS_PCH_TGP(dev_priv))
4180 return icl_hpd_pin(dev_priv, port);
4181
4182 return HPD_PORT_A + port - PORT_A;
4183 }
4184
intel_ddi_is_tc(struct drm_i915_private * i915,enum port port)4185 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4186 {
4187 if (DISPLAY_VER(i915) >= 12)
4188 return port >= PORT_TC1;
4189 else if (DISPLAY_VER(i915) >= 11)
4190 return port >= PORT_C;
4191 else
4192 return false;
4193 }
4194
intel_ddi_encoder_suspend(struct intel_encoder * encoder)4195 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4196 {
4197 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4198 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4199 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4200 enum phy phy = intel_port_to_phy(i915, encoder->port);
4201
4202 intel_dp_encoder_suspend(encoder);
4203
4204 if (!intel_phy_is_tc(i915, phy))
4205 return;
4206
4207 intel_tc_port_flush_work(dig_port);
4208 }
4209
intel_ddi_encoder_shutdown(struct intel_encoder * encoder)4210 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4211 {
4212 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4213 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4214 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4215 enum phy phy = intel_port_to_phy(i915, encoder->port);
4216
4217 intel_dp_encoder_shutdown(encoder);
4218 intel_hdmi_encoder_shutdown(encoder);
4219
4220 if (!intel_phy_is_tc(i915, phy))
4221 return;
4222
4223 intel_tc_port_flush_work(dig_port);
4224 }
4225
4226 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4227 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4228
intel_ddi_init(struct drm_i915_private * dev_priv,enum port port)4229 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4230 {
4231 struct intel_digital_port *dig_port;
4232 struct intel_encoder *encoder;
4233 const struct intel_bios_encoder_data *devdata;
4234 bool init_hdmi, init_dp;
4235 enum phy phy = intel_port_to_phy(dev_priv, port);
4236
4237 /*
4238 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4239 * have taken over some of the PHYs and made them unavailable to the
4240 * driver. In that case we should skip initializing the corresponding
4241 * outputs.
4242 */
4243 if (hti_uses_phy(dev_priv, phy)) {
4244 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4245 port_name(port), phy_name(phy));
4246 return;
4247 }
4248
4249 devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4250 if (!devdata) {
4251 drm_dbg_kms(&dev_priv->drm,
4252 "VBT says port %c is not present\n",
4253 port_name(port));
4254 return;
4255 }
4256
4257 init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4258 intel_bios_encoder_supports_hdmi(devdata);
4259 init_dp = intel_bios_encoder_supports_dp(devdata);
4260
4261 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4262 /*
4263 * Lspcon device needs to be driven with DP connector
4264 * with special detection sequence. So make sure DP
4265 * is initialized before lspcon.
4266 */
4267 init_dp = true;
4268 init_hdmi = false;
4269 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4270 port_name(port));
4271 }
4272
4273 if (!init_dp && !init_hdmi) {
4274 drm_dbg_kms(&dev_priv->drm,
4275 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4276 port_name(port));
4277 return;
4278 }
4279
4280 if (intel_phy_is_snps(dev_priv, phy) &&
4281 dev_priv->snps_phy_failed_calibration & BIT(phy)) {
4282 drm_dbg_kms(&dev_priv->drm,
4283 "SNPS PHY %c failed to calibrate, proceeding anyway\n",
4284 phy_name(phy));
4285 }
4286
4287 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4288 if (!dig_port)
4289 return;
4290
4291 encoder = &dig_port->base;
4292 encoder->devdata = devdata;
4293
4294 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4295 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4296 DRM_MODE_ENCODER_TMDS,
4297 "DDI %c/PHY %c",
4298 port_name(port - PORT_D_XELPD + PORT_D),
4299 phy_name(phy));
4300 } else if (DISPLAY_VER(dev_priv) >= 12) {
4301 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4302
4303 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4304 DRM_MODE_ENCODER_TMDS,
4305 "DDI %s%c/PHY %s%c",
4306 port >= PORT_TC1 ? "TC" : "",
4307 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4308 tc_port != TC_PORT_NONE ? "TC" : "",
4309 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4310 } else if (DISPLAY_VER(dev_priv) >= 11) {
4311 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4312
4313 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4314 DRM_MODE_ENCODER_TMDS,
4315 "DDI %c%s/PHY %s%c",
4316 port_name(port),
4317 port >= PORT_C ? " (TC)" : "",
4318 tc_port != TC_PORT_NONE ? "TC" : "",
4319 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4320 } else {
4321 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4322 DRM_MODE_ENCODER_TMDS,
4323 "DDI %c/PHY %c", port_name(port), phy_name(phy));
4324 }
4325
4326 mutex_init(&dig_port->hdcp_mutex);
4327 dig_port->num_hdcp_streams = 0;
4328
4329 encoder->hotplug = intel_ddi_hotplug;
4330 encoder->compute_output_type = intel_ddi_compute_output_type;
4331 encoder->compute_config = intel_ddi_compute_config;
4332 encoder->compute_config_late = intel_ddi_compute_config_late;
4333 encoder->enable = intel_enable_ddi;
4334 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4335 encoder->pre_enable = intel_ddi_pre_enable;
4336 encoder->disable = intel_disable_ddi;
4337 encoder->post_disable = intel_ddi_post_disable;
4338 encoder->update_pipe = intel_ddi_update_pipe;
4339 encoder->get_hw_state = intel_ddi_get_hw_state;
4340 encoder->sync_state = intel_ddi_sync_state;
4341 encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4342 encoder->suspend = intel_ddi_encoder_suspend;
4343 encoder->shutdown = intel_ddi_encoder_shutdown;
4344 encoder->get_power_domains = intel_ddi_get_power_domains;
4345
4346 encoder->type = INTEL_OUTPUT_DDI;
4347 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
4348 encoder->port = port;
4349 encoder->cloneable = 0;
4350 encoder->pipe_mask = ~0;
4351
4352 if (IS_DG2(dev_priv)) {
4353 encoder->enable_clock = intel_mpllb_enable;
4354 encoder->disable_clock = intel_mpllb_disable;
4355 encoder->get_config = dg2_ddi_get_config;
4356 } else if (IS_ALDERLAKE_S(dev_priv)) {
4357 encoder->enable_clock = adls_ddi_enable_clock;
4358 encoder->disable_clock = adls_ddi_disable_clock;
4359 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4360 encoder->get_config = adls_ddi_get_config;
4361 } else if (IS_ROCKETLAKE(dev_priv)) {
4362 encoder->enable_clock = rkl_ddi_enable_clock;
4363 encoder->disable_clock = rkl_ddi_disable_clock;
4364 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4365 encoder->get_config = rkl_ddi_get_config;
4366 } else if (IS_DG1(dev_priv)) {
4367 encoder->enable_clock = dg1_ddi_enable_clock;
4368 encoder->disable_clock = dg1_ddi_disable_clock;
4369 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4370 encoder->get_config = dg1_ddi_get_config;
4371 } else if (IS_JSL_EHL(dev_priv)) {
4372 if (intel_ddi_is_tc(dev_priv, port)) {
4373 encoder->enable_clock = jsl_ddi_tc_enable_clock;
4374 encoder->disable_clock = jsl_ddi_tc_disable_clock;
4375 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4376 encoder->get_config = icl_ddi_combo_get_config;
4377 } else {
4378 encoder->enable_clock = icl_ddi_combo_enable_clock;
4379 encoder->disable_clock = icl_ddi_combo_disable_clock;
4380 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4381 encoder->get_config = icl_ddi_combo_get_config;
4382 }
4383 } else if (DISPLAY_VER(dev_priv) >= 11) {
4384 if (intel_ddi_is_tc(dev_priv, port)) {
4385 encoder->enable_clock = icl_ddi_tc_enable_clock;
4386 encoder->disable_clock = icl_ddi_tc_disable_clock;
4387 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4388 encoder->get_config = icl_ddi_tc_get_config;
4389 } else {
4390 encoder->enable_clock = icl_ddi_combo_enable_clock;
4391 encoder->disable_clock = icl_ddi_combo_disable_clock;
4392 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4393 encoder->get_config = icl_ddi_combo_get_config;
4394 }
4395 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4396 /* BXT/GLK have fixed PLL->port mapping */
4397 encoder->get_config = bxt_ddi_get_config;
4398 } else if (DISPLAY_VER(dev_priv) == 9) {
4399 encoder->enable_clock = skl_ddi_enable_clock;
4400 encoder->disable_clock = skl_ddi_disable_clock;
4401 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4402 encoder->get_config = skl_ddi_get_config;
4403 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4404 encoder->enable_clock = hsw_ddi_enable_clock;
4405 encoder->disable_clock = hsw_ddi_disable_clock;
4406 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4407 encoder->get_config = hsw_ddi_get_config;
4408 }
4409
4410 if (IS_DG2(dev_priv)) {
4411 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
4412 } else if (DISPLAY_VER(dev_priv) >= 12) {
4413 if (intel_phy_is_combo(dev_priv, phy))
4414 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4415 else
4416 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
4417 } else if (DISPLAY_VER(dev_priv) >= 11) {
4418 if (intel_phy_is_combo(dev_priv, phy))
4419 encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4420 else
4421 encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
4422 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4423 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
4424 } else {
4425 encoder->set_signal_levels = hsw_set_signal_levels;
4426 }
4427
4428 intel_ddi_buf_trans_init(encoder);
4429
4430 if (DISPLAY_VER(dev_priv) >= 13)
4431 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4432 else if (IS_DG1(dev_priv))
4433 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4434 else if (IS_ROCKETLAKE(dev_priv))
4435 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4436 else if (DISPLAY_VER(dev_priv) >= 12)
4437 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4438 else if (IS_JSL_EHL(dev_priv))
4439 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4440 else if (DISPLAY_VER(dev_priv) == 11)
4441 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4442 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4443 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4444 else
4445 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4446
4447 if (DISPLAY_VER(dev_priv) >= 11)
4448 dig_port->saved_port_bits =
4449 intel_de_read(dev_priv, DDI_BUF_CTL(port))
4450 & DDI_BUF_PORT_REVERSAL;
4451 else
4452 dig_port->saved_port_bits =
4453 intel_de_read(dev_priv, DDI_BUF_CTL(port))
4454 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4455
4456 if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4457 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4458
4459 dig_port->dp.output_reg = INVALID_MMIO_REG;
4460 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4461 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4462
4463 if (intel_phy_is_tc(dev_priv, phy)) {
4464 bool is_legacy =
4465 !intel_bios_encoder_supports_typec_usb(devdata) &&
4466 !intel_bios_encoder_supports_tbt(devdata);
4467
4468 intel_tc_port_init(dig_port, is_legacy);
4469
4470 encoder->update_prepare = intel_ddi_update_prepare;
4471 encoder->update_complete = intel_ddi_update_complete;
4472 }
4473
4474 drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4475 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
4476
4477 if (init_dp) {
4478 if (!intel_ddi_init_dp_connector(dig_port))
4479 goto err;
4480
4481 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4482
4483 if (dig_port->dp.mso_link_count)
4484 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4485 }
4486
4487 /* In theory we don't need the encoder->type check, but leave it just in
4488 * case we have some really bad VBTs... */
4489 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4490 if (!intel_ddi_init_hdmi_connector(dig_port))
4491 goto err;
4492 }
4493
4494 if (DISPLAY_VER(dev_priv) >= 11) {
4495 if (intel_phy_is_tc(dev_priv, phy))
4496 dig_port->connected = intel_tc_port_connected;
4497 else
4498 dig_port->connected = lpt_digital_port_connected;
4499 } else if (DISPLAY_VER(dev_priv) >= 8) {
4500 if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4501 IS_BROXTON(dev_priv))
4502 dig_port->connected = bdw_digital_port_connected;
4503 else
4504 dig_port->connected = lpt_digital_port_connected;
4505 } else {
4506 if (port == PORT_A)
4507 dig_port->connected = hsw_digital_port_connected;
4508 else
4509 dig_port->connected = lpt_digital_port_connected;
4510 }
4511
4512 intel_infoframe_init(dig_port);
4513
4514 return;
4515
4516 err:
4517 drm_encoder_cleanup(&encoder->base);
4518 kfree(dig_port);
4519 }
4520