1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 */
5
6 #include "i915_reg.h"
7 #include "intel_combo_phy.h"
8 #include "intel_combo_phy_regs.h"
9 #include "intel_de.h"
10 #include "intel_display_types.h"
11
12 #define for_each_combo_phy(__dev_priv, __phy) \
13 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
14 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
15
16 #define for_each_combo_phy_reverse(__dev_priv, __phy) \
17 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
18 for_each_if(intel_phy_is_combo(__dev_priv, __phy))
19
20 enum {
21 PROCMON_0_85V_DOT_0,
22 PROCMON_0_95V_DOT_0,
23 PROCMON_0_95V_DOT_1,
24 PROCMON_1_05V_DOT_0,
25 PROCMON_1_05V_DOT_1,
26 };
27
28 static const struct icl_procmon {
29 const char *name;
30 u32 dw1, dw9, dw10;
31 } icl_procmon_values[] = {
32 [PROCMON_0_85V_DOT_0] = {
33 .name = "0.85V dot0 (low-voltage)",
34 .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96,
35 },
36 [PROCMON_0_95V_DOT_0] = {
37 .name = "0.95V dot0",
38 .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB,
39 },
40 [PROCMON_0_95V_DOT_1] = {
41 .name = "0.95V dot1",
42 .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5,
43 },
44 [PROCMON_1_05V_DOT_0] = {
45 .name = "1.05V dot0",
46 .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1,
47 },
48 [PROCMON_1_05V_DOT_1] = {
49 .name = "1.05V dot1",
50 .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1,
51 },
52 };
53
54 static const struct icl_procmon *
icl_get_procmon_ref_values(struct drm_i915_private * dev_priv,enum phy phy)55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56 {
57 u32 val;
58
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
60 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
61 default:
62 MISSING_CASE(val);
63 fallthrough;
64 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
65 return &icl_procmon_values[PROCMON_0_85V_DOT_0];
66 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
67 return &icl_procmon_values[PROCMON_0_95V_DOT_0];
68 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
69 return &icl_procmon_values[PROCMON_0_95V_DOT_1];
70 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
71 return &icl_procmon_values[PROCMON_1_05V_DOT_0];
72 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
73 return &icl_procmon_values[PROCMON_1_05V_DOT_1];
74 }
75 }
76
icl_set_procmon_ref_values(struct drm_i915_private * dev_priv,enum phy phy)77 static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
78 enum phy phy)
79 {
80 const struct icl_procmon *procmon;
81
82 procmon = icl_get_procmon_ref_values(dev_priv, phy);
83
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy),
85 (0xff << 16) | 0xff, procmon->dw1);
86
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
89 }
90
check_phy_reg(struct drm_i915_private * dev_priv,enum phy phy,i915_reg_t reg,u32 mask,u32 expected_val)91 static bool check_phy_reg(struct drm_i915_private *dev_priv,
92 enum phy phy, i915_reg_t reg, u32 mask,
93 u32 expected_val)
94 {
95 u32 val = intel_de_read(dev_priv, reg);
96
97 if ((val & mask) != expected_val) {
98 drm_dbg(&dev_priv->drm,
99 "Combo PHY %c reg %08x state mismatch: "
100 "current %08x mask %08x expected %08x\n",
101 phy_name(phy),
102 reg.reg, val, mask, expected_val);
103 return false;
104 }
105
106 return true;
107 }
108
icl_verify_procmon_ref_values(struct drm_i915_private * dev_priv,enum phy phy)109 static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
110 enum phy phy)
111 {
112 const struct icl_procmon *procmon;
113 bool ret;
114
115 procmon = icl_get_procmon_ref_values(dev_priv, phy);
116
117 drm_dbg_kms(&dev_priv->drm,
118 "Combo PHY %c Voltage/Process Info : %s\n",
119 phy_name(phy), procmon->name);
120
121 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
122 (0xff << 16) | 0xff, procmon->dw1);
123 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
124 -1U, procmon->dw9);
125 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
126 -1U, procmon->dw10);
127
128 return ret;
129 }
130
has_phy_misc(struct drm_i915_private * i915,enum phy phy)131 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
132 {
133 /*
134 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
135 * PHY-B and may not even have instances of the register for the
136 * other combo PHY's.
137 *
138 * ADL-S technically has three instances of PHY_MISC, but only requires
139 * that we program it for PHY A.
140 */
141
142 if (IS_ALDERLAKE_S(i915))
143 return phy == PHY_A;
144 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
145 IS_ROCKETLAKE(i915) ||
146 IS_DG1(i915))
147 return phy < PHY_C;
148
149 return true;
150 }
151
icl_combo_phy_enabled(struct drm_i915_private * dev_priv,enum phy phy)152 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
153 enum phy phy)
154 {
155 /* The PHY C added by EHL has no PHY_MISC register */
156 if (!has_phy_misc(dev_priv, phy))
157 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
158 else
159 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
160 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
161 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
162 }
163
ehl_vbt_ddi_d_present(struct drm_i915_private * i915)164 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
165 {
166 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
167 bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
168 bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
169
170 /*
171 * VBT's 'dvo port' field for child devices references the DDI, not
172 * the PHY. So if combo PHY A is wired up to drive an external
173 * display, we should see a child device present on PORT_D and
174 * nothing on PORT_A and no DSI.
175 */
176 if (ddi_d_present && !ddi_a_present && !dsi_present)
177 return true;
178
179 /*
180 * If we encounter a VBT that claims to have an external display on
181 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
182 * in the log and let the internal display win.
183 */
184 if (ddi_d_present)
185 drm_err(&i915->drm,
186 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n");
187
188 return false;
189 }
190
phy_is_master(struct drm_i915_private * dev_priv,enum phy phy)191 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
192 {
193 /*
194 * Certain PHYs are connected to compensation resistors and act
195 * as masters to other PHYs.
196 *
197 * ICL,TGL:
198 * A(master) -> B(slave), C(slave)
199 * RKL,DG1:
200 * A(master) -> B(slave)
201 * C(master) -> D(slave)
202 * ADL-S:
203 * A(master) -> B(slave), C(slave)
204 * D(master) -> E(slave)
205 *
206 * We must set the IREFGEN bit for any PHY acting as a master
207 * to another PHY.
208 */
209 if (phy == PHY_A)
210 return true;
211 else if (IS_ALDERLAKE_S(dev_priv))
212 return phy == PHY_D;
213 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
214 return phy == PHY_C;
215
216 return false;
217 }
218
icl_combo_phy_verify_state(struct drm_i915_private * dev_priv,enum phy phy)219 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
220 enum phy phy)
221 {
222 bool ret = true;
223 u32 expected_val = 0;
224
225 if (!icl_combo_phy_enabled(dev_priv, phy))
226 return false;
227
228 if (DISPLAY_VER(dev_priv) >= 12) {
229 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
230 ICL_PORT_TX_DW8_ODCC_CLK_SEL |
231 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
232 ICL_PORT_TX_DW8_ODCC_CLK_SEL |
233 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
234
235 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
236 DCC_MODE_SELECT_MASK, RUN_DCC_ONCE);
237 }
238
239 ret &= icl_verify_procmon_ref_values(dev_priv, phy);
240
241 if (phy_is_master(dev_priv, phy)) {
242 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
243 IREFGEN, IREFGEN);
244
245 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
246 if (ehl_vbt_ddi_d_present(dev_priv))
247 expected_val = ICL_PHY_MISC_MUX_DDID;
248
249 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
250 ICL_PHY_MISC_MUX_DDID,
251 expected_val);
252 }
253 }
254
255 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
256 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
257
258 return ret;
259 }
260
intel_combo_phy_power_up_lanes(struct drm_i915_private * dev_priv,enum phy phy,bool is_dsi,int lane_count,bool lane_reversal)261 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
262 enum phy phy, bool is_dsi,
263 int lane_count, bool lane_reversal)
264 {
265 u8 lane_mask;
266
267 if (is_dsi) {
268 drm_WARN_ON(&dev_priv->drm, lane_reversal);
269
270 switch (lane_count) {
271 case 1:
272 lane_mask = PWR_DOWN_LN_3_1_0;
273 break;
274 case 2:
275 lane_mask = PWR_DOWN_LN_3_1;
276 break;
277 case 3:
278 lane_mask = PWR_DOWN_LN_3;
279 break;
280 default:
281 MISSING_CASE(lane_count);
282 fallthrough;
283 case 4:
284 lane_mask = PWR_UP_ALL_LANES;
285 break;
286 }
287 } else {
288 switch (lane_count) {
289 case 1:
290 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
291 PWR_DOWN_LN_3_2_1;
292 break;
293 case 2:
294 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
295 PWR_DOWN_LN_3_2;
296 break;
297 default:
298 MISSING_CASE(lane_count);
299 fallthrough;
300 case 4:
301 lane_mask = PWR_UP_ALL_LANES;
302 break;
303 }
304 }
305
306 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy),
307 PWR_DOWN_LN_MASK, lane_mask);
308 }
309
icl_combo_phys_init(struct drm_i915_private * dev_priv)310 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
311 {
312 enum phy phy;
313
314 for_each_combo_phy(dev_priv, phy) {
315 u32 val;
316
317 if (icl_combo_phy_verify_state(dev_priv, phy)) {
318 drm_dbg(&dev_priv->drm,
319 "Combo PHY %c already enabled, won't reprogram it.\n",
320 phy_name(phy));
321 continue;
322 }
323
324 if (!has_phy_misc(dev_priv, phy))
325 goto skip_phy_misc;
326
327 /*
328 * EHL's combo PHY A can be hooked up to either an external
329 * display (via DDI-D) or an internal display (via DDI-A or
330 * the DSI DPHY). This is a motherboard design decision that
331 * can't be changed on the fly, so initialize the PHY's mux
332 * based on whether our VBT indicates the presence of any
333 * "internal" child devices.
334 */
335 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
336 if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
337 phy == PHY_A) {
338 val &= ~ICL_PHY_MISC_MUX_DDID;
339
340 if (ehl_vbt_ddi_d_present(dev_priv))
341 val |= ICL_PHY_MISC_MUX_DDID;
342 }
343
344 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
345 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
346
347 skip_phy_misc:
348 if (DISPLAY_VER(dev_priv) >= 12) {
349 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
350 val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
351 val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
352 val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
353 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
354
355 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
356 val &= ~DCC_MODE_SELECT_MASK;
357 val |= RUN_DCC_ONCE;
358 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
359 }
360
361 icl_set_procmon_ref_values(dev_priv, phy);
362
363 if (phy_is_master(dev_priv, phy))
364 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy),
365 0, IREFGEN);
366
367 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
368 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
369 0, CL_POWER_DOWN_ENABLE);
370 }
371 }
372
icl_combo_phys_uninit(struct drm_i915_private * dev_priv)373 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
374 {
375 enum phy phy;
376
377 for_each_combo_phy_reverse(dev_priv, phy) {
378 if (phy == PHY_A &&
379 !icl_combo_phy_verify_state(dev_priv, phy)) {
380 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
381 /*
382 * A known problem with old ifwi:
383 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411
384 * Suppress the warning for CI. Remove ASAP!
385 */
386 drm_dbg_kms(&dev_priv->drm,
387 "Combo PHY %c HW state changed unexpectedly\n",
388 phy_name(phy));
389 } else {
390 drm_warn(&dev_priv->drm,
391 "Combo PHY %c HW state changed unexpectedly\n",
392 phy_name(phy));
393 }
394 }
395
396 if (!has_phy_misc(dev_priv, phy))
397 goto skip_phy_misc;
398
399 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0,
400 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN);
401
402 skip_phy_misc:
403 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);
404 }
405 }
406
intel_combo_phy_init(struct drm_i915_private * i915)407 void intel_combo_phy_init(struct drm_i915_private *i915)
408 {
409 icl_combo_phys_init(i915);
410 }
411
intel_combo_phy_uninit(struct drm_i915_private * i915)412 void intel_combo_phy_uninit(struct drm_i915_private *i915)
413 {
414 icl_combo_phys_uninit(i915);
415 }
416