1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/component.h>
25 #include <linux/kernel.h>
26
27 #include <drm/drm_edid.h>
28 #include <drm/i915_component.h>
29
30 #include "i915_drv.h"
31 #include "intel_atomic.h"
32 #include "intel_audio.h"
33 #include "intel_cdclk.h"
34 #include "intel_crtc.h"
35 #include "intel_de.h"
36 #include "intel_display_types.h"
37 #include "intel_lpe_audio.h"
38
39 /**
40 * DOC: High Definition Audio over HDMI and Display Port
41 *
42 * The graphics and audio drivers together support High Definition Audio over
43 * HDMI and Display Port. The audio programming sequences are divided into audio
44 * codec and controller enable and disable sequences. The graphics driver
45 * handles the audio codec sequences, while the audio driver handles the audio
46 * controller sequences.
47 *
48 * The disable sequences must be performed before disabling the transcoder or
49 * port. The enable sequences may only be performed after enabling the
50 * transcoder and port, and after completed link training. Therefore the audio
51 * enable/disable sequences are part of the modeset sequence.
52 *
53 * The codec and controller sequences could be done either parallel or serial,
54 * but generally the ELDV/PD change in the codec sequence indicates to the audio
55 * driver that the controller sequence should start. Indeed, most of the
56 * co-operation between the graphics and audio drivers is handled via audio
57 * related registers. (The notable exception is the power management, not
58 * covered here.)
59 *
60 * The struct &i915_audio_component is used to interact between the graphics
61 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
62 * defined in graphics driver and called in audio driver. The
63 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
64 */
65
66 struct intel_audio_funcs {
67 void (*audio_codec_enable)(struct intel_encoder *encoder,
68 const struct intel_crtc_state *crtc_state,
69 const struct drm_connector_state *conn_state);
70 void (*audio_codec_disable)(struct intel_encoder *encoder,
71 const struct intel_crtc_state *old_crtc_state,
72 const struct drm_connector_state *old_conn_state);
73 };
74
75 /* DP N/M table */
76 #define LC_810M 810000
77 #define LC_540M 540000
78 #define LC_270M 270000
79 #define LC_162M 162000
80
81 struct dp_aud_n_m {
82 int sample_rate;
83 int clock;
84 u16 m;
85 u16 n;
86 };
87
88 struct hdmi_aud_ncts {
89 int sample_rate;
90 int clock;
91 int n;
92 int cts;
93 };
94
95 /* Values according to DP 1.4 Table 2-104 */
96 static const struct dp_aud_n_m dp_aud_n_m[] = {
97 { 32000, LC_162M, 1024, 10125 },
98 { 44100, LC_162M, 784, 5625 },
99 { 48000, LC_162M, 512, 3375 },
100 { 64000, LC_162M, 2048, 10125 },
101 { 88200, LC_162M, 1568, 5625 },
102 { 96000, LC_162M, 1024, 3375 },
103 { 128000, LC_162M, 4096, 10125 },
104 { 176400, LC_162M, 3136, 5625 },
105 { 192000, LC_162M, 2048, 3375 },
106 { 32000, LC_270M, 1024, 16875 },
107 { 44100, LC_270M, 784, 9375 },
108 { 48000, LC_270M, 512, 5625 },
109 { 64000, LC_270M, 2048, 16875 },
110 { 88200, LC_270M, 1568, 9375 },
111 { 96000, LC_270M, 1024, 5625 },
112 { 128000, LC_270M, 4096, 16875 },
113 { 176400, LC_270M, 3136, 9375 },
114 { 192000, LC_270M, 2048, 5625 },
115 { 32000, LC_540M, 1024, 33750 },
116 { 44100, LC_540M, 784, 18750 },
117 { 48000, LC_540M, 512, 11250 },
118 { 64000, LC_540M, 2048, 33750 },
119 { 88200, LC_540M, 1568, 18750 },
120 { 96000, LC_540M, 1024, 11250 },
121 { 128000, LC_540M, 4096, 33750 },
122 { 176400, LC_540M, 3136, 18750 },
123 { 192000, LC_540M, 2048, 11250 },
124 { 32000, LC_810M, 1024, 50625 },
125 { 44100, LC_810M, 784, 28125 },
126 { 48000, LC_810M, 512, 16875 },
127 { 64000, LC_810M, 2048, 50625 },
128 { 88200, LC_810M, 1568, 28125 },
129 { 96000, LC_810M, 1024, 16875 },
130 { 128000, LC_810M, 4096, 50625 },
131 { 176400, LC_810M, 3136, 28125 },
132 { 192000, LC_810M, 2048, 16875 },
133 };
134
135 static const struct dp_aud_n_m *
audio_config_dp_get_n_m(const struct intel_crtc_state * crtc_state,int rate)136 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
137 {
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
141 if (rate == dp_aud_n_m[i].sample_rate &&
142 crtc_state->port_clock == dp_aud_n_m[i].clock)
143 return &dp_aud_n_m[i];
144 }
145
146 return NULL;
147 }
148
149 static const struct {
150 int clock;
151 u32 config;
152 } hdmi_audio_clock[] = {
153 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
154 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
155 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
156 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
157 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
158 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
159 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
160 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
161 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
162 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
163 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
164 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
165 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
166 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
167 };
168
169 /* HDMI N/CTS table */
170 #define TMDS_297M 297000
171 #define TMDS_296M 296703
172 #define TMDS_594M 594000
173 #define TMDS_593M 593407
174
175 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
176 { 32000, TMDS_296M, 5824, 421875 },
177 { 32000, TMDS_297M, 3072, 222750 },
178 { 32000, TMDS_593M, 5824, 843750 },
179 { 32000, TMDS_594M, 3072, 445500 },
180 { 44100, TMDS_296M, 4459, 234375 },
181 { 44100, TMDS_297M, 4704, 247500 },
182 { 44100, TMDS_593M, 8918, 937500 },
183 { 44100, TMDS_594M, 9408, 990000 },
184 { 88200, TMDS_296M, 8918, 234375 },
185 { 88200, TMDS_297M, 9408, 247500 },
186 { 88200, TMDS_593M, 17836, 937500 },
187 { 88200, TMDS_594M, 18816, 990000 },
188 { 176400, TMDS_296M, 17836, 234375 },
189 { 176400, TMDS_297M, 18816, 247500 },
190 { 176400, TMDS_593M, 35672, 937500 },
191 { 176400, TMDS_594M, 37632, 990000 },
192 { 48000, TMDS_296M, 5824, 281250 },
193 { 48000, TMDS_297M, 5120, 247500 },
194 { 48000, TMDS_593M, 5824, 562500 },
195 { 48000, TMDS_594M, 6144, 594000 },
196 { 96000, TMDS_296M, 11648, 281250 },
197 { 96000, TMDS_297M, 10240, 247500 },
198 { 96000, TMDS_593M, 11648, 562500 },
199 { 96000, TMDS_594M, 12288, 594000 },
200 { 192000, TMDS_296M, 23296, 281250 },
201 { 192000, TMDS_297M, 20480, 247500 },
202 { 192000, TMDS_593M, 23296, 562500 },
203 { 192000, TMDS_594M, 24576, 594000 },
204 };
205
206 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
207 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
208 #define TMDS_371M 371250
209 #define TMDS_370M 370878
210
211 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
212 { 32000, TMDS_370M, 5824, 527344 },
213 { 32000, TMDS_371M, 6144, 556875 },
214 { 44100, TMDS_370M, 8918, 585938 },
215 { 44100, TMDS_371M, 4704, 309375 },
216 { 88200, TMDS_370M, 17836, 585938 },
217 { 88200, TMDS_371M, 9408, 309375 },
218 { 176400, TMDS_370M, 35672, 585938 },
219 { 176400, TMDS_371M, 18816, 309375 },
220 { 48000, TMDS_370M, 11648, 703125 },
221 { 48000, TMDS_371M, 5120, 309375 },
222 { 96000, TMDS_370M, 23296, 703125 },
223 { 96000, TMDS_371M, 10240, 309375 },
224 { 192000, TMDS_370M, 46592, 703125 },
225 { 192000, TMDS_371M, 20480, 309375 },
226 };
227
228 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
229 #define TMDS_445_5M 445500
230 #define TMDS_445M 445054
231
232 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
233 { 32000, TMDS_445M, 5824, 632813 },
234 { 32000, TMDS_445_5M, 4096, 445500 },
235 { 44100, TMDS_445M, 8918, 703125 },
236 { 44100, TMDS_445_5M, 4704, 371250 },
237 { 88200, TMDS_445M, 17836, 703125 },
238 { 88200, TMDS_445_5M, 9408, 371250 },
239 { 176400, TMDS_445M, 35672, 703125 },
240 { 176400, TMDS_445_5M, 18816, 371250 },
241 { 48000, TMDS_445M, 5824, 421875 },
242 { 48000, TMDS_445_5M, 5120, 371250 },
243 { 96000, TMDS_445M, 11648, 421875 },
244 { 96000, TMDS_445_5M, 10240, 371250 },
245 { 192000, TMDS_445M, 23296, 421875 },
246 { 192000, TMDS_445_5M, 20480, 371250 },
247 };
248
249 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
audio_config_hdmi_pixel_clock(const struct intel_crtc_state * crtc_state)250 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
251 {
252 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
253 const struct drm_display_mode *adjusted_mode =
254 &crtc_state->hw.adjusted_mode;
255 int i;
256
257 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
258 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
259 break;
260 }
261
262 if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
263 i = ARRAY_SIZE(hdmi_audio_clock);
264
265 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
266 drm_dbg_kms(&dev_priv->drm,
267 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
268 adjusted_mode->crtc_clock);
269 i = 1;
270 }
271
272 drm_dbg_kms(&dev_priv->drm,
273 "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
274 hdmi_audio_clock[i].clock,
275 hdmi_audio_clock[i].config);
276
277 return hdmi_audio_clock[i].config;
278 }
279
audio_config_hdmi_get_n(const struct intel_crtc_state * crtc_state,int rate)280 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
281 int rate)
282 {
283 const struct hdmi_aud_ncts *hdmi_ncts_table;
284 int i, size;
285
286 if (crtc_state->pipe_bpp == 36) {
287 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
288 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
289 } else if (crtc_state->pipe_bpp == 30) {
290 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
291 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
292 } else {
293 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
294 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
295 }
296
297 for (i = 0; i < size; i++) {
298 if (rate == hdmi_ncts_table[i].sample_rate &&
299 crtc_state->port_clock == hdmi_ncts_table[i].clock) {
300 return hdmi_ncts_table[i].n;
301 }
302 }
303 return 0;
304 }
305
intel_eld_uptodate(struct drm_connector * connector,i915_reg_t reg_eldv,u32 bits_eldv,i915_reg_t reg_elda,u32 bits_elda,i915_reg_t reg_edid)306 static bool intel_eld_uptodate(struct drm_connector *connector,
307 i915_reg_t reg_eldv, u32 bits_eldv,
308 i915_reg_t reg_elda, u32 bits_elda,
309 i915_reg_t reg_edid)
310 {
311 struct drm_i915_private *dev_priv = to_i915(connector->dev);
312 const u8 *eld = connector->eld;
313 u32 tmp;
314 int i;
315
316 tmp = intel_de_read(dev_priv, reg_eldv);
317 tmp &= bits_eldv;
318
319 if (!tmp)
320 return false;
321
322 tmp = intel_de_read(dev_priv, reg_elda);
323 tmp &= ~bits_elda;
324 intel_de_write(dev_priv, reg_elda, tmp);
325
326 for (i = 0; i < drm_eld_size(eld) / 4; i++)
327 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
328 return false;
329
330 return true;
331 }
332
g4x_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)333 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
334 const struct intel_crtc_state *old_crtc_state,
335 const struct drm_connector_state *old_conn_state)
336 {
337 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
338 u32 eldv, tmp;
339
340 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
341 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
342 eldv = G4X_ELDV_DEVCL_DEVBLC;
343 else
344 eldv = G4X_ELDV_DEVCTG;
345
346 /* Invalidate ELD */
347 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
348 tmp &= ~eldv;
349 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
350 }
351
g4x_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)352 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
353 const struct intel_crtc_state *crtc_state,
354 const struct drm_connector_state *conn_state)
355 {
356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
357 struct drm_connector *connector = conn_state->connector;
358 const u8 *eld = connector->eld;
359 u32 eldv;
360 u32 tmp;
361 int len, i;
362
363 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
364 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
365 eldv = G4X_ELDV_DEVCL_DEVBLC;
366 else
367 eldv = G4X_ELDV_DEVCTG;
368
369 if (intel_eld_uptodate(connector,
370 G4X_AUD_CNTL_ST, eldv,
371 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
372 G4X_HDMIW_HDMIEDID))
373 return;
374
375 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
376 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
377 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
378 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
379
380 len = min(drm_eld_size(eld) / 4, len);
381 for (i = 0; i < len; i++)
382 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
383 *((const u32 *)eld + i));
384
385 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
386 tmp |= eldv;
387 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
388 }
389
390 static void
hsw_dp_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)391 hsw_dp_audio_config_update(struct intel_encoder *encoder,
392 const struct intel_crtc_state *crtc_state)
393 {
394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
395 struct i915_audio_component *acomp = dev_priv->audio.component;
396 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
397 enum port port = encoder->port;
398 const struct dp_aud_n_m *nm;
399 int rate;
400 u32 tmp;
401
402 rate = acomp ? acomp->aud_sample_rate[port] : 0;
403 nm = audio_config_dp_get_n_m(crtc_state, rate);
404 if (nm)
405 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m,
406 nm->n);
407 else
408 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
409
410 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
411 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
412 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
413 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
414 tmp |= AUD_CONFIG_N_VALUE_INDEX;
415
416 if (nm) {
417 tmp &= ~AUD_CONFIG_N_MASK;
418 tmp |= AUD_CONFIG_N(nm->n);
419 tmp |= AUD_CONFIG_N_PROG_ENABLE;
420 }
421
422 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
423
424 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
425 tmp &= ~AUD_CONFIG_M_MASK;
426 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
427 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
428
429 if (nm) {
430 tmp |= nm->m;
431 tmp |= AUD_M_CTS_M_VALUE_INDEX;
432 tmp |= AUD_M_CTS_M_PROG_ENABLE;
433 }
434
435 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
436 }
437
438 static void
hsw_hdmi_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)439 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
440 const struct intel_crtc_state *crtc_state)
441 {
442 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
443 struct i915_audio_component *acomp = dev_priv->audio.component;
444 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
445 enum port port = encoder->port;
446 int n, rate;
447 u32 tmp;
448
449 rate = acomp ? acomp->aud_sample_rate[port] : 0;
450
451 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
452 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
453 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
454 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
455 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
456
457 n = audio_config_hdmi_get_n(crtc_state, rate);
458 if (n != 0) {
459 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n);
460
461 tmp &= ~AUD_CONFIG_N_MASK;
462 tmp |= AUD_CONFIG_N(n);
463 tmp |= AUD_CONFIG_N_PROG_ENABLE;
464 } else {
465 drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
466 }
467
468 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
469
470 /*
471 * Let's disable "Enable CTS or M Prog bit"
472 * and let HW calculate the value
473 */
474 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
475 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
476 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
477 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
478 }
479
480 static void
hsw_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)481 hsw_audio_config_update(struct intel_encoder *encoder,
482 const struct intel_crtc_state *crtc_state)
483 {
484 if (intel_crtc_has_dp_encoder(crtc_state))
485 hsw_dp_audio_config_update(encoder, crtc_state);
486 else
487 hsw_hdmi_audio_config_update(encoder, crtc_state);
488 }
489
hsw_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)490 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
491 const struct intel_crtc_state *old_crtc_state,
492 const struct drm_connector_state *old_conn_state)
493 {
494 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
496 u32 tmp;
497
498 mutex_lock(&dev_priv->audio.mutex);
499
500 /* Disable timestamps */
501 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
502 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
503 tmp |= AUD_CONFIG_N_PROG_ENABLE;
504 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
505 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
506 if (intel_crtc_has_dp_encoder(old_crtc_state))
507 tmp |= AUD_CONFIG_N_VALUE_INDEX;
508 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
509
510 /* Invalidate ELD */
511 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
512 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
513 tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
514 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
515
516 mutex_unlock(&dev_priv->audio.mutex);
517 }
518
calc_hblank_early_prog(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)519 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
520 const struct intel_crtc_state *crtc_state)
521 {
522 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
523 unsigned int link_clks_available, link_clks_required;
524 unsigned int tu_data, tu_line, link_clks_active;
525 unsigned int h_active, h_total, hblank_delta, pixel_clk;
526 unsigned int fec_coeff, cdclk, vdsc_bpp;
527 unsigned int link_clk, lanes;
528 unsigned int hblank_rise;
529
530 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
531 h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
532 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
533 vdsc_bpp = crtc_state->dsc.compressed_bpp;
534 cdclk = i915->cdclk.hw.cdclk;
535 /* fec= 0.972261, using rounding multiplier of 1000000 */
536 fec_coeff = 972261;
537 link_clk = crtc_state->port_clock;
538 lanes = crtc_state->lane_count;
539
540 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
541 "lanes = %u vdsc_bpp = %u cdclk = %u\n",
542 h_active, link_clk, lanes, vdsc_bpp, cdclk);
543
544 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
545 return 0;
546
547 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
548 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
549
550 if (link_clks_available > link_clks_required)
551 hblank_delta = 32;
552 else
553 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
554 mul_u32_u32(link_clk, cdclk));
555
556 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
557 mul_u32_u32(link_clk * lanes, fec_coeff));
558 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
559 mul_u32_u32(64 * pixel_clk, 1000000));
560 link_clks_active = (tu_line - 1) * 64 + tu_data;
561
562 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
563
564 return h_active - hblank_rise + hblank_delta;
565 }
566
calc_samples_room(const struct intel_crtc_state * crtc_state)567 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
568 {
569 unsigned int h_active, h_total, pixel_clk;
570 unsigned int link_clk, lanes;
571
572 h_active = crtc_state->hw.adjusted_mode.hdisplay;
573 h_total = crtc_state->hw.adjusted_mode.htotal;
574 pixel_clk = crtc_state->hw.adjusted_mode.clock;
575 link_clk = crtc_state->port_clock;
576 lanes = crtc_state->lane_count;
577
578 return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
579 (pixel_clk * (48 / lanes + 2));
580 }
581
enable_audio_dsc_wa(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)582 static void enable_audio_dsc_wa(struct intel_encoder *encoder,
583 const struct intel_crtc_state *crtc_state)
584 {
585 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
586 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
587 enum pipe pipe = crtc->pipe;
588 unsigned int hblank_early_prog, samples_room;
589 unsigned int val;
590
591 if (DISPLAY_VER(i915) < 11)
592 return;
593
594 val = intel_de_read(i915, AUD_CONFIG_BE);
595
596 if (DISPLAY_VER(i915) == 11)
597 val |= HBLANK_EARLY_ENABLE_ICL(pipe);
598 else if (DISPLAY_VER(i915) >= 12)
599 val |= HBLANK_EARLY_ENABLE_TGL(pipe);
600
601 if (crtc_state->dsc.compression_enable &&
602 crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
603 crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
604 /* Get hblank early enable value required */
605 val &= ~HBLANK_START_COUNT_MASK(pipe);
606 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
607 if (hblank_early_prog < 32)
608 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
609 else if (hblank_early_prog < 64)
610 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
611 else if (hblank_early_prog < 96)
612 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
613 else
614 val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
615
616 /* Get samples room value required */
617 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
618 samples_room = calc_samples_room(crtc_state);
619 if (samples_room < 3)
620 val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
621 else /* Program 0 i.e "All Samples available in buffer" */
622 val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
623 }
624
625 intel_de_write(i915, AUD_CONFIG_BE, val);
626 }
627
628 #undef ROUNDING_FACTOR
629
hsw_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)630 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
631 const struct intel_crtc_state *crtc_state,
632 const struct drm_connector_state *conn_state)
633 {
634 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
635 struct drm_connector *connector = conn_state->connector;
636 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
637 const u8 *eld = connector->eld;
638 u32 tmp;
639 int len, i;
640
641 mutex_lock(&dev_priv->audio.mutex);
642
643 /* Enable Audio WA for 4k DSC usecases */
644 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
645 enable_audio_dsc_wa(encoder, crtc_state);
646
647 /* Enable audio presence detect, invalidate ELD */
648 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
649 tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
650 tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
651 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
652
653 /*
654 * FIXME: We're supposed to wait for vblank here, but we have vblanks
655 * disabled during the mode set. The proper fix would be to push the
656 * rest of the setup into a vblank work item, queued here, but the
657 * infrastructure is not there yet.
658 */
659
660 /* Reset ELD write address */
661 tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
662 tmp &= ~IBX_ELD_ADDRESS_MASK;
663 intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
664
665 /* Up to 84 bytes of hw ELD buffer */
666 len = min(drm_eld_size(eld), 84);
667 for (i = 0; i < len / 4; i++)
668 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
669 *((const u32 *)eld + i));
670
671 /* ELD valid */
672 tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
673 tmp |= AUDIO_ELD_VALID(cpu_transcoder);
674 intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
675
676 /* Enable timestamps */
677 hsw_audio_config_update(encoder, crtc_state);
678
679 mutex_unlock(&dev_priv->audio.mutex);
680 }
681
ilk_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)682 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
683 const struct intel_crtc_state *old_crtc_state,
684 const struct drm_connector_state *old_conn_state)
685 {
686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
687 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
688 enum pipe pipe = crtc->pipe;
689 enum port port = encoder->port;
690 u32 tmp, eldv;
691 i915_reg_t aud_config, aud_cntrl_st2;
692
693 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
694 return;
695
696 if (HAS_PCH_IBX(dev_priv)) {
697 aud_config = IBX_AUD_CFG(pipe);
698 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
699 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
700 aud_config = VLV_AUD_CFG(pipe);
701 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
702 } else {
703 aud_config = CPT_AUD_CFG(pipe);
704 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
705 }
706
707 /* Disable timestamps */
708 tmp = intel_de_read(dev_priv, aud_config);
709 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
710 tmp |= AUD_CONFIG_N_PROG_ENABLE;
711 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
712 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
713 if (intel_crtc_has_dp_encoder(old_crtc_state))
714 tmp |= AUD_CONFIG_N_VALUE_INDEX;
715 intel_de_write(dev_priv, aud_config, tmp);
716
717 eldv = IBX_ELD_VALID(port);
718
719 /* Invalidate ELD */
720 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
721 tmp &= ~eldv;
722 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
723 }
724
ilk_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)725 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
726 const struct intel_crtc_state *crtc_state,
727 const struct drm_connector_state *conn_state)
728 {
729 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
730 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
731 struct drm_connector *connector = conn_state->connector;
732 enum pipe pipe = crtc->pipe;
733 enum port port = encoder->port;
734 const u8 *eld = connector->eld;
735 u32 tmp, eldv;
736 int len, i;
737 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
738
739 if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
740 return;
741
742 /*
743 * FIXME: We're supposed to wait for vblank here, but we have vblanks
744 * disabled during the mode set. The proper fix would be to push the
745 * rest of the setup into a vblank work item, queued here, but the
746 * infrastructure is not there yet.
747 */
748
749 if (HAS_PCH_IBX(dev_priv)) {
750 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
751 aud_config = IBX_AUD_CFG(pipe);
752 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
753 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
754 } else if (IS_VALLEYVIEW(dev_priv) ||
755 IS_CHERRYVIEW(dev_priv)) {
756 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
757 aud_config = VLV_AUD_CFG(pipe);
758 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
759 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
760 } else {
761 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
762 aud_config = CPT_AUD_CFG(pipe);
763 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
764 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
765 }
766
767 eldv = IBX_ELD_VALID(port);
768
769 /* Invalidate ELD */
770 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
771 tmp &= ~eldv;
772 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
773
774 /* Reset ELD write address */
775 tmp = intel_de_read(dev_priv, aud_cntl_st);
776 tmp &= ~IBX_ELD_ADDRESS_MASK;
777 intel_de_write(dev_priv, aud_cntl_st, tmp);
778
779 /* Up to 84 bytes of hw ELD buffer */
780 len = min(drm_eld_size(eld), 84);
781 for (i = 0; i < len / 4; i++)
782 intel_de_write(dev_priv, hdmiw_hdmiedid,
783 *((const u32 *)eld + i));
784
785 /* ELD valid */
786 tmp = intel_de_read(dev_priv, aud_cntrl_st2);
787 tmp |= eldv;
788 intel_de_write(dev_priv, aud_cntrl_st2, tmp);
789
790 /* Enable timestamps */
791 tmp = intel_de_read(dev_priv, aud_config);
792 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
793 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
794 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
795 if (intel_crtc_has_dp_encoder(crtc_state))
796 tmp |= AUD_CONFIG_N_VALUE_INDEX;
797 else
798 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
799 intel_de_write(dev_priv, aud_config, tmp);
800 }
801
802 /**
803 * intel_audio_codec_enable - Enable the audio codec for HD audio
804 * @encoder: encoder on which to enable audio
805 * @crtc_state: pointer to the current crtc state.
806 * @conn_state: pointer to the current connector state.
807 *
808 * The enable sequences may only be performed after enabling the transcoder and
809 * port, and after completed link training.
810 */
intel_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)811 void intel_audio_codec_enable(struct intel_encoder *encoder,
812 const struct intel_crtc_state *crtc_state,
813 const struct drm_connector_state *conn_state)
814 {
815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
816 struct i915_audio_component *acomp = dev_priv->audio.component;
817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
818 struct drm_connector *connector = conn_state->connector;
819 const struct drm_display_mode *adjusted_mode =
820 &crtc_state->hw.adjusted_mode;
821 enum port port = encoder->port;
822 enum pipe pipe = crtc->pipe;
823
824 if (!crtc_state->has_audio)
825 return;
826
827 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on pipe %c, %u bytes ELD\n",
828 connector->base.id, connector->name,
829 encoder->base.base.id, encoder->base.name,
830 pipe_name(pipe), drm_eld_size(connector->eld));
831
832 /* FIXME precompute the ELD in .compute_config() */
833 if (!connector->eld[0])
834 drm_dbg_kms(&dev_priv->drm,
835 "Bogus ELD on [CONNECTOR:%d:%s]\n",
836 connector->base.id, connector->name);
837
838 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
839
840 if (dev_priv->audio.funcs)
841 dev_priv->audio.funcs->audio_codec_enable(encoder,
842 crtc_state,
843 conn_state);
844
845 mutex_lock(&dev_priv->audio.mutex);
846 encoder->audio_connector = connector;
847
848 /* referred in audio callbacks */
849 dev_priv->audio.encoder_map[pipe] = encoder;
850 mutex_unlock(&dev_priv->audio.mutex);
851
852 if (acomp && acomp->base.audio_ops &&
853 acomp->base.audio_ops->pin_eld_notify) {
854 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
855 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
856 pipe = -1;
857 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
858 (int) port, (int) pipe);
859 }
860
861 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
862 crtc_state->port_clock,
863 intel_crtc_has_dp_encoder(crtc_state));
864 }
865
866 /**
867 * intel_audio_codec_disable - Disable the audio codec for HD audio
868 * @encoder: encoder on which to disable audio
869 * @old_crtc_state: pointer to the old crtc state.
870 * @old_conn_state: pointer to the old connector state.
871 *
872 * The disable sequences must be performed before disabling the transcoder or
873 * port.
874 */
intel_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)875 void intel_audio_codec_disable(struct intel_encoder *encoder,
876 const struct intel_crtc_state *old_crtc_state,
877 const struct drm_connector_state *old_conn_state)
878 {
879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
880 struct i915_audio_component *acomp = dev_priv->audio.component;
881 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
882 struct drm_connector *connector = old_conn_state->connector;
883 enum port port = encoder->port;
884 enum pipe pipe = crtc->pipe;
885
886 if (!old_crtc_state->has_audio)
887 return;
888
889 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on pipe %c\n",
890 connector->base.id, connector->name,
891 encoder->base.base.id, encoder->base.name, pipe_name(pipe));
892
893 if (dev_priv->audio.funcs)
894 dev_priv->audio.funcs->audio_codec_disable(encoder,
895 old_crtc_state,
896 old_conn_state);
897
898 mutex_lock(&dev_priv->audio.mutex);
899 encoder->audio_connector = NULL;
900 dev_priv->audio.encoder_map[pipe] = NULL;
901 mutex_unlock(&dev_priv->audio.mutex);
902
903 if (acomp && acomp->base.audio_ops &&
904 acomp->base.audio_ops->pin_eld_notify) {
905 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
906 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
907 pipe = -1;
908 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
909 (int) port, (int) pipe);
910 }
911
912 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
913 }
914
915 static const struct intel_audio_funcs g4x_audio_funcs = {
916 .audio_codec_enable = g4x_audio_codec_enable,
917 .audio_codec_disable = g4x_audio_codec_disable,
918 };
919
920 static const struct intel_audio_funcs ilk_audio_funcs = {
921 .audio_codec_enable = ilk_audio_codec_enable,
922 .audio_codec_disable = ilk_audio_codec_disable,
923 };
924
925 static const struct intel_audio_funcs hsw_audio_funcs = {
926 .audio_codec_enable = hsw_audio_codec_enable,
927 .audio_codec_disable = hsw_audio_codec_disable,
928 };
929
930 /**
931 * intel_audio_hooks_init - Set up chip specific audio hooks
932 * @dev_priv: device private
933 */
intel_audio_hooks_init(struct drm_i915_private * dev_priv)934 void intel_audio_hooks_init(struct drm_i915_private *dev_priv)
935 {
936 if (IS_G4X(dev_priv)) {
937 dev_priv->audio.funcs = &g4x_audio_funcs;
938 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
939 dev_priv->audio.funcs = &ilk_audio_funcs;
940 } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
941 dev_priv->audio.funcs = &hsw_audio_funcs;
942 } else if (HAS_PCH_SPLIT(dev_priv)) {
943 dev_priv->audio.funcs = &ilk_audio_funcs;
944 }
945 }
946
947 struct aud_ts_cdclk_m_n {
948 u8 m;
949 u16 n;
950 };
951
intel_audio_cdclk_change_pre(struct drm_i915_private * i915)952 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915)
953 {
954 if (DISPLAY_VER(i915) >= 13)
955 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);
956 }
957
get_aud_ts_cdclk_m_n(int refclk,int cdclk,struct aud_ts_cdclk_m_n * aud_ts)958 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts)
959 {
960 if (refclk == 24000)
961 aud_ts->m = 12;
962 else
963 aud_ts->m = 15;
964
965 aud_ts->n = cdclk * aud_ts->m / 24000;
966 }
967
intel_audio_cdclk_change_post(struct drm_i915_private * i915)968 void intel_audio_cdclk_change_post(struct drm_i915_private *i915)
969 {
970 struct aud_ts_cdclk_m_n aud_ts;
971
972 if (DISPLAY_VER(i915) >= 13) {
973 get_aud_ts_cdclk_m_n(i915->cdclk.hw.ref, i915->cdclk.hw.cdclk, &aud_ts);
974
975 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
976 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
977 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n);
978 }
979 }
980
glk_force_audio_cdclk_commit(struct intel_atomic_state * state,struct intel_crtc * crtc,bool enable)981 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
982 struct intel_crtc *crtc,
983 bool enable)
984 {
985 struct intel_cdclk_state *cdclk_state;
986 int ret;
987
988 /* need to hold at least one crtc lock for the global state */
989 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
990 if (ret)
991 return ret;
992
993 cdclk_state = intel_atomic_get_cdclk_state(state);
994 if (IS_ERR(cdclk_state))
995 return PTR_ERR(cdclk_state);
996
997 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
998
999 return drm_atomic_commit(&state->base);
1000 }
1001
glk_force_audio_cdclk(struct drm_i915_private * dev_priv,bool enable)1002 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
1003 bool enable)
1004 {
1005 struct drm_modeset_acquire_ctx ctx;
1006 struct drm_atomic_state *state;
1007 struct intel_crtc *crtc;
1008 int ret;
1009
1010 crtc = intel_first_crtc(dev_priv);
1011 if (!crtc)
1012 return;
1013
1014 drm_modeset_acquire_init(&ctx, 0);
1015 state = drm_atomic_state_alloc(&dev_priv->drm);
1016 if (drm_WARN_ON(&dev_priv->drm, !state))
1017 return;
1018
1019 state->acquire_ctx = &ctx;
1020
1021 retry:
1022 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
1023 enable);
1024 if (ret == -EDEADLK) {
1025 drm_atomic_state_clear(state);
1026 drm_modeset_backoff(&ctx);
1027 goto retry;
1028 }
1029
1030 drm_WARN_ON(&dev_priv->drm, ret);
1031
1032 drm_atomic_state_put(state);
1033
1034 drm_modeset_drop_locks(&ctx);
1035 drm_modeset_acquire_fini(&ctx);
1036 }
1037
i915_audio_component_get_power(struct device * kdev)1038 static unsigned long i915_audio_component_get_power(struct device *kdev)
1039 {
1040 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1041 intel_wakeref_t ret;
1042
1043 /* Catch potential impedance mismatches before they occur! */
1044 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1045
1046 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
1047
1048 if (dev_priv->audio.power_refcount++ == 0) {
1049 if (DISPLAY_VER(dev_priv) >= 9) {
1050 intel_de_write(dev_priv, AUD_FREQ_CNTRL,
1051 dev_priv->audio.freq_cntrl);
1052 drm_dbg_kms(&dev_priv->drm,
1053 "restored AUD_FREQ_CNTRL to 0x%x\n",
1054 dev_priv->audio.freq_cntrl);
1055 }
1056
1057 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1058 if (IS_GEMINILAKE(dev_priv))
1059 glk_force_audio_cdclk(dev_priv, true);
1060
1061 if (DISPLAY_VER(dev_priv) >= 10)
1062 intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
1063 (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
1064 }
1065
1066 return ret;
1067 }
1068
i915_audio_component_put_power(struct device * kdev,unsigned long cookie)1069 static void i915_audio_component_put_power(struct device *kdev,
1070 unsigned long cookie)
1071 {
1072 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1073
1074 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1075 if (--dev_priv->audio.power_refcount == 0)
1076 if (IS_GEMINILAKE(dev_priv))
1077 glk_force_audio_cdclk(dev_priv, false);
1078
1079 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
1080 }
1081
i915_audio_component_codec_wake_override(struct device * kdev,bool enable)1082 static void i915_audio_component_codec_wake_override(struct device *kdev,
1083 bool enable)
1084 {
1085 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1086 unsigned long cookie;
1087 u32 tmp;
1088
1089 if (DISPLAY_VER(dev_priv) < 9)
1090 return;
1091
1092 cookie = i915_audio_component_get_power(kdev);
1093
1094 /*
1095 * Enable/disable generating the codec wake signal, overriding the
1096 * internal logic to generate the codec wake to controller.
1097 */
1098 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1099 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
1100 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1101 usleep_range(1000, 1500);
1102
1103 if (enable) {
1104 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1105 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
1106 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1107 usleep_range(1000, 1500);
1108 }
1109
1110 i915_audio_component_put_power(kdev, cookie);
1111 }
1112
1113 /* Get CDCLK in kHz */
i915_audio_component_get_cdclk_freq(struct device * kdev)1114 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1115 {
1116 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1117
1118 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
1119 return -ENODEV;
1120
1121 return dev_priv->cdclk.hw.cdclk;
1122 }
1123
1124 /*
1125 * get the intel_encoder according to the parameter port and pipe
1126 * intel_encoder is saved by the index of pipe
1127 * MST & (pipe >= 0): return the audio.encoder_map[pipe],
1128 * when port is matched
1129 * MST & (pipe < 0): this is invalid
1130 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
1131 * will get the right intel_encoder with port matched
1132 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
1133 */
get_saved_enc(struct drm_i915_private * dev_priv,int port,int pipe)1134 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
1135 int port, int pipe)
1136 {
1137 struct intel_encoder *encoder;
1138
1139 /* MST */
1140 if (pipe >= 0) {
1141 if (drm_WARN_ON(&dev_priv->drm,
1142 pipe >= ARRAY_SIZE(dev_priv->audio.encoder_map)))
1143 return NULL;
1144
1145 encoder = dev_priv->audio.encoder_map[pipe];
1146 /*
1147 * when bootup, audio driver may not know it is
1148 * MST or not. So it will poll all the port & pipe
1149 * combinations
1150 */
1151 if (encoder != NULL && encoder->port == port &&
1152 encoder->type == INTEL_OUTPUT_DP_MST)
1153 return encoder;
1154 }
1155
1156 /* Non-MST */
1157 if (pipe > 0)
1158 return NULL;
1159
1160 for_each_pipe(dev_priv, pipe) {
1161 encoder = dev_priv->audio.encoder_map[pipe];
1162 if (encoder == NULL)
1163 continue;
1164
1165 if (encoder->type == INTEL_OUTPUT_DP_MST)
1166 continue;
1167
1168 if (port == encoder->port)
1169 return encoder;
1170 }
1171
1172 return NULL;
1173 }
1174
i915_audio_component_sync_audio_rate(struct device * kdev,int port,int pipe,int rate)1175 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1176 int pipe, int rate)
1177 {
1178 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1179 struct i915_audio_component *acomp = dev_priv->audio.component;
1180 struct intel_encoder *encoder;
1181 struct intel_crtc *crtc;
1182 unsigned long cookie;
1183 int err = 0;
1184
1185 if (!HAS_DDI(dev_priv))
1186 return 0;
1187
1188 cookie = i915_audio_component_get_power(kdev);
1189 mutex_lock(&dev_priv->audio.mutex);
1190
1191 /* 1. get the pipe */
1192 encoder = get_saved_enc(dev_priv, port, pipe);
1193 if (!encoder || !encoder->base.crtc) {
1194 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1195 port_name(port));
1196 err = -ENODEV;
1197 goto unlock;
1198 }
1199
1200 crtc = to_intel_crtc(encoder->base.crtc);
1201
1202 /* port must be valid now, otherwise the pipe will be invalid */
1203 acomp->aud_sample_rate[port] = rate;
1204
1205 hsw_audio_config_update(encoder, crtc->config);
1206
1207 unlock:
1208 mutex_unlock(&dev_priv->audio.mutex);
1209 i915_audio_component_put_power(kdev, cookie);
1210 return err;
1211 }
1212
i915_audio_component_get_eld(struct device * kdev,int port,int pipe,bool * enabled,unsigned char * buf,int max_bytes)1213 static int i915_audio_component_get_eld(struct device *kdev, int port,
1214 int pipe, bool *enabled,
1215 unsigned char *buf, int max_bytes)
1216 {
1217 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1218 struct intel_encoder *intel_encoder;
1219 const u8 *eld;
1220 int ret = -EINVAL;
1221
1222 mutex_lock(&dev_priv->audio.mutex);
1223
1224 intel_encoder = get_saved_enc(dev_priv, port, pipe);
1225 if (!intel_encoder) {
1226 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1227 port_name(port));
1228 mutex_unlock(&dev_priv->audio.mutex);
1229 return ret;
1230 }
1231
1232 ret = 0;
1233 *enabled = intel_encoder->audio_connector != NULL;
1234 if (*enabled) {
1235 eld = intel_encoder->audio_connector->eld;
1236 ret = drm_eld_size(eld);
1237 memcpy(buf, eld, min(max_bytes, ret));
1238 }
1239
1240 mutex_unlock(&dev_priv->audio.mutex);
1241 return ret;
1242 }
1243
1244 static const struct drm_audio_component_ops i915_audio_component_ops = {
1245 .owner = THIS_MODULE,
1246 .get_power = i915_audio_component_get_power,
1247 .put_power = i915_audio_component_put_power,
1248 .codec_wake_override = i915_audio_component_codec_wake_override,
1249 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1250 .sync_audio_rate = i915_audio_component_sync_audio_rate,
1251 .get_eld = i915_audio_component_get_eld,
1252 };
1253
i915_audio_component_bind(struct device * i915_kdev,struct device * hda_kdev,void * data)1254 static int i915_audio_component_bind(struct device *i915_kdev,
1255 struct device *hda_kdev, void *data)
1256 {
1257 struct i915_audio_component *acomp = data;
1258 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1259 int i;
1260
1261 if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev))
1262 return -EEXIST;
1263
1264 if (drm_WARN_ON(&dev_priv->drm,
1265 !device_link_add(hda_kdev, i915_kdev,
1266 DL_FLAG_STATELESS)))
1267 return -ENOMEM;
1268
1269 drm_modeset_lock_all(&dev_priv->drm);
1270 acomp->base.ops = &i915_audio_component_ops;
1271 acomp->base.dev = i915_kdev;
1272 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1273 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1274 acomp->aud_sample_rate[i] = 0;
1275 dev_priv->audio.component = acomp;
1276 drm_modeset_unlock_all(&dev_priv->drm);
1277
1278 return 0;
1279 }
1280
i915_audio_component_unbind(struct device * i915_kdev,struct device * hda_kdev,void * data)1281 static void i915_audio_component_unbind(struct device *i915_kdev,
1282 struct device *hda_kdev, void *data)
1283 {
1284 struct i915_audio_component *acomp = data;
1285 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1286
1287 drm_modeset_lock_all(&dev_priv->drm);
1288 acomp->base.ops = NULL;
1289 acomp->base.dev = NULL;
1290 dev_priv->audio.component = NULL;
1291 drm_modeset_unlock_all(&dev_priv->drm);
1292
1293 device_link_remove(hda_kdev, i915_kdev);
1294
1295 if (dev_priv->audio.power_refcount)
1296 drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
1297 dev_priv->audio.power_refcount);
1298 }
1299
1300 static const struct component_ops i915_audio_component_bind_ops = {
1301 .bind = i915_audio_component_bind,
1302 .unbind = i915_audio_component_unbind,
1303 };
1304
1305 #define AUD_FREQ_TMODE_SHIFT 14
1306 #define AUD_FREQ_4T 0
1307 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT)
1308 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11)
1309 #define AUD_FREQ_BCLK_96M BIT(4)
1310
1311 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
1312 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
1313
1314 /**
1315 * i915_audio_component_init - initialize and register the audio component
1316 * @dev_priv: i915 device instance
1317 *
1318 * This will register with the component framework a child component which
1319 * will bind dynamically to the snd_hda_intel driver's corresponding master
1320 * component when the latter is registered. During binding the child
1321 * initializes an instance of struct i915_audio_component which it receives
1322 * from the master. The master can then start to use the interface defined by
1323 * this struct. Each side can break the binding at any point by deregistering
1324 * its own component after which each side's component unbind callback is
1325 * called.
1326 *
1327 * We ignore any error during registration and continue with reduced
1328 * functionality (i.e. without HDMI audio).
1329 */
i915_audio_component_init(struct drm_i915_private * dev_priv)1330 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1331 {
1332 u32 aud_freq, aud_freq_init;
1333 int ret;
1334
1335 ret = component_add_typed(dev_priv->drm.dev,
1336 &i915_audio_component_bind_ops,
1337 I915_COMPONENT_AUDIO);
1338 if (ret < 0) {
1339 drm_err(&dev_priv->drm,
1340 "failed to add audio component (%d)\n", ret);
1341 /* continue with reduced functionality */
1342 return;
1343 }
1344
1345 if (DISPLAY_VER(dev_priv) >= 9) {
1346 aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL);
1347
1348 if (DISPLAY_VER(dev_priv) >= 12)
1349 aud_freq = AUD_FREQ_GEN12;
1350 else
1351 aud_freq = aud_freq_init;
1352
1353 /* use BIOS provided value for TGL and RKL unless it is a known bad value */
1354 if ((IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) &&
1355 aud_freq_init != AUD_FREQ_TGL_BROKEN)
1356 aud_freq = aud_freq_init;
1357
1358 drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
1359 aud_freq, aud_freq_init);
1360
1361 dev_priv->audio.freq_cntrl = aud_freq;
1362 }
1363
1364 /* init with current cdclk */
1365 intel_audio_cdclk_change_post(dev_priv);
1366
1367 dev_priv->audio.component_registered = true;
1368 }
1369
1370 /**
1371 * i915_audio_component_cleanup - deregister the audio component
1372 * @dev_priv: i915 device instance
1373 *
1374 * Deregisters the audio component, breaking any existing binding to the
1375 * corresponding snd_hda_intel driver's master component.
1376 */
i915_audio_component_cleanup(struct drm_i915_private * dev_priv)1377 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1378 {
1379 if (!dev_priv->audio.component_registered)
1380 return;
1381
1382 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1383 dev_priv->audio.component_registered = false;
1384 }
1385
1386 /**
1387 * intel_audio_init() - Initialize the audio driver either using
1388 * component framework or using lpe audio bridge
1389 * @dev_priv: the i915 drm device private data
1390 *
1391 */
intel_audio_init(struct drm_i915_private * dev_priv)1392 void intel_audio_init(struct drm_i915_private *dev_priv)
1393 {
1394 if (intel_lpe_audio_init(dev_priv) < 0)
1395 i915_audio_component_init(dev_priv);
1396 }
1397
1398 /**
1399 * intel_audio_deinit() - deinitialize the audio driver
1400 * @dev_priv: the i915 drm device private data
1401 *
1402 */
intel_audio_deinit(struct drm_i915_private * dev_priv)1403 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1404 {
1405 if ((dev_priv)->audio.lpe.platdev != NULL)
1406 intel_lpe_audio_teardown(dev_priv);
1407 else
1408 i915_audio_component_cleanup(dev_priv);
1409 }
1410