1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #ifndef __HNAE3_H
5 #define __HNAE3_H
6 
7 /* Names used in this framework:
8  *      ae handle (handle):
9  *        a set of queues provided by AE
10  *      ring buffer queue (rbq):
11  *        the channel between upper layer and the AE, can do tx and rx
12  *      ring:
13  *        a tx or rx channel within a rbq
14  *      ring description (desc):
15  *        an element in the ring with packet information
16  *      buffer:
17  *        a memory region referred by desc with the full packet payload
18  *
19  * "num" means a static number set as a parameter, "count" mean a dynamic
20  *   number set while running
21  * "cb" means control block
22  */
23 
24 #include <linux/acpi.h>
25 #include <linux/dcbnl.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/ethtool.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/pci.h>
32 #include <linux/pkt_sched.h>
33 #include <linux/types.h>
34 #include <net/pkt_cls.h>
35 
36 #define HNAE3_MOD_VERSION "1.0"
37 
38 #define HNAE3_MIN_VECTOR_NUM	2 /* first one for misc, another for IO */
39 
40 /* Device version */
41 #define HNAE3_DEVICE_VERSION_V1   0x00020
42 #define HNAE3_DEVICE_VERSION_V2   0x00021
43 #define HNAE3_DEVICE_VERSION_V3   0x00030
44 
45 #define HNAE3_PCI_REVISION_BIT_SIZE		8
46 
47 /* Device IDs */
48 #define HNAE3_DEV_ID_GE				0xA220
49 #define HNAE3_DEV_ID_25GE			0xA221
50 #define HNAE3_DEV_ID_25GE_RDMA			0xA222
51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC		0xA223
52 #define HNAE3_DEV_ID_50GE_RDMA			0xA224
53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC		0xA225
54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC		0xA226
55 #define HNAE3_DEV_ID_200G_RDMA			0xA228
56 #define HNAE3_DEV_ID_VF				0xA22E
57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF		0xA22F
58 
59 #define HNAE3_CLASS_NAME_SIZE 16
60 
61 #define HNAE3_DEV_INITED_B			0x0
62 #define HNAE3_DEV_SUPPORT_ROCE_B		0x1
63 #define HNAE3_DEV_SUPPORT_DCB_B			0x2
64 #define HNAE3_KNIC_CLIENT_INITED_B		0x3
65 #define HNAE3_UNIC_CLIENT_INITED_B		0x4
66 #define HNAE3_ROCE_CLIENT_INITED_B		0x5
67 
68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
69 		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
70 
71 #define hnae3_dev_roce_supported(hdev) \
72 	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
73 
74 #define hnae3_dev_dcb_supported(hdev) \
75 	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
76 
77 enum HNAE3_DEV_CAP_BITS {
78 	HNAE3_DEV_SUPPORT_FD_B,
79 	HNAE3_DEV_SUPPORT_GRO_B,
80 	HNAE3_DEV_SUPPORT_FEC_B,
81 	HNAE3_DEV_SUPPORT_UDP_GSO_B,
82 	HNAE3_DEV_SUPPORT_QB_B,
83 	HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
84 	HNAE3_DEV_SUPPORT_PTP_B,
85 	HNAE3_DEV_SUPPORT_INT_QL_B,
86 	HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
87 	HNAE3_DEV_SUPPORT_TX_PUSH_B,
88 	HNAE3_DEV_SUPPORT_PHY_IMP_B,
89 	HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
90 	HNAE3_DEV_SUPPORT_HW_PAD_B,
91 	HNAE3_DEV_SUPPORT_STASH_B,
92 	HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
93 	HNAE3_DEV_SUPPORT_PAUSE_B,
94 	HNAE3_DEV_SUPPORT_RAS_IMP_B,
95 	HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
96 	HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
97 	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
98 	HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
99 	HNAE3_DEV_SUPPORT_CQ_B,
100 };
101 
102 #define hnae3_dev_fd_supported(hdev) \
103 	test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)
104 
105 #define hnae3_dev_gro_supported(hdev) \
106 	test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps)
107 
108 #define hnae3_dev_fec_supported(hdev) \
109 	test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
110 
111 #define hnae3_dev_udp_gso_supported(hdev) \
112 	test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
113 
114 #define hnae3_dev_qb_supported(hdev) \
115 	test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
116 
117 #define hnae3_dev_fd_forward_tc_supported(hdev) \
118 	test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
119 
120 #define hnae3_dev_ptp_supported(hdev) \
121 	test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
122 
123 #define hnae3_dev_int_ql_supported(hdev) \
124 	test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
125 
126 #define hnae3_dev_hw_csum_supported(hdev) \
127 	test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
128 
129 #define hnae3_dev_tx_push_supported(hdev) \
130 	test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
131 
132 #define hnae3_dev_phy_imp_supported(hdev) \
133 	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
134 
135 #define hnae3_dev_ras_imp_supported(hdev) \
136 	test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
137 
138 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \
139 	test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
140 
141 #define hnae3_dev_hw_pad_supported(hdev) \
142 	test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
143 
144 #define hnae3_dev_stash_supported(hdev) \
145 	test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
146 
147 #define hnae3_dev_pause_supported(hdev) \
148 	test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
149 
150 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
151 	test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
152 
153 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
154 	test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
155 
156 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
157 	test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
158 
159 #define hnae3_ae_dev_cq_supported(ae_dev) \
160 	test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
161 
162 enum HNAE3_PF_CAP_BITS {
163 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
164 };
165 #define ring_ptr_move_fw(ring, p) \
166 	((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
167 #define ring_ptr_move_bw(ring, p) \
168 	((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
169 
170 struct hnae3_handle;
171 
172 struct hnae3_queue {
173 	void __iomem *io_base;
174 	void __iomem *mem_base;
175 	struct hnae3_ae_algo *ae_algo;
176 	struct hnae3_handle *handle;
177 	int tqp_index;		/* index in a handle */
178 	u32 buf_size;		/* size for hnae_desc->addr, preset by AE */
179 	u16 tx_desc_num;	/* total number of tx desc */
180 	u16 rx_desc_num;	/* total number of rx desc */
181 };
182 
183 struct hns3_mac_stats {
184 	u64 tx_pause_cnt;
185 	u64 rx_pause_cnt;
186 };
187 
188 /* hnae3 loop mode */
189 enum hnae3_loop {
190 	HNAE3_LOOP_APP,
191 	HNAE3_LOOP_SERIAL_SERDES,
192 	HNAE3_LOOP_PARALLEL_SERDES,
193 	HNAE3_LOOP_PHY,
194 	HNAE3_LOOP_NONE,
195 };
196 
197 enum hnae3_client_type {
198 	HNAE3_CLIENT_KNIC,
199 	HNAE3_CLIENT_ROCE,
200 };
201 
202 /* mac media type */
203 enum hnae3_media_type {
204 	HNAE3_MEDIA_TYPE_UNKNOWN,
205 	HNAE3_MEDIA_TYPE_FIBER,
206 	HNAE3_MEDIA_TYPE_COPPER,
207 	HNAE3_MEDIA_TYPE_BACKPLANE,
208 	HNAE3_MEDIA_TYPE_NONE,
209 };
210 
211 /* must be consistent with definition in firmware */
212 enum hnae3_module_type {
213 	HNAE3_MODULE_TYPE_UNKNOWN	= 0x00,
214 	HNAE3_MODULE_TYPE_FIBRE_LR	= 0x01,
215 	HNAE3_MODULE_TYPE_FIBRE_SR	= 0x02,
216 	HNAE3_MODULE_TYPE_AOC		= 0x03,
217 	HNAE3_MODULE_TYPE_CR		= 0x04,
218 	HNAE3_MODULE_TYPE_KR		= 0x05,
219 	HNAE3_MODULE_TYPE_TP		= 0x06,
220 };
221 
222 enum hnae3_fec_mode {
223 	HNAE3_FEC_AUTO = 0,
224 	HNAE3_FEC_BASER,
225 	HNAE3_FEC_RS,
226 	HNAE3_FEC_USER_DEF,
227 };
228 
229 enum hnae3_reset_notify_type {
230 	HNAE3_UP_CLIENT,
231 	HNAE3_DOWN_CLIENT,
232 	HNAE3_INIT_CLIENT,
233 	HNAE3_UNINIT_CLIENT,
234 };
235 
236 enum hnae3_hw_error_type {
237 	HNAE3_PPU_POISON_ERROR,
238 	HNAE3_CMDQ_ECC_ERROR,
239 	HNAE3_IMP_RD_POISON_ERROR,
240 	HNAE3_ROCEE_AXI_RESP_ERROR,
241 };
242 
243 enum hnae3_reset_type {
244 	HNAE3_VF_RESET,
245 	HNAE3_VF_FUNC_RESET,
246 	HNAE3_VF_PF_FUNC_RESET,
247 	HNAE3_VF_FULL_RESET,
248 	HNAE3_FLR_RESET,
249 	HNAE3_FUNC_RESET,
250 	HNAE3_GLOBAL_RESET,
251 	HNAE3_IMP_RESET,
252 	HNAE3_NONE_RESET,
253 	HNAE3_MAX_RESET,
254 };
255 
256 enum hnae3_port_base_vlan_state {
257 	HNAE3_PORT_BASE_VLAN_DISABLE,
258 	HNAE3_PORT_BASE_VLAN_ENABLE,
259 	HNAE3_PORT_BASE_VLAN_MODIFY,
260 	HNAE3_PORT_BASE_VLAN_NOCHANGE,
261 };
262 
263 enum hnae3_dbg_cmd {
264 	HNAE3_DBG_CMD_TM_NODES,
265 	HNAE3_DBG_CMD_TM_PRI,
266 	HNAE3_DBG_CMD_TM_QSET,
267 	HNAE3_DBG_CMD_TM_MAP,
268 	HNAE3_DBG_CMD_TM_PG,
269 	HNAE3_DBG_CMD_TM_PORT,
270 	HNAE3_DBG_CMD_TC_SCH_INFO,
271 	HNAE3_DBG_CMD_QOS_PAUSE_CFG,
272 	HNAE3_DBG_CMD_QOS_PRI_MAP,
273 	HNAE3_DBG_CMD_QOS_BUF_CFG,
274 	HNAE3_DBG_CMD_DEV_INFO,
275 	HNAE3_DBG_CMD_TX_BD,
276 	HNAE3_DBG_CMD_RX_BD,
277 	HNAE3_DBG_CMD_MAC_UC,
278 	HNAE3_DBG_CMD_MAC_MC,
279 	HNAE3_DBG_CMD_MNG_TBL,
280 	HNAE3_DBG_CMD_LOOPBACK,
281 	HNAE3_DBG_CMD_PTP_INFO,
282 	HNAE3_DBG_CMD_INTERRUPT_INFO,
283 	HNAE3_DBG_CMD_RESET_INFO,
284 	HNAE3_DBG_CMD_IMP_INFO,
285 	HNAE3_DBG_CMD_NCL_CONFIG,
286 	HNAE3_DBG_CMD_REG_BIOS_COMMON,
287 	HNAE3_DBG_CMD_REG_SSU,
288 	HNAE3_DBG_CMD_REG_IGU_EGU,
289 	HNAE3_DBG_CMD_REG_RPU,
290 	HNAE3_DBG_CMD_REG_NCSI,
291 	HNAE3_DBG_CMD_REG_RTC,
292 	HNAE3_DBG_CMD_REG_PPP,
293 	HNAE3_DBG_CMD_REG_RCB,
294 	HNAE3_DBG_CMD_REG_TQP,
295 	HNAE3_DBG_CMD_REG_MAC,
296 	HNAE3_DBG_CMD_REG_DCB,
297 	HNAE3_DBG_CMD_VLAN_CONFIG,
298 	HNAE3_DBG_CMD_QUEUE_MAP,
299 	HNAE3_DBG_CMD_RX_QUEUE_INFO,
300 	HNAE3_DBG_CMD_TX_QUEUE_INFO,
301 	HNAE3_DBG_CMD_FD_TCAM,
302 	HNAE3_DBG_CMD_FD_COUNTER,
303 	HNAE3_DBG_CMD_MAC_TNL_STATUS,
304 	HNAE3_DBG_CMD_SERV_INFO,
305 	HNAE3_DBG_CMD_UMV_INFO,
306 	HNAE3_DBG_CMD_PAGE_POOL_INFO,
307 	HNAE3_DBG_CMD_COAL_INFO,
308 	HNAE3_DBG_CMD_UNKNOWN,
309 };
310 
311 struct hnae3_vector_info {
312 	u8 __iomem *io_addr;
313 	int vector;
314 };
315 
316 #define HNAE3_RING_TYPE_B 0
317 #define HNAE3_RING_TYPE_TX 0
318 #define HNAE3_RING_TYPE_RX 1
319 #define HNAE3_RING_GL_IDX_S 0
320 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
321 #define HNAE3_RING_GL_RX 0
322 #define HNAE3_RING_GL_TX 1
323 
324 #define HNAE3_FW_VERSION_BYTE3_SHIFT	24
325 #define HNAE3_FW_VERSION_BYTE3_MASK	GENMASK(31, 24)
326 #define HNAE3_FW_VERSION_BYTE2_SHIFT	16
327 #define HNAE3_FW_VERSION_BYTE2_MASK	GENMASK(23, 16)
328 #define HNAE3_FW_VERSION_BYTE1_SHIFT	8
329 #define HNAE3_FW_VERSION_BYTE1_MASK	GENMASK(15, 8)
330 #define HNAE3_FW_VERSION_BYTE0_SHIFT	0
331 #define HNAE3_FW_VERSION_BYTE0_MASK	GENMASK(7, 0)
332 
333 struct hnae3_ring_chain_node {
334 	struct hnae3_ring_chain_node *next;
335 	u32 tqp_index;
336 	u32 flag;
337 	u32 int_gl_idx;
338 };
339 
340 #define HNAE3_IS_TX_RING(node) \
341 	(((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
342 
343 /* device specification info from firmware */
344 struct hnae3_dev_specs {
345 	u32 mac_entry_num; /* number of mac-vlan table entry */
346 	u32 mng_entry_num; /* number of manager table entry */
347 	u32 max_tm_rate;
348 	u16 rss_ind_tbl_size;
349 	u16 rss_key_size;
350 	u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
351 	u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
352 	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
353 	u16 max_frm_size;
354 	u16 max_qset_num;
355 	u16 umv_size;
356 	u16 mc_mac_size;
357 	u32 mac_stats_num;
358 };
359 
360 struct hnae3_client_ops {
361 	int (*init_instance)(struct hnae3_handle *handle);
362 	void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
363 	void (*link_status_change)(struct hnae3_handle *handle, bool state);
364 	int (*reset_notify)(struct hnae3_handle *handle,
365 			    enum hnae3_reset_notify_type type);
366 	void (*process_hw_error)(struct hnae3_handle *handle,
367 				 enum hnae3_hw_error_type);
368 };
369 
370 #define HNAE3_CLIENT_NAME_LENGTH 16
371 struct hnae3_client {
372 	char name[HNAE3_CLIENT_NAME_LENGTH];
373 	unsigned long state;
374 	enum hnae3_client_type type;
375 	const struct hnae3_client_ops *ops;
376 	struct list_head node;
377 };
378 
379 #define HNAE3_DEV_CAPS_MAX_NUM	96
380 struct hnae3_ae_dev {
381 	struct pci_dev *pdev;
382 	const struct hnae3_ae_ops *ops;
383 	struct list_head node;
384 	u32 flag;
385 	unsigned long hw_err_reset_req;
386 	struct hnae3_dev_specs dev_specs;
387 	u32 dev_version;
388 	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
389 	void *priv;
390 };
391 
392 /* This struct defines the operation on the handle.
393  *
394  * init_ae_dev(): (mandatory)
395  *   Get PF configure from pci_dev and initialize PF hardware
396  * uninit_ae_dev()
397  *   Disable PF device and release PF resource
398  * register_client
399  *   Register client to ae_dev
400  * unregister_client()
401  *   Unregister client from ae_dev
402  * start()
403  *   Enable the hardware
404  * stop()
405  *   Disable the hardware
406  * start_client()
407  *   Inform the hclge that client has been started
408  * stop_client()
409  *   Inform the hclge that client has been stopped
410  * get_status()
411  *   Get the carrier state of the back channel of the handle, 1 for ok, 0 for
412  *   non-ok
413  * get_ksettings_an_result()
414  *   Get negotiation status,speed and duplex
415  * get_media_type()
416  *   Get media type of MAC
417  * check_port_speed()
418  *   Check target speed whether is supported
419  * adjust_link()
420  *   Adjust link status
421  * set_loopback()
422  *   Set loopback
423  * set_promisc_mode
424  *   Set promisc mode
425  * request_update_promisc_mode
426  *   request to hclge(vf) to update promisc mode
427  * set_mtu()
428  *   set mtu
429  * get_pauseparam()
430  *   get tx and rx of pause frame use
431  * set_pauseparam()
432  *   set tx and rx of pause frame use
433  * set_autoneg()
434  *   set auto autonegotiation of pause frame use
435  * get_autoneg()
436  *   get auto autonegotiation of pause frame use
437  * restart_autoneg()
438  *   restart autonegotiation
439  * halt_autoneg()
440  *   halt/resume autonegotiation when autonegotiation on
441  * get_coalesce_usecs()
442  *   get usecs to delay a TX interrupt after a packet is sent
443  * get_rx_max_coalesced_frames()
444  *   get Maximum number of packets to be sent before a TX interrupt.
445  * set_coalesce_usecs()
446  *   set usecs to delay a TX interrupt after a packet is sent
447  * set_coalesce_frames()
448  *   set Maximum number of packets to be sent before a TX interrupt.
449  * get_mac_addr()
450  *   get mac address
451  * set_mac_addr()
452  *   set mac address
453  * add_uc_addr
454  *   Add unicast addr to mac table
455  * rm_uc_addr
456  *   Remove unicast addr from mac table
457  * set_mc_addr()
458  *   Set multicast address
459  * add_mc_addr
460  *   Add multicast address to mac table
461  * rm_mc_addr
462  *   Remove multicast address from mac table
463  * update_stats()
464  *   Update Old network device statistics
465  * get_mac_stats()
466  *   get mac pause statistics including tx_cnt and rx_cnt
467  * get_ethtool_stats()
468  *   Get ethtool network device statistics
469  * get_strings()
470  *   Get a set of strings that describe the requested objects
471  * get_sset_count()
472  *   Get number of strings that @get_strings will write
473  * update_led_status()
474  *   Update the led status
475  * set_led_id()
476  *   Set led id
477  * get_regs()
478  *   Get regs dump
479  * get_regs_len()
480  *   Get the len of the regs dump
481  * get_rss_key_size()
482  *   Get rss key size
483  * get_rss()
484  *   Get rss table
485  * set_rss()
486  *   Set rss table
487  * get_tc_size()
488  *   Get tc size of handle
489  * get_vector()
490  *   Get vector number and vector information
491  * put_vector()
492  *   Put the vector in hdev
493  * map_ring_to_vector()
494  *   Map rings to vector
495  * unmap_ring_from_vector()
496  *   Unmap rings from vector
497  * reset_queue()
498  *   Reset queue
499  * get_fw_version()
500  *   Get firmware version
501  * get_mdix_mode()
502  *   Get media typr of phy
503  * enable_vlan_filter()
504  *   Enable vlan filter
505  * set_vlan_filter()
506  *   Set vlan filter config of Ports
507  * set_vf_vlan_filter()
508  *   Set vlan filter config of vf
509  * enable_hw_strip_rxvtag()
510  *   Enable/disable hardware strip vlan tag of packets received
511  * set_gro_en
512  *   Enable/disable HW GRO
513  * add_arfs_entry
514  *   Check the 5-tuples of flow, and create flow director rule
515  * get_vf_config
516  *   Get the VF configuration setting by the host
517  * set_vf_link_state
518  *   Set VF link status
519  * set_vf_spoofchk
520  *   Enable/disable spoof check for specified vf
521  * set_vf_trust
522  *   Enable/disable trust for specified vf, if the vf being trusted, then
523  *   it can enable promisc mode
524  * set_vf_rate
525  *   Set the max tx rate of specified vf.
526  * set_vf_mac
527  *   Configure the default MAC for specified VF
528  * get_module_eeprom
529  *   Get the optical module eeprom info.
530  * add_cls_flower
531  *   Add clsflower rule
532  * del_cls_flower
533  *   Delete clsflower rule
534  * cls_flower_active
535  *   Check if any cls flower rule exist
536  * dbg_read_cmd
537  *   Execute debugfs read command.
538  * set_tx_hwts_info
539  *   Save information for 1588 tx packet
540  * get_rx_hwts
541  *   Get 1588 rx hwstamp
542  * get_ts_info
543  *   Get phc info
544  * clean_vf_config
545  *   Clean residual vf info after disable sriov
546  */
547 struct hnae3_ae_ops {
548 	int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
549 	void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
550 	void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
551 			      enum hnae3_reset_type rst_type);
552 	void (*reset_done)(struct hnae3_ae_dev *ae_dev);
553 	int (*init_client_instance)(struct hnae3_client *client,
554 				    struct hnae3_ae_dev *ae_dev);
555 	void (*uninit_client_instance)(struct hnae3_client *client,
556 				       struct hnae3_ae_dev *ae_dev);
557 	int (*start)(struct hnae3_handle *handle);
558 	void (*stop)(struct hnae3_handle *handle);
559 	int (*client_start)(struct hnae3_handle *handle);
560 	void (*client_stop)(struct hnae3_handle *handle);
561 	int (*get_status)(struct hnae3_handle *handle);
562 	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
563 					u8 *auto_neg, u32 *speed, u8 *duplex);
564 
565 	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
566 				   u8 duplex);
567 
568 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
569 			       u8 *module_type);
570 	int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
571 	void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
572 			u8 *fec_mode);
573 	int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
574 	void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
575 	int (*set_loopback)(struct hnae3_handle *handle,
576 			    enum hnae3_loop loop_mode, bool en);
577 
578 	int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
579 				bool en_mc_pmc);
580 	void (*request_update_promisc_mode)(struct hnae3_handle *handle);
581 	int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
582 
583 	void (*get_pauseparam)(struct hnae3_handle *handle,
584 			       u32 *auto_neg, u32 *rx_en, u32 *tx_en);
585 	int (*set_pauseparam)(struct hnae3_handle *handle,
586 			      u32 auto_neg, u32 rx_en, u32 tx_en);
587 
588 	int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
589 	int (*get_autoneg)(struct hnae3_handle *handle);
590 	int (*restart_autoneg)(struct hnae3_handle *handle);
591 	int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
592 
593 	void (*get_coalesce_usecs)(struct hnae3_handle *handle,
594 				   u32 *tx_usecs, u32 *rx_usecs);
595 	void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
596 					    u32 *tx_frames, u32 *rx_frames);
597 	int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
598 	int (*set_coalesce_frames)(struct hnae3_handle *handle,
599 				   u32 coalesce_frames);
600 	void (*get_coalesce_range)(struct hnae3_handle *handle,
601 				   u32 *tx_frames_low, u32 *rx_frames_low,
602 				   u32 *tx_frames_high, u32 *rx_frames_high,
603 				   u32 *tx_usecs_low, u32 *rx_usecs_low,
604 				   u32 *tx_usecs_high, u32 *rx_usecs_high);
605 
606 	void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
607 	int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,
608 			    bool is_first);
609 	int (*do_ioctl)(struct hnae3_handle *handle,
610 			struct ifreq *ifr, int cmd);
611 	int (*add_uc_addr)(struct hnae3_handle *handle,
612 			   const unsigned char *addr);
613 	int (*rm_uc_addr)(struct hnae3_handle *handle,
614 			  const unsigned char *addr);
615 	int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
616 	int (*add_mc_addr)(struct hnae3_handle *handle,
617 			   const unsigned char *addr);
618 	int (*rm_mc_addr)(struct hnae3_handle *handle,
619 			  const unsigned char *addr);
620 	void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
621 	void (*update_stats)(struct hnae3_handle *handle,
622 			     struct net_device_stats *net_stats);
623 	void (*get_stats)(struct hnae3_handle *handle, u64 *data);
624 	void (*get_mac_stats)(struct hnae3_handle *handle,
625 			      struct hns3_mac_stats *mac_stats);
626 	void (*get_strings)(struct hnae3_handle *handle,
627 			    u32 stringset, u8 *data);
628 	int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
629 
630 	void (*get_regs)(struct hnae3_handle *handle, u32 *version,
631 			 void *data);
632 	int (*get_regs_len)(struct hnae3_handle *handle);
633 
634 	u32 (*get_rss_key_size)(struct hnae3_handle *handle);
635 	int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
636 		       u8 *hfunc);
637 	int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
638 		       const u8 *key, const u8 hfunc);
639 	int (*set_rss_tuple)(struct hnae3_handle *handle,
640 			     struct ethtool_rxnfc *cmd);
641 	int (*get_rss_tuple)(struct hnae3_handle *handle,
642 			     struct ethtool_rxnfc *cmd);
643 
644 	int (*get_tc_size)(struct hnae3_handle *handle);
645 
646 	int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
647 			  struct hnae3_vector_info *vector_info);
648 	int (*put_vector)(struct hnae3_handle *handle, int vector_num);
649 	int (*map_ring_to_vector)(struct hnae3_handle *handle,
650 				  int vector_num,
651 				  struct hnae3_ring_chain_node *vr_chain);
652 	int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
653 				      int vector_num,
654 				      struct hnae3_ring_chain_node *vr_chain);
655 
656 	int (*reset_queue)(struct hnae3_handle *handle);
657 	u32 (*get_fw_version)(struct hnae3_handle *handle);
658 	void (*get_mdix_mode)(struct hnae3_handle *handle,
659 			      u8 *tp_mdix_ctrl, u8 *tp_mdix);
660 
661 	int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
662 	int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
663 			       u16 vlan_id, bool is_kill);
664 	int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
665 				  u16 vlan, u8 qos, __be16 proto);
666 	int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
667 	void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
668 	enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
669 						 unsigned long *addr);
670 	void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
671 					  enum hnae3_reset_type rst_type);
672 	void (*get_channels)(struct hnae3_handle *handle,
673 			     struct ethtool_channels *ch);
674 	void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
675 				      u16 *alloc_tqps, u16 *max_rss_size);
676 	int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
677 			    bool rxfh_configured);
678 	void (*get_flowctrl_adv)(struct hnae3_handle *handle,
679 				 u32 *flowctrl_adv);
680 	int (*set_led_id)(struct hnae3_handle *handle,
681 			  enum ethtool_phys_id_state status);
682 	void (*get_link_mode)(struct hnae3_handle *handle,
683 			      unsigned long *supported,
684 			      unsigned long *advertising);
685 	int (*add_fd_entry)(struct hnae3_handle *handle,
686 			    struct ethtool_rxnfc *cmd);
687 	int (*del_fd_entry)(struct hnae3_handle *handle,
688 			    struct ethtool_rxnfc *cmd);
689 	int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
690 			       struct ethtool_rxnfc *cmd);
691 	int (*get_fd_rule_info)(struct hnae3_handle *handle,
692 				struct ethtool_rxnfc *cmd);
693 	int (*get_fd_all_rules)(struct hnae3_handle *handle,
694 				struct ethtool_rxnfc *cmd, u32 *rule_locs);
695 	void (*enable_fd)(struct hnae3_handle *handle, bool enable);
696 	int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
697 			      u16 flow_id, struct flow_keys *fkeys);
698 	int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
699 			    char *buf, int len);
700 	pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
701 	bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
702 	bool (*ae_dev_resetting)(struct hnae3_handle *handle);
703 	unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
704 	int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
705 	u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
706 	void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
707 	int (*mac_connect_phy)(struct hnae3_handle *handle);
708 	void (*mac_disconnect_phy)(struct hnae3_handle *handle);
709 	int (*get_vf_config)(struct hnae3_handle *handle, int vf,
710 			     struct ifla_vf_info *ivf);
711 	int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
712 				 int link_state);
713 	int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
714 			       bool enable);
715 	int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
716 	int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
717 			   int min_tx_rate, int max_tx_rate, bool force);
718 	int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
719 	int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
720 				 u32 len, u8 *data);
721 	bool (*get_cmdq_stat)(struct hnae3_handle *handle);
722 	int (*add_cls_flower)(struct hnae3_handle *handle,
723 			      struct flow_cls_offload *cls_flower, int tc);
724 	int (*del_cls_flower)(struct hnae3_handle *handle,
725 			      struct flow_cls_offload *cls_flower);
726 	bool (*cls_flower_active)(struct hnae3_handle *handle);
727 	int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
728 				      struct ethtool_link_ksettings *cmd);
729 	int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
730 				      const struct ethtool_link_ksettings *cmd);
731 	bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
732 				 struct sk_buff *skb);
733 	void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
734 			    u32 nsec, u32 sec);
735 	int (*get_ts_info)(struct hnae3_handle *handle,
736 			   struct ethtool_ts_info *info);
737 	int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
738 				       u32 *status_code);
739 	void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
740 };
741 
742 struct hnae3_dcb_ops {
743 	/* IEEE 802.1Qaz std */
744 	int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
745 	int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
746 	int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
747 	int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
748 
749 	/* DCBX configuration */
750 	u8   (*getdcbx)(struct hnae3_handle *);
751 	u8   (*setdcbx)(struct hnae3_handle *, u8);
752 
753 	int (*setup_tc)(struct hnae3_handle *handle,
754 			struct tc_mqprio_qopt_offload *mqprio_qopt);
755 };
756 
757 struct hnae3_ae_algo {
758 	const struct hnae3_ae_ops *ops;
759 	struct list_head node;
760 	const struct pci_device_id *pdev_id_table;
761 };
762 
763 #define HNAE3_INT_NAME_LEN        32
764 #define HNAE3_ITR_COUNTDOWN_START 100
765 
766 #define HNAE3_MAX_TC		8
767 #define HNAE3_MAX_USER_PRIO	8
768 struct hnae3_tc_info {
769 	u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
770 	u16 tqp_count[HNAE3_MAX_TC];
771 	u16 tqp_offset[HNAE3_MAX_TC];
772 	u8 max_tc; /* Total number of TCs */
773 	u8 num_tc; /* Total number of enabled TCs */
774 	bool mqprio_active;
775 };
776 
777 struct hnae3_knic_private_info {
778 	struct net_device *netdev; /* Set by KNIC client when init instance */
779 	u16 rss_size;		   /* Allocated RSS queues */
780 	u16 req_rss_size;
781 	u16 rx_buf_len;
782 	u16 num_tx_desc;
783 	u16 num_rx_desc;
784 	u32 tx_spare_buf_size;
785 
786 	struct hnae3_tc_info tc_info;
787 
788 	u16 num_tqps;		  /* total number of TQPs in this handle */
789 	struct hnae3_queue **tqp;  /* array base of all TQPs in this instance */
790 	const struct hnae3_dcb_ops *dcb_ops;
791 
792 	u16 int_rl_setting;
793 	enum pkt_hash_types rss_type;
794 	void __iomem *io_base;
795 };
796 
797 struct hnae3_roce_private_info {
798 	struct net_device *netdev;
799 	void __iomem *roce_io_base;
800 	void __iomem *roce_mem_base;
801 	int base_vector;
802 	int num_vectors;
803 
804 	/* The below attributes defined for RoCE client, hnae3 gives
805 	 * initial values to them, and RoCE client can modify and use
806 	 * them.
807 	 */
808 	unsigned long reset_state;
809 	unsigned long instance_state;
810 	unsigned long state;
811 };
812 
813 #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
814 #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
815 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
816 #define HNAE3_SUPPORT_VF	      BIT(3)
817 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK	BIT(4)
818 
819 #define HNAE3_USER_UPE		BIT(0)	/* unicast promisc enabled by user */
820 #define HNAE3_USER_MPE		BIT(1)	/* mulitcast promisc enabled by user */
821 #define HNAE3_BPE		BIT(2)	/* broadcast promisc enable */
822 #define HNAE3_OVERFLOW_UPE	BIT(3)	/* unicast mac vlan overflow */
823 #define HNAE3_OVERFLOW_MPE	BIT(4)	/* multicast mac vlan overflow */
824 #define HNAE3_UPE		(HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
825 #define HNAE3_MPE		(HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
826 
827 enum hnae3_pflag {
828 	HNAE3_PFLAG_LIMIT_PROMISC,
829 	HNAE3_PFLAG_MAX
830 };
831 
832 struct hnae3_handle {
833 	struct hnae3_client *client;
834 	struct pci_dev *pdev;
835 	void *priv;
836 	struct hnae3_ae_algo *ae_algo;  /* the class who provides this handle */
837 	u64 flags; /* Indicate the capabilities for this handle */
838 
839 	union {
840 		struct net_device *netdev; /* first member */
841 		struct hnae3_knic_private_info kinfo;
842 		struct hnae3_roce_private_info rinfo;
843 	};
844 
845 	u32 numa_node_mask;	/* for multi-chip support */
846 
847 	enum hnae3_port_base_vlan_state port_base_vlan_state;
848 
849 	u8 netdev_flags;
850 	struct dentry *hnae3_dbgfs;
851 	/* protects concurrent contention between debugfs commands */
852 	struct mutex dbgfs_lock;
853 	char **dbgfs_buf;
854 
855 	/* Network interface message level enabled bits */
856 	u32 msg_enable;
857 
858 	unsigned long supported_pflags;
859 	unsigned long priv_flags;
860 };
861 
862 #define hnae3_set_field(origin, mask, shift, val) \
863 	do { \
864 		(origin) &= (~(mask)); \
865 		(origin) |= ((val) << (shift)) & (mask); \
866 	} while (0)
867 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
868 
869 #define hnae3_set_bit(origin, shift, val) \
870 	hnae3_set_field(origin, 0x1 << (shift), shift, val)
871 #define hnae3_get_bit(origin, shift) \
872 	hnae3_get_field(origin, 0x1 << (shift), shift)
873 
874 #define HNAE3_FORMAT_MAC_ADDR_LEN	18
875 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0	0
876 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4	4
877 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5	5
878 
hnae3_format_mac_addr(char * format_mac_addr,const u8 * mac_addr)879 static inline void hnae3_format_mac_addr(char *format_mac_addr,
880 					 const u8 *mac_addr)
881 {
882 	snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x",
883 		 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],
884 		 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],
885 		 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);
886 }
887 
888 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
889 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
890 
891 void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
892 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
893 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
894 
895 void hnae3_unregister_client(struct hnae3_client *client);
896 int hnae3_register_client(struct hnae3_client *client);
897 
898 void hnae3_set_client_init_flag(struct hnae3_client *client,
899 				struct hnae3_ae_dev *ae_dev,
900 				unsigned int inited);
901 #endif
902