1 /*
2 * linux/drivers/ide/pci/piix.c Version 0.42 January 11, 2003
3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 *
8 * May be copied or modified under the terms of the GNU General Public License
9 *
10 * PIO mode setting function for Intel chipsets.
11 * For use instead of BIOS settings.
12 *
13 * 40-41
14 * 42-43
15 *
16 * 41
17 * 43
18 *
19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
23 *
24 * sitre = word40 & 0x4000; primary
25 * sitre = word42 & 0x4000; secondary
26 *
27 * 44 8421|8421 hdd|hdb
28 *
29 * 48 8421 hdd|hdc|hdb|hda udma enabled
30 *
31 * 0001 hda
32 * 0010 hdb
33 * 0100 hdc
34 * 1000 hdd
35 *
36 * 4a 84|21 hdb|hda
37 * 4b 84|21 hdd|hdc
38 *
39 * ata-33/82371AB
40 * ata-33/82371EB
41 * ata-33/82801AB ata-66/82801AA
42 * 00|00 udma 0 00|00 reserved
43 * 01|01 udma 1 01|01 udma 3
44 * 10|10 udma 2 10|10 udma 4
45 * 11|11 reserved 11|11 reserved
46 *
47 * 54 8421|8421 ata66 drive|ata66 enable
48 *
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
52 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
54 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
55 *
56 * Documentation
57 * Publically available from Intel web site. Errata documentation
58 * is also publically available. As an aide to anyone hacking on this
59 * driver the list of errata that are relevant is below.going back to
60 * PIIX4. Older device documentation is now a bit tricky to find.
61 *
62 * Errata of note:
63 *
64 * Unfixable
65 * PIIX4 errata #9 - Only on ultra obscure hw
66 * ICH3 errata #13 - Not observed to affect real hw
67 * by Intel
68 *
69 * Things we must deal with
70 * PIIX4 errata #10 - BM IDE hang with non UDMA
71 * (must stop/start dma to recover)
72 * 440MX errata #15 - As PIIX4 errata #10
73 * PIIX4 errata #15 - Must not read control registers
74 * during a PIO transfer
75 * 440MX errata #13 - As PIIX4 errata #15
76 * ICH2 errata #21 - DMA mode 0 doesn't work right
77 * ICH0/1 errata #55 - As ICH2 errata #21
78 * ICH2 spec c #9 - Extra operations needed to handle
79 * drive hotswap [NOT YET SUPPORTED]
80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
81 * and must be dword aligned
82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
83 *
84 * Should have been BIOS fixed:
85 * 450NX: errata #19 - DMA hangs on old 450NX
86 * 450NX: errata #20 - DMA hangs on old 450NX
87 * 450NX: errata #25 - Corruption with DMA on old 450NX
88 * ICH3 errata #15 - IDE deadlock under high load
89 * (BIOS must set dev 31 fn 0 bit 23)
90 * ICH3 errata #18 - Don't use native mode
91 */
92
93 #include <linux/config.h>
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
103
104 #include <asm/io.h>
105
106 #include "ide_modes.h"
107 #include "piix.h"
108
109 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
110 #include <linux/stat.h>
111 #include <linux/proc_fs.h>
112
113 static u8 piix_proc = 0;
114 #define PIIX_MAX_DEVS 5
115 static struct pci_dev *piix_devs[PIIX_MAX_DEVS];
116 static int n_piix_devs;
117 static int no_piix_dma = 0;
118
119 /**
120 * piix_get_info - fill in /proc for PIIX ide
121 * @buffer: buffer to fill
122 * @addr: address of user start in buffer
123 * @offset: offset into 'file'
124 * @count: buffer count
125 *
126 * Walks the PIIX devices and outputs summary data on the tuning and
127 * anything else that will help with debugging
128 */
129
piix_get_info(char * buffer,char ** addr,off_t offset,int count)130 static int piix_get_info (char *buffer, char **addr, off_t offset, int count)
131 {
132 char *p = buffer;
133 int i;
134
135 for (i = 0; i < n_piix_devs; i++) {
136 struct pci_dev *dev = piix_devs[i];
137 unsigned long bibma = pci_resource_start(dev, 4);
138 u16 reg40 = 0, psitre = 0, reg42 = 0, ssitre = 0;
139 u8 c0 = 0, c1 = 0, reg54 = 0, reg55 = 0;
140 u8 reg44 = 0, reg48 = 0, reg4a = 0, reg4b = 0;
141
142 p += sprintf(p, "\nController: %d\n", i);
143 p += sprintf(p, "\n Intel ");
144 switch(dev->device) {
145 case PCI_DEVICE_ID_INTEL_82801EB_1:
146 p += sprintf(p, "PIIX4 SATA 150 ");
147 break;
148 case PCI_DEVICE_ID_INTEL_82801BA_8:
149 case PCI_DEVICE_ID_INTEL_82801BA_9:
150 case PCI_DEVICE_ID_INTEL_82801CA_10:
151 case PCI_DEVICE_ID_INTEL_82801CA_11:
152 case PCI_DEVICE_ID_INTEL_82801DB_10:
153 case PCI_DEVICE_ID_INTEL_82801DB_11:
154 case PCI_DEVICE_ID_INTEL_82801EB_11:
155 case PCI_DEVICE_ID_INTEL_82801E_11:
156 case PCI_DEVICE_ID_INTEL_ESB_2:
157 case PCI_DEVICE_ID_INTEL_ICH6_2:
158 case PCI_DEVICE_ID_INTEL_ICH7_21:
159 p += sprintf(p, "PIIX4 Ultra 100 ");
160 break;
161 case PCI_DEVICE_ID_INTEL_82372FB_1:
162 case PCI_DEVICE_ID_INTEL_82801AA_1:
163 p += sprintf(p, "PIIX4 Ultra 66 ");
164 break;
165 case PCI_DEVICE_ID_INTEL_82451NX:
166 case PCI_DEVICE_ID_INTEL_82801AB_1:
167 case PCI_DEVICE_ID_INTEL_82443MX_1:
168 case PCI_DEVICE_ID_INTEL_82371AB:
169 p += sprintf(p, "PIIX4 Ultra 33 ");
170 break;
171 case PCI_DEVICE_ID_INTEL_82371SB_1:
172 p += sprintf(p, "PIIX3 ");
173 break;
174 case PCI_DEVICE_ID_INTEL_82371MX:
175 p += sprintf(p, "MPIIX ");
176 break;
177 case PCI_DEVICE_ID_INTEL_82371FB_1:
178 case PCI_DEVICE_ID_INTEL_82371FB_0:
179 default:
180 p += sprintf(p, "PIIX ");
181 break;
182 }
183 p += sprintf(p, "Chipset.\n");
184
185 if (dev->device == PCI_DEVICE_ID_INTEL_82371MX)
186 continue;
187
188 pci_read_config_word(dev, 0x40, ®40);
189 pci_read_config_word(dev, 0x42, ®42);
190 pci_read_config_byte(dev, 0x44, ®44);
191 pci_read_config_byte(dev, 0x48, ®48);
192 pci_read_config_byte(dev, 0x4a, ®4a);
193 pci_read_config_byte(dev, 0x4b, ®4b);
194 pci_read_config_byte(dev, 0x54, ®54);
195 pci_read_config_byte(dev, 0x55, ®55);
196
197 psitre = (reg40 & 0x4000) ? 1 : 0;
198 ssitre = (reg42 & 0x4000) ? 1 : 0;
199
200 /*
201 * at that point bibma+0x2 et bibma+0xa are byte registers
202 * to investigate:
203 */
204 c0 = inb(bibma + 0x02);
205 c1 = inb(bibma + 0x0a);
206
207 p += sprintf(p, "--------------- Primary Channel "
208 "---------------- Secondary Channel "
209 "-------------\n");
210 p += sprintf(p, " %sabled "
211 " %sabled\n",
212 (c0&0x80) ? "dis" : " en",
213 (c1&0x80) ? "dis" : " en");
214 p += sprintf(p, "--------------- drive0 --------- drive1 "
215 "-------- drive0 ---------- drive1 ------\n");
216 p += sprintf(p, "DMA enabled: %s %s "
217 " %s %s\n",
218 (c0&0x20) ? "yes" : "no ",
219 (c0&0x40) ? "yes" : "no ",
220 (c1&0x20) ? "yes" : "no ",
221 (c1&0x40) ? "yes" : "no " );
222 p += sprintf(p, "UDMA enabled: %s %s "
223 " %s %s\n",
224 (reg48&0x01) ? "yes" : "no ",
225 (reg48&0x02) ? "yes" : "no ",
226 (reg48&0x04) ? "yes" : "no ",
227 (reg48&0x08) ? "yes" : "no " );
228 p += sprintf(p, "UDMA enabled: %s %s "
229 " %s %s\n",
230 ((reg54&0x11) &&
231 (reg55&0x10) && (reg4a&0x01)) ? "5" :
232 ((reg54&0x11) && (reg4a&0x02)) ? "4" :
233 ((reg54&0x11) && (reg4a&0x01)) ? "3" :
234 (reg4a&0x02) ? "2" :
235 (reg4a&0x01) ? "1" :
236 (reg4a&0x00) ? "0" : "X",
237 ((reg54&0x22) &&
238 (reg55&0x20) && (reg4a&0x10)) ? "5" :
239 ((reg54&0x22) && (reg4a&0x20)) ? "4" :
240 ((reg54&0x22) && (reg4a&0x10)) ? "3" :
241 (reg4a&0x20) ? "2" :
242 (reg4a&0x10) ? "1" :
243 (reg4a&0x00) ? "0" : "X",
244 ((reg54&0x44) &&
245 (reg55&0x40) && (reg4b&0x03)) ? "5" :
246 ((reg54&0x44) && (reg4b&0x02)) ? "4" :
247 ((reg54&0x44) && (reg4b&0x01)) ? "3" :
248 (reg4b&0x02) ? "2" :
249 (reg4b&0x01) ? "1" :
250 (reg4b&0x00) ? "0" : "X",
251 ((reg54&0x88) &&
252 (reg55&0x80) && (reg4b&0x30)) ? "5" :
253 ((reg54&0x88) && (reg4b&0x20)) ? "4" :
254 ((reg54&0x88) && (reg4b&0x10)) ? "3" :
255 (reg4b&0x20) ? "2" :
256 (reg4b&0x10) ? "1" :
257 (reg4b&0x00) ? "0" : "X");
258
259 p += sprintf(p, "UDMA\n");
260 p += sprintf(p, "DMA\n");
261 p += sprintf(p, "PIO\n");
262
263 /*
264 * FIXME.... Add configuration junk data....blah blah......
265 */
266 }
267 return p-buffer; /* => must be less than 4k! */
268 }
269 #endif /* defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS) */
270
271 /**
272 * piix_ratemask - compute rate mask for PIIX IDE
273 * @drive: IDE drive to compute for
274 *
275 * Returns the available modes for the PIIX IDE controller.
276 */
277
piix_ratemask(ide_drive_t * drive)278 static u8 piix_ratemask (ide_drive_t *drive)
279 {
280 struct pci_dev *dev = HWIF(drive)->pci_dev;
281 u8 mode;
282
283 switch(dev->device) {
284 case PCI_DEVICE_ID_INTEL_82801EB_1:
285 mode = 3;
286 break;
287 /* UDMA 100 capable */
288 case PCI_DEVICE_ID_INTEL_82801BA_8:
289 case PCI_DEVICE_ID_INTEL_82801BA_9:
290 case PCI_DEVICE_ID_INTEL_82801CA_10:
291 case PCI_DEVICE_ID_INTEL_82801CA_11:
292 case PCI_DEVICE_ID_INTEL_82801E_11:
293 case PCI_DEVICE_ID_INTEL_82801DB_10:
294 case PCI_DEVICE_ID_INTEL_82801DB_11:
295 case PCI_DEVICE_ID_INTEL_82801EB_11:
296 case PCI_DEVICE_ID_INTEL_ESB_2:
297 case PCI_DEVICE_ID_INTEL_ICH6_2:
298 case PCI_DEVICE_ID_INTEL_ICH7_21:
299 mode = 3;
300 break;
301 /* UDMA 66 capable */
302 case PCI_DEVICE_ID_INTEL_82801AA_1:
303 case PCI_DEVICE_ID_INTEL_82372FB_1:
304 mode = 2;
305 break;
306 /* UDMA 33 capable */
307 case PCI_DEVICE_ID_INTEL_82371AB:
308 case PCI_DEVICE_ID_INTEL_82443MX_1:
309 case PCI_DEVICE_ID_INTEL_82451NX:
310 case PCI_DEVICE_ID_INTEL_82801AB_1:
311 return 1;
312 /* Non UDMA capable (MWDMA2) */
313 case PCI_DEVICE_ID_INTEL_82371SB_1:
314 case PCI_DEVICE_ID_INTEL_82371FB_1:
315 case PCI_DEVICE_ID_INTEL_82371FB_0:
316 case PCI_DEVICE_ID_INTEL_82371MX:
317 default:
318 return 0;
319 }
320
321 /*
322 * If we are UDMA66 capable fall back to UDMA33
323 * if the drive cannot see an 80pin cable.
324 */
325 if (!eighty_ninty_three(drive))
326 mode = min(mode, (u8)1);
327 return mode;
328 }
329
330 /**
331 * piix_dma_2_pio - return the PIO mode matching DMA
332 * @xfer_rate: transfer speed
333 *
334 * Returns the nearest equivalent PIO timing for the PIO or DMA
335 * mode requested by the controller.
336 */
337
piix_dma_2_pio(u8 xfer_rate)338 static u8 piix_dma_2_pio (u8 xfer_rate) {
339 switch(xfer_rate) {
340 case XFER_UDMA_6:
341 case XFER_UDMA_5:
342 case XFER_UDMA_4:
343 case XFER_UDMA_3:
344 case XFER_UDMA_2:
345 case XFER_UDMA_1:
346 case XFER_UDMA_0:
347 case XFER_MW_DMA_2:
348 case XFER_PIO_4:
349 return 4;
350 case XFER_MW_DMA_1:
351 case XFER_PIO_3:
352 return 3;
353 case XFER_SW_DMA_2:
354 case XFER_PIO_2:
355 return 2;
356 case XFER_MW_DMA_0:
357 case XFER_SW_DMA_1:
358 case XFER_SW_DMA_0:
359 case XFER_PIO_1:
360 case XFER_PIO_0:
361 case XFER_PIO_SLOW:
362 default:
363 return 0;
364 }
365 }
366
367 /**
368 * piix_tune_drive - tune a drive attached to a PIIX
369 * @drive: drive to tune
370 * @pio: desired PIO mode
371 *
372 * Set the interface PIO mode based upon the settings done by AMI BIOS
373 * (might be useful if drive is not registered in CMOS for any reason).
374 */
piix_tune_drive(ide_drive_t * drive,u8 pio)375 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
376 {
377 ide_hwif_t *hwif = HWIF(drive);
378 struct pci_dev *dev = hwif->pci_dev;
379 int is_slave = (&hwif->drives[1] == drive);
380 int master_port = hwif->channel ? 0x42 : 0x40;
381 int slave_port = 0x44;
382 unsigned long flags;
383 u16 master_data;
384 u8 slave_data;
385 /* ISP RTC */
386 u8 timings[][2] = { { 0, 0 },
387 { 0, 0 },
388 { 1, 0 },
389 { 2, 1 },
390 { 2, 3 }, };
391
392 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
393 spin_lock_irqsave(&ide_lock, flags);
394 pci_read_config_word(dev, master_port, &master_data);
395 if (is_slave) {
396 master_data = master_data | 0x4000;
397 if (pio > 1)
398 /* enable PPE, IE and TIME */
399 master_data = master_data | 0x0070;
400 pci_read_config_byte(dev, slave_port, &slave_data);
401 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
402 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
403 } else {
404 master_data = master_data & 0xccf8;
405 if (pio > 1)
406 /* enable PPE, IE and TIME */
407 master_data = master_data | 0x0007;
408 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
409 }
410 pci_write_config_word(dev, master_port, master_data);
411 if (is_slave)
412 pci_write_config_byte(dev, slave_port, slave_data);
413 spin_unlock_irqrestore(&ide_lock, flags);
414 }
415
416 /**
417 * piix_tune_chipset - tune a PIIX interface
418 * @drive: IDE drive to tune
419 * @xferspeed: speed to configure
420 *
421 * Set a PIIX interface channel to the desired speeds. This involves
422 * requires the right timing data into the PIIX configuration space
423 * then setting the drive parameters appropriately
424 */
425
piix_tune_chipset(ide_drive_t * drive,u8 xferspeed)426 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
427 {
428 ide_hwif_t *hwif = HWIF(drive);
429 struct pci_dev *dev = hwif->pci_dev;
430 u8 maslave = hwif->channel ? 0x42 : 0x40;
431 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
432 int a_speed = 3 << (drive->dn * 4);
433 int u_flag = 1 << drive->dn;
434 int v_flag = 0x01 << drive->dn;
435 int w_flag = 0x10 << drive->dn;
436 int u_speed = 0;
437 int sitre;
438 u16 reg4042, reg4a;
439 u8 reg48, reg54, reg55;
440
441 pci_read_config_word(dev, maslave, ®4042);
442 sitre = (reg4042 & 0x4000) ? 1 : 0;
443 pci_read_config_byte(dev, 0x48, ®48);
444 pci_read_config_word(dev, 0x4a, ®4a);
445 pci_read_config_byte(dev, 0x54, ®54);
446 pci_read_config_byte(dev, 0x55, ®55);
447
448 switch(speed) {
449 case XFER_UDMA_4:
450 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
451 case XFER_UDMA_5:
452 case XFER_UDMA_3:
453 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
454 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
455 case XFER_MW_DMA_2:
456 case XFER_MW_DMA_1:
457 case XFER_SW_DMA_2: break;
458 case XFER_PIO_4:
459 case XFER_PIO_3:
460 case XFER_PIO_2:
461 case XFER_PIO_0: break;
462 default: return -1;
463 }
464
465 if (speed >= XFER_UDMA_0) {
466 if (!(reg48 & u_flag))
467 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
468 if (speed == XFER_UDMA_5) {
469 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
470 } else {
471 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
472 }
473 if ((reg4a & a_speed) != u_speed)
474 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
475 if (speed > XFER_UDMA_2) {
476 if (!(reg54 & v_flag))
477 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
478 } else
479 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
480 } else {
481 if (reg48 & u_flag)
482 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
483 if (reg4a & a_speed)
484 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
485 if (reg54 & v_flag)
486 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
487 if (reg55 & w_flag)
488 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
489 }
490
491 piix_tune_drive(drive, piix_dma_2_pio(speed));
492 return (ide_config_drive_speed(drive, speed));
493 }
494
495 /**
496 * piix_faulty_dma0 - check for DMA0 errata
497 * @hwif: IDE interface to check
498 *
499 * If an ICH/ICH0/ICH2 interface is is operating in multi-word
500 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
501 * inadvertently provide an extra piece of secondary data to the primary
502 * device resulting in data corruption.
503 *
504 * With such a device this test function returns true. This allows
505 * our tuning code to follow Intel recommendations and use PIO on
506 * such devices.
507 */
508
piix_faulty_dma0(ide_hwif_t * hwif)509 static int piix_faulty_dma0(ide_hwif_t *hwif)
510 {
511 switch(hwif->pci_dev->device)
512 {
513 case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
514 case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
515 case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
516 case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
517 return 1;
518 }
519 return 0;
520 }
521
522 /**
523 * piix_config_drive_for_dma - configure drive for DMA
524 * @drive: IDE drive to configure
525 *
526 * Set up a PIIX interface channel for the best available speed.
527 * We prefer UDMA if it is available and then MWDMA. If DMA is
528 * not available we switch to PIO and return 0.
529 */
530
piix_config_drive_for_dma(ide_drive_t * drive)531 static int piix_config_drive_for_dma (ide_drive_t *drive)
532 {
533 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
534
535 /* Some ICH devices cannot support DMA mode 0 */
536 if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
537 speed = 0;
538
539 /* If no DMA speed was available or the chipset has DMA bugs
540 then disable DMA and use PIO */
541
542 if (!speed || no_piix_dma) {
543 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
544 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
545 }
546
547 (void) piix_tune_chipset(drive, speed);
548 return ide_dma_enable(drive);
549 }
550
551 /**
552 * piix_config_drive_xfer_rate - set up an IDE device
553 * @drive: IDE drive to configure
554 *
555 * Set up the PIIX interface for the best available speed on this
556 * interface, preferring DMA to PIO.
557 */
558
piix_config_drive_xfer_rate(ide_drive_t * drive)559 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
560 {
561 ide_hwif_t *hwif = HWIF(drive);
562 struct hd_driveid *id = drive->id;
563
564 drive->init_speed = 0;
565
566 if ((id->capability & 1) && (drive->autodma)) {
567
568 /* Consult the list of known "bad" drives. */
569 if (hwif->ide_dma_bad_drive(drive)) {
570 goto fast_ata_pio;
571 }
572
573 /**
574 * Try to turn DMA on if:
575 * - UDMA or EIDE modes are supported or
576 * - drive is a known "good" drive
577 *
578 * Checks for best mode supported are down later by
579 * piix_config_drive_for_dma() -> ide_dma_speed()
580 */
581 if ((id->field_valid & (4 | 2)) ||
582 (hwif->ide_dma_good_drive(drive) && (id->eide_dma_time < 150))) {
583 if (piix_config_drive_for_dma(drive)) {
584 return hwif->ide_dma_on(drive);
585 }
586 }
587
588 /* For some reason DMA wasn't turned on, so try PIO. */
589 goto fast_ata_pio;
590
591 } else if ((id->capability & 8) || (id->field_valid & 2)) {
592
593 /* Find best PIO mode. */
594 fast_ata_pio:
595 hwif->tuneproc(drive, 255);
596 return hwif->ide_dma_off_quietly(drive);
597
598 }
599
600 /* IORDY not supported */
601 return 0;
602 }
603
604 /**
605 * ich3_busproc - bus isolation ioctl
606 * @drive: drive to isolate/restore
607 * @state: bus state to set
608 *
609 * Used by the ICH3 to handle bus isolation. We have to do
610 * a little bit of fixing to keep the hardware happy.
611 */
612
ich3_busproc(ide_drive_t * drive,int state)613 static int ich3_busproc (ide_drive_t * drive, int state)
614 {
615 ide_hwif_t *hwif = HWIF(drive);
616 u32 sig_mode;
617 int shift;
618 int bits;
619
620 if(hwif->channel == 0)
621 shift = 17;
622 else
623 shift = 19;
624
625 switch (state) {
626 case BUSSTATE_ON:
627 bits = 0x00;
628 hwif->drives[0].failures = 0;
629 hwif->drives[1].failures = 0;
630 break;
631 case BUSSTATE_OFF:
632 bits = 0x01;
633 break;
634 case BUSSTATE_TRISTATE:
635 bits = 0x10;
636 break;
637 default:
638 return -EINVAL;
639 }
640
641 if(bits)
642 {
643 int port = hwif->channel == 0 ? 0x40 : 0x42;
644 u16 reg;
645 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
646 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
647 /* Turn off IORDY checking to avoid hangs */
648 pci_read_config_word(hwif->pci_dev, port, ®);
649 reg&=~(1<<5)|(1<<1);
650 pci_write_config_word(hwif->pci_dev, port, reg);
651 }
652 /* Todo: Check locking */
653 pci_read_config_dword(hwif->pci_dev, 0x54, &sig_mode);
654 sig_mode&=~(3<<shift);
655 sig_mode|=(bits<<shift);
656 pci_write_config_dword(hwif->pci_dev, 0x54, sig_mode);
657
658 hwif->bus_state = state;
659 return 0;
660 }
661
662
663 /**
664 * init_chipset_piix - set up the PIIX chipset
665 * @dev: PCI device to set up
666 * @name: Name of the device
667 *
668 * Initialize the PCI device as required. For the PIIX this turns
669 * out to be nice and simple
670 */
671
init_chipset_piix(struct pci_dev * dev,const char * name)672 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
673 {
674 switch(dev->device) {
675 case PCI_DEVICE_ID_INTEL_82801EB_1:
676 case PCI_DEVICE_ID_INTEL_82801AA_1:
677 case PCI_DEVICE_ID_INTEL_82801AB_1:
678 case PCI_DEVICE_ID_INTEL_82801BA_8:
679 case PCI_DEVICE_ID_INTEL_82801BA_9:
680 case PCI_DEVICE_ID_INTEL_82801CA_10:
681 case PCI_DEVICE_ID_INTEL_82801CA_11:
682 case PCI_DEVICE_ID_INTEL_82801DB_10:
683 case PCI_DEVICE_ID_INTEL_82801DB_11:
684 case PCI_DEVICE_ID_INTEL_82801EB_11:
685 case PCI_DEVICE_ID_INTEL_82801E_11:
686 case PCI_DEVICE_ID_INTEL_ESB_2:
687 case PCI_DEVICE_ID_INTEL_ICH6_2:
688 case PCI_DEVICE_ID_INTEL_ICH7_21:
689 {
690 unsigned int extra = 0;
691 pci_read_config_dword(dev, 0x54, &extra);
692 pci_write_config_dword(dev, 0x54, extra|0x400);
693 }
694 default:
695 break;
696 }
697
698 #if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
699 piix_devs[n_piix_devs++] = dev;
700
701 if (!piix_proc) {
702 piix_proc = 1;
703 ide_pci_register_host_proc(&piix_procs[0]);
704 }
705 #endif /* DISPLAY_PIIX_TIMINGS && CONFIG_PROC_FS */
706 return 0;
707 }
708
709 /**
710 * init_hwif_piix - fill in the hwif for the PIIX
711 * @hwif: IDE interface
712 *
713 * Set up the ide_hwif_t for the PIIX interface according to the
714 * capabilities of the hardware.
715 */
716
init_hwif_piix(ide_hwif_t * hwif)717 static void __init init_hwif_piix (ide_hwif_t *hwif)
718 {
719 u8 reg54h = 0, reg55h = 0, ata66 = 0;
720 u8 mask = hwif->channel ? 0xc0 : 0x30;
721
722 #ifndef CONFIG_IA64
723 if (!hwif->irq)
724 hwif->irq = hwif->channel ? 15 : 14;
725 #endif /* CONFIG_IA64 */
726
727 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
728 /* This is a painful system best to let it self tune for now */
729 return;
730 }
731
732 hwif->autodma = 0;
733 hwif->tuneproc = &piix_tune_drive;
734 hwif->speedproc = &piix_tune_chipset;
735 hwif->drives[0].autotune = 1;
736 hwif->drives[1].autotune = 1;
737
738 if (!hwif->dma_base)
739 return;
740
741 hwif->atapi_dma = 1;
742 hwif->ultra_mask = 0x3f;
743 hwif->mwdma_mask = 0x06;
744 hwif->swdma_mask = 0x04;
745
746 switch(hwif->pci_dev->device) {
747 case PCI_DEVICE_ID_INTEL_82371MX:
748 hwif->mwdma_mask = 0x80;
749 hwif->swdma_mask = 0x80;
750 case PCI_DEVICE_ID_INTEL_82371FB_0:
751 case PCI_DEVICE_ID_INTEL_82371FB_1:
752 case PCI_DEVICE_ID_INTEL_82371SB_1:
753 hwif->ultra_mask = 0x80;
754 break;
755 case PCI_DEVICE_ID_INTEL_82371AB:
756 case PCI_DEVICE_ID_INTEL_82443MX_1:
757 case PCI_DEVICE_ID_INTEL_82451NX:
758 case PCI_DEVICE_ID_INTEL_82801AB_1:
759 hwif->ultra_mask = 0x07;
760 break;
761 case PCI_DEVICE_ID_INTEL_82801CA_10:
762 case PCI_DEVICE_ID_INTEL_82801CA_11:
763 hwif->busproc = ich3_busproc;
764 /* fall through */
765 default:
766 pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
767 pci_read_config_byte(hwif->pci_dev, 0x55, ®55h);
768 ata66 = (reg54h & mask) ? 1 : 0;
769 break;
770 }
771
772 if (!(hwif->udma_four))
773 hwif->udma_four = ata66;
774 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
775 if (!noautodma)
776 hwif->autodma = 1;
777
778 hwif->drives[1].autodma = hwif->autodma;
779 hwif->drives[0].autodma = hwif->autodma;
780 }
781
782 /**
783 * init_dma_piix - set up the PIIX DMA
784 * @hwif: IDE interface
785 * @dmabase: DMA PCI base
786 *
787 * Set up the DMA on the PIIX controller, providing a DMA base is
788 * available. The PIIX follows the normal specs so we do nothing
789 * magical here.
790 */
791
init_dma_piix(ide_hwif_t * hwif,unsigned long dmabase)792 static void __init init_dma_piix (ide_hwif_t *hwif, unsigned long dmabase)
793 {
794 ide_setup_dma(hwif, dmabase, 8);
795 }
796
797 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
798
799 /**
800 * init_setup_piix - callback for IDE initialize
801 * @dev: PIIX PCI device
802 * @d: IDE pci info
803 *
804 * Enable the xp fixup for the PIIX controller and then perform
805 * a standard ide PCI setup
806 */
807
init_setup_piix(struct pci_dev * dev,ide_pci_device_t * d)808 static void __init init_setup_piix (struct pci_dev *dev, ide_pci_device_t *d)
809 {
810 ide_setup_pci_device(dev, d);
811 }
812
813 /**
814 * piix_init_one - called when a PIIX is found
815 * @dev: the piix device
816 * @id: the matching pci id
817 *
818 * Called when the PCI registration layer (or the IDE initialization)
819 * finds a device matching our IDE device tables.
820 */
821
piix_init_one(struct pci_dev * dev,const struct pci_device_id * id)822 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
823 {
824 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
825
826 if (dev->device != d->device)
827 BUG();
828 d->init_setup(dev, d);
829 MOD_INC_USE_COUNT;
830 return 0;
831 }
832
833 /**
834 * piix_check_450nx - Check for problem 450NX setup
835 *
836 * Check for the present of 450NX errata #19 and errata #25. If
837 * they are found, disable use of DMA IDE
838 */
839
piix_check_450nx(void)840 static void __init piix_check_450nx(void)
841 {
842 struct pci_dev *pdev = NULL;
843 u16 cfg;
844 u8 rev;
845 while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
846 {
847 /* Look for 450NX PXB. Check for problem configurations
848 A PCI quirk checks bit 6 already */
849 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
850 pci_read_config_word(pdev, 0x41, &cfg);
851 /* Only on the original revision: IDE DMA can hang */
852 if(rev == 0x00)
853 no_piix_dma = 1;
854 /* On all revisions PXB bus lock must be disabled for IDE */
855 else if(cfg & (1<<14))
856 no_piix_dma = 2;
857 }
858 if(no_piix_dma)
859 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
860 if(no_piix_dma == 2)
861 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
862 }
863
864 static struct pci_device_id piix_pci_tbl[] __devinitdata = {
865 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
866 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
867 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
868 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
869 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
870 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
871 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
872 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
873 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
875 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
876 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
877 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
879 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
881 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
882 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
883 #ifdef CONFIG_BLK_DEV_IDE_SATA
884 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
885 #endif
886 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
887 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
888 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
889 { 0, },
890 };
891
892 static struct pci_driver driver = {
893 .name = "PIIX IDE",
894 .id_table = piix_pci_tbl,
895 .probe = piix_init_one,
896 };
897
piix_ide_init(void)898 static int piix_ide_init(void)
899 {
900 piix_check_450nx();
901 return ide_pci_register_driver(&driver);
902 }
903
piix_ide_exit(void)904 static void piix_ide_exit(void)
905 {
906 ide_pci_unregister_driver(&driver);
907 }
908
909 module_init(piix_ide_init);
910 module_exit(piix_ide_exit);
911
912 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
913 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
914 MODULE_LICENSE("GPL");
915
916 EXPORT_NO_SYMBOLS;
917