1 2 /* cnic.c: Broadcom CNIC core network driver. 3 * 4 * Copyright (c) 2006-2010 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 */ 11 12 #ifndef CNIC_DEFS_H 13 #define CNIC_DEFS_H 14 15 /* KWQ (kernel work queue) request op codes */ 16 #define L2_KWQE_OPCODE_VALUE_FLUSH (4) 17 #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE (8) 18 19 #define L4_KWQE_OPCODE_VALUE_CONNECT1 (50) 20 #define L4_KWQE_OPCODE_VALUE_CONNECT2 (51) 21 #define L4_KWQE_OPCODE_VALUE_CONNECT3 (52) 22 #define L4_KWQE_OPCODE_VALUE_RESET (53) 23 #define L4_KWQE_OPCODE_VALUE_CLOSE (54) 24 #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET (60) 25 #define L4_KWQE_OPCODE_VALUE_INIT_ULP (61) 26 27 #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG (1) 28 #define L4_KWQE_OPCODE_VALUE_UPDATE_PG (9) 29 #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG (14) 30 31 #define L5CM_RAMROD_CMD_ID_BASE (0x80) 32 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3) 33 #define L5CM_RAMROD_CMD_ID_CLOSE (L5CM_RAMROD_CMD_ID_BASE + 12) 34 #define L5CM_RAMROD_CMD_ID_ABORT (L5CM_RAMROD_CMD_ID_BASE + 13) 35 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14) 36 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15) 37 38 #define FCOE_KCQE_OPCODE_INIT_FUNC (0x10) 39 #define FCOE_KCQE_OPCODE_DESTROY_FUNC (0x11) 40 #define FCOE_KCQE_OPCODE_STAT_FUNC (0x12) 41 #define FCOE_KCQE_OPCODE_OFFLOAD_CONN (0x15) 42 #define FCOE_KCQE_OPCODE_ENABLE_CONN (0x16) 43 #define FCOE_KCQE_OPCODE_DISABLE_CONN (0x17) 44 #define FCOE_KCQE_OPCODE_DESTROY_CONN (0x18) 45 #define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20) 46 #define FCOE_KCQE_OPCODE_FCOE_ERROR (0x21) 47 48 #define FCOE_RAMROD_CMD_ID_INIT (FCOE_KCQE_OPCODE_INIT_FUNC) 49 #define FCOE_RAMROD_CMD_ID_DESTROY (FCOE_KCQE_OPCODE_DESTROY_FUNC) 50 #define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN (FCOE_KCQE_OPCODE_OFFLOAD_CONN) 51 #define FCOE_RAMROD_CMD_ID_ENABLE_CONN (FCOE_KCQE_OPCODE_ENABLE_CONN) 52 #define FCOE_RAMROD_CMD_ID_DISABLE_CONN (FCOE_KCQE_OPCODE_DISABLE_CONN) 53 #define FCOE_RAMROD_CMD_ID_DESTROY_CONN (FCOE_KCQE_OPCODE_DESTROY_CONN) 54 #define FCOE_RAMROD_CMD_ID_STAT (FCOE_KCQE_OPCODE_STAT_FUNC) 55 #define FCOE_RAMROD_CMD_ID_TERMINATE_CONN (0x81) 56 57 #define FCOE_KWQE_OPCODE_INIT1 (0) 58 #define FCOE_KWQE_OPCODE_INIT2 (1) 59 #define FCOE_KWQE_OPCODE_INIT3 (2) 60 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN1 (3) 61 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN2 (4) 62 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN3 (5) 63 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN4 (6) 64 #define FCOE_KWQE_OPCODE_ENABLE_CONN (7) 65 #define FCOE_KWQE_OPCODE_DISABLE_CONN (8) 66 #define FCOE_KWQE_OPCODE_DESTROY_CONN (9) 67 #define FCOE_KWQE_OPCODE_DESTROY (10) 68 #define FCOE_KWQE_OPCODE_STAT (11) 69 70 #define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3) 71 72 /* KCQ (kernel completion queue) response op codes */ 73 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) 74 #define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) 75 #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE (55) 76 #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE (56) 77 #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED (57) 78 #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED (58) 79 #define L4_KCQE_OPCODE_VALUE_INIT_ULP (61) 80 81 #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG (1) 82 #define L4_KCQE_OPCODE_VALUE_UPDATE_PG (9) 83 #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG (14) 84 85 /* KCQ (kernel completion queue) completion status */ 86 #define L4_KCQE_COMPLETION_STATUS_SUCCESS (0) 87 #define L4_KCQE_COMPLETION_STATUS_TIMEOUT (0x93) 88 89 #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL (0x83) 90 #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG (0x89) 91 92 #define L4_KCQE_OPCODE_VALUE_OOO_EVENT_NOTIFICATION (0xa0) 93 #define L4_KCQE_OPCODE_VALUE_OOO_FLUSH (0xa1) 94 95 #define L4_LAYER_CODE (4) 96 #define L2_LAYER_CODE (2) 97 98 /* 99 * L4 KCQ CQE 100 */ 101 struct l4_kcq { 102 u32 cid; 103 u32 pg_cid; 104 u32 conn_id; 105 u32 pg_host_opaque; 106 #if defined(__BIG_ENDIAN) 107 u16 status; 108 u16 reserved1; 109 #elif defined(__LITTLE_ENDIAN) 110 u16 reserved1; 111 u16 status; 112 #endif 113 u32 reserved2[2]; 114 #if defined(__BIG_ENDIAN) 115 u8 flags; 116 #define L4_KCQ_RESERVED3 (0x7<<0) 117 #define L4_KCQ_RESERVED3_SHIFT 0 118 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ 119 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 120 #define L4_KCQ_LAYER_CODE (0x7<<4) 121 #define L4_KCQ_LAYER_CODE_SHIFT 4 122 #define L4_KCQ_RESERVED4 (0x1<<7) 123 #define L4_KCQ_RESERVED4_SHIFT 7 124 u8 op_code; 125 u16 qe_self_seq; 126 #elif defined(__LITTLE_ENDIAN) 127 u16 qe_self_seq; 128 u8 op_code; 129 u8 flags; 130 #define L4_KCQ_RESERVED3 (0xF<<0) 131 #define L4_KCQ_RESERVED3_SHIFT 0 132 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ 133 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 134 #define L4_KCQ_LAYER_CODE (0x7<<4) 135 #define L4_KCQ_LAYER_CODE_SHIFT 4 136 #define L4_KCQ_RESERVED4 (0x1<<7) 137 #define L4_KCQ_RESERVED4_SHIFT 7 138 #endif 139 }; 140 141 142 /* 143 * L4 KCQ CQE PG upload 144 */ 145 struct l4_kcq_upload_pg { 146 u32 pg_cid; 147 #if defined(__BIG_ENDIAN) 148 u16 pg_status; 149 u16 pg_ipid_count; 150 #elif defined(__LITTLE_ENDIAN) 151 u16 pg_ipid_count; 152 u16 pg_status; 153 #endif 154 u32 reserved1[5]; 155 #if defined(__BIG_ENDIAN) 156 u8 flags; 157 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) 158 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 159 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) 160 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 161 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) 162 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 163 u8 op_code; 164 u16 qe_self_seq; 165 #elif defined(__LITTLE_ENDIAN) 166 u16 qe_self_seq; 167 u8 op_code; 168 u8 flags; 169 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) 170 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 171 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) 172 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 173 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) 174 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 175 #endif 176 }; 177 178 179 /* 180 * Gracefully close the connection request 181 */ 182 struct l4_kwq_close_req { 183 #if defined(__BIG_ENDIAN) 184 u8 flags; 185 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) 186 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 187 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) 188 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 189 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) 190 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 191 u8 op_code; 192 u16 reserved0; 193 #elif defined(__LITTLE_ENDIAN) 194 u16 reserved0; 195 u8 op_code; 196 u8 flags; 197 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) 198 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 199 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) 200 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 201 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) 202 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 203 #endif 204 u32 cid; 205 u32 reserved2[6]; 206 }; 207 208 209 /* 210 * The first request to be passed in order to establish connection in option2 211 */ 212 struct l4_kwq_connect_req1 { 213 #if defined(__BIG_ENDIAN) 214 u8 flags; 215 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) 216 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 217 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) 218 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 219 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) 220 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 221 u8 op_code; 222 u8 reserved0; 223 u8 conn_flags; 224 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) 225 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 226 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) 227 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 228 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) 229 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 230 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) 231 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 232 #elif defined(__LITTLE_ENDIAN) 233 u8 conn_flags; 234 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) 235 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 236 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) 237 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 238 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) 239 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 240 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) 241 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 242 u8 reserved0; 243 u8 op_code; 244 u8 flags; 245 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) 246 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 247 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) 248 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 249 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) 250 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 251 #endif 252 u32 cid; 253 u32 pg_cid; 254 u32 src_ip; 255 u32 dst_ip; 256 #if defined(__BIG_ENDIAN) 257 u16 dst_port; 258 u16 src_port; 259 #elif defined(__LITTLE_ENDIAN) 260 u16 src_port; 261 u16 dst_port; 262 #endif 263 #if defined(__BIG_ENDIAN) 264 u8 rsrv1[3]; 265 u8 tcp_flags; 266 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) 267 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 268 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) 269 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 270 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) 271 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 272 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) 273 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 274 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) 275 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 276 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) 277 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 278 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 279 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 280 #elif defined(__LITTLE_ENDIAN) 281 u8 tcp_flags; 282 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) 283 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 284 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) 285 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 286 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) 287 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 288 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) 289 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 290 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) 291 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 292 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) 293 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 294 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 295 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 296 u8 rsrv1[3]; 297 #endif 298 u32 rsrv2; 299 }; 300 301 302 /* 303 * The second ( optional )request to be passed in order to establish 304 * connection in option2 - for IPv6 only 305 */ 306 struct l4_kwq_connect_req2 { 307 #if defined(__BIG_ENDIAN) 308 u8 flags; 309 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) 310 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 311 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) 312 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 313 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) 314 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 315 u8 op_code; 316 u8 reserved0; 317 u8 rsrv; 318 #elif defined(__LITTLE_ENDIAN) 319 u8 rsrv; 320 u8 reserved0; 321 u8 op_code; 322 u8 flags; 323 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) 324 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 325 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) 326 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 327 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) 328 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 329 #endif 330 u32 reserved2; 331 u32 src_ip_v6_2; 332 u32 src_ip_v6_3; 333 u32 src_ip_v6_4; 334 u32 dst_ip_v6_2; 335 u32 dst_ip_v6_3; 336 u32 dst_ip_v6_4; 337 }; 338 339 340 /* 341 * The third ( and last )request to be passed in order to establish 342 * connection in option2 343 */ 344 struct l4_kwq_connect_req3 { 345 #if defined(__BIG_ENDIAN) 346 u8 flags; 347 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) 348 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 349 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) 350 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 351 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) 352 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 353 u8 op_code; 354 u16 reserved0; 355 #elif defined(__LITTLE_ENDIAN) 356 u16 reserved0; 357 u8 op_code; 358 u8 flags; 359 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) 360 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 361 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) 362 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 363 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) 364 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 365 #endif 366 u32 ka_timeout; 367 u32 ka_interval ; 368 #if defined(__BIG_ENDIAN) 369 u8 snd_seq_scale; 370 u8 ttl; 371 u8 tos; 372 u8 ka_max_probe_count; 373 #elif defined(__LITTLE_ENDIAN) 374 u8 ka_max_probe_count; 375 u8 tos; 376 u8 ttl; 377 u8 snd_seq_scale; 378 #endif 379 #if defined(__BIG_ENDIAN) 380 u16 pmtu; 381 u16 mss; 382 #elif defined(__LITTLE_ENDIAN) 383 u16 mss; 384 u16 pmtu; 385 #endif 386 u32 rcv_buf; 387 u32 snd_buf; 388 u32 seed; 389 }; 390 391 392 /* 393 * a KWQE request to offload a PG connection 394 */ 395 struct l4_kwq_offload_pg { 396 #if defined(__BIG_ENDIAN) 397 u8 flags; 398 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) 399 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 400 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) 401 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 402 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) 403 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 404 u8 op_code; 405 u16 reserved0; 406 #elif defined(__LITTLE_ENDIAN) 407 u16 reserved0; 408 u8 op_code; 409 u8 flags; 410 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) 411 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 412 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) 413 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 414 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) 415 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 416 #endif 417 #if defined(__BIG_ENDIAN) 418 u8 l2hdr_nbytes; 419 u8 pg_flags; 420 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) 421 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 422 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) 423 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 424 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) 425 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 426 u8 da0; 427 u8 da1; 428 #elif defined(__LITTLE_ENDIAN) 429 u8 da1; 430 u8 da0; 431 u8 pg_flags; 432 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) 433 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 434 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) 435 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 436 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) 437 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 438 u8 l2hdr_nbytes; 439 #endif 440 #if defined(__BIG_ENDIAN) 441 u8 da2; 442 u8 da3; 443 u8 da4; 444 u8 da5; 445 #elif defined(__LITTLE_ENDIAN) 446 u8 da5; 447 u8 da4; 448 u8 da3; 449 u8 da2; 450 #endif 451 #if defined(__BIG_ENDIAN) 452 u8 sa0; 453 u8 sa1; 454 u8 sa2; 455 u8 sa3; 456 #elif defined(__LITTLE_ENDIAN) 457 u8 sa3; 458 u8 sa2; 459 u8 sa1; 460 u8 sa0; 461 #endif 462 #if defined(__BIG_ENDIAN) 463 u8 sa4; 464 u8 sa5; 465 u16 etype; 466 #elif defined(__LITTLE_ENDIAN) 467 u16 etype; 468 u8 sa5; 469 u8 sa4; 470 #endif 471 #if defined(__BIG_ENDIAN) 472 u16 vlan_tag; 473 u16 ipid_start; 474 #elif defined(__LITTLE_ENDIAN) 475 u16 ipid_start; 476 u16 vlan_tag; 477 #endif 478 #if defined(__BIG_ENDIAN) 479 u16 ipid_count; 480 u16 reserved3; 481 #elif defined(__LITTLE_ENDIAN) 482 u16 reserved3; 483 u16 ipid_count; 484 #endif 485 u32 host_opaque; 486 }; 487 488 489 /* 490 * Abortively close the connection request 491 */ 492 struct l4_kwq_reset_req { 493 #if defined(__BIG_ENDIAN) 494 u8 flags; 495 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) 496 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 497 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) 498 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 499 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) 500 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 501 u8 op_code; 502 u16 reserved0; 503 #elif defined(__LITTLE_ENDIAN) 504 u16 reserved0; 505 u8 op_code; 506 u8 flags; 507 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) 508 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 509 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) 510 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 511 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) 512 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 513 #endif 514 u32 cid; 515 u32 reserved2[6]; 516 }; 517 518 519 /* 520 * a KWQE request to update a PG connection 521 */ 522 struct l4_kwq_update_pg { 523 #if defined(__BIG_ENDIAN) 524 u8 flags; 525 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) 526 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 527 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) 528 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 529 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) 530 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 531 u8 opcode; 532 u16 oper16; 533 #elif defined(__LITTLE_ENDIAN) 534 u16 oper16; 535 u8 opcode; 536 u8 flags; 537 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) 538 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 539 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) 540 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 541 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) 542 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 543 #endif 544 u32 pg_cid; 545 u32 pg_host_opaque; 546 #if defined(__BIG_ENDIAN) 547 u8 pg_valids; 548 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) 549 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 550 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) 551 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 552 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) 553 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 554 u8 pg_unused_a; 555 u16 pg_ipid_count; 556 #elif defined(__LITTLE_ENDIAN) 557 u16 pg_ipid_count; 558 u8 pg_unused_a; 559 u8 pg_valids; 560 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) 561 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 562 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) 563 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 564 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) 565 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 566 #endif 567 #if defined(__BIG_ENDIAN) 568 u16 reserverd3; 569 u8 da0; 570 u8 da1; 571 #elif defined(__LITTLE_ENDIAN) 572 u8 da1; 573 u8 da0; 574 u16 reserverd3; 575 #endif 576 #if defined(__BIG_ENDIAN) 577 u8 da2; 578 u8 da3; 579 u8 da4; 580 u8 da5; 581 #elif defined(__LITTLE_ENDIAN) 582 u8 da5; 583 u8 da4; 584 u8 da3; 585 u8 da2; 586 #endif 587 u32 reserved4; 588 u32 reserved5; 589 }; 590 591 592 /* 593 * a KWQE request to upload a PG or L4 context 594 */ 595 struct l4_kwq_upload { 596 #if defined(__BIG_ENDIAN) 597 u8 flags; 598 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) 599 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 600 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) 601 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 602 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) 603 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 604 u8 opcode; 605 u16 oper16; 606 #elif defined(__LITTLE_ENDIAN) 607 u16 oper16; 608 u8 opcode; 609 u8 flags; 610 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) 611 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 612 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) 613 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 614 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) 615 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 616 #endif 617 u32 cid; 618 u32 reserved2[6]; 619 }; 620 621 /* 622 * bnx2x structures 623 */ 624 625 /* 626 * The iscsi aggregative context of Cstorm 627 */ 628 struct cstorm_iscsi_ag_context { 629 u32 agg_vars1; 630 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) 631 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0 632 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) 633 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8 634 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) 635 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9 636 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) 637 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10 638 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) 639 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11 640 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) 641 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12 642 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) 643 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13 644 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF (0x3<<14) 645 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF_SHIFT 14 646 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) 647 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16 648 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) 649 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18 650 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION0_CF_EN (0x1<<19) 651 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION0_CF_EN_SHIFT 19 652 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION1_CF_EN (0x1<<20) 653 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION1_CF_EN_SHIFT 20 654 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION2_CF_EN (0x1<<21) 655 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION2_CF_EN_SHIFT 21 656 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF_EN (0x1<<22) 657 #define __CSTORM_ISCSI_AG_CONTEXT_PENDING_COMPLETION3_CF_EN_SHIFT 22 658 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) 659 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23 660 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) 661 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26 662 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) 663 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28 664 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) 665 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30 666 #if defined(__BIG_ENDIAN) 667 u8 __aux1_th; 668 u8 __aux1_val; 669 u16 __agg_vars2; 670 #elif defined(__LITTLE_ENDIAN) 671 u16 __agg_vars2; 672 u8 __aux1_val; 673 u8 __aux1_th; 674 #endif 675 u32 rel_seq; 676 u32 rel_seq_th; 677 #if defined(__BIG_ENDIAN) 678 u16 hq_cons; 679 u16 hq_prod; 680 #elif defined(__LITTLE_ENDIAN) 681 u16 hq_prod; 682 u16 hq_cons; 683 #endif 684 #if defined(__BIG_ENDIAN) 685 u8 __reserved62; 686 u8 __reserved61; 687 u8 __reserved60; 688 u8 __reserved59; 689 #elif defined(__LITTLE_ENDIAN) 690 u8 __reserved59; 691 u8 __reserved60; 692 u8 __reserved61; 693 u8 __reserved62; 694 #endif 695 #if defined(__BIG_ENDIAN) 696 u16 __reserved64; 697 u16 __cq_u_prod0; 698 #elif defined(__LITTLE_ENDIAN) 699 u16 __cq_u_prod0; 700 u16 __reserved64; 701 #endif 702 u32 __cq_u_prod1; 703 #if defined(__BIG_ENDIAN) 704 u16 __agg_vars3; 705 u16 __cq_u_prod2; 706 #elif defined(__LITTLE_ENDIAN) 707 u16 __cq_u_prod2; 708 u16 __agg_vars3; 709 #endif 710 #if defined(__BIG_ENDIAN) 711 u16 __aux2_th; 712 u16 __cq_u_prod3; 713 #elif defined(__LITTLE_ENDIAN) 714 u16 __cq_u_prod3; 715 u16 __aux2_th; 716 #endif 717 }; 718 719 /* 720 * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and used in FCoE context section 721 */ 722 struct ustorm_fcoe_params { 723 #if defined(__BIG_ENDIAN) 724 u16 fcoe_conn_id; 725 u16 flags; 726 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) 727 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 728 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) 729 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 730 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) 731 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 732 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) 733 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 734 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) 735 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 736 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) 737 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 738 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) 739 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 740 #define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7) 741 #define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7 742 #define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8) 743 #define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8 744 #define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9) 745 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9 746 #elif defined(__LITTLE_ENDIAN) 747 u16 flags; 748 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) 749 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 750 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) 751 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 752 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) 753 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 754 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) 755 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 756 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) 757 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 758 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) 759 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 760 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) 761 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 762 #define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7) 763 #define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7 764 #define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8) 765 #define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8 766 #define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9) 767 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9 768 u16 fcoe_conn_id; 769 #endif 770 #if defined(__BIG_ENDIAN) 771 u8 hc_csdm_byte_en; 772 u8 func_id; 773 u8 port_id; 774 u8 vnic_id; 775 #elif defined(__LITTLE_ENDIAN) 776 u8 vnic_id; 777 u8 port_id; 778 u8 func_id; 779 u8 hc_csdm_byte_en; 780 #endif 781 #if defined(__BIG_ENDIAN) 782 u16 rx_total_conc_seqs; 783 u16 rx_max_fc_pay_len; 784 #elif defined(__LITTLE_ENDIAN) 785 u16 rx_max_fc_pay_len; 786 u16 rx_total_conc_seqs; 787 #endif 788 #if defined(__BIG_ENDIAN) 789 u16 ox_id; 790 u16 rx_max_conc_seqs; 791 #elif defined(__LITTLE_ENDIAN) 792 u16 rx_max_conc_seqs; 793 u16 ox_id; 794 #endif 795 }; 796 797 /* 798 * FCoE 16-bits index structure 799 */ 800 struct fcoe_idx16_fields { 801 u16 fields; 802 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) 803 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0 804 #define FCOE_IDX16_FIELDS_MSB (0x1<<15) 805 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15 806 }; 807 808 /* 809 * FCoE 16-bits index union 810 */ 811 union fcoe_idx16_field_union { 812 struct fcoe_idx16_fields fields; 813 u16 val; 814 }; 815 816 /* 817 * 4 regs size 818 */ 819 struct fcoe_bd_ctx { 820 u32 buf_addr_hi; 821 u32 buf_addr_lo; 822 #if defined(__BIG_ENDIAN) 823 u16 rsrv0; 824 u16 buf_len; 825 #elif defined(__LITTLE_ENDIAN) 826 u16 buf_len; 827 u16 rsrv0; 828 #endif 829 #if defined(__BIG_ENDIAN) 830 u16 rsrv1; 831 u16 flags; 832 #elif defined(__LITTLE_ENDIAN) 833 u16 flags; 834 u16 rsrv1; 835 #endif 836 }; 837 838 /* 839 * Parameters required for placement according to SGL 840 */ 841 struct ustorm_fcoe_data_place { 842 #if defined(__BIG_ENDIAN) 843 u16 cached_sge_off; 844 u8 cached_num_sges; 845 u8 cached_sge_idx; 846 #elif defined(__LITTLE_ENDIAN) 847 u8 cached_sge_idx; 848 u8 cached_num_sges; 849 u16 cached_sge_off; 850 #endif 851 struct fcoe_bd_ctx cached_sge[3]; 852 }; 853 854 struct fcoe_task_ctx_entry_txwr_rxrd { 855 #if defined(__BIG_ENDIAN) 856 u16 verify_tx_seq; 857 u8 init_flags; 858 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0) 859 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0 860 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3) 861 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3 862 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4) 863 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4 864 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5) 865 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5 866 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6) 867 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6 868 u8 tx_flags; 869 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0) 870 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0 871 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4) 872 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4 873 #elif defined(__LITTLE_ENDIAN) 874 u8 tx_flags; 875 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0) 876 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0 877 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4) 878 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4 879 u8 init_flags; 880 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0) 881 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0 882 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3) 883 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3 884 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4) 885 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4 886 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5) 887 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5 888 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6) 889 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6 890 u16 verify_tx_seq; 891 #endif 892 }; 893 894 struct fcoe_fcp_cmd_payload { 895 u32 opaque[8]; 896 }; 897 898 struct fcoe_fc_hdr { 899 #if defined(__BIG_ENDIAN) 900 u8 cs_ctl; 901 u8 s_id[3]; 902 #elif defined(__LITTLE_ENDIAN) 903 u8 s_id[3]; 904 u8 cs_ctl; 905 #endif 906 #if defined(__BIG_ENDIAN) 907 u8 r_ctl; 908 u8 d_id[3]; 909 #elif defined(__LITTLE_ENDIAN) 910 u8 d_id[3]; 911 u8 r_ctl; 912 #endif 913 #if defined(__BIG_ENDIAN) 914 u8 seq_id; 915 u8 df_ctl; 916 u16 seq_cnt; 917 #elif defined(__LITTLE_ENDIAN) 918 u16 seq_cnt; 919 u8 df_ctl; 920 u8 seq_id; 921 #endif 922 #if defined(__BIG_ENDIAN) 923 u8 type; 924 u8 f_ctl[3]; 925 #elif defined(__LITTLE_ENDIAN) 926 u8 f_ctl[3]; 927 u8 type; 928 #endif 929 u32 parameters; 930 #if defined(__BIG_ENDIAN) 931 u16 ox_id; 932 u16 rx_id; 933 #elif defined(__LITTLE_ENDIAN) 934 u16 rx_id; 935 u16 ox_id; 936 #endif 937 }; 938 939 struct fcoe_fc_frame { 940 struct fcoe_fc_hdr fc_hdr; 941 u32 reserved0[2]; 942 }; 943 944 union fcoe_cmd_flow_info { 945 struct fcoe_fcp_cmd_payload fcp_cmd_payload; 946 struct fcoe_fc_frame mp_fc_frame; 947 }; 948 949 struct fcoe_read_flow_info { 950 struct fcoe_fc_hdr fc_data_in_hdr; 951 u32 reserved[2]; 952 }; 953 954 struct fcoe_fcp_xfr_rdy_payload { 955 u32 burst_len; 956 u32 data_ro; 957 }; 958 959 struct fcoe_write_flow_info { 960 struct fcoe_fc_hdr fc_data_out_hdr; 961 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload; 962 }; 963 964 struct fcoe_fcp_rsp_flags { 965 u8 flags; 966 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) 967 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 968 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) 969 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 970 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) 971 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 972 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) 973 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 974 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) 975 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 976 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) 977 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 978 }; 979 980 struct fcoe_fcp_rsp_payload { 981 struct regpair reserved0; 982 u32 fcp_resid; 983 #if defined(__BIG_ENDIAN) 984 u16 retry_delay_timer; 985 struct fcoe_fcp_rsp_flags fcp_flags; 986 u8 scsi_status_code; 987 #elif defined(__LITTLE_ENDIAN) 988 u8 scsi_status_code; 989 struct fcoe_fcp_rsp_flags fcp_flags; 990 u16 retry_delay_timer; 991 #endif 992 u32 fcp_rsp_len; 993 u32 fcp_sns_len; 994 }; 995 996 /* 997 * Fixed size structure in order to plant it in Union structure 998 */ 999 struct fcoe_fcp_rsp_union { 1000 struct fcoe_fcp_rsp_payload payload; 1001 struct regpair reserved0; 1002 }; 1003 1004 /* 1005 * Fixed size structure in order to plant it in Union structure 1006 */ 1007 struct fcoe_abts_rsp_union { 1008 u32 r_ctl; 1009 u32 abts_rsp_payload[7]; 1010 }; 1011 1012 union fcoe_rsp_flow_info { 1013 struct fcoe_fcp_rsp_union fcp_rsp; 1014 struct fcoe_abts_rsp_union abts_rsp; 1015 }; 1016 1017 struct fcoe_cleanup_flow_info { 1018 #if defined(__BIG_ENDIAN) 1019 u16 reserved1; 1020 u16 task_id; 1021 #elif defined(__LITTLE_ENDIAN) 1022 u16 task_id; 1023 u16 reserved1; 1024 #endif 1025 u32 reserved2[7]; 1026 }; 1027 1028 /* 1029 * 32 bytes used for general purposes 1030 */ 1031 union fcoe_general_task_ctx { 1032 union fcoe_cmd_flow_info cmd_info; 1033 struct fcoe_read_flow_info read_info; 1034 struct fcoe_write_flow_info write_info; 1035 union fcoe_rsp_flow_info rsp_info; 1036 struct fcoe_cleanup_flow_info cleanup_info; 1037 u32 comp_info[8]; 1038 }; 1039 1040 struct fcoe_s_stat_ctx { 1041 u8 flags; 1042 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) 1043 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 1044 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) 1045 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 1046 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) 1047 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 1048 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) 1049 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 1050 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) 1051 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4 1052 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) 1053 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 1054 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) 1055 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 1056 }; 1057 1058 /* 1059 * Common section. Both TX and RX processing might write and read from it in different flows 1060 */ 1061 struct fcoe_task_ctx_entry_tx_rx_cmn { 1062 u32 data_2_trns; 1063 union fcoe_general_task_ctx general; 1064 #if defined(__BIG_ENDIAN) 1065 u16 tx_low_seq_cnt; 1066 struct fcoe_s_stat_ctx tx_s_stat; 1067 u8 tx_seq_id; 1068 #elif defined(__LITTLE_ENDIAN) 1069 u8 tx_seq_id; 1070 struct fcoe_s_stat_ctx tx_s_stat; 1071 u16 tx_low_seq_cnt; 1072 #endif 1073 u32 common_flags; 1074 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0) 1075 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0 1076 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24) 1077 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24 1078 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25) 1079 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25 1080 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26) 1081 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26 1082 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27) 1083 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27 1084 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28) 1085 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28 1086 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29) 1087 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29 1088 }; 1089 1090 struct fcoe_task_ctx_entry_rxwr_txrd { 1091 #if defined(__BIG_ENDIAN) 1092 u16 rx_id; 1093 u16 rx_flags; 1094 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0) 1095 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0 1096 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4) 1097 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4 1098 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7) 1099 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7 1100 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8) 1101 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8 1102 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9) 1103 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9 1104 #elif defined(__LITTLE_ENDIAN) 1105 u16 rx_flags; 1106 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0) 1107 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0 1108 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4) 1109 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4 1110 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7) 1111 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7 1112 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8) 1113 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8 1114 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9) 1115 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9 1116 u16 rx_id; 1117 #endif 1118 }; 1119 1120 struct fcoe_seq_ctx { 1121 #if defined(__BIG_ENDIAN) 1122 u16 low_seq_cnt; 1123 struct fcoe_s_stat_ctx s_stat; 1124 u8 seq_id; 1125 #elif defined(__LITTLE_ENDIAN) 1126 u8 seq_id; 1127 struct fcoe_s_stat_ctx s_stat; 1128 u16 low_seq_cnt; 1129 #endif 1130 #if defined(__BIG_ENDIAN) 1131 u16 err_seq_cnt; 1132 u16 high_seq_cnt; 1133 #elif defined(__LITTLE_ENDIAN) 1134 u16 high_seq_cnt; 1135 u16 err_seq_cnt; 1136 #endif 1137 u32 low_exp_ro; 1138 u32 high_exp_ro; 1139 }; 1140 1141 struct fcoe_single_sge_ctx { 1142 struct regpair cur_buf_addr; 1143 #if defined(__BIG_ENDIAN) 1144 u16 reserved0; 1145 u16 cur_buf_rem; 1146 #elif defined(__LITTLE_ENDIAN) 1147 u16 cur_buf_rem; 1148 u16 reserved0; 1149 #endif 1150 }; 1151 1152 struct fcoe_mul_sges_ctx { 1153 struct regpair cur_sge_addr; 1154 #if defined(__BIG_ENDIAN) 1155 u8 sgl_size; 1156 u8 cur_sge_idx; 1157 u16 cur_sge_off; 1158 #elif defined(__LITTLE_ENDIAN) 1159 u16 cur_sge_off; 1160 u8 cur_sge_idx; 1161 u8 sgl_size; 1162 #endif 1163 }; 1164 1165 union fcoe_sgl_ctx { 1166 struct fcoe_single_sge_ctx single_sge; 1167 struct fcoe_mul_sges_ctx mul_sges; 1168 }; 1169 1170 struct fcoe_task_ctx_entry_rx_only { 1171 struct fcoe_seq_ctx seq_ctx; 1172 struct fcoe_seq_ctx ooo_seq_ctx; 1173 u32 rsrv3; 1174 union fcoe_sgl_ctx sgl_ctx; 1175 }; 1176 1177 struct ustorm_fcoe_task_ctx_entry_rd { 1178 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd; 1179 struct fcoe_task_ctx_entry_tx_rx_cmn cmn; 1180 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd; 1181 struct fcoe_task_ctx_entry_rx_only rx_wr; 1182 u32 reserved; 1183 }; 1184 1185 /* 1186 * Ustorm FCoE Storm Context 1187 */ 1188 struct ustorm_fcoe_st_context { 1189 struct ustorm_fcoe_params fcoe_params; 1190 struct regpair task_addr; 1191 struct regpair cq_base_addr; 1192 struct regpair rq_pbl_base; 1193 struct regpair rq_cur_page_addr; 1194 struct regpair confq_pbl_base_addr; 1195 struct regpair conn_db_base; 1196 struct regpair xfrq_base_addr; 1197 struct regpair lcq_base_addr; 1198 #if defined(__BIG_ENDIAN) 1199 union fcoe_idx16_field_union rq_cons; 1200 union fcoe_idx16_field_union rq_prod; 1201 #elif defined(__LITTLE_ENDIAN) 1202 union fcoe_idx16_field_union rq_prod; 1203 union fcoe_idx16_field_union rq_cons; 1204 #endif 1205 #if defined(__BIG_ENDIAN) 1206 u16 xfrq_prod; 1207 u16 cq_cons; 1208 #elif defined(__LITTLE_ENDIAN) 1209 u16 cq_cons; 1210 u16 xfrq_prod; 1211 #endif 1212 #if defined(__BIG_ENDIAN) 1213 u16 lcq_cons; 1214 u16 hc_cram_address; 1215 #elif defined(__LITTLE_ENDIAN) 1216 u16 hc_cram_address; 1217 u16 lcq_cons; 1218 #endif 1219 #if defined(__BIG_ENDIAN) 1220 u16 sq_xfrq_lcq_confq_size; 1221 u16 confq_prod; 1222 #elif defined(__LITTLE_ENDIAN) 1223 u16 confq_prod; 1224 u16 sq_xfrq_lcq_confq_size; 1225 #endif 1226 #if defined(__BIG_ENDIAN) 1227 u8 hc_csdm_agg_int; 1228 u8 flags; 1229 #define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0) 1230 #define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0 1231 #define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1) 1232 #define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1 1233 #define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2) 1234 #define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2 1235 #define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3) 1236 #define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3 1237 u8 available_rqes; 1238 u8 sp_q_flush_cnt; 1239 #elif defined(__LITTLE_ENDIAN) 1240 u8 sp_q_flush_cnt; 1241 u8 available_rqes; 1242 u8 flags; 1243 #define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0) 1244 #define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0 1245 #define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1) 1246 #define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1 1247 #define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2) 1248 #define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2 1249 #define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3) 1250 #define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3 1251 u8 hc_csdm_agg_int; 1252 #endif 1253 struct ustorm_fcoe_data_place data_place; 1254 struct ustorm_fcoe_task_ctx_entry_rd tce; 1255 }; 1256 1257 /* 1258 * The FCoE non-aggregative context of Tstorm 1259 */ 1260 struct tstorm_fcoe_st_context { 1261 struct regpair reserved0; 1262 struct regpair reserved1; 1263 }; 1264 1265 /* 1266 * The fcoe aggregative context section of Xstorm 1267 */ 1268 struct xstorm_fcoe_extra_ag_context_section { 1269 #if defined(__BIG_ENDIAN) 1270 u8 tcp_agg_vars1; 1271 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) 1272 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 1273 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1274 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1275 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4) 1276 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4 1277 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) 1278 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 1279 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) 1280 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 1281 u8 __reserved_da_cnt; 1282 u16 __mtu; 1283 #elif defined(__LITTLE_ENDIAN) 1284 u16 __mtu; 1285 u8 __reserved_da_cnt; 1286 u8 tcp_agg_vars1; 1287 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) 1288 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 1289 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1290 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1291 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4) 1292 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4 1293 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) 1294 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 1295 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) 1296 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 1297 #endif 1298 u32 __task_addr_lo; 1299 u32 __task_addr_hi; 1300 u32 __reserved55; 1301 u32 __tx_prods; 1302 #if defined(__BIG_ENDIAN) 1303 u8 __agg_val8_th; 1304 u8 __agg_val8; 1305 u16 tcp_agg_vars2; 1306 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) 1307 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 1308 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) 1309 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 1310 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) 1311 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 1312 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1313 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1314 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1315 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1316 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) 1317 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 1318 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) 1319 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 1320 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7) 1321 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7 1322 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) 1323 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 1324 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1325 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1326 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1327 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1328 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1329 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1330 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14) 1331 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14 1332 #elif defined(__LITTLE_ENDIAN) 1333 u16 tcp_agg_vars2; 1334 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) 1335 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 1336 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) 1337 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 1338 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) 1339 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 1340 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1341 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1342 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1343 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1344 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) 1345 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 1346 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) 1347 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 1348 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7) 1349 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7 1350 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) 1351 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 1352 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1353 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1354 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1355 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1356 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1357 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1358 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14) 1359 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14 1360 u8 __agg_val8; 1361 u8 __agg_val8_th; 1362 #endif 1363 u32 __sq_base_addr_lo; 1364 u32 __sq_base_addr_hi; 1365 u32 __xfrq_base_addr_lo; 1366 u32 __xfrq_base_addr_hi; 1367 #if defined(__BIG_ENDIAN) 1368 u16 __xfrq_cons; 1369 u16 __xfrq_prod; 1370 #elif defined(__LITTLE_ENDIAN) 1371 u16 __xfrq_prod; 1372 u16 __xfrq_cons; 1373 #endif 1374 #if defined(__BIG_ENDIAN) 1375 u8 __tcp_agg_vars5; 1376 u8 __tcp_agg_vars4; 1377 u8 __tcp_agg_vars3; 1378 u8 __reserved_force_pure_ack_cnt; 1379 #elif defined(__LITTLE_ENDIAN) 1380 u8 __reserved_force_pure_ack_cnt; 1381 u8 __tcp_agg_vars3; 1382 u8 __tcp_agg_vars4; 1383 u8 __tcp_agg_vars5; 1384 #endif 1385 u32 __tcp_agg_vars6; 1386 #if defined(__BIG_ENDIAN) 1387 u16 __agg_misc6; 1388 u16 __tcp_agg_vars7; 1389 #elif defined(__LITTLE_ENDIAN) 1390 u16 __tcp_agg_vars7; 1391 u16 __agg_misc6; 1392 #endif 1393 u32 __agg_val10; 1394 u32 __agg_val10_th; 1395 #if defined(__BIG_ENDIAN) 1396 u16 __reserved3; 1397 u8 __reserved2; 1398 u8 __da_only_cnt; 1399 #elif defined(__LITTLE_ENDIAN) 1400 u8 __da_only_cnt; 1401 u8 __reserved2; 1402 u16 __reserved3; 1403 #endif 1404 }; 1405 1406 /* 1407 * The fcoe aggregative context of Xstorm 1408 */ 1409 struct xstorm_fcoe_ag_context { 1410 #if defined(__BIG_ENDIAN) 1411 u16 agg_val1; 1412 u8 agg_vars1; 1413 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1414 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1415 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1416 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1417 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) 1418 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 1419 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) 1420 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 1421 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1422 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1423 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) 1424 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 1425 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1426 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1427 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) 1428 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 1429 u8 __state; 1430 #elif defined(__LITTLE_ENDIAN) 1431 u8 __state; 1432 u8 agg_vars1; 1433 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1434 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1435 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1436 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1437 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) 1438 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 1439 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) 1440 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 1441 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1442 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1443 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) 1444 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 1445 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1446 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1447 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) 1448 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 1449 u16 agg_val1; 1450 #endif 1451 #if defined(__BIG_ENDIAN) 1452 u8 cdu_reserved; 1453 u8 __agg_vars4; 1454 u8 agg_vars3; 1455 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1456 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1457 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) 1458 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 1459 u8 agg_vars2; 1460 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) 1461 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 1462 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1463 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1464 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1465 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1466 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1467 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1468 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1469 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1470 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1471 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1472 #elif defined(__LITTLE_ENDIAN) 1473 u8 agg_vars2; 1474 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) 1475 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 1476 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1477 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1478 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1479 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1480 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1481 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1482 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1483 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1484 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1485 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1486 u8 agg_vars3; 1487 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1488 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1489 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) 1490 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 1491 u8 __agg_vars4; 1492 u8 cdu_reserved; 1493 #endif 1494 u32 more_to_send; 1495 #if defined(__BIG_ENDIAN) 1496 u16 agg_vars5; 1497 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 1498 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 1499 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 1500 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 1501 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 1502 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 1503 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) 1504 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 1505 u16 sq_cons; 1506 #elif defined(__LITTLE_ENDIAN) 1507 u16 sq_cons; 1508 u16 agg_vars5; 1509 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 1510 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 1511 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 1512 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 1513 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 1514 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 1515 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) 1516 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 1517 #endif 1518 struct xstorm_fcoe_extra_ag_context_section __extra_section; 1519 #if defined(__BIG_ENDIAN) 1520 u16 agg_vars7; 1521 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 1522 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 1523 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) 1524 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 1525 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) 1526 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 1527 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 1528 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 1529 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) 1530 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 1531 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) 1532 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 1533 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 1534 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 1535 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) 1536 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 1537 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) 1538 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 1539 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) 1540 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 1541 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) 1542 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 1543 u8 agg_val3_th; 1544 u8 agg_vars6; 1545 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 1546 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 1547 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) 1548 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 1549 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) 1550 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 1551 #elif defined(__LITTLE_ENDIAN) 1552 u8 agg_vars6; 1553 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 1554 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 1555 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) 1556 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 1557 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) 1558 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 1559 u8 agg_val3_th; 1560 u16 agg_vars7; 1561 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 1562 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 1563 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) 1564 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 1565 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) 1566 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 1567 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 1568 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 1569 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) 1570 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 1571 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) 1572 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 1573 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 1574 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 1575 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) 1576 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 1577 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) 1578 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 1579 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) 1580 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 1581 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) 1582 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 1583 #endif 1584 #if defined(__BIG_ENDIAN) 1585 u16 __agg_val11_th; 1586 u16 __agg_val11; 1587 #elif defined(__LITTLE_ENDIAN) 1588 u16 __agg_val11; 1589 u16 __agg_val11_th; 1590 #endif 1591 #if defined(__BIG_ENDIAN) 1592 u8 __reserved1; 1593 u8 __agg_val6_th; 1594 u16 __confq_tx_prod; 1595 #elif defined(__LITTLE_ENDIAN) 1596 u16 __confq_tx_prod; 1597 u8 __agg_val6_th; 1598 u8 __reserved1; 1599 #endif 1600 #if defined(__BIG_ENDIAN) 1601 u16 confq_cons; 1602 u16 confq_prod; 1603 #elif defined(__LITTLE_ENDIAN) 1604 u16 confq_prod; 1605 u16 confq_cons; 1606 #endif 1607 u32 agg_vars8; 1608 #define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX (0xFFFFFF<<0) 1609 #define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX_SHIFT 0 1610 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 1611 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24 1612 #if defined(__BIG_ENDIAN) 1613 u16 ox_id; 1614 u16 sq_prod; 1615 #elif defined(__LITTLE_ENDIAN) 1616 u16 sq_prod; 1617 u16 ox_id; 1618 #endif 1619 #if defined(__BIG_ENDIAN) 1620 u8 agg_val3; 1621 u8 agg_val6; 1622 u8 agg_val5_th; 1623 u8 agg_val5; 1624 #elif defined(__LITTLE_ENDIAN) 1625 u8 agg_val5; 1626 u8 agg_val5_th; 1627 u8 agg_val6; 1628 u8 agg_val3; 1629 #endif 1630 #if defined(__BIG_ENDIAN) 1631 u16 __pbf_tx_seq_ack; 1632 u16 agg_limit1; 1633 #elif defined(__LITTLE_ENDIAN) 1634 u16 agg_limit1; 1635 u16 __pbf_tx_seq_ack; 1636 #endif 1637 u32 completion_seq; 1638 u32 confq_pbl_base_lo; 1639 u32 confq_pbl_base_hi; 1640 }; 1641 1642 /* 1643 * The fcoe extra aggregative context section of Tstorm 1644 */ 1645 struct tstorm_fcoe_extra_ag_context_section { 1646 u32 __agg_val1; 1647 #if defined(__BIG_ENDIAN) 1648 u8 __tcp_agg_vars2; 1649 u8 __agg_val3; 1650 u16 __agg_val2; 1651 #elif defined(__LITTLE_ENDIAN) 1652 u16 __agg_val2; 1653 u8 __agg_val3; 1654 u8 __tcp_agg_vars2; 1655 #endif 1656 #if defined(__BIG_ENDIAN) 1657 u16 __agg_val5; 1658 u8 __agg_val6; 1659 u8 __tcp_agg_vars3; 1660 #elif defined(__LITTLE_ENDIAN) 1661 u8 __tcp_agg_vars3; 1662 u8 __agg_val6; 1663 u16 __agg_val5; 1664 #endif 1665 u32 __lcq_prod; 1666 u32 rtt_seq; 1667 u32 rtt_time; 1668 u32 __reserved66; 1669 u32 wnd_right_edge; 1670 u32 tcp_agg_vars1; 1671 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 1672 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 1673 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) 1674 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 1675 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 1676 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 1677 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 1678 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 1679 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) 1680 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 1681 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) 1682 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 1683 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) 1684 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 1685 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) 1686 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9 1687 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) 1688 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 1689 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) 1690 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 1691 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) 1692 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 1693 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) 1694 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 1695 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) 1696 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 1697 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) 1698 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 1699 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) 1700 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 1701 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) 1702 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 1703 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) 1704 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 1705 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) 1706 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 1707 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) 1708 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 1709 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) 1710 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 1711 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) 1712 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 1713 u32 snd_max; 1714 u32 __lcq_cons; 1715 u32 __reserved2; 1716 }; 1717 1718 /* 1719 * The fcoe aggregative context of Tstorm 1720 */ 1721 struct tstorm_fcoe_ag_context { 1722 #if defined(__BIG_ENDIAN) 1723 u16 ulp_credit; 1724 u8 agg_vars1; 1725 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1726 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1727 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1728 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1729 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1730 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1731 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1732 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1733 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) 1734 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 1735 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) 1736 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 1737 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) 1738 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 1739 u8 state; 1740 #elif defined(__LITTLE_ENDIAN) 1741 u8 state; 1742 u8 agg_vars1; 1743 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1744 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1745 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1746 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1747 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1748 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1749 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1750 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1751 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) 1752 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 1753 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) 1754 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 1755 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) 1756 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 1757 u16 ulp_credit; 1758 #endif 1759 #if defined(__BIG_ENDIAN) 1760 u16 __agg_val4; 1761 u16 agg_vars2; 1762 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) 1763 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 1764 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) 1765 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 1766 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) 1767 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 1768 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) 1769 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 1770 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) 1771 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 1772 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) 1773 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 1774 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) 1775 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 1776 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) 1777 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 1778 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) 1779 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 1780 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) 1781 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 1782 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 1783 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 1784 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 1785 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 1786 #elif defined(__LITTLE_ENDIAN) 1787 u16 agg_vars2; 1788 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) 1789 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 1790 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) 1791 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 1792 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) 1793 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 1794 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) 1795 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 1796 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) 1797 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 1798 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) 1799 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 1800 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) 1801 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 1802 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) 1803 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 1804 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) 1805 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 1806 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) 1807 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 1808 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 1809 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 1810 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 1811 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 1812 u16 __agg_val4; 1813 #endif 1814 struct tstorm_fcoe_extra_ag_context_section __extra_section; 1815 }; 1816 1817 /* 1818 * The fcoe aggregative context of Ustorm 1819 */ 1820 struct ustorm_fcoe_ag_context { 1821 #if defined(__BIG_ENDIAN) 1822 u8 __aux_counter_flags; 1823 u8 agg_vars2; 1824 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) 1825 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 1826 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) 1827 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 1828 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1829 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1830 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1831 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1832 u8 agg_vars1; 1833 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1834 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1835 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1836 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1837 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1838 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1839 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1840 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1841 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) 1842 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 1843 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1844 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1845 u8 state; 1846 #elif defined(__LITTLE_ENDIAN) 1847 u8 state; 1848 u8 agg_vars1; 1849 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1850 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1851 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1852 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1853 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1854 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1855 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1856 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1857 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) 1858 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 1859 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1860 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1861 u8 agg_vars2; 1862 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) 1863 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 1864 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) 1865 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 1866 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1867 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1868 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1869 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1870 u8 __aux_counter_flags; 1871 #endif 1872 #if defined(__BIG_ENDIAN) 1873 u8 cdu_usage; 1874 u8 agg_misc2; 1875 u16 pbf_tx_seq_ack; 1876 #elif defined(__LITTLE_ENDIAN) 1877 u16 pbf_tx_seq_ack; 1878 u8 agg_misc2; 1879 u8 cdu_usage; 1880 #endif 1881 u32 agg_misc4; 1882 #if defined(__BIG_ENDIAN) 1883 u8 agg_val3_th; 1884 u8 agg_val3; 1885 u16 agg_misc3; 1886 #elif defined(__LITTLE_ENDIAN) 1887 u16 agg_misc3; 1888 u8 agg_val3; 1889 u8 agg_val3_th; 1890 #endif 1891 u32 expired_task_id; 1892 u32 agg_misc4_th; 1893 #if defined(__BIG_ENDIAN) 1894 u16 cq_prod; 1895 u16 cq_cons; 1896 #elif defined(__LITTLE_ENDIAN) 1897 u16 cq_cons; 1898 u16 cq_prod; 1899 #endif 1900 #if defined(__BIG_ENDIAN) 1901 u16 __reserved2; 1902 u8 decision_rules; 1903 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) 1904 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 1905 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1906 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1907 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) 1908 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 1909 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) 1910 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 1911 u8 decision_rule_enable_bits; 1912 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) 1913 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 1914 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1915 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1916 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) 1917 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 1918 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1919 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1920 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) 1921 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 1922 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) 1923 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 1924 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1925 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1926 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1927 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1928 #elif defined(__LITTLE_ENDIAN) 1929 u8 decision_rule_enable_bits; 1930 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) 1931 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 1932 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1933 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1934 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) 1935 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 1936 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1937 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1938 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) 1939 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 1940 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) 1941 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 1942 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1943 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1944 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1945 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1946 u8 decision_rules; 1947 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) 1948 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 1949 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1950 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1951 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) 1952 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 1953 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) 1954 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 1955 u16 __reserved2; 1956 #endif 1957 }; 1958 1959 /* 1960 * Ethernet context section 1961 */ 1962 struct xstorm_fcoe_eth_context_section { 1963 #if defined(__BIG_ENDIAN) 1964 u8 remote_addr_4; 1965 u8 remote_addr_5; 1966 u8 local_addr_0; 1967 u8 local_addr_1; 1968 #elif defined(__LITTLE_ENDIAN) 1969 u8 local_addr_1; 1970 u8 local_addr_0; 1971 u8 remote_addr_5; 1972 u8 remote_addr_4; 1973 #endif 1974 #if defined(__BIG_ENDIAN) 1975 u8 remote_addr_0; 1976 u8 remote_addr_1; 1977 u8 remote_addr_2; 1978 u8 remote_addr_3; 1979 #elif defined(__LITTLE_ENDIAN) 1980 u8 remote_addr_3; 1981 u8 remote_addr_2; 1982 u8 remote_addr_1; 1983 u8 remote_addr_0; 1984 #endif 1985 #if defined(__BIG_ENDIAN) 1986 u16 reserved_vlan_type; 1987 u16 params; 1988 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 1989 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 1990 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) 1991 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 1992 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 1993 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 1994 #elif defined(__LITTLE_ENDIAN) 1995 u16 params; 1996 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 1997 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 1998 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) 1999 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 2000 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 2001 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 2002 u16 reserved_vlan_type; 2003 #endif 2004 #if defined(__BIG_ENDIAN) 2005 u8 local_addr_2; 2006 u8 local_addr_3; 2007 u8 local_addr_4; 2008 u8 local_addr_5; 2009 #elif defined(__LITTLE_ENDIAN) 2010 u8 local_addr_5; 2011 u8 local_addr_4; 2012 u8 local_addr_3; 2013 u8 local_addr_2; 2014 #endif 2015 }; 2016 2017 /* 2018 * Flags used in FCoE context section - 1 byte 2019 */ 2020 struct xstorm_fcoe_context_flags { 2021 u8 flags; 2022 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) 2023 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0 2024 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) 2025 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2 2026 #define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED (0x1<<3) 2027 #define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED_SHIFT 3 2028 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) 2029 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4 2030 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) 2031 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5 2032 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) 2033 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6 2034 #define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED (0x1<<7) 2035 #define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED_SHIFT 7 2036 }; 2037 2038 /* 2039 * FCoE SQ element 2040 */ 2041 struct fcoe_sqe { 2042 u16 wqe; 2043 #define FCOE_SQE_TASK_ID (0x7FFF<<0) 2044 #define FCOE_SQE_TASK_ID_SHIFT 0 2045 #define FCOE_SQE_TOGGLE_BIT (0x1<<15) 2046 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15 2047 }; 2048 2049 /* 2050 * FCoE XFRQ element 2051 */ 2052 struct fcoe_xfrqe { 2053 u16 wqe; 2054 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) 2055 #define FCOE_XFRQE_TASK_ID_SHIFT 0 2056 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) 2057 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 2058 }; 2059 2060 /* 2061 * FCoE SQ\XFRQ element 2062 */ 2063 struct fcoe_cached_wqe { 2064 #if defined(__BIG_ENDIAN) 2065 struct fcoe_xfrqe xfrqe; 2066 struct fcoe_sqe sqe; 2067 #elif defined(__LITTLE_ENDIAN) 2068 struct fcoe_sqe sqe; 2069 struct fcoe_xfrqe xfrqe; 2070 #endif 2071 }; 2072 2073 struct fcoe_task_ctx_entry_tx_only { 2074 union fcoe_sgl_ctx sgl_ctx; 2075 }; 2076 2077 struct xstorm_fcoe_task_ctx_entry_rd { 2078 struct fcoe_task_ctx_entry_tx_only tx_wr; 2079 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd; 2080 struct fcoe_task_ctx_entry_tx_rx_cmn cmn; 2081 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd; 2082 }; 2083 2084 /* 2085 * Cached SGEs 2086 */ 2087 struct common_fcoe_sgl { 2088 struct fcoe_bd_ctx sge[2]; 2089 }; 2090 2091 /* 2092 * FCP_DATA parameters required for transmission 2093 */ 2094 struct xstorm_fcoe_fcp_data { 2095 u32 io_rem; 2096 #if defined(__BIG_ENDIAN) 2097 u16 cached_sge_off; 2098 u8 cached_num_sges; 2099 u8 cached_sge_idx; 2100 #elif defined(__LITTLE_ENDIAN) 2101 u8 cached_sge_idx; 2102 u8 cached_num_sges; 2103 u16 cached_sge_off; 2104 #endif 2105 struct common_fcoe_sgl cached_sgl; 2106 }; 2107 2108 /* 2109 * FCoE context section 2110 */ 2111 struct xstorm_fcoe_context_section { 2112 #if defined(__BIG_ENDIAN) 2113 u8 vlan_flag; 2114 u8 s_id[3]; 2115 #elif defined(__LITTLE_ENDIAN) 2116 u8 s_id[3]; 2117 u8 vlan_flag; 2118 #endif 2119 #if defined(__BIG_ENDIAN) 2120 u8 func_id; 2121 u8 d_id[3]; 2122 #elif defined(__LITTLE_ENDIAN) 2123 u8 d_id[3]; 2124 u8 func_id; 2125 #endif 2126 #if defined(__BIG_ENDIAN) 2127 u16 sq_xfrq_lcq_confq_size; 2128 u16 tx_max_fc_pay_len; 2129 #elif defined(__LITTLE_ENDIAN) 2130 u16 tx_max_fc_pay_len; 2131 u16 sq_xfrq_lcq_confq_size; 2132 #endif 2133 u32 lcq_prod; 2134 #if defined(__BIG_ENDIAN) 2135 u8 port_id; 2136 u8 tx_max_conc_seqs_c3; 2137 u8 seq_id; 2138 struct xstorm_fcoe_context_flags tx_flags; 2139 #elif defined(__LITTLE_ENDIAN) 2140 struct xstorm_fcoe_context_flags tx_flags; 2141 u8 seq_id; 2142 u8 tx_max_conc_seqs_c3; 2143 u8 port_id; 2144 #endif 2145 #if defined(__BIG_ENDIAN) 2146 u16 verify_tx_seq; 2147 u8 func_mode; 2148 u8 vnic_id; 2149 #elif defined(__LITTLE_ENDIAN) 2150 u8 vnic_id; 2151 u8 func_mode; 2152 u16 verify_tx_seq; 2153 #endif 2154 struct regpair confq_curr_page_addr; 2155 struct fcoe_cached_wqe cached_wqe[8]; 2156 struct regpair lcq_base_addr; 2157 struct xstorm_fcoe_task_ctx_entry_rd tce; 2158 struct xstorm_fcoe_fcp_data fcp_data; 2159 #if defined(__BIG_ENDIAN) 2160 u16 fcoe_tx_stat_params_ram_addr; 2161 u16 cmng_port_ram_addr; 2162 #elif defined(__LITTLE_ENDIAN) 2163 u16 cmng_port_ram_addr; 2164 u16 fcoe_tx_stat_params_ram_addr; 2165 #endif 2166 #if defined(__BIG_ENDIAN) 2167 u8 fcp_cmd_pb_cmd_size; 2168 u8 eth_hdr_size; 2169 u16 pbf_addr; 2170 #elif defined(__LITTLE_ENDIAN) 2171 u16 pbf_addr; 2172 u8 eth_hdr_size; 2173 u8 fcp_cmd_pb_cmd_size; 2174 #endif 2175 #if defined(__BIG_ENDIAN) 2176 u8 reserved2[2]; 2177 u8 cos; 2178 u8 dcb_version; 2179 #elif defined(__LITTLE_ENDIAN) 2180 u8 dcb_version; 2181 u8 cos; 2182 u8 reserved2[2]; 2183 #endif 2184 u32 reserved3; 2185 struct regpair reserved4[2]; 2186 }; 2187 2188 /* 2189 * Xstorm FCoE Storm Context 2190 */ 2191 struct xstorm_fcoe_st_context { 2192 struct xstorm_fcoe_eth_context_section eth; 2193 struct xstorm_fcoe_context_section fcoe; 2194 }; 2195 2196 /* 2197 * Fcoe connection context 2198 */ 2199 struct fcoe_context { 2200 struct ustorm_fcoe_st_context ustorm_st_context; 2201 struct tstorm_fcoe_st_context tstorm_st_context; 2202 struct xstorm_fcoe_ag_context xstorm_ag_context; 2203 struct tstorm_fcoe_ag_context tstorm_ag_context; 2204 struct ustorm_fcoe_ag_context ustorm_ag_context; 2205 struct timers_block_context timers_context; 2206 struct xstorm_fcoe_st_context xstorm_st_context; 2207 }; 2208 2209 /* 2210 * iSCSI context region, used only in iSCSI 2211 */ 2212 struct ustorm_iscsi_rq_db { 2213 struct regpair pbl_base; 2214 struct regpair curr_pbe; 2215 }; 2216 2217 /* 2218 * iSCSI context region, used only in iSCSI 2219 */ 2220 struct ustorm_iscsi_r2tq_db { 2221 struct regpair pbl_base; 2222 struct regpair curr_pbe; 2223 }; 2224 2225 /* 2226 * iSCSI context region, used only in iSCSI 2227 */ 2228 struct ustorm_iscsi_cq_db { 2229 #if defined(__BIG_ENDIAN) 2230 u16 cq_sn; 2231 u16 prod; 2232 #elif defined(__LITTLE_ENDIAN) 2233 u16 prod; 2234 u16 cq_sn; 2235 #endif 2236 struct regpair curr_pbe; 2237 }; 2238 2239 /* 2240 * iSCSI context region, used only in iSCSI 2241 */ 2242 struct rings_db { 2243 struct ustorm_iscsi_rq_db rq; 2244 struct ustorm_iscsi_r2tq_db r2tq; 2245 struct ustorm_iscsi_cq_db cq[8]; 2246 #if defined(__BIG_ENDIAN) 2247 u16 rq_prod; 2248 u16 r2tq_prod; 2249 #elif defined(__LITTLE_ENDIAN) 2250 u16 r2tq_prod; 2251 u16 rq_prod; 2252 #endif 2253 struct regpair cq_pbl_base; 2254 }; 2255 2256 /* 2257 * iSCSI context region, used only in iSCSI 2258 */ 2259 struct ustorm_iscsi_placement_db { 2260 u32 sgl_base_lo; 2261 u32 sgl_base_hi; 2262 u32 local_sge_0_address_hi; 2263 u32 local_sge_0_address_lo; 2264 #if defined(__BIG_ENDIAN) 2265 u16 curr_sge_offset; 2266 u16 local_sge_0_size; 2267 #elif defined(__LITTLE_ENDIAN) 2268 u16 local_sge_0_size; 2269 u16 curr_sge_offset; 2270 #endif 2271 u32 local_sge_1_address_hi; 2272 u32 local_sge_1_address_lo; 2273 #if defined(__BIG_ENDIAN) 2274 u16 reserved6; 2275 u16 local_sge_1_size; 2276 #elif defined(__LITTLE_ENDIAN) 2277 u16 local_sge_1_size; 2278 u16 reserved6; 2279 #endif 2280 #if defined(__BIG_ENDIAN) 2281 u8 sgl_size; 2282 u8 local_sge_index_2b; 2283 u16 reserved7; 2284 #elif defined(__LITTLE_ENDIAN) 2285 u16 reserved7; 2286 u8 local_sge_index_2b; 2287 u8 sgl_size; 2288 #endif 2289 u32 rem_pdu; 2290 u32 place_db_bitfield_1; 2291 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) 2292 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 2293 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) 2294 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 2295 u32 place_db_bitfield_2; 2296 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) 2297 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 2298 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) 2299 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 2300 u32 nal; 2301 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) 2302 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 2303 #define USTORM_ISCSI_PLACEMENT_DB_EXP_PADDING_2B (0x3<<24) 2304 #define USTORM_ISCSI_PLACEMENT_DB_EXP_PADDING_2B_SHIFT 24 2305 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0x7<<26) 2306 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 26 2307 #define USTORM_ISCSI_PLACEMENT_DB_NAL_LEN_3B (0x7<<29) 2308 #define USTORM_ISCSI_PLACEMENT_DB_NAL_LEN_3B_SHIFT 29 2309 }; 2310 2311 /* 2312 * Ustorm iSCSI Storm Context 2313 */ 2314 struct ustorm_iscsi_st_context { 2315 u32 exp_stat_sn; 2316 u32 exp_data_sn; 2317 struct rings_db ring; 2318 struct regpair task_pbl_base; 2319 struct regpair tce_phy_addr; 2320 struct ustorm_iscsi_placement_db place_db; 2321 u32 reserved8; 2322 u32 rem_rcv_len; 2323 #if defined(__BIG_ENDIAN) 2324 u16 hdr_itt; 2325 u16 iscsi_conn_id; 2326 #elif defined(__LITTLE_ENDIAN) 2327 u16 iscsi_conn_id; 2328 u16 hdr_itt; 2329 #endif 2330 u32 nal_bytes; 2331 #if defined(__BIG_ENDIAN) 2332 u8 hdr_second_byte_union; 2333 u8 bitfield_0; 2334 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) 2335 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 2336 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) 2337 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 2338 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) 2339 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 2340 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) 2341 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 2342 u8 task_pdu_cache_index; 2343 u8 task_pbe_cache_index; 2344 #elif defined(__LITTLE_ENDIAN) 2345 u8 task_pbe_cache_index; 2346 u8 task_pdu_cache_index; 2347 u8 bitfield_0; 2348 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) 2349 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 2350 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) 2351 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 2352 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) 2353 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 2354 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) 2355 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 2356 u8 hdr_second_byte_union; 2357 #endif 2358 #if defined(__BIG_ENDIAN) 2359 u16 reserved3; 2360 u8 reserved2; 2361 u8 acDecrement; 2362 #elif defined(__LITTLE_ENDIAN) 2363 u8 acDecrement; 2364 u8 reserved2; 2365 u16 reserved3; 2366 #endif 2367 u32 task_stat; 2368 #if defined(__BIG_ENDIAN) 2369 u8 hdr_opcode; 2370 u8 num_cqs; 2371 u16 reserved5; 2372 #elif defined(__LITTLE_ENDIAN) 2373 u16 reserved5; 2374 u8 num_cqs; 2375 u8 hdr_opcode; 2376 #endif 2377 u32 negotiated_rx; 2378 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) 2379 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 2380 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) 2381 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 2382 u32 negotiated_rx_and_flags; 2383 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) 2384 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 2385 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) 2386 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 2387 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) 2388 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 2389 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) 2390 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 2391 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) 2392 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 2393 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) 2394 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 2395 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) 2396 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 2397 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) 2398 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 2399 }; 2400 2401 /* 2402 * TCP context region, shared in TOE, RDMA and ISCSI 2403 */ 2404 struct tstorm_tcp_st_context_section { 2405 u32 flags1; 2406 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0) 2407 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0 2408 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) 2409 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 2410 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) 2411 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 2412 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) 2413 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26 2414 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) 2415 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 2416 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) 2417 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 2418 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) 2419 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 2420 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) 2421 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 2422 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) 2423 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31 2424 u32 flags2; 2425 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0) 2426 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0 2427 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) 2428 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 2429 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) 2430 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 2431 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) 2432 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 2433 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) 2434 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 2435 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) 2436 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 2437 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) 2438 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 2439 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) 2440 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30 2441 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) 2442 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31 2443 #if defined(__BIG_ENDIAN) 2444 u16 mss; 2445 u8 tcp_sm_state; 2446 u8 rto_exp; 2447 #elif defined(__LITTLE_ENDIAN) 2448 u8 rto_exp; 2449 u8 tcp_sm_state; 2450 u16 mss; 2451 #endif 2452 u32 rcv_nxt; 2453 u32 timestamp_recent; 2454 u32 timestamp_recent_time; 2455 u32 cwnd; 2456 u32 ss_thresh; 2457 u32 cwnd_accum; 2458 u32 prev_seg_seq; 2459 u32 expected_rel_seq; 2460 u32 recover; 2461 #if defined(__BIG_ENDIAN) 2462 u8 retransmit_count; 2463 u8 ka_max_probe_count; 2464 u8 persist_probe_count; 2465 u8 ka_probe_count; 2466 #elif defined(__LITTLE_ENDIAN) 2467 u8 ka_probe_count; 2468 u8 persist_probe_count; 2469 u8 ka_max_probe_count; 2470 u8 retransmit_count; 2471 #endif 2472 #if defined(__BIG_ENDIAN) 2473 u8 statistics_counter_id; 2474 u8 ooo_support_mode; 2475 u8 snd_wnd_scale; 2476 u8 dup_ack_count; 2477 #elif defined(__LITTLE_ENDIAN) 2478 u8 dup_ack_count; 2479 u8 snd_wnd_scale; 2480 u8 ooo_support_mode; 2481 u8 statistics_counter_id; 2482 #endif 2483 u32 retransmit_start_time; 2484 u32 ka_timeout; 2485 u32 ka_interval; 2486 u32 isle_start_seq; 2487 u32 isle_end_seq; 2488 #if defined(__BIG_ENDIAN) 2489 u16 second_isle_address; 2490 u16 recent_seg_wnd; 2491 #elif defined(__LITTLE_ENDIAN) 2492 u16 recent_seg_wnd; 2493 u16 second_isle_address; 2494 #endif 2495 #if defined(__BIG_ENDIAN) 2496 u8 max_isles_ever_happened; 2497 u8 isles_number; 2498 u16 last_isle_address; 2499 #elif defined(__LITTLE_ENDIAN) 2500 u16 last_isle_address; 2501 u8 isles_number; 2502 u8 max_isles_ever_happened; 2503 #endif 2504 u32 max_rt_time; 2505 #if defined(__BIG_ENDIAN) 2506 u16 lsb_mac_address; 2507 u16 vlan_id; 2508 #elif defined(__LITTLE_ENDIAN) 2509 u16 vlan_id; 2510 u16 lsb_mac_address; 2511 #endif 2512 u32 msb_mac_address; 2513 u32 rightmost_received_seq; 2514 }; 2515 2516 /* 2517 * Termination variables 2518 */ 2519 struct iscsi_term_vars { 2520 u8 BitMap; 2521 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) 2522 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 2523 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) 2524 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 2525 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) 2526 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 2527 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) 2528 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 2529 #define ISCSI_TERM_VARS_RSRV (0x1<<7) 2530 #define ISCSI_TERM_VARS_RSRV_SHIFT 7 2531 }; 2532 2533 /* 2534 * iSCSI context region, used only in iSCSI 2535 */ 2536 struct tstorm_iscsi_st_context_section { 2537 #if defined(__BIG_ENDIAN) 2538 u16 rem_tcp_data_len; 2539 u16 brb_offset; 2540 #elif defined(__LITTLE_ENDIAN) 2541 u16 brb_offset; 2542 u16 rem_tcp_data_len; 2543 #endif 2544 u32 b2nh; 2545 #if defined(__BIG_ENDIAN) 2546 u16 rq_cons; 2547 u8 flags; 2548 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) 2549 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 2550 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) 2551 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 2552 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) 2553 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 2554 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) 2555 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 2556 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) 2557 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 2558 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV (0x7<<5) 2559 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV_SHIFT 5 2560 u8 hdr_bytes_2_fetch; 2561 #elif defined(__LITTLE_ENDIAN) 2562 u8 hdr_bytes_2_fetch; 2563 u8 flags; 2564 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) 2565 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 2566 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) 2567 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 2568 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) 2569 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 2570 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) 2571 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 2572 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) 2573 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 2574 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV (0x7<<5) 2575 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV_SHIFT 5 2576 u16 rq_cons; 2577 #endif 2578 struct regpair rq_db_phy_addr; 2579 #if defined(__BIG_ENDIAN) 2580 struct iscsi_term_vars term_vars; 2581 u8 scratchpad_idx; 2582 u16 iscsi_conn_id; 2583 #elif defined(__LITTLE_ENDIAN) 2584 u16 iscsi_conn_id; 2585 u8 scratchpad_idx; 2586 struct iscsi_term_vars term_vars; 2587 #endif 2588 u32 process_nxt; 2589 }; 2590 2591 /* 2592 * The iSCSI non-aggregative context of Tstorm 2593 */ 2594 struct tstorm_iscsi_st_context { 2595 struct tstorm_tcp_st_context_section tcp; 2596 struct tstorm_iscsi_st_context_section iscsi; 2597 }; 2598 2599 /* 2600 * The tcp aggregative context section of Xstorm 2601 */ 2602 struct xstorm_tcp_tcp_ag_context_section { 2603 #if defined(__BIG_ENDIAN) 2604 u8 __tcp_agg_vars1; 2605 u8 __da_cnt; 2606 u16 mss; 2607 #elif defined(__LITTLE_ENDIAN) 2608 u16 mss; 2609 u8 __da_cnt; 2610 u8 __tcp_agg_vars1; 2611 #endif 2612 u32 snd_nxt; 2613 u32 tx_wnd; 2614 u32 snd_una; 2615 u32 local_adv_wnd; 2616 #if defined(__BIG_ENDIAN) 2617 u8 __agg_val8_th; 2618 u8 __agg_val8; 2619 u16 tcp_agg_vars2; 2620 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) 2621 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 2622 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) 2623 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 2624 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) 2625 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 2626 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 2627 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 2628 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 2629 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 2630 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) 2631 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 2632 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) 2633 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 2634 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN (0x1<<7) 2635 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN_SHIFT 7 2636 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) 2637 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 2638 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 2639 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 2640 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 2641 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 2642 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 2643 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 2644 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14) 2645 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14 2646 #elif defined(__LITTLE_ENDIAN) 2647 u16 tcp_agg_vars2; 2648 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) 2649 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 2650 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) 2651 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 2652 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) 2653 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 2654 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 2655 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 2656 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 2657 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 2658 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) 2659 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 2660 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) 2661 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 2662 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN (0x1<<7) 2663 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_CF_EN_SHIFT 7 2664 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) 2665 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 2666 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 2667 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 2668 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 2669 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 2670 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 2671 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 2672 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14) 2673 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14 2674 u8 __agg_val8; 2675 u8 __agg_val8_th; 2676 #endif 2677 u32 ack_to_far_end; 2678 u32 rto_timer; 2679 u32 ka_timer; 2680 u32 ts_to_echo; 2681 #if defined(__BIG_ENDIAN) 2682 u16 __agg_val7_th; 2683 u16 __agg_val7; 2684 #elif defined(__LITTLE_ENDIAN) 2685 u16 __agg_val7; 2686 u16 __agg_val7_th; 2687 #endif 2688 #if defined(__BIG_ENDIAN) 2689 u8 __tcp_agg_vars5; 2690 u8 __tcp_agg_vars4; 2691 u8 __tcp_agg_vars3; 2692 u8 __force_pure_ack_cnt; 2693 #elif defined(__LITTLE_ENDIAN) 2694 u8 __force_pure_ack_cnt; 2695 u8 __tcp_agg_vars3; 2696 u8 __tcp_agg_vars4; 2697 u8 __tcp_agg_vars5; 2698 #endif 2699 u32 tcp_agg_vars6; 2700 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) 2701 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 2702 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_EN (0x1<<1) 2703 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX8_CF_EN_SHIFT 1 2704 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) 2705 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 2706 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) 2707 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 2708 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) 2709 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 2710 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) 2711 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 2712 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) 2713 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 2714 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) 2715 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 2716 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) 2717 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 2718 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) 2719 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 2720 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) 2721 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 2722 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) 2723 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 2724 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) 2725 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 2726 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) 2727 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 2728 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) 2729 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 2730 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) 2731 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 2732 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) 2733 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 2734 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) 2735 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 2736 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) 2737 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 2738 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) 2739 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 2740 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) 2741 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 2742 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) 2743 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 2744 #if defined(__BIG_ENDIAN) 2745 u16 __agg_misc6; 2746 u16 __tcp_agg_vars7; 2747 #elif defined(__LITTLE_ENDIAN) 2748 u16 __tcp_agg_vars7; 2749 u16 __agg_misc6; 2750 #endif 2751 u32 __agg_val10; 2752 u32 __agg_val10_th; 2753 #if defined(__BIG_ENDIAN) 2754 u16 __reserved3; 2755 u8 __reserved2; 2756 u8 __da_only_cnt; 2757 #elif defined(__LITTLE_ENDIAN) 2758 u8 __da_only_cnt; 2759 u8 __reserved2; 2760 u16 __reserved3; 2761 #endif 2762 }; 2763 2764 /* 2765 * The iscsi aggregative context of Xstorm 2766 */ 2767 struct xstorm_iscsi_ag_context { 2768 #if defined(__BIG_ENDIAN) 2769 u16 agg_val1; 2770 u8 agg_vars1; 2771 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 2772 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 2773 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 2774 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 2775 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 2776 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 2777 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 2778 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 2779 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 2780 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 2781 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) 2782 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 2783 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 2784 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 2785 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 2786 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 2787 u8 state; 2788 #elif defined(__LITTLE_ENDIAN) 2789 u8 state; 2790 u8 agg_vars1; 2791 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 2792 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 2793 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 2794 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 2795 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 2796 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 2797 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 2798 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 2799 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 2800 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 2801 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) 2802 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 2803 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 2804 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 2805 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 2806 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 2807 u16 agg_val1; 2808 #endif 2809 #if defined(__BIG_ENDIAN) 2810 u8 cdu_reserved; 2811 u8 __agg_vars4; 2812 u8 agg_vars3; 2813 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2814 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2815 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2816 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2817 u8 agg_vars2; 2818 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) 2819 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 2820 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 2821 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 2822 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) 2823 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2824 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2825 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2826 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2827 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2828 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 2829 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 2830 #elif defined(__LITTLE_ENDIAN) 2831 u8 agg_vars2; 2832 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) 2833 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 2834 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 2835 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 2836 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) 2837 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2838 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2839 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2840 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2841 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2842 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 2843 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 2844 u8 agg_vars3; 2845 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2846 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2847 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2848 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2849 u8 __agg_vars4; 2850 u8 cdu_reserved; 2851 #endif 2852 u32 more_to_send; 2853 #if defined(__BIG_ENDIAN) 2854 u16 agg_vars5; 2855 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2856 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2857 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2858 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2859 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2860 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2861 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2862 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2863 u16 sq_cons; 2864 #elif defined(__LITTLE_ENDIAN) 2865 u16 sq_cons; 2866 u16 agg_vars5; 2867 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2868 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2869 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2870 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2871 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2872 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2873 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2874 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2875 #endif 2876 struct xstorm_tcp_tcp_ag_context_section tcp; 2877 #if defined(__BIG_ENDIAN) 2878 u16 agg_vars7; 2879 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2880 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2881 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2882 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2883 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2884 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2885 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2886 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2887 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) 2888 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 2889 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2890 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2891 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2892 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2893 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2894 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2895 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2896 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2897 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2898 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2899 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2900 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2901 u8 agg_val3_th; 2902 u8 agg_vars6; 2903 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2904 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2905 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2906 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2907 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2908 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2909 #elif defined(__LITTLE_ENDIAN) 2910 u8 agg_vars6; 2911 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2912 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2913 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2914 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2915 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2916 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2917 u8 agg_val3_th; 2918 u16 agg_vars7; 2919 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2920 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2921 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2922 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2923 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2924 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2925 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2926 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2927 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) 2928 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 2929 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2930 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2931 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2932 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2933 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2934 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2935 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2936 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2937 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2938 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2939 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2940 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2941 #endif 2942 #if defined(__BIG_ENDIAN) 2943 u16 __agg_val11_th; 2944 u16 __gen_data; 2945 #elif defined(__LITTLE_ENDIAN) 2946 u16 __gen_data; 2947 u16 __agg_val11_th; 2948 #endif 2949 #if defined(__BIG_ENDIAN) 2950 u8 __reserved1; 2951 u8 __agg_val6_th; 2952 u16 __agg_val9; 2953 #elif defined(__LITTLE_ENDIAN) 2954 u16 __agg_val9; 2955 u8 __agg_val6_th; 2956 u8 __reserved1; 2957 #endif 2958 #if defined(__BIG_ENDIAN) 2959 u16 hq_prod; 2960 u16 hq_cons; 2961 #elif defined(__LITTLE_ENDIAN) 2962 u16 hq_cons; 2963 u16 hq_prod; 2964 #endif 2965 u32 agg_vars8; 2966 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 2967 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0 2968 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 2969 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24 2970 #if defined(__BIG_ENDIAN) 2971 u16 r2tq_prod; 2972 u16 sq_prod; 2973 #elif defined(__LITTLE_ENDIAN) 2974 u16 sq_prod; 2975 u16 r2tq_prod; 2976 #endif 2977 #if defined(__BIG_ENDIAN) 2978 u8 agg_val3; 2979 u8 agg_val6; 2980 u8 agg_val5_th; 2981 u8 agg_val5; 2982 #elif defined(__LITTLE_ENDIAN) 2983 u8 agg_val5; 2984 u8 agg_val5_th; 2985 u8 agg_val6; 2986 u8 agg_val3; 2987 #endif 2988 #if defined(__BIG_ENDIAN) 2989 u16 __agg_misc1; 2990 u16 agg_limit1; 2991 #elif defined(__LITTLE_ENDIAN) 2992 u16 agg_limit1; 2993 u16 __agg_misc1; 2994 #endif 2995 u32 hq_cons_tcp_seq; 2996 u32 exp_stat_sn; 2997 u32 rst_seq_num; 2998 }; 2999 3000 /* 3001 * The tcp aggregative context section of Tstorm 3002 */ 3003 struct tstorm_tcp_tcp_ag_context_section { 3004 u32 __agg_val1; 3005 #if defined(__BIG_ENDIAN) 3006 u8 __tcp_agg_vars2; 3007 u8 __agg_val3; 3008 u16 __agg_val2; 3009 #elif defined(__LITTLE_ENDIAN) 3010 u16 __agg_val2; 3011 u8 __agg_val3; 3012 u8 __tcp_agg_vars2; 3013 #endif 3014 #if defined(__BIG_ENDIAN) 3015 u16 __agg_val5; 3016 u8 __agg_val6; 3017 u8 __tcp_agg_vars3; 3018 #elif defined(__LITTLE_ENDIAN) 3019 u8 __tcp_agg_vars3; 3020 u8 __agg_val6; 3021 u16 __agg_val5; 3022 #endif 3023 u32 snd_nxt; 3024 u32 rtt_seq; 3025 u32 rtt_time; 3026 u32 __reserved66; 3027 u32 wnd_right_edge; 3028 u32 tcp_agg_vars1; 3029 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 3030 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 3031 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) 3032 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 3033 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 3034 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 3035 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 3036 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 3037 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) 3038 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 3039 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) 3040 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 3041 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) 3042 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 3043 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) 3044 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 3045 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) 3046 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 3047 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) 3048 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 3049 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) 3050 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 3051 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) 3052 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 3053 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) 3054 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 3055 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) 3056 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 3057 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) 3058 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 3059 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) 3060 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 3061 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) 3062 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 3063 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) 3064 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 3065 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) 3066 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 3067 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) 3068 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 3069 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) 3070 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 3071 u32 snd_max; 3072 u32 snd_una; 3073 u32 __reserved2; 3074 }; 3075 3076 /* 3077 * The iscsi aggregative context of Tstorm 3078 */ 3079 struct tstorm_iscsi_ag_context { 3080 #if defined(__BIG_ENDIAN) 3081 u16 ulp_credit; 3082 u8 agg_vars1; 3083 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 3084 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 3085 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 3086 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 3087 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 3088 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 3089 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 3090 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 3091 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) 3092 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 3093 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) 3094 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 3095 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) 3096 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 3097 u8 state; 3098 #elif defined(__LITTLE_ENDIAN) 3099 u8 state; 3100 u8 agg_vars1; 3101 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 3102 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 3103 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 3104 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 3105 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 3106 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 3107 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 3108 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 3109 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) 3110 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 3111 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) 3112 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 3113 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) 3114 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 3115 u16 ulp_credit; 3116 #endif 3117 #if defined(__BIG_ENDIAN) 3118 u16 __agg_val4; 3119 u16 agg_vars2; 3120 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) 3121 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 3122 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) 3123 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 3124 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) 3125 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 3126 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) 3127 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 3128 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) 3129 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 3130 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) 3131 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 3132 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) 3133 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 3134 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) 3135 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 3136 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) 3137 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 3138 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) 3139 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 3140 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 3141 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 3142 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 3143 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 3144 #elif defined(__LITTLE_ENDIAN) 3145 u16 agg_vars2; 3146 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) 3147 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 3148 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) 3149 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 3150 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) 3151 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 3152 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) 3153 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 3154 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) 3155 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 3156 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) 3157 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 3158 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) 3159 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 3160 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) 3161 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 3162 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) 3163 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 3164 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) 3165 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 3166 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 3167 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 3168 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 3169 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 3170 u16 __agg_val4; 3171 #endif 3172 struct tstorm_tcp_tcp_ag_context_section tcp; 3173 }; 3174 3175 /* 3176 * The iscsi aggregative context of Ustorm 3177 */ 3178 struct ustorm_iscsi_ag_context { 3179 #if defined(__BIG_ENDIAN) 3180 u8 __aux_counter_flags; 3181 u8 agg_vars2; 3182 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) 3183 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 3184 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) 3185 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 3186 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 3187 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 3188 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 3189 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 3190 u8 agg_vars1; 3191 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 3192 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 3193 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 3194 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 3195 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 3196 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 3197 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 3198 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 3199 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) 3200 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 3201 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) 3202 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 3203 u8 state; 3204 #elif defined(__LITTLE_ENDIAN) 3205 u8 state; 3206 u8 agg_vars1; 3207 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 3208 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 3209 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 3210 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 3211 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 3212 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 3213 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 3214 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 3215 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) 3216 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 3217 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) 3218 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 3219 u8 agg_vars2; 3220 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) 3221 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 3222 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) 3223 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 3224 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 3225 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 3226 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 3227 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 3228 u8 __aux_counter_flags; 3229 #endif 3230 #if defined(__BIG_ENDIAN) 3231 u8 cdu_usage; 3232 u8 agg_misc2; 3233 u16 __cq_local_comp_itt_val; 3234 #elif defined(__LITTLE_ENDIAN) 3235 u16 __cq_local_comp_itt_val; 3236 u8 agg_misc2; 3237 u8 cdu_usage; 3238 #endif 3239 u32 agg_misc4; 3240 #if defined(__BIG_ENDIAN) 3241 u8 agg_val3_th; 3242 u8 agg_val3; 3243 u16 agg_misc3; 3244 #elif defined(__LITTLE_ENDIAN) 3245 u16 agg_misc3; 3246 u8 agg_val3; 3247 u8 agg_val3_th; 3248 #endif 3249 u32 agg_val1; 3250 u32 agg_misc4_th; 3251 #if defined(__BIG_ENDIAN) 3252 u16 agg_val2_th; 3253 u16 agg_val2; 3254 #elif defined(__LITTLE_ENDIAN) 3255 u16 agg_val2; 3256 u16 agg_val2_th; 3257 #endif 3258 #if defined(__BIG_ENDIAN) 3259 u16 __reserved2; 3260 u8 decision_rules; 3261 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) 3262 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 3263 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 3264 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 3265 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) 3266 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 3267 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) 3268 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 3269 u8 decision_rule_enable_bits; 3270 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) 3271 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 3272 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 3273 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 3274 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) 3275 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 3276 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 3277 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 3278 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) 3279 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 3280 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) 3281 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 3282 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 3283 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 3284 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 3285 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 3286 #elif defined(__LITTLE_ENDIAN) 3287 u8 decision_rule_enable_bits; 3288 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) 3289 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 3290 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 3291 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 3292 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) 3293 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 3294 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 3295 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 3296 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) 3297 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 3298 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) 3299 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 3300 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 3301 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 3302 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 3303 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 3304 u8 decision_rules; 3305 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) 3306 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 3307 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 3308 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 3309 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) 3310 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 3311 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) 3312 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 3313 u16 __reserved2; 3314 #endif 3315 }; 3316 3317 /* 3318 * Ethernet context section, shared in TOE, RDMA and ISCSI 3319 */ 3320 struct xstorm_eth_context_section { 3321 #if defined(__BIG_ENDIAN) 3322 u8 remote_addr_4; 3323 u8 remote_addr_5; 3324 u8 local_addr_0; 3325 u8 local_addr_1; 3326 #elif defined(__LITTLE_ENDIAN) 3327 u8 local_addr_1; 3328 u8 local_addr_0; 3329 u8 remote_addr_5; 3330 u8 remote_addr_4; 3331 #endif 3332 #if defined(__BIG_ENDIAN) 3333 u8 remote_addr_0; 3334 u8 remote_addr_1; 3335 u8 remote_addr_2; 3336 u8 remote_addr_3; 3337 #elif defined(__LITTLE_ENDIAN) 3338 u8 remote_addr_3; 3339 u8 remote_addr_2; 3340 u8 remote_addr_1; 3341 u8 remote_addr_0; 3342 #endif 3343 #if defined(__BIG_ENDIAN) 3344 u16 reserved_vlan_type; 3345 u16 params; 3346 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 3347 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 3348 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) 3349 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 3350 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 3351 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 3352 #elif defined(__LITTLE_ENDIAN) 3353 u16 params; 3354 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 3355 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 3356 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) 3357 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 3358 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 3359 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 3360 u16 reserved_vlan_type; 3361 #endif 3362 #if defined(__BIG_ENDIAN) 3363 u8 local_addr_2; 3364 u8 local_addr_3; 3365 u8 local_addr_4; 3366 u8 local_addr_5; 3367 #elif defined(__LITTLE_ENDIAN) 3368 u8 local_addr_5; 3369 u8 local_addr_4; 3370 u8 local_addr_3; 3371 u8 local_addr_2; 3372 #endif 3373 }; 3374 3375 /* 3376 * IpV4 context section, shared in TOE, RDMA and ISCSI 3377 */ 3378 struct xstorm_ip_v4_context_section { 3379 #if defined(__BIG_ENDIAN) 3380 u16 __pbf_hdr_cmd_rsvd_id; 3381 u16 __pbf_hdr_cmd_rsvd_flags_offset; 3382 #elif defined(__LITTLE_ENDIAN) 3383 u16 __pbf_hdr_cmd_rsvd_flags_offset; 3384 u16 __pbf_hdr_cmd_rsvd_id; 3385 #endif 3386 #if defined(__BIG_ENDIAN) 3387 u8 __pbf_hdr_cmd_rsvd_ver_ihl; 3388 u8 tos; 3389 u16 __pbf_hdr_cmd_rsvd_length; 3390 #elif defined(__LITTLE_ENDIAN) 3391 u16 __pbf_hdr_cmd_rsvd_length; 3392 u8 tos; 3393 u8 __pbf_hdr_cmd_rsvd_ver_ihl; 3394 #endif 3395 u32 ip_local_addr; 3396 #if defined(__BIG_ENDIAN) 3397 u8 ttl; 3398 u8 __pbf_hdr_cmd_rsvd_protocol; 3399 u16 __pbf_hdr_cmd_rsvd_csum; 3400 #elif defined(__LITTLE_ENDIAN) 3401 u16 __pbf_hdr_cmd_rsvd_csum; 3402 u8 __pbf_hdr_cmd_rsvd_protocol; 3403 u8 ttl; 3404 #endif 3405 u32 __pbf_hdr_cmd_rsvd_1; 3406 u32 ip_remote_addr; 3407 }; 3408 3409 /* 3410 * context section, shared in TOE, RDMA and ISCSI 3411 */ 3412 struct xstorm_padded_ip_v4_context_section { 3413 struct xstorm_ip_v4_context_section ip_v4; 3414 u32 reserved1[4]; 3415 }; 3416 3417 /* 3418 * IpV6 context section, shared in TOE, RDMA and ISCSI 3419 */ 3420 struct xstorm_ip_v6_context_section { 3421 #if defined(__BIG_ENDIAN) 3422 u16 pbf_hdr_cmd_rsvd_payload_len; 3423 u8 pbf_hdr_cmd_rsvd_nxt_hdr; 3424 u8 hop_limit; 3425 #elif defined(__LITTLE_ENDIAN) 3426 u8 hop_limit; 3427 u8 pbf_hdr_cmd_rsvd_nxt_hdr; 3428 u16 pbf_hdr_cmd_rsvd_payload_len; 3429 #endif 3430 u32 priority_flow_label; 3431 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) 3432 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0 3433 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) 3434 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20 3435 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) 3436 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28 3437 u32 ip_local_addr_lo_hi; 3438 u32 ip_local_addr_lo_lo; 3439 u32 ip_local_addr_hi_hi; 3440 u32 ip_local_addr_hi_lo; 3441 u32 ip_remote_addr_lo_hi; 3442 u32 ip_remote_addr_lo_lo; 3443 u32 ip_remote_addr_hi_hi; 3444 u32 ip_remote_addr_hi_lo; 3445 }; 3446 3447 union xstorm_ip_context_section_types { 3448 struct xstorm_padded_ip_v4_context_section padded_ip_v4; 3449 struct xstorm_ip_v6_context_section ip_v6; 3450 }; 3451 3452 /* 3453 * TCP context section, shared in TOE, RDMA and ISCSI 3454 */ 3455 struct xstorm_tcp_context_section { 3456 u32 snd_max; 3457 #if defined(__BIG_ENDIAN) 3458 u16 remote_port; 3459 u16 local_port; 3460 #elif defined(__LITTLE_ENDIAN) 3461 u16 local_port; 3462 u16 remote_port; 3463 #endif 3464 #if defined(__BIG_ENDIAN) 3465 u8 original_nagle_1b; 3466 u8 ts_enabled; 3467 u16 tcp_params; 3468 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) 3469 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 3470 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) 3471 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 3472 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) 3473 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 3474 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) 3475 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 3476 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) 3477 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 3478 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) 3479 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 3480 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) 3481 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 3482 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) 3483 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 3484 #elif defined(__LITTLE_ENDIAN) 3485 u16 tcp_params; 3486 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) 3487 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 3488 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) 3489 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 3490 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) 3491 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 3492 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) 3493 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 3494 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) 3495 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 3496 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) 3497 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 3498 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) 3499 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 3500 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) 3501 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 3502 u8 ts_enabled; 3503 u8 original_nagle_1b; 3504 #endif 3505 #if defined(__BIG_ENDIAN) 3506 u16 pseudo_csum; 3507 u16 window_scaling_factor; 3508 #elif defined(__LITTLE_ENDIAN) 3509 u16 window_scaling_factor; 3510 u16 pseudo_csum; 3511 #endif 3512 u32 reserved2; 3513 u32 ts_time_diff; 3514 u32 __next_timer_expir; 3515 }; 3516 3517 /* 3518 * Common context section, shared in TOE, RDMA and ISCSI 3519 */ 3520 struct xstorm_common_context_section { 3521 struct xstorm_eth_context_section ethernet; 3522 union xstorm_ip_context_section_types ip_union; 3523 struct xstorm_tcp_context_section tcp; 3524 #if defined(__BIG_ENDIAN) 3525 u16 reserved; 3526 u8 statistics_params; 3527 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) 3528 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 3529 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) 3530 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 3531 #define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID (0x1F<<2) 3532 #define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID_SHIFT 2 3533 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_EXISTS (0x1<<7) 3534 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_EXISTS_SHIFT 7 3535 u8 ip_version_1b; 3536 #elif defined(__LITTLE_ENDIAN) 3537 u8 ip_version_1b; 3538 u8 statistics_params; 3539 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) 3540 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 3541 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) 3542 #define XSTORM_COMMON_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 3543 #define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID (0x1F<<2) 3544 #define XSTORM_COMMON_CONTEXT_SECTION_STATISTICS_COUNTER_ID_SHIFT 2 3545 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_EXISTS (0x1<<7) 3546 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_EXISTS_SHIFT 7 3547 u16 reserved; 3548 #endif 3549 }; 3550 3551 /* 3552 * Flags used in ISCSI context section 3553 */ 3554 struct xstorm_iscsi_context_flags { 3555 u8 flags; 3556 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) 3557 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0 3558 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) 3559 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1 3560 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) 3561 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2 3562 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) 3563 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3 3564 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) 3565 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4 3566 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) 3567 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5 3568 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) 3569 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6 3570 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) 3571 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7 3572 }; 3573 3574 struct iscsi_task_context_entry_x { 3575 u32 data_out_buffer_offset; 3576 u32 itt; 3577 u32 data_sn; 3578 }; 3579 3580 struct iscsi_task_context_entry_xuc_x_write_only { 3581 u32 tx_r2t_sn; 3582 }; 3583 3584 struct iscsi_task_context_entry_xuc_xu_write_both { 3585 u32 sgl_base_lo; 3586 u32 sgl_base_hi; 3587 #if defined(__BIG_ENDIAN) 3588 u8 sgl_size; 3589 u8 sge_index; 3590 u16 sge_offset; 3591 #elif defined(__LITTLE_ENDIAN) 3592 u16 sge_offset; 3593 u8 sge_index; 3594 u8 sgl_size; 3595 #endif 3596 }; 3597 3598 /* 3599 * iSCSI context section 3600 */ 3601 struct xstorm_iscsi_context_section { 3602 u32 first_burst_length; 3603 u32 max_send_pdu_length; 3604 struct regpair sq_pbl_base; 3605 struct regpair sq_curr_pbe; 3606 struct regpair hq_pbl_base; 3607 struct regpair hq_curr_pbe_base; 3608 struct regpair r2tq_pbl_base; 3609 struct regpair r2tq_curr_pbe_base; 3610 struct regpair task_pbl_base; 3611 #if defined(__BIG_ENDIAN) 3612 u16 data_out_count; 3613 struct xstorm_iscsi_context_flags flags; 3614 u8 task_pbl_cache_idx; 3615 #elif defined(__LITTLE_ENDIAN) 3616 u8 task_pbl_cache_idx; 3617 struct xstorm_iscsi_context_flags flags; 3618 u16 data_out_count; 3619 #endif 3620 u32 seq_more_2_send; 3621 u32 pdu_more_2_send; 3622 struct iscsi_task_context_entry_x temp_tce_x; 3623 struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr; 3624 struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr; 3625 struct regpair lun; 3626 u32 exp_data_transfer_len_ttt; 3627 u32 pdu_data_2_rxmit; 3628 u32 rxmit_bytes_2_dr; 3629 #if defined(__BIG_ENDIAN) 3630 u16 rxmit_sge_offset; 3631 u16 hq_rxmit_cons; 3632 #elif defined(__LITTLE_ENDIAN) 3633 u16 hq_rxmit_cons; 3634 u16 rxmit_sge_offset; 3635 #endif 3636 #if defined(__BIG_ENDIAN) 3637 u16 r2tq_cons; 3638 u8 rxmit_flags; 3639 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) 3640 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 3641 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) 3642 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 3643 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) 3644 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 3645 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) 3646 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 3647 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) 3648 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 3649 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) 3650 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 3651 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) 3652 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 3653 u8 rxmit_sge_idx; 3654 #elif defined(__LITTLE_ENDIAN) 3655 u8 rxmit_sge_idx; 3656 u8 rxmit_flags; 3657 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) 3658 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 3659 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) 3660 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 3661 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) 3662 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 3663 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) 3664 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 3665 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) 3666 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 3667 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) 3668 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 3669 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) 3670 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 3671 u16 r2tq_cons; 3672 #endif 3673 u32 hq_rxmit_tcp_seq; 3674 }; 3675 3676 /* 3677 * Xstorm iSCSI Storm Context 3678 */ 3679 struct xstorm_iscsi_st_context { 3680 struct xstorm_common_context_section common; 3681 struct xstorm_iscsi_context_section iscsi; 3682 }; 3683 3684 /* 3685 * CQ DB CQ producer and pending completion counter 3686 */ 3687 struct iscsi_cq_db_prod_pnd_cmpltn_cnt { 3688 #if defined(__BIG_ENDIAN) 3689 u16 cntr; 3690 u16 prod; 3691 #elif defined(__LITTLE_ENDIAN) 3692 u16 prod; 3693 u16 cntr; 3694 #endif 3695 }; 3696 3697 /* 3698 * CQ DB pending completion ITT array 3699 */ 3700 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr { 3701 struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8]; 3702 }; 3703 3704 /* 3705 * Cstorm CQ sequence to notify array, updated by driver 3706 */ 3707 struct iscsi_cq_db_sqn_2_notify_arr { 3708 u16 sqn[8]; 3709 }; 3710 3711 /* 3712 * Cstorm iSCSI Storm Context 3713 */ 3714 struct cstorm_iscsi_st_context { 3715 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr; 3716 struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr; 3717 struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr; 3718 struct regpair hq_pbl_base; 3719 struct regpair hq_curr_pbe; 3720 struct regpair task_pbl_base; 3721 struct regpair cq_db_base; 3722 #if defined(__BIG_ENDIAN) 3723 u16 hq_bd_itt; 3724 u16 iscsi_conn_id; 3725 #elif defined(__LITTLE_ENDIAN) 3726 u16 iscsi_conn_id; 3727 u16 hq_bd_itt; 3728 #endif 3729 u32 hq_bd_data_segment_len; 3730 u32 hq_bd_buffer_offset; 3731 #if defined(__BIG_ENDIAN) 3732 u8 timer_entry_idx; 3733 u8 cq_proc_en_bit_map; 3734 u8 cq_pend_comp_itt_valid_bit_map; 3735 u8 hq_bd_opcode; 3736 #elif defined(__LITTLE_ENDIAN) 3737 u8 hq_bd_opcode; 3738 u8 cq_pend_comp_itt_valid_bit_map; 3739 u8 cq_proc_en_bit_map; 3740 u8 timer_entry_idx; 3741 #endif 3742 u32 hq_tcp_seq; 3743 #if defined(__BIG_ENDIAN) 3744 u16 flags; 3745 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) 3746 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 3747 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) 3748 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 3749 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) 3750 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 3751 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) 3752 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 3753 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) 3754 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 3755 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) 3756 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 3757 u16 hq_cons; 3758 #elif defined(__LITTLE_ENDIAN) 3759 u16 hq_cons; 3760 u16 flags; 3761 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) 3762 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 3763 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) 3764 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 3765 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) 3766 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 3767 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) 3768 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 3769 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) 3770 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 3771 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) 3772 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 3773 #endif 3774 struct regpair rsrv1; 3775 }; 3776 3777 /* 3778 * Iscsi connection context 3779 */ 3780 struct iscsi_context { 3781 struct ustorm_iscsi_st_context ustorm_st_context; 3782 struct tstorm_iscsi_st_context tstorm_st_context; 3783 struct xstorm_iscsi_ag_context xstorm_ag_context; 3784 struct tstorm_iscsi_ag_context tstorm_ag_context; 3785 struct cstorm_iscsi_ag_context cstorm_ag_context; 3786 struct ustorm_iscsi_ag_context ustorm_ag_context; 3787 struct timers_block_context timers_context; 3788 struct regpair upb_context; 3789 struct xstorm_iscsi_st_context xstorm_st_context; 3790 struct regpair xpb_context; 3791 struct cstorm_iscsi_st_context cstorm_st_context; 3792 }; 3793 3794 /* 3795 * FCoE KCQ CQE parameters 3796 */ 3797 union fcoe_kcqe_params { 3798 u32 reserved0[4]; 3799 }; 3800 3801 /* 3802 * FCoE KCQ CQE 3803 */ 3804 struct fcoe_kcqe { 3805 u32 fcoe_conn_id; 3806 u32 completion_status; 3807 u32 fcoe_conn_context_id; 3808 union fcoe_kcqe_params params; 3809 #if defined(__BIG_ENDIAN) 3810 u8 flags; 3811 #define FCOE_KCQE_RESERVED0 (0x7<<0) 3812 #define FCOE_KCQE_RESERVED0_SHIFT 0 3813 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) 3814 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 3815 #define FCOE_KCQE_LAYER_CODE (0x7<<4) 3816 #define FCOE_KCQE_LAYER_CODE_SHIFT 4 3817 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 3818 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 3819 u8 op_code; 3820 u16 qe_self_seq; 3821 #elif defined(__LITTLE_ENDIAN) 3822 u16 qe_self_seq; 3823 u8 op_code; 3824 u8 flags; 3825 #define FCOE_KCQE_RESERVED0 (0x7<<0) 3826 #define FCOE_KCQE_RESERVED0_SHIFT 0 3827 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) 3828 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 3829 #define FCOE_KCQE_LAYER_CODE (0x7<<4) 3830 #define FCOE_KCQE_LAYER_CODE_SHIFT 4 3831 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 3832 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 3833 #endif 3834 }; 3835 3836 /* 3837 * FCoE KWQE header 3838 */ 3839 struct fcoe_kwqe_header { 3840 #if defined(__BIG_ENDIAN) 3841 u8 flags; 3842 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 3843 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 3844 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) 3845 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 3846 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 3847 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 3848 u8 op_code; 3849 #elif defined(__LITTLE_ENDIAN) 3850 u8 op_code; 3851 u8 flags; 3852 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 3853 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 3854 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) 3855 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 3856 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 3857 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 3858 #endif 3859 }; 3860 3861 /* 3862 * FCoE firmware init request 1 3863 */ 3864 struct fcoe_kwqe_init1 { 3865 #if defined(__BIG_ENDIAN) 3866 struct fcoe_kwqe_header hdr; 3867 u16 num_tasks; 3868 #elif defined(__LITTLE_ENDIAN) 3869 u16 num_tasks; 3870 struct fcoe_kwqe_header hdr; 3871 #endif 3872 u32 task_list_pbl_addr_lo; 3873 u32 task_list_pbl_addr_hi; 3874 u32 dummy_buffer_addr_lo; 3875 u32 dummy_buffer_addr_hi; 3876 #if defined(__BIG_ENDIAN) 3877 u16 rq_num_wqes; 3878 u16 sq_num_wqes; 3879 #elif defined(__LITTLE_ENDIAN) 3880 u16 sq_num_wqes; 3881 u16 rq_num_wqes; 3882 #endif 3883 #if defined(__BIG_ENDIAN) 3884 u16 cq_num_wqes; 3885 u16 rq_buffer_log_size; 3886 #elif defined(__LITTLE_ENDIAN) 3887 u16 rq_buffer_log_size; 3888 u16 cq_num_wqes; 3889 #endif 3890 #if defined(__BIG_ENDIAN) 3891 u8 flags; 3892 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 3893 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 3894 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) 3895 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 3896 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 3897 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 3898 u8 num_sessions_log; 3899 u16 mtu; 3900 #elif defined(__LITTLE_ENDIAN) 3901 u16 mtu; 3902 u8 num_sessions_log; 3903 u8 flags; 3904 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 3905 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 3906 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) 3907 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 3908 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 3909 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 3910 #endif 3911 }; 3912 3913 /* 3914 * FCoE firmware init request 2 3915 */ 3916 struct fcoe_kwqe_init2 { 3917 #if defined(__BIG_ENDIAN) 3918 struct fcoe_kwqe_header hdr; 3919 u16 reserved0; 3920 #elif defined(__LITTLE_ENDIAN) 3921 u16 reserved0; 3922 struct fcoe_kwqe_header hdr; 3923 #endif 3924 u32 hash_tbl_pbl_addr_lo; 3925 u32 hash_tbl_pbl_addr_hi; 3926 u32 t2_hash_tbl_addr_lo; 3927 u32 t2_hash_tbl_addr_hi; 3928 u32 t2_ptr_hash_tbl_addr_lo; 3929 u32 t2_ptr_hash_tbl_addr_hi; 3930 u32 free_list_count; 3931 }; 3932 3933 /* 3934 * FCoE firmware init request 3 3935 */ 3936 struct fcoe_kwqe_init3 { 3937 #if defined(__BIG_ENDIAN) 3938 struct fcoe_kwqe_header hdr; 3939 u16 reserved0; 3940 #elif defined(__LITTLE_ENDIAN) 3941 u16 reserved0; 3942 struct fcoe_kwqe_header hdr; 3943 #endif 3944 u32 error_bit_map_lo; 3945 u32 error_bit_map_hi; 3946 #if defined(__BIG_ENDIAN) 3947 u8 reserved21[3]; 3948 u8 cached_session_enable; 3949 #elif defined(__LITTLE_ENDIAN) 3950 u8 cached_session_enable; 3951 u8 reserved21[3]; 3952 #endif 3953 u32 reserved2[4]; 3954 }; 3955 3956 /* 3957 * FCoE connection offload request 1 3958 */ 3959 struct fcoe_kwqe_conn_offload1 { 3960 #if defined(__BIG_ENDIAN) 3961 struct fcoe_kwqe_header hdr; 3962 u16 fcoe_conn_id; 3963 #elif defined(__LITTLE_ENDIAN) 3964 u16 fcoe_conn_id; 3965 struct fcoe_kwqe_header hdr; 3966 #endif 3967 u32 sq_addr_lo; 3968 u32 sq_addr_hi; 3969 u32 rq_pbl_addr_lo; 3970 u32 rq_pbl_addr_hi; 3971 u32 rq_first_pbe_addr_lo; 3972 u32 rq_first_pbe_addr_hi; 3973 #if defined(__BIG_ENDIAN) 3974 u16 reserved0; 3975 u16 rq_prod; 3976 #elif defined(__LITTLE_ENDIAN) 3977 u16 rq_prod; 3978 u16 reserved0; 3979 #endif 3980 }; 3981 3982 /* 3983 * FCoE connection offload request 2 3984 */ 3985 struct fcoe_kwqe_conn_offload2 { 3986 #if defined(__BIG_ENDIAN) 3987 struct fcoe_kwqe_header hdr; 3988 u16 tx_max_fc_pay_len; 3989 #elif defined(__LITTLE_ENDIAN) 3990 u16 tx_max_fc_pay_len; 3991 struct fcoe_kwqe_header hdr; 3992 #endif 3993 u32 cq_addr_lo; 3994 u32 cq_addr_hi; 3995 u32 xferq_addr_lo; 3996 u32 xferq_addr_hi; 3997 u32 conn_db_addr_lo; 3998 u32 conn_db_addr_hi; 3999 u32 reserved1; 4000 }; 4001 4002 /* 4003 * FCoE connection offload request 3 4004 */ 4005 struct fcoe_kwqe_conn_offload3 { 4006 #if defined(__BIG_ENDIAN) 4007 struct fcoe_kwqe_header hdr; 4008 u16 vlan_tag; 4009 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 4010 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 4011 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 4012 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 4013 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 4014 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 4015 #elif defined(__LITTLE_ENDIAN) 4016 u16 vlan_tag; 4017 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 4018 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 4019 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 4020 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 4021 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 4022 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 4023 struct fcoe_kwqe_header hdr; 4024 #endif 4025 #if defined(__BIG_ENDIAN) 4026 u8 tx_max_conc_seqs_c3; 4027 u8 s_id[3]; 4028 #elif defined(__LITTLE_ENDIAN) 4029 u8 s_id[3]; 4030 u8 tx_max_conc_seqs_c3; 4031 #endif 4032 #if defined(__BIG_ENDIAN) 4033 u8 flags; 4034 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 4035 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 4036 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) 4037 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 4038 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) 4039 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 4040 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) 4041 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 4042 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) 4043 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 4044 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) 4045 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 4046 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) 4047 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 4048 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 4049 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 4050 u8 d_id[3]; 4051 #elif defined(__LITTLE_ENDIAN) 4052 u8 d_id[3]; 4053 u8 flags; 4054 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 4055 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 4056 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) 4057 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 4058 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) 4059 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 4060 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) 4061 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 4062 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) 4063 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 4064 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) 4065 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 4066 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) 4067 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 4068 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 4069 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 4070 #endif 4071 u32 reserved; 4072 u32 confq_first_pbe_addr_lo; 4073 u32 confq_first_pbe_addr_hi; 4074 #if defined(__BIG_ENDIAN) 4075 u16 rx_max_fc_pay_len; 4076 u16 tx_total_conc_seqs; 4077 #elif defined(__LITTLE_ENDIAN) 4078 u16 tx_total_conc_seqs; 4079 u16 rx_max_fc_pay_len; 4080 #endif 4081 #if defined(__BIG_ENDIAN) 4082 u8 rx_open_seqs_exch_c3; 4083 u8 rx_max_conc_seqs_c3; 4084 u16 rx_total_conc_seqs; 4085 #elif defined(__LITTLE_ENDIAN) 4086 u16 rx_total_conc_seqs; 4087 u8 rx_max_conc_seqs_c3; 4088 u8 rx_open_seqs_exch_c3; 4089 #endif 4090 }; 4091 4092 /* 4093 * FCoE connection offload request 4 4094 */ 4095 struct fcoe_kwqe_conn_offload4 { 4096 #if defined(__BIG_ENDIAN) 4097 struct fcoe_kwqe_header hdr; 4098 u8 reserved2; 4099 u8 e_d_tov_timer_val; 4100 #elif defined(__LITTLE_ENDIAN) 4101 u8 e_d_tov_timer_val; 4102 u8 reserved2; 4103 struct fcoe_kwqe_header hdr; 4104 #endif 4105 u8 src_mac_addr_lo32[4]; 4106 #if defined(__BIG_ENDIAN) 4107 u8 dst_mac_addr_hi16[2]; 4108 u8 src_mac_addr_hi16[2]; 4109 #elif defined(__LITTLE_ENDIAN) 4110 u8 src_mac_addr_hi16[2]; 4111 u8 dst_mac_addr_hi16[2]; 4112 #endif 4113 u8 dst_mac_addr_lo32[4]; 4114 u32 lcq_addr_lo; 4115 u32 lcq_addr_hi; 4116 u32 confq_pbl_base_addr_lo; 4117 u32 confq_pbl_base_addr_hi; 4118 }; 4119 4120 /* 4121 * FCoE connection enable request 4122 */ 4123 struct fcoe_kwqe_conn_enable_disable { 4124 #if defined(__BIG_ENDIAN) 4125 struct fcoe_kwqe_header hdr; 4126 u16 reserved0; 4127 #elif defined(__LITTLE_ENDIAN) 4128 u16 reserved0; 4129 struct fcoe_kwqe_header hdr; 4130 #endif 4131 u8 src_mac_addr_lo32[4]; 4132 #if defined(__BIG_ENDIAN) 4133 u16 vlan_tag; 4134 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 4135 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 4136 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) 4137 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 4138 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 4139 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 4140 u8 src_mac_addr_hi16[2]; 4141 #elif defined(__LITTLE_ENDIAN) 4142 u8 src_mac_addr_hi16[2]; 4143 u16 vlan_tag; 4144 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 4145 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 4146 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) 4147 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 4148 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 4149 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 4150 #endif 4151 u8 dst_mac_addr_lo32[4]; 4152 #if defined(__BIG_ENDIAN) 4153 u16 reserved1; 4154 u8 dst_mac_addr_hi16[2]; 4155 #elif defined(__LITTLE_ENDIAN) 4156 u8 dst_mac_addr_hi16[2]; 4157 u16 reserved1; 4158 #endif 4159 #if defined(__BIG_ENDIAN) 4160 u8 vlan_flag; 4161 u8 s_id[3]; 4162 #elif defined(__LITTLE_ENDIAN) 4163 u8 s_id[3]; 4164 u8 vlan_flag; 4165 #endif 4166 #if defined(__BIG_ENDIAN) 4167 u8 reserved3; 4168 u8 d_id[3]; 4169 #elif defined(__LITTLE_ENDIAN) 4170 u8 d_id[3]; 4171 u8 reserved3; 4172 #endif 4173 u32 context_id; 4174 u32 conn_id; 4175 u32 reserved4; 4176 }; 4177 4178 /* 4179 * FCoE connection destroy request 4180 */ 4181 struct fcoe_kwqe_conn_destroy { 4182 #if defined(__BIG_ENDIAN) 4183 struct fcoe_kwqe_header hdr; 4184 u16 reserved0; 4185 #elif defined(__LITTLE_ENDIAN) 4186 u16 reserved0; 4187 struct fcoe_kwqe_header hdr; 4188 #endif 4189 u32 context_id; 4190 u32 conn_id; 4191 u32 reserved1[5]; 4192 }; 4193 4194 /* 4195 * FCoe destroy request 4196 */ 4197 struct fcoe_kwqe_destroy { 4198 #if defined(__BIG_ENDIAN) 4199 struct fcoe_kwqe_header hdr; 4200 u16 reserved0; 4201 #elif defined(__LITTLE_ENDIAN) 4202 u16 reserved0; 4203 struct fcoe_kwqe_header hdr; 4204 #endif 4205 u32 reserved1[7]; 4206 }; 4207 4208 /* 4209 * FCoe statistics request 4210 */ 4211 struct fcoe_kwqe_stat { 4212 #if defined(__BIG_ENDIAN) 4213 struct fcoe_kwqe_header hdr; 4214 u16 reserved0; 4215 #elif defined(__LITTLE_ENDIAN) 4216 u16 reserved0; 4217 struct fcoe_kwqe_header hdr; 4218 #endif 4219 u32 stat_params_addr_lo; 4220 u32 stat_params_addr_hi; 4221 u32 reserved1[5]; 4222 }; 4223 4224 /* 4225 * FCoE KWQ WQE 4226 */ 4227 union fcoe_kwqe { 4228 struct fcoe_kwqe_init1 init1; 4229 struct fcoe_kwqe_init2 init2; 4230 struct fcoe_kwqe_init3 init3; 4231 struct fcoe_kwqe_conn_offload1 conn_offload1; 4232 struct fcoe_kwqe_conn_offload2 conn_offload2; 4233 struct fcoe_kwqe_conn_offload3 conn_offload3; 4234 struct fcoe_kwqe_conn_offload4 conn_offload4; 4235 struct fcoe_kwqe_conn_enable_disable conn_enable_disable; 4236 struct fcoe_kwqe_conn_destroy conn_destroy; 4237 struct fcoe_kwqe_destroy destroy; 4238 struct fcoe_kwqe_stat statistics; 4239 }; 4240 4241 struct fcoe_task_ctx_entry { 4242 struct fcoe_task_ctx_entry_tx_only tx_wr_only; 4243 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd; 4244 struct fcoe_task_ctx_entry_tx_rx_cmn cmn; 4245 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd; 4246 struct fcoe_task_ctx_entry_rx_only rx_wr_only; 4247 u32 reserved[4]; 4248 }; 4249 4250 /* 4251 * FCoE connection enable\disable params passed by driver to FW in FCoE enable ramrod 4252 */ 4253 struct fcoe_conn_enable_disable_ramrod_params { 4254 struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe; 4255 }; 4256 4257 4258 /* 4259 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod 4260 */ 4261 struct fcoe_conn_offload_ramrod_params { 4262 struct fcoe_kwqe_conn_offload1 offload_kwqe1; 4263 struct fcoe_kwqe_conn_offload2 offload_kwqe2; 4264 struct fcoe_kwqe_conn_offload3 offload_kwqe3; 4265 struct fcoe_kwqe_conn_offload4 offload_kwqe4; 4266 }; 4267 4268 /* 4269 * FCoE init params passed by driver to FW in FCoE init ramrod 4270 */ 4271 struct fcoe_init_ramrod_params { 4272 struct fcoe_kwqe_init1 init_kwqe1; 4273 struct fcoe_kwqe_init2 init_kwqe2; 4274 struct fcoe_kwqe_init3 init_kwqe3; 4275 struct regpair eq_addr; 4276 struct regpair eq_next_page_addr; 4277 #if defined(__BIG_ENDIAN) 4278 u16 sb_num; 4279 u16 eq_prod; 4280 #elif defined(__LITTLE_ENDIAN) 4281 u16 eq_prod; 4282 u16 sb_num; 4283 #endif 4284 #if defined(__BIG_ENDIAN) 4285 u16 reserved1; 4286 u8 reserved0; 4287 u8 sb_id; 4288 #elif defined(__LITTLE_ENDIAN) 4289 u8 sb_id; 4290 u8 reserved0; 4291 u16 reserved1; 4292 #endif 4293 }; 4294 4295 4296 /* 4297 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod 4298 */ 4299 struct fcoe_stat_ramrod_params { 4300 struct fcoe_kwqe_stat stat_kwqe; 4301 }; 4302 4303 4304 /* 4305 * FCoE 16-bits vlan structure 4306 */ 4307 struct fcoe_vlan_fields { 4308 u16 fields; 4309 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0) 4310 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 4311 #define FCOE_VLAN_FIELDS_CLI (0x1<<12) 4312 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 4313 #define FCOE_VLAN_FIELDS_PRI (0x7<<13) 4314 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 4315 }; 4316 4317 4318 /* 4319 * FCoE 16-bits vlan union 4320 */ 4321 union fcoe_vlan_field_union { 4322 struct fcoe_vlan_fields fields; 4323 u16 val; 4324 }; 4325 4326 /* 4327 * Parameters used for Class 2 verifications 4328 */ 4329 struct ustorm_fcoe_c2_params { 4330 #if defined(__BIG_ENDIAN) 4331 u16 e2e_credit; 4332 u16 con_seq; 4333 #elif defined(__LITTLE_ENDIAN) 4334 u16 con_seq; 4335 u16 e2e_credit; 4336 #endif 4337 #if defined(__BIG_ENDIAN) 4338 u16 ackq_prod; 4339 u16 open_seq_per_exch; 4340 #elif defined(__LITTLE_ENDIAN) 4341 u16 open_seq_per_exch; 4342 u16 ackq_prod; 4343 #endif 4344 struct regpair ackq_pbl_base; 4345 struct regpair ackq_cur_seg; 4346 }; 4347 4348 /* 4349 * Parameters used for Class 2 verifications 4350 */ 4351 struct xstorm_fcoe_c2_params { 4352 #if defined(__BIG_ENDIAN) 4353 u16 reserved0; 4354 u8 ackq_x_prod; 4355 u8 max_conc_seqs_c2; 4356 #elif defined(__LITTLE_ENDIAN) 4357 u8 max_conc_seqs_c2; 4358 u8 ackq_x_prod; 4359 u16 reserved0; 4360 #endif 4361 struct regpair ackq_pbl_base; 4362 struct regpair ackq_cur_seg; 4363 }; 4364 4365 /* 4366 * Buffer per connection, used in Tstorm 4367 */ 4368 struct iscsi_conn_buf { 4369 struct regpair reserved[8]; 4370 }; 4371 4372 /* 4373 * ipv6 structure 4374 */ 4375 struct ip_v6_addr { 4376 u32 ip_addr_lo_lo; 4377 u32 ip_addr_lo_hi; 4378 u32 ip_addr_hi_lo; 4379 u32 ip_addr_hi_hi; 4380 }; 4381 4382 /* 4383 * l5cm- connection identification params 4384 */ 4385 struct l5cm_conn_addr_params { 4386 u32 pmtu; 4387 #if defined(__BIG_ENDIAN) 4388 u8 remote_addr_3; 4389 u8 remote_addr_2; 4390 u8 remote_addr_1; 4391 u8 remote_addr_0; 4392 #elif defined(__LITTLE_ENDIAN) 4393 u8 remote_addr_0; 4394 u8 remote_addr_1; 4395 u8 remote_addr_2; 4396 u8 remote_addr_3; 4397 #endif 4398 #if defined(__BIG_ENDIAN) 4399 u16 params; 4400 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) 4401 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 4402 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) 4403 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 4404 u8 remote_addr_5; 4405 u8 remote_addr_4; 4406 #elif defined(__LITTLE_ENDIAN) 4407 u8 remote_addr_4; 4408 u8 remote_addr_5; 4409 u16 params; 4410 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) 4411 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 4412 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) 4413 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 4414 #endif 4415 struct ip_v6_addr local_ip_addr; 4416 struct ip_v6_addr remote_ip_addr; 4417 u32 ipv6_flow_label_20b; 4418 u32 reserved1; 4419 #if defined(__BIG_ENDIAN) 4420 u16 remote_tcp_port; 4421 u16 local_tcp_port; 4422 #elif defined(__LITTLE_ENDIAN) 4423 u16 local_tcp_port; 4424 u16 remote_tcp_port; 4425 #endif 4426 }; 4427 4428 /* 4429 * l5cm-xstorm connection buffer 4430 */ 4431 struct l5cm_xstorm_conn_buffer { 4432 #if defined(__BIG_ENDIAN) 4433 u16 rsrv1; 4434 u16 params; 4435 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) 4436 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 4437 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 4438 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 4439 #elif defined(__LITTLE_ENDIAN) 4440 u16 params; 4441 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) 4442 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 4443 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 4444 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 4445 u16 rsrv1; 4446 #endif 4447 #if defined(__BIG_ENDIAN) 4448 u16 mss; 4449 u16 pseudo_header_checksum; 4450 #elif defined(__LITTLE_ENDIAN) 4451 u16 pseudo_header_checksum; 4452 u16 mss; 4453 #endif 4454 u32 rcv_buf; 4455 u32 rsrv2; 4456 struct regpair context_addr; 4457 }; 4458 4459 /* 4460 * l5cm-tstorm connection buffer 4461 */ 4462 struct l5cm_tstorm_conn_buffer { 4463 u32 snd_buf; 4464 u32 rcv_buf; 4465 #if defined(__BIG_ENDIAN) 4466 u16 params; 4467 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) 4468 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 4469 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 4470 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 4471 u8 ka_max_probe_count; 4472 u8 ka_enable; 4473 #elif defined(__LITTLE_ENDIAN) 4474 u8 ka_enable; 4475 u8 ka_max_probe_count; 4476 u16 params; 4477 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) 4478 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 4479 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 4480 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 4481 #endif 4482 u32 ka_timeout; 4483 u32 ka_interval; 4484 u32 max_rt_time; 4485 }; 4486 4487 /* 4488 * l5cm connection buffer for active side 4489 */ 4490 struct l5cm_active_conn_buffer { 4491 struct l5cm_conn_addr_params conn_addr_buf; 4492 struct l5cm_xstorm_conn_buffer xstorm_conn_buffer; 4493 struct l5cm_tstorm_conn_buffer tstorm_conn_buffer; 4494 }; 4495 4496 /* 4497 * l5cm slow path element 4498 */ 4499 struct l5cm_packet_size { 4500 u32 size; 4501 u32 rsrv; 4502 }; 4503 4504 /* 4505 * l5cm connection parameters 4506 */ 4507 union l5cm_reduce_param_union { 4508 u32 opaque1; 4509 u32 opaque2; 4510 }; 4511 4512 /* 4513 * l5cm connection parameters 4514 */ 4515 struct l5cm_reduce_conn { 4516 union l5cm_reduce_param_union opaque1; 4517 u32 opaque2; 4518 }; 4519 4520 /* 4521 * l5cm slow path element 4522 */ 4523 union l5cm_specific_data { 4524 u8 protocol_data[8]; 4525 struct regpair phy_address; 4526 struct l5cm_packet_size packet_size; 4527 struct l5cm_reduce_conn reduced_conn; 4528 }; 4529 4530 /* 4531 * l5 slow path element 4532 */ 4533 struct l5cm_spe { 4534 struct spe_hdr hdr; 4535 union l5cm_specific_data data; 4536 }; 4537 4538 /* 4539 * Tstorm Tcp flags 4540 */ 4541 struct tstorm_l5cm_tcp_flags { 4542 u16 flags; 4543 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) 4544 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0 4545 #define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12) 4546 #define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12 4547 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) 4548 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13 4549 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) 4550 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14 4551 }; 4552 4553 /* 4554 * Xstorm Tcp flags 4555 */ 4556 struct xstorm_l5cm_tcp_flags { 4557 u8 flags; 4558 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0) 4559 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0 4560 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1) 4561 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1 4562 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2) 4563 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2 4564 #define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3) 4565 #define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3 4566 }; 4567 4568 #endif /* CNIC_DEFS_H */ 4569