1/*
2 *  This file contains the power_save function for 6xx & 7xxx CPUs
3 *  rewritten in assembler
4 *
5 *  Warning ! This code assumes that if your machine has a 750fx
6 *  it will have PLL 1 set to low speed mode (used during NAP/DOZE).
7 *  if this is not the case some additional changes will have to
8 *  be done to check a runtime var (a bit like powersave-nap)
9 *
10 *  This program is free software; you can redistribute it and/or
11 *  modify it under the terms of the GNU General Public License
12 *  as published by the Free Software Foundation; either version
13 *  2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/threads.h>
18#include <asm/processor.h>
19#include <asm/page.h>
20#include <asm/cputable.h>
21#include <asm/ppc_asm.h>
22#include "ppc_defs.h"
23
24#undef DEBUG
25
26	.text
27
28/*
29 * Init idle, called at early CPU setup time from head.S for each CPU
30 * Make sure no rest of NAP mode remains in HID0, save default
31 * values for some CPU specific registers. Called with r24
32 * containing CPU number and r3 reloc offset
33 */
34 	.globl	init_idle_6xx
35init_idle_6xx:
36BEGIN_FTR_SECTION
37	mfspr	r4,SPRN_HID0
38	rlwinm	r4,r4,0,10,8	/* Clear NAP */
39	mtspr	SPRN_HID0, r4
40	b	1f
41END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
42	blr
431:
44	slwi	r5,r24,2
45	add	r5,r5,r3
46BEGIN_FTR_SECTION
47	mfspr	r4,SPRN_MSSCR0
48	addis	r6,r5, nap_save_msscr0@ha
49	stw	r4,nap_save_msscr0@l(r6)
50END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
51BEGIN_FTR_SECTION
52	mfspr	r4,SPRN_HID1
53	addis	r6,r5,nap_save_hid1@ha
54	stw	r4,nap_save_hid1@l(r6)
55END_FTR_SECTION_IFSET(CPU_FTR_750FX)
56	blr
57
58/*
59 * Here is the power_save function. This could eventually be
60 * split into several functions & changing the function pointer
61 * depending on the various features.
62 */
63	.globl	power_save
64power_save:
65	/* Check if we can nap or doze, put HID0 mask in r3
66	 */
67	lis	r3, 0
68BEGIN_FTR_SECTION
69	lis	r3,HID0_DOZE@h
70END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
71BEGIN_FTR_SECTION
72	/* We must dynamically check for the NAP feature as it
73	 * can be cleared by CPU init after the fixups are done
74	 */
75	lis	r4,cur_cpu_spec@ha
76	lwz	r4,cur_cpu_spec@l(r4)
77	lwz	r4,CPU_SPEC_FEATURES(r4)
78	andi.	r0,r4,CPU_FTR_CAN_NAP
79	beq	1f
80	/* Now check if user or arch enabled NAP mode */
81	lis	r4,powersave_nap@ha
82	lwz	r4,powersave_nap@l(r4)
83	cmpi	0,r4,0
84	beq	1f
85	lis	r3,HID0_NAP@h
861:
87END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
88	cmpi	0,r3,0
89	beqlr
90
91	/* Clear MSR:EE */
92	mfmsr	r7
93	rlwinm	r0,r7,0,17,15
94	mtmsr	r0
95
96	/* Check current->need_resched */
97	lwz	r4,NEED_RESCHED(r2)
98	cmpi	0,r4,0
99	beq+	1f
100	mtmsr	r7	/* out of line this ? */
101	blr
1021:
103	/* Some pre-nap cleanups needed on some CPUs */
104	andis.	r0,r3,HID0_NAP@h
105	beq	2f
106BEGIN_FTR_SECTION
107	/* Disable L2 prefetch on some 745x and try to ensure
108	 * L2 prefetch engines are idle. As explained by errata
109	 * text, we can't be sure they are, we just hope very hard
110	 * that well be enough (sic !). At least I noticed Apple
111	 * doesn't even bother doing the dcbf's here...
112	 */
113	mfspr	r4,SPRN_MSSCR0
114	rlwinm	r4,r4,0,0,29
115	sync
116	mtspr	SPRN_MSSCR0,r4
117	sync
118	isync
119	lis	r4,KERNELBASE@h
120	dcbf	0,r4
121	dcbf	0,r4
122	dcbf	0,r4
123	dcbf	0,r4
124END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
125#ifdef DEBUG
126	lis	r6,nap_enter_count@ha
127	lwz	r4,nap_enter_count@l(r6)
128	addi	r4,r4,1
129	stw	r4,nap_enter_count@l(r6)
130#endif
1312:
132BEGIN_FTR_SECTION
133	/* Go to low speed mode on some 750FX */
134	lis	r4,powersave_lowspeed@ha
135	lwz	r4,powersave_lowspeed@l(r4)
136	cmpi	0,r4,0
137	beq	1f
138	mfspr	r4,SPRN_HID1
139	oris	r4,r4,0x0001
140	mtspr	SPRN_HID1,r4
1411:
142END_FTR_SECTION_IFSET(CPU_FTR_750FX)
143
144	/* Go to NAP or DOZE now */
145	mfspr	r4,SPRN_HID0
146	lis	r5,(HID0_NAP|HID0_SLEEP)@h
147BEGIN_FTR_SECTION
148	oris	r5,r5,HID0_DOZE@h
149END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
150	andc	r4,r4,r5
151	or	r4,r4,r3
152BEGIN_FTR_SECTION
153	oris	r4,r4,HID0_DPM@h	/* that should be done once for all  */
154END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
155	mtspr	SPRN_HID0,r4
156BEGIN_FTR_SECTION
157	DSSALL
158	sync
159END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
160	ori	r7,r7,MSR_EE /* Could be ommited (already set) */
161	oris	r7,r7,MSR_POW@h
162	sync
163	isync
164	mtmsr	r7
165	.globl	power_save_6xx_ret
166power_save_6xx_ret:
167	isync
168	sync
169	blr
170
171/*
172 * Return from NAP/DOZE mode, restore some CPU specific registers,
173 * we are called with DR/IR still off and r2 containing physical
174 * address of current.
175 */
176 	.globl power_save_6xx_restore
177power_save_6xx_restore:
178	mfspr	r22,SPRN_HID0
179	rlwinm.	r22,r22,0,10,8	/* Clear NAP & copy NAP bit !state to cr1 EQ */
180	cror	4*cr1+eq,4*cr0+eq,4*cr0+eq
181BEGIN_FTR_SECTION
182	rlwinm	r22,r22,0,9,7	/* Clear DOZE */
183END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
184	mtspr	SPRN_HID0, r22
185
186#ifdef DEBUG
187	beq	cr1,1f
188	lis	r22,(nap_return_count-KERNELBASE)@ha
189	lwz	r24,nap_return_count@l(r22)
190	addi	r24,r24,1
191	stw	r24,nap_return_count@l(r22)
1921:
193#endif
194
195	lwz	r24,PROCESSOR(r2)
196	slwi	r24,r24,2
197	/* Todo make sure all these are in the same page
198	 * and load r22 (@ha part + CPU offset) only once
199	 */
200BEGIN_FTR_SECTION
201	beq	cr1,1f
202	addis	r22,r24,(nap_save_msscr0-KERNELBASE)@ha
203	lwz	r22,nap_save_msscr0@l(r22)
204	mtspr	SPRN_MSSCR0, r22
205	sync
206	isync
2071:
208END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
209BEGIN_FTR_SECTION
210	addis	r22,r24,(nap_save_hid1-KERNELBASE)@ha
211	lwz	r22,nap_save_hid1@l(r22)
212	mtspr	SPRN_HID1, r22
213END_FTR_SECTION_IFSET(CPU_FTR_750FX)
214	b	transfer_to_handler_cont
215
216	.data
217
218	.globl nap_save_msscr0
219nap_save_msscr0:
220	.space	4*NR_CPUS
221
222	.globl nap_save_hid1
223nap_save_hid1:
224	.space	4*NR_CPUS
225
226#ifdef DEBUG
227	.globl nap_enter_count
228nap_enter_count:
229	.space	4
230	.globl nap_return_count
231nap_return_count:
232	.space	4
233#endif
234