1 #ifndef __eth_defs_h 2 #define __eth_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: eth.r 7 * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp 8 * last modfied: Mon Jan 9 06:06:41 2006 9 * 10 * by /n/asic/design/tools/rdesc/rdes2c eth.r 11 * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 /* Main access macros */ 17 #ifndef REG_RD 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #endif 22 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #endif 28 29 #ifndef REG_RD_VECT 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34 #endif 35 36 #ifndef REG_WR_VECT 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41 #endif 42 43 #ifndef REG_RD_INT 44 #define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46 #endif 47 48 #ifndef REG_WR_INT 49 #define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51 #endif 52 53 #ifndef REG_RD_INT_VECT 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57 #endif 58 59 #ifndef REG_WR_INT_VECT 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63 #endif 64 65 #ifndef REG_TYPE_CONV 66 #define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68 #endif 69 70 #ifndef reg_page_size 71 #define reg_page_size 8192 72 #endif 73 74 #ifndef REG_ADDR 75 #define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77 #endif 78 79 #ifndef REG_ADDR_VECT 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83 #endif 84 85 /* C-code for register scope eth */ 86 87 /* Register rw_ma0_lo, scope eth, type rw */ 88 typedef struct { 89 unsigned int addr : 32; 90 } reg_eth_rw_ma0_lo; 91 #define REG_RD_ADDR_eth_rw_ma0_lo 0 92 #define REG_WR_ADDR_eth_rw_ma0_lo 0 93 94 /* Register rw_ma0_hi, scope eth, type rw */ 95 typedef struct { 96 unsigned int addr : 16; 97 unsigned int dummy1 : 16; 98 } reg_eth_rw_ma0_hi; 99 #define REG_RD_ADDR_eth_rw_ma0_hi 4 100 #define REG_WR_ADDR_eth_rw_ma0_hi 4 101 102 /* Register rw_ma1_lo, scope eth, type rw */ 103 typedef struct { 104 unsigned int addr : 32; 105 } reg_eth_rw_ma1_lo; 106 #define REG_RD_ADDR_eth_rw_ma1_lo 8 107 #define REG_WR_ADDR_eth_rw_ma1_lo 8 108 109 /* Register rw_ma1_hi, scope eth, type rw */ 110 typedef struct { 111 unsigned int addr : 16; 112 unsigned int dummy1 : 16; 113 } reg_eth_rw_ma1_hi; 114 #define REG_RD_ADDR_eth_rw_ma1_hi 12 115 #define REG_WR_ADDR_eth_rw_ma1_hi 12 116 117 /* Register rw_ga_lo, scope eth, type rw */ 118 typedef struct { 119 unsigned int tbl : 32; 120 } reg_eth_rw_ga_lo; 121 #define REG_RD_ADDR_eth_rw_ga_lo 16 122 #define REG_WR_ADDR_eth_rw_ga_lo 16 123 124 /* Register rw_ga_hi, scope eth, type rw */ 125 typedef struct { 126 unsigned int tbl : 32; 127 } reg_eth_rw_ga_hi; 128 #define REG_RD_ADDR_eth_rw_ga_hi 20 129 #define REG_WR_ADDR_eth_rw_ga_hi 20 130 131 /* Register rw_gen_ctrl, scope eth, type rw */ 132 typedef struct { 133 unsigned int en : 1; 134 unsigned int phy : 2; 135 unsigned int protocol : 1; 136 unsigned int loopback : 1; 137 unsigned int flow_ctrl : 1; 138 unsigned int gtxclk_out : 1; 139 unsigned int phyrst_n : 1; 140 unsigned int dummy1 : 24; 141 } reg_eth_rw_gen_ctrl; 142 #define REG_RD_ADDR_eth_rw_gen_ctrl 24 143 #define REG_WR_ADDR_eth_rw_gen_ctrl 24 144 145 /* Register rw_rec_ctrl, scope eth, type rw */ 146 typedef struct { 147 unsigned int ma0 : 1; 148 unsigned int ma1 : 1; 149 unsigned int individual : 1; 150 unsigned int broadcast : 1; 151 unsigned int undersize : 1; 152 unsigned int oversize : 1; 153 unsigned int bad_crc : 1; 154 unsigned int duplex : 1; 155 unsigned int max_size : 16; 156 unsigned int dummy1 : 8; 157 } reg_eth_rw_rec_ctrl; 158 #define REG_RD_ADDR_eth_rw_rec_ctrl 28 159 #define REG_WR_ADDR_eth_rw_rec_ctrl 28 160 161 /* Register rw_tr_ctrl, scope eth, type rw */ 162 typedef struct { 163 unsigned int crc : 1; 164 unsigned int pad : 1; 165 unsigned int retry : 1; 166 unsigned int ignore_col : 1; 167 unsigned int cancel : 1; 168 unsigned int hsh_delay : 1; 169 unsigned int ignore_crs : 1; 170 unsigned int carrier_ext : 1; 171 unsigned int dummy1 : 24; 172 } reg_eth_rw_tr_ctrl; 173 #define REG_RD_ADDR_eth_rw_tr_ctrl 32 174 #define REG_WR_ADDR_eth_rw_tr_ctrl 32 175 176 /* Register rw_clr_err, scope eth, type rw */ 177 typedef struct { 178 unsigned int clr : 1; 179 unsigned int dummy1 : 31; 180 } reg_eth_rw_clr_err; 181 #define REG_RD_ADDR_eth_rw_clr_err 36 182 #define REG_WR_ADDR_eth_rw_clr_err 36 183 184 /* Register rw_mgm_ctrl, scope eth, type rw */ 185 typedef struct { 186 unsigned int mdio : 1; 187 unsigned int mdoe : 1; 188 unsigned int mdc : 1; 189 unsigned int dummy1 : 29; 190 } reg_eth_rw_mgm_ctrl; 191 #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 192 #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 193 194 /* Register r_stat, scope eth, type r */ 195 typedef struct { 196 unsigned int mdio : 1; 197 unsigned int exc_col : 1; 198 unsigned int urun : 1; 199 unsigned int clk_125 : 1; 200 unsigned int dummy1 : 28; 201 } reg_eth_r_stat; 202 #define REG_RD_ADDR_eth_r_stat 44 203 204 /* Register rs_rec_cnt, scope eth, type rs */ 205 typedef struct { 206 unsigned int crc_err : 8; 207 unsigned int align_err : 8; 208 unsigned int oversize : 8; 209 unsigned int congestion : 8; 210 } reg_eth_rs_rec_cnt; 211 #define REG_RD_ADDR_eth_rs_rec_cnt 48 212 213 /* Register r_rec_cnt, scope eth, type r */ 214 typedef struct { 215 unsigned int crc_err : 8; 216 unsigned int align_err : 8; 217 unsigned int oversize : 8; 218 unsigned int congestion : 8; 219 } reg_eth_r_rec_cnt; 220 #define REG_RD_ADDR_eth_r_rec_cnt 52 221 222 /* Register rs_tr_cnt, scope eth, type rs */ 223 typedef struct { 224 unsigned int single_col : 8; 225 unsigned int mult_col : 8; 226 unsigned int late_col : 8; 227 unsigned int deferred : 8; 228 } reg_eth_rs_tr_cnt; 229 #define REG_RD_ADDR_eth_rs_tr_cnt 56 230 231 /* Register r_tr_cnt, scope eth, type r */ 232 typedef struct { 233 unsigned int single_col : 8; 234 unsigned int mult_col : 8; 235 unsigned int late_col : 8; 236 unsigned int deferred : 8; 237 } reg_eth_r_tr_cnt; 238 #define REG_RD_ADDR_eth_r_tr_cnt 60 239 240 /* Register rs_phy_cnt, scope eth, type rs */ 241 typedef struct { 242 unsigned int carrier_loss : 8; 243 unsigned int sqe_err : 8; 244 unsigned int dummy1 : 16; 245 } reg_eth_rs_phy_cnt; 246 #define REG_RD_ADDR_eth_rs_phy_cnt 64 247 248 /* Register r_phy_cnt, scope eth, type r */ 249 typedef struct { 250 unsigned int carrier_loss : 8; 251 unsigned int sqe_err : 8; 252 unsigned int dummy1 : 16; 253 } reg_eth_r_phy_cnt; 254 #define REG_RD_ADDR_eth_r_phy_cnt 68 255 256 /* Register rw_test_ctrl, scope eth, type rw */ 257 typedef struct { 258 unsigned int snmp_inc : 1; 259 unsigned int snmp : 1; 260 unsigned int backoff : 1; 261 unsigned int dummy1 : 29; 262 } reg_eth_rw_test_ctrl; 263 #define REG_RD_ADDR_eth_rw_test_ctrl 72 264 #define REG_WR_ADDR_eth_rw_test_ctrl 72 265 266 /* Register rw_intr_mask, scope eth, type rw */ 267 typedef struct { 268 unsigned int crc : 1; 269 unsigned int align : 1; 270 unsigned int oversize : 1; 271 unsigned int congestion : 1; 272 unsigned int single_col : 1; 273 unsigned int mult_col : 1; 274 unsigned int late_col : 1; 275 unsigned int deferred : 1; 276 unsigned int carrier_loss : 1; 277 unsigned int sqe_test_err : 1; 278 unsigned int orun : 1; 279 unsigned int urun : 1; 280 unsigned int exc_col : 1; 281 unsigned int mdio : 1; 282 unsigned int dummy1 : 18; 283 } reg_eth_rw_intr_mask; 284 #define REG_RD_ADDR_eth_rw_intr_mask 76 285 #define REG_WR_ADDR_eth_rw_intr_mask 76 286 287 /* Register rw_ack_intr, scope eth, type rw */ 288 typedef struct { 289 unsigned int crc : 1; 290 unsigned int align : 1; 291 unsigned int oversize : 1; 292 unsigned int congestion : 1; 293 unsigned int single_col : 1; 294 unsigned int mult_col : 1; 295 unsigned int late_col : 1; 296 unsigned int deferred : 1; 297 unsigned int carrier_loss : 1; 298 unsigned int sqe_test_err : 1; 299 unsigned int orun : 1; 300 unsigned int urun : 1; 301 unsigned int exc_col : 1; 302 unsigned int mdio : 1; 303 unsigned int dummy1 : 18; 304 } reg_eth_rw_ack_intr; 305 #define REG_RD_ADDR_eth_rw_ack_intr 80 306 #define REG_WR_ADDR_eth_rw_ack_intr 80 307 308 /* Register r_intr, scope eth, type r */ 309 typedef struct { 310 unsigned int crc : 1; 311 unsigned int align : 1; 312 unsigned int oversize : 1; 313 unsigned int congestion : 1; 314 unsigned int single_col : 1; 315 unsigned int mult_col : 1; 316 unsigned int late_col : 1; 317 unsigned int deferred : 1; 318 unsigned int carrier_loss : 1; 319 unsigned int sqe_test_err : 1; 320 unsigned int orun : 1; 321 unsigned int urun : 1; 322 unsigned int exc_col : 1; 323 unsigned int mdio : 1; 324 unsigned int dummy1 : 18; 325 } reg_eth_r_intr; 326 #define REG_RD_ADDR_eth_r_intr 84 327 328 /* Register r_masked_intr, scope eth, type r */ 329 typedef struct { 330 unsigned int crc : 1; 331 unsigned int align : 1; 332 unsigned int oversize : 1; 333 unsigned int congestion : 1; 334 unsigned int single_col : 1; 335 unsigned int mult_col : 1; 336 unsigned int late_col : 1; 337 unsigned int deferred : 1; 338 unsigned int carrier_loss : 1; 339 unsigned int sqe_test_err : 1; 340 unsigned int orun : 1; 341 unsigned int urun : 1; 342 unsigned int exc_col : 1; 343 unsigned int mdio : 1; 344 unsigned int dummy1 : 18; 345 } reg_eth_r_masked_intr; 346 #define REG_RD_ADDR_eth_r_masked_intr 88 347 348 349 /* Constants */ 350 enum { 351 regk_eth_discard = 0x00000000, 352 regk_eth_ether = 0x00000000, 353 regk_eth_full = 0x00000001, 354 regk_eth_gmii = 0x00000003, 355 regk_eth_gtxclk = 0x00000001, 356 regk_eth_half = 0x00000000, 357 regk_eth_hsh = 0x00000001, 358 regk_eth_mii = 0x00000001, 359 regk_eth_mii_arec = 0x00000002, 360 regk_eth_mii_clk = 0x00000000, 361 regk_eth_no = 0x00000000, 362 regk_eth_phyrst = 0x00000000, 363 regk_eth_rec = 0x00000001, 364 regk_eth_rw_ga_hi_default = 0x00000000, 365 regk_eth_rw_ga_lo_default = 0x00000000, 366 regk_eth_rw_gen_ctrl_default = 0x00000000, 367 regk_eth_rw_intr_mask_default = 0x00000000, 368 regk_eth_rw_ma0_hi_default = 0x00000000, 369 regk_eth_rw_ma0_lo_default = 0x00000000, 370 regk_eth_rw_ma1_hi_default = 0x00000000, 371 regk_eth_rw_ma1_lo_default = 0x00000000, 372 regk_eth_rw_mgm_ctrl_default = 0x00000000, 373 regk_eth_rw_test_ctrl_default = 0x00000000, 374 regk_eth_size1518 = 0x000005ee, 375 regk_eth_size1522 = 0x000005f2, 376 regk_eth_yes = 0x00000001 377 }; 378 #endif /* __eth_defs_h */ 379