1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * core.h - DesignWare HS OTG Controller common declarations
4  *
5  * Copyright (C) 2004-2013 Synopsys, Inc.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The names of the above-listed copyright holders may not be used
17  *    to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * ALTERNATIVELY, this software may be distributed under the terms of the
21  * GNU General Public License ("GPL") as published by the Free Software
22  * Foundation; either version 2 of the License, or (at your option) any
23  * later version.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __DWC2_CORE_H__
39 #define __DWC2_CORE_H__
40 
41 #include <linux/acpi.h>
42 #include <linux/phy/phy.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/usb/otg.h>
46 #include <linux/usb/phy.h>
47 #include "hw.h"
48 
49 /*
50  * Suggested defines for tracers:
51  * - no_printk:    Disable tracing
52  * - pr_info:      Print this info to the console
53  * - trace_printk: Print this info to trace buffer (good for verbose logging)
54  */
55 
56 #define DWC2_TRACE_SCHEDULER		no_printk
57 #define DWC2_TRACE_SCHEDULER_VB		no_printk
58 
59 /* Detailed scheduler tracing, but won't overwhelm console */
60 #define dwc2_sch_dbg(hsotg, fmt, ...)					\
61 	DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt),			\
62 			     dev_name(hsotg->dev), ##__VA_ARGS__)
63 
64 /* Verbose scheduler tracing */
65 #define dwc2_sch_vdbg(hsotg, fmt, ...)					\
66 	DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt),		\
67 				dev_name(hsotg->dev), ##__VA_ARGS__)
68 
69 /* Maximum number of Endpoints/HostChannels */
70 #define MAX_EPS_CHANNELS	16
71 
72 /* dwc2-hsotg declarations */
73 static const char * const dwc2_hsotg_supply_names[] = {
74 	"vusb_d",               /* digital USB supply, 1.2V */
75 	"vusb_a",               /* analog USB supply, 1.1V */
76 };
77 
78 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
79 
80 /*
81  * EP0_MPS_LIMIT
82  *
83  * Unfortunately there seems to be a limit of the amount of data that can
84  * be transferred by IN transactions on EP0. This is either 127 bytes or 3
85  * packets (which practically means 1 packet and 63 bytes of data) when the
86  * MPS is set to 64.
87  *
88  * This means if we are wanting to move >127 bytes of data, we need to
89  * split the transactions up, but just doing one packet at a time does
90  * not work (this may be an implicit DATA0 PID on first packet of the
91  * transaction) and doing 2 packets is outside the controller's limits.
92  *
93  * If we try to lower the MPS size for EP0, then no transfers work properly
94  * for EP0, and the system will fail basic enumeration. As no cause for this
95  * has currently been found, we cannot support any large IN transfers for
96  * EP0.
97  */
98 #define EP0_MPS_LIMIT   64
99 
100 struct dwc2_hsotg;
101 struct dwc2_hsotg_req;
102 
103 /**
104  * struct dwc2_hsotg_ep - driver endpoint definition.
105  * @ep: The gadget layer representation of the endpoint.
106  * @name: The driver generated name for the endpoint.
107  * @queue: Queue of requests for this endpoint.
108  * @parent: Reference back to the parent device structure.
109  * @req: The current request that the endpoint is processing. This is
110  *       used to indicate an request has been loaded onto the endpoint
111  *       and has yet to be completed (maybe due to data move, or simply
112  *       awaiting an ack from the core all the data has been completed).
113  * @debugfs: File entry for debugfs file for this endpoint.
114  * @dir_in: Set to true if this endpoint is of the IN direction, which
115  *          means that it is sending data to the Host.
116  * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
117  * @index: The index for the endpoint registers.
118  * @mc: Multi Count - number of transactions per microframe
119  * @interval: Interval for periodic endpoints, in frames or microframes.
120  * @name: The name array passed to the USB core.
121  * @halted: Set if the endpoint has been halted.
122  * @periodic: Set if this is a periodic ep, such as Interrupt
123  * @isochronous: Set if this is a isochronous ep
124  * @send_zlp: Set if we need to send a zero-length packet.
125  * @wedged: Set if ep is wedged.
126  * @desc_list_dma: The DMA address of descriptor chain currently in use.
127  * @desc_list: Pointer to descriptor DMA chain head currently in use.
128  * @desc_count: Count of entries within the DMA descriptor chain of EP.
129  * @next_desc: index of next free descriptor in the ISOC chain under SW control.
130  * @compl_desc: index of next descriptor to be completed by xFerComplete
131  * @total_data: The total number of data bytes done.
132  * @fifo_size: The size of the FIFO (for periodic IN endpoints)
133  * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
134  * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
135  * @last_load: The offset of data for the last start of request.
136  * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
137  * @target_frame: Targeted frame num to setup next ISOC transfer
138  * @frame_overrun: Indicates SOF number overrun in DSTS
139  *
140  * This is the driver's state for each registered endpoint, allowing it
141  * to keep track of transactions that need doing. Each endpoint has a
142  * lock to protect the state, to try and avoid using an overall lock
143  * for the host controller as much as possible.
144  *
145  * For periodic IN endpoints, we have fifo_size and fifo_load to try
146  * and keep track of the amount of data in the periodic FIFO for each
147  * of these as we don't have a status register that tells us how much
148  * is in each of them. (note, this may actually be useless information
149  * as in shared-fifo mode periodic in acts like a single-frame packet
150  * buffer than a fifo)
151  */
152 struct dwc2_hsotg_ep {
153 	struct usb_ep           ep;
154 	struct list_head        queue;
155 	struct dwc2_hsotg       *parent;
156 	struct dwc2_hsotg_req    *req;
157 	struct dentry           *debugfs;
158 
159 	unsigned long           total_data;
160 	unsigned int            size_loaded;
161 	unsigned int            last_load;
162 	unsigned int            fifo_load;
163 	unsigned short          fifo_size;
164 	unsigned short		fifo_index;
165 
166 	unsigned char           dir_in;
167 	unsigned char           map_dir;
168 	unsigned char           index;
169 	unsigned char           mc;
170 	u16                     interval;
171 
172 	unsigned int            halted:1;
173 	unsigned int            periodic:1;
174 	unsigned int            isochronous:1;
175 	unsigned int            send_zlp:1;
176 	unsigned int            wedged:1;
177 	unsigned int            target_frame;
178 #define TARGET_FRAME_INITIAL   0xFFFFFFFF
179 	bool			frame_overrun;
180 
181 	dma_addr_t		desc_list_dma;
182 	struct dwc2_dma_desc	*desc_list;
183 	u8			desc_count;
184 
185 	unsigned int		next_desc;
186 	unsigned int		compl_desc;
187 
188 	char                    name[10];
189 };
190 
191 /**
192  * struct dwc2_hsotg_req - data transfer request
193  * @req: The USB gadget request
194  * @queue: The list of requests for the endpoint this is queued for.
195  * @saved_req_buf: variable to save req.buf when bounce buffers are used.
196  */
197 struct dwc2_hsotg_req {
198 	struct usb_request      req;
199 	struct list_head        queue;
200 	void *saved_req_buf;
201 };
202 
203 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
204 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
205 #define call_gadget(_hs, _entry) \
206 do { \
207 	if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
208 		(_hs)->driver && (_hs)->driver->_entry) { \
209 		spin_unlock(&_hs->lock); \
210 		(_hs)->driver->_entry(&(_hs)->gadget); \
211 		spin_lock(&_hs->lock); \
212 	} \
213 } while (0)
214 #else
215 #define call_gadget(_hs, _entry)	do {} while (0)
216 #endif
217 
218 struct dwc2_hsotg;
219 struct dwc2_host_chan;
220 
221 /* Device States */
222 enum dwc2_lx_state {
223 	DWC2_L0,	/* On state */
224 	DWC2_L1,	/* LPM sleep state */
225 	DWC2_L2,	/* USB suspend state */
226 	DWC2_L3,	/* Off state */
227 };
228 
229 /* Gadget ep0 states */
230 enum dwc2_ep0_state {
231 	DWC2_EP0_SETUP,
232 	DWC2_EP0_DATA_IN,
233 	DWC2_EP0_DATA_OUT,
234 	DWC2_EP0_STATUS_IN,
235 	DWC2_EP0_STATUS_OUT,
236 };
237 
238 /**
239  * struct dwc2_core_params - Parameters for configuring the core
240  *
241  * @otg_caps:           Specifies the OTG capabilities. OTG caps from the platform parameters,
242  *                      used to setup the:
243  *                       - HNP and SRP capable
244  *                       - SRP Only capable
245  *                       - No HNP/SRP capable (always available)
246  *                       Defaults to best available option
247  *                       - OTG revision number the device is compliant with, in binary-coded
248  *                         decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps)
249  * @host_dma:           Specifies whether to use slave or DMA mode for accessing
250  *                      the data FIFOs. The driver will automatically detect the
251  *                      value for this parameter if none is specified.
252  *                       0 - Slave (always available)
253  *                       1 - DMA (default, if available)
254  * @dma_desc_enable:    When DMA mode is enabled, specifies whether to use
255  *                      address DMA mode or descriptor DMA mode for accessing
256  *                      the data FIFOs. The driver will automatically detect the
257  *                      value for this if none is specified.
258  *                       0 - Address DMA
259  *                       1 - Descriptor DMA (default, if available)
260  * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
261  *                      address DMA mode or descriptor DMA mode for accessing
262  *                      the data FIFOs in Full Speed mode only. The driver
263  *                      will automatically detect the value for this if none is
264  *                      specified.
265  *                       0 - Address DMA
266  *                       1 - Descriptor DMA in FS (default, if available)
267  * @speed:              Specifies the maximum speed of operation in host and
268  *                      device mode. The actual speed depends on the speed of
269  *                      the attached device and the value of phy_type.
270  *                       0 - High Speed
271  *                           (default when phy_type is UTMI+ or ULPI)
272  *                       1 - Full Speed
273  *                           (default when phy_type is Full Speed)
274  * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
275  *                       1 - Allow dynamic FIFO sizing (default, if available)
276  * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
277  *                      are enabled for non-periodic IN endpoints in device
278  *                      mode.
279  * @host_rx_fifo_size:  Number of 4-byte words in the Rx FIFO in host mode when
280  *                      dynamic FIFO sizing is enabled
281  *                       16 to 32768
282  *                      Actual maximum value is autodetected and also
283  *                      the default.
284  * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
285  *                      in host mode when dynamic FIFO sizing is enabled
286  *                       16 to 32768
287  *                      Actual maximum value is autodetected and also
288  *                      the default.
289  * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
290  *                      host mode when dynamic FIFO sizing is enabled
291  *                       16 to 32768
292  *                      Actual maximum value is autodetected and also
293  *                      the default.
294  * @max_transfer_size:  The maximum transfer size supported, in bytes
295  *                       2047 to 65,535
296  *                      Actual maximum value is autodetected and also
297  *                      the default.
298  * @max_packet_count:   The maximum number of packets in a transfer
299  *                       15 to 511
300  *                      Actual maximum value is autodetected and also
301  *                      the default.
302  * @host_channels:      The number of host channel registers to use
303  *                       1 to 16
304  *                      Actual maximum value is autodetected and also
305  *                      the default.
306  * @phy_type:           Specifies the type of PHY interface to use. By default,
307  *                      the driver will automatically detect the phy_type.
308  *                       0 - Full Speed Phy
309  *                       1 - UTMI+ Phy
310  *                       2 - ULPI Phy
311  *                      Defaults to best available option (2, 1, then 0)
312  * @phy_utmi_width:     Specifies the UTMI+ Data Width (in bits). This parameter
313  *                      is applicable for a phy_type of UTMI+ or ULPI. (For a
314  *                      ULPI phy_type, this parameter indicates the data width
315  *                      between the MAC and the ULPI Wrapper.) Also, this
316  *                      parameter is applicable only if the OTG_HSPHY_WIDTH cC
317  *                      parameter was set to "8 and 16 bits", meaning that the
318  *                      core has been configured to work at either data path
319  *                      width.
320  *                       8 or 16 (default 16 if available)
321  * @phy_ulpi_ddr:       Specifies whether the ULPI operates at double or single
322  *                      data rate. This parameter is only applicable if phy_type
323  *                      is ULPI.
324  *                       0 - single data rate ULPI interface with 8 bit wide
325  *                           data bus (default)
326  *                       1 - double data rate ULPI interface with 4 bit wide
327  *                           data bus
328  * @phy_ulpi_ext_vbus:  For a ULPI phy, specifies whether to use the internal or
329  *                      external supply to drive the VBus
330  *                       0 - Internal supply (default)
331  *                       1 - External supply
332  * @i2c_enable:         Specifies whether to use the I2Cinterface for a full
333  *                      speed PHY. This parameter is only applicable if phy_type
334  *                      is FS.
335  *                       0 - No (default)
336  *                       1 - Yes
337  * @ipg_isoc_en:        Indicates the IPG supports is enabled or disabled.
338  *                       0 - Disable (default)
339  *                       1 - Enable
340  * @acg_enable:		For enabling Active Clock Gating in the controller
341  *                       0 - No
342  *                       1 - Yes
343  * @ulpi_fs_ls:         Make ULPI phy operate in FS/LS mode only
344  *                       0 - No (default)
345  *                       1 - Yes
346  * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
347  *                      when attached to a Full Speed or Low Speed device in
348  *                      host mode.
349  *                       0 - Don't support low power mode (default)
350  *                       1 - Support low power mode
351  * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
352  *                      when connected to a Low Speed device in host
353  *                      mode. This parameter is applicable only if
354  *                      host_support_fs_ls_low_power is enabled.
355  *                       0 - 48 MHz
356  *                           (default when phy_type is UTMI+ or ULPI)
357  *                       1 - 6 MHz
358  *                           (default when phy_type is Full Speed)
359  * @oc_disable:		Flag to disable overcurrent condition.
360  *			0 - Allow overcurrent condition to get detected
361  *			1 - Disable overcurrent condtion to get detected
362  * @ts_dline:           Enable Term Select Dline pulsing
363  *                       0 - No (default)
364  *                       1 - Yes
365  * @reload_ctl:         Allow dynamic reloading of HFIR register during runtime
366  *                       0 - No (default for core < 2.92a)
367  *                       1 - Yes (default for core >= 2.92a)
368  * @ahbcfg:             This field allows the default value of the GAHBCFG
369  *                      register to be overridden
370  *                       -1         - GAHBCFG value will be set to 0x06
371  *                                    (INCR, default)
372  *                       all others - GAHBCFG value will be overridden with
373  *                                    this value
374  *                      Not all bits can be controlled like this, the
375  *                      bits defined by GAHBCFG_CTRL_MASK are controlled
376  *                      by the driver and are ignored in this
377  *                      configuration value.
378  * @uframe_sched:       True to enable the microframe scheduler
379  * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
380  *                      Disable CONIDSTSCHNG controller interrupt in such
381  *                      case.
382  *                      0 - No (default)
383  *                      1 - Yes
384  * @power_down:         Specifies whether the controller support power_down.
385  *			If power_down is enabled, the controller will enter
386  *			power_down in both peripheral and host mode when
387  *			needed.
388  *			0 - No (default)
389  *			1 - Partial power down
390  *			2 - Hibernation
391  * @no_clock_gating:	Specifies whether to avoid clock gating feature.
392  *			0 - No (use clock gating)
393  *			1 - Yes (avoid it)
394  * @lpm:		Enable LPM support.
395  *			0 - No
396  *			1 - Yes
397  * @lpm_clock_gating:		Enable core PHY clock gating.
398  *			0 - No
399  *			1 - Yes
400  * @besl:		Enable LPM Errata support.
401  *			0 - No
402  *			1 - Yes
403  * @hird_threshold_en:	HIRD or HIRD Threshold enable.
404  *			0 - No
405  *			1 - Yes
406  * @hird_threshold:	Value of BESL or HIRD Threshold.
407  * @ref_clk_per:        Indicates in terms of pico seconds the period
408  *                      of ref_clk.
409  *			62500 - 16MHz
410  *                      58823 - 17MHz
411  *                      52083 - 19.2MHz
412  *			50000 - 20MHz
413  *			41666 - 24MHz
414  *			33333 - 30MHz (default)
415  *			25000 - 40MHz
416  * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
417  *                      the controller should generate an interrupt if the
418  *                      device had been in L1 state until that period.
419  *                      This is used by SW to initiate Remote WakeUp in the
420  *                      controller so as to sync to the uF number from the host.
421  * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
422  *			register.
423  *			0 - Deactivate the transceiver (default)
424  *			1 - Activate the transceiver
425  * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
426  *			detection using GGPIO register.
427  *			0 - Deactivate the external level detection (default)
428  *			1 - Activate the external level detection
429  * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent
430  *			detection.
431  *			0 - Deactivate the overcurrent detection
432  *			1 - Activate the overcurrent detection (default)
433  * @g_dma:              Enables gadget dma usage (default: autodetect).
434  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
435  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in
436  *			DWORDS from 16-32768 (default: 2048 if
437  *			possible, otherwise autodetect).
438  * @g_np_tx_fifo_size:	The non-periodic tx fifo size for the device in
439  *			DWORDS from 16-32768 (default: 1024 if
440  *			possible, otherwise autodetect).
441  * @g_tx_fifo_size:	An array of TX fifo sizes in dedicated fifo
442  *			mode. Each value corresponds to one EP
443  *			starting from EP1 (max 15 values). Sizes are
444  *			in DWORDS with possible values from
445  *			16-32768 (default: 256, 256, 256, 256, 768,
446  *			768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
447  * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
448  *                      while full&low speed device connect. And change speed
449  *                      back to DWC2_SPEED_PARAM_HIGH while device is gone.
450  *			0 - No (default)
451  *			1 - Yes
452  * @service_interval:   Enable service interval based scheduling.
453  *                      0 - No
454  *                      1 - Yes
455  *
456  * The following parameters may be specified when starting the module. These
457  * parameters define how the DWC_otg controller should be configured. A
458  * value of -1 (or any other out of range value) for any parameter means
459  * to read the value from hardware (if possible) or use the builtin
460  * default described above.
461  */
462 struct dwc2_core_params {
463 	struct usb_otg_caps otg_caps;
464 	u8 phy_type;
465 #define DWC2_PHY_TYPE_PARAM_FS		0
466 #define DWC2_PHY_TYPE_PARAM_UTMI	1
467 #define DWC2_PHY_TYPE_PARAM_ULPI	2
468 
469 	u8 speed;
470 #define DWC2_SPEED_PARAM_HIGH	0
471 #define DWC2_SPEED_PARAM_FULL	1
472 #define DWC2_SPEED_PARAM_LOW	2
473 
474 	u8 phy_utmi_width;
475 	bool phy_ulpi_ddr;
476 	bool phy_ulpi_ext_vbus;
477 	bool enable_dynamic_fifo;
478 	bool en_multiple_tx_fifo;
479 	bool i2c_enable;
480 	bool acg_enable;
481 	bool ulpi_fs_ls;
482 	bool ts_dline;
483 	bool reload_ctl;
484 	bool uframe_sched;
485 	bool external_id_pin_ctl;
486 
487 	int power_down;
488 #define DWC2_POWER_DOWN_PARAM_NONE		0
489 #define DWC2_POWER_DOWN_PARAM_PARTIAL		1
490 #define DWC2_POWER_DOWN_PARAM_HIBERNATION	2
491 	bool no_clock_gating;
492 
493 	bool lpm;
494 	bool lpm_clock_gating;
495 	bool besl;
496 	bool hird_threshold_en;
497 	bool service_interval;
498 	u8 hird_threshold;
499 	bool activate_stm_fs_transceiver;
500 	bool activate_stm_id_vb_detection;
501 	bool activate_ingenic_overcurrent_detection;
502 	bool ipg_isoc_en;
503 	u16 max_packet_count;
504 	u32 max_transfer_size;
505 	u32 ahbcfg;
506 
507 	/* GREFCLK parameters */
508 	u32 ref_clk_per;
509 	u16 sof_cnt_wkup_alert;
510 
511 	/* Host parameters */
512 	bool host_dma;
513 	bool dma_desc_enable;
514 	bool dma_desc_fs_enable;
515 	bool host_support_fs_ls_low_power;
516 	bool host_ls_low_power_phy_clk;
517 	bool oc_disable;
518 
519 	u8 host_channels;
520 	u16 host_rx_fifo_size;
521 	u16 host_nperio_tx_fifo_size;
522 	u16 host_perio_tx_fifo_size;
523 
524 	/* Gadget parameters */
525 	bool g_dma;
526 	bool g_dma_desc;
527 	u32 g_rx_fifo_size;
528 	u32 g_np_tx_fifo_size;
529 	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
530 
531 	bool change_speed_quirk;
532 };
533 
534 /**
535  * struct dwc2_hw_params - Autodetected parameters.
536  *
537  * These parameters are the various parameters read from hardware
538  * registers during initialization. They typically contain the best
539  * supported or maximum value that can be configured in the
540  * corresponding dwc2_core_params value.
541  *
542  * The values that are not in dwc2_core_params are documented below.
543  *
544  * @op_mode:             Mode of Operation
545  *                       0 - HNP- and SRP-Capable OTG (Host & Device)
546  *                       1 - SRP-Capable OTG (Host & Device)
547  *                       2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
548  *                       3 - SRP-Capable Device
549  *                       4 - Non-OTG Device
550  *                       5 - SRP-Capable Host
551  *                       6 - Non-OTG Host
552  * @arch:                Architecture
553  *                       0 - Slave only
554  *                       1 - External DMA
555  *                       2 - Internal DMA
556  * @ipg_isoc_en:        This feature indicates that the controller supports
557  *                      the worst-case scenario of Rx followed by Rx
558  *                      Interpacket Gap (IPG) (32 bitTimes) as per the utmi
559  *                      specification for any token following ISOC OUT token.
560  *                       0 - Don't support
561  *                       1 - Support
562  * @power_optimized:    Are power optimizations enabled?
563  * @num_dev_ep:         Number of device endpoints available
564  * @num_dev_in_eps:     Number of device IN endpoints available
565  * @num_dev_perio_in_ep: Number of device periodic IN endpoints
566  *                       available
567  * @dev_token_q_depth:  Device Mode IN Token Sequence Learning Queue
568  *                      Depth
569  *                       0 to 30
570  * @host_perio_tx_q_depth:
571  *                      Host Mode Periodic Request Queue Depth
572  *                       2, 4 or 8
573  * @nperio_tx_q_depth:
574  *                      Non-Periodic Request Queue Depth
575  *                       2, 4 or 8
576  * @hs_phy_type:         High-speed PHY interface type
577  *                       0 - High-speed interface not supported
578  *                       1 - UTMI+
579  *                       2 - ULPI
580  *                       3 - UTMI+ and ULPI
581  * @fs_phy_type:         Full-speed PHY interface type
582  *                       0 - Full speed interface not supported
583  *                       1 - Dedicated full speed interface
584  *                       2 - FS pins shared with UTMI+ pins
585  *                       3 - FS pins shared with ULPI pins
586  * @total_fifo_size:    Total internal RAM for FIFOs (bytes)
587  * @hibernation:	Is hibernation enabled?
588  * @utmi_phy_data_width: UTMI+ PHY data width
589  *                       0 - 8 bits
590  *                       1 - 16 bits
591  *                       2 - 8 or 16 bits
592  * @snpsid:             Value from SNPSID register
593  * @dev_ep_dirs:        Direction of device endpoints (GHWCFG1)
594  * @g_tx_fifo_size:	Power-on values of TxFIFO sizes
595  * @dma_desc_enable:    When DMA mode is enabled, specifies whether to use
596  *                      address DMA mode or descriptor DMA mode for accessing
597  *                      the data FIFOs. The driver will automatically detect the
598  *                      value for this if none is specified.
599  *                       0 - Address DMA
600  *                       1 - Descriptor DMA (default, if available)
601  * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
602  *                       1 - Allow dynamic FIFO sizing (default, if available)
603  * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
604  *                      are enabled for non-periodic IN endpoints in device
605  *                      mode.
606  * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
607  *                      in host mode when dynamic FIFO sizing is enabled
608  *                       16 to 32768
609  *                      Actual maximum value is autodetected and also
610  *                      the default.
611  * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
612  *                      host mode when dynamic FIFO sizing is enabled
613  *                       16 to 32768
614  *                      Actual maximum value is autodetected and also
615  *                      the default.
616  * @max_transfer_size:  The maximum transfer size supported, in bytes
617  *                       2047 to 65,535
618  *                      Actual maximum value is autodetected and also
619  *                      the default.
620  * @max_packet_count:   The maximum number of packets in a transfer
621  *                       15 to 511
622  *                      Actual maximum value is autodetected and also
623  *                      the default.
624  * @host_channels:      The number of host channel registers to use
625  *                       1 to 16
626  *                      Actual maximum value is autodetected and also
627  *                      the default.
628  * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
629  *			     in device mode when dynamic FIFO sizing is enabled
630  *			     16 to 32768
631  *			     Actual maximum value is autodetected and also
632  *			     the default.
633  * @i2c_enable:         Specifies whether to use the I2Cinterface for a full
634  *                      speed PHY. This parameter is only applicable if phy_type
635  *                      is FS.
636  *                       0 - No (default)
637  *                       1 - Yes
638  * @acg_enable:		For enabling Active Clock Gating in the controller
639  *                       0 - Disable
640  *                       1 - Enable
641  * @lpm_mode:		For enabling Link Power Management in the controller
642  *                       0 - Disable
643  *                       1 - Enable
644  * @rx_fifo_size:	Number of 4-byte words in the  Rx FIFO when dynamic
645  *			FIFO sizing is enabled 16 to 32768
646  *			Actual maximum value is autodetected and also
647  *			the default.
648  * @service_interval_mode: For enabling service interval based scheduling in the
649  *                         controller.
650  *                           0 - Disable
651  *                           1 - Enable
652  */
653 struct dwc2_hw_params {
654 	unsigned op_mode:3;
655 	unsigned arch:2;
656 	unsigned dma_desc_enable:1;
657 	unsigned enable_dynamic_fifo:1;
658 	unsigned en_multiple_tx_fifo:1;
659 	unsigned rx_fifo_size:16;
660 	unsigned host_nperio_tx_fifo_size:16;
661 	unsigned dev_nperio_tx_fifo_size:16;
662 	unsigned host_perio_tx_fifo_size:16;
663 	unsigned nperio_tx_q_depth:3;
664 	unsigned host_perio_tx_q_depth:3;
665 	unsigned dev_token_q_depth:5;
666 	unsigned max_transfer_size:26;
667 	unsigned max_packet_count:11;
668 	unsigned host_channels:5;
669 	unsigned hs_phy_type:2;
670 	unsigned fs_phy_type:2;
671 	unsigned i2c_enable:1;
672 	unsigned acg_enable:1;
673 	unsigned num_dev_ep:4;
674 	unsigned num_dev_in_eps : 4;
675 	unsigned num_dev_perio_in_ep:4;
676 	unsigned total_fifo_size:16;
677 	unsigned power_optimized:1;
678 	unsigned hibernation:1;
679 	unsigned utmi_phy_data_width:2;
680 	unsigned lpm_mode:1;
681 	unsigned ipg_isoc_en:1;
682 	unsigned service_interval_mode:1;
683 	u32 snpsid;
684 	u32 dev_ep_dirs;
685 	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
686 };
687 
688 /* Size of control and EP0 buffers */
689 #define DWC2_CTRL_BUFF_SIZE 8
690 
691 /**
692  * struct dwc2_gregs_backup - Holds global registers state before
693  * entering partial power down
694  * @gotgctl:		Backup of GOTGCTL register
695  * @gintmsk:		Backup of GINTMSK register
696  * @gahbcfg:		Backup of GAHBCFG register
697  * @gusbcfg:		Backup of GUSBCFG register
698  * @grxfsiz:		Backup of GRXFSIZ register
699  * @gnptxfsiz:		Backup of GNPTXFSIZ register
700  * @gi2cctl:		Backup of GI2CCTL register
701  * @glpmcfg:		Backup of GLPMCFG register
702  * @gdfifocfg:		Backup of GDFIFOCFG register
703  * @pcgcctl:		Backup of PCGCCTL register
704  * @pcgcctl1:		Backup of PCGCCTL1 register
705  * @dtxfsiz:		Backup of DTXFSIZ registers for each endpoint
706  * @gpwrdn:		Backup of GPWRDN register
707  * @valid:		True if registers values backuped.
708  */
709 struct dwc2_gregs_backup {
710 	u32 gotgctl;
711 	u32 gintmsk;
712 	u32 gahbcfg;
713 	u32 gusbcfg;
714 	u32 grxfsiz;
715 	u32 gnptxfsiz;
716 	u32 gi2cctl;
717 	u32 glpmcfg;
718 	u32 pcgcctl;
719 	u32 pcgcctl1;
720 	u32 gdfifocfg;
721 	u32 gpwrdn;
722 	bool valid;
723 };
724 
725 /**
726  * struct dwc2_dregs_backup - Holds device registers state before
727  * entering partial power down
728  * @dcfg:		Backup of DCFG register
729  * @dctl:		Backup of DCTL register
730  * @daintmsk:		Backup of DAINTMSK register
731  * @diepmsk:		Backup of DIEPMSK register
732  * @doepmsk:		Backup of DOEPMSK register
733  * @diepctl:		Backup of DIEPCTL register
734  * @dieptsiz:		Backup of DIEPTSIZ register
735  * @diepdma:		Backup of DIEPDMA register
736  * @doepctl:		Backup of DOEPCTL register
737  * @doeptsiz:		Backup of DOEPTSIZ register
738  * @doepdma:		Backup of DOEPDMA register
739  * @dtxfsiz:		Backup of DTXFSIZ registers for each endpoint
740  * @valid:      True if registers values backuped.
741  */
742 struct dwc2_dregs_backup {
743 	u32 dcfg;
744 	u32 dctl;
745 	u32 daintmsk;
746 	u32 diepmsk;
747 	u32 doepmsk;
748 	u32 diepctl[MAX_EPS_CHANNELS];
749 	u32 dieptsiz[MAX_EPS_CHANNELS];
750 	u32 diepdma[MAX_EPS_CHANNELS];
751 	u32 doepctl[MAX_EPS_CHANNELS];
752 	u32 doeptsiz[MAX_EPS_CHANNELS];
753 	u32 doepdma[MAX_EPS_CHANNELS];
754 	u32 dtxfsiz[MAX_EPS_CHANNELS];
755 	bool valid;
756 };
757 
758 /**
759  * struct dwc2_hregs_backup - Holds host registers state before
760  * entering partial power down
761  * @hcfg:		Backup of HCFG register
762  * @haintmsk:		Backup of HAINTMSK register
763  * @hcintmsk:		Backup of HCINTMSK register
764  * @hprt0:		Backup of HPTR0 register
765  * @hfir:		Backup of HFIR register
766  * @hptxfsiz:		Backup of HPTXFSIZ register
767  * @valid:      True if registers values backuped.
768  */
769 struct dwc2_hregs_backup {
770 	u32 hcfg;
771 	u32 haintmsk;
772 	u32 hcintmsk[MAX_EPS_CHANNELS];
773 	u32 hprt0;
774 	u32 hfir;
775 	u32 hptxfsiz;
776 	bool valid;
777 };
778 
779 /*
780  * Constants related to high speed periodic scheduling
781  *
782  * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long.  From a
783  * reservation point of view it's assumed that the schedule goes right back to
784  * the beginning after the end of the schedule.
785  *
786  * What does that mean for scheduling things with a long interval?  It means
787  * we'll reserve time for them in every possible microframe that they could
788  * ever be scheduled in.  ...but we'll still only actually schedule them as
789  * often as they were requested.
790  *
791  * We keep our schedule in a "bitmap" structure.  This simplifies having
792  * to keep track of and merge intervals: we just let the bitmap code do most
793  * of the heavy lifting.  In a way scheduling is much like memory allocation.
794  *
795  * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
796  * supposed to schedule for periodic transfers).  That's according to spec.
797  *
798  * Note that though we only schedule 80% of each microframe, the bitmap that we
799  * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
800  * space for each uFrame).
801  *
802  * Requirements:
803  * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
804  * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
805  *   could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
806  *   be bugs).  The 8 comes from the USB spec: number of microframes per frame.
807  */
808 #define DWC2_US_PER_UFRAME		125
809 #define DWC2_HS_PERIODIC_US_PER_UFRAME	100
810 
811 #define DWC2_HS_SCHEDULE_UFRAMES	8
812 #define DWC2_HS_SCHEDULE_US		(DWC2_HS_SCHEDULE_UFRAMES * \
813 					 DWC2_HS_PERIODIC_US_PER_UFRAME)
814 
815 /*
816  * Constants related to low speed scheduling
817  *
818  * For high speed we schedule every 1us.  For low speed that's a bit overkill,
819  * so we make up a unit called a "slice" that's worth 25us.  There are 40
820  * slices in a full frame and we can schedule 36 of those (90%) for periodic
821  * transfers.
822  *
823  * Our low speed schedule can be as short as 1 frame or could be longer.  When
824  * we only schedule 1 frame it means that we'll need to reserve a time every
825  * frame even for things that only transfer very rarely, so something that runs
826  * every 2048 frames will get time reserved in every frame.  Our low speed
827  * schedule can be longer and we'll be able to handle more overlap, but that
828  * will come at increased memory cost and increased time to schedule.
829  *
830  * Note: one other advantage of a short low speed schedule is that if we mess
831  * up and miss scheduling we can jump in and use any of the slots that we
832  * happened to reserve.
833  *
834  * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
835  * the schedule.  There will be one schedule per TT.
836  *
837  * Requirements:
838  * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
839  */
840 #define DWC2_US_PER_SLICE	25
841 #define DWC2_SLICES_PER_UFRAME	(DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
842 
843 #define DWC2_ROUND_US_TO_SLICE(us) \
844 				(DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
845 				 DWC2_US_PER_SLICE)
846 
847 #define DWC2_LS_PERIODIC_US_PER_FRAME \
848 				900
849 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
850 				(DWC2_LS_PERIODIC_US_PER_FRAME / \
851 				 DWC2_US_PER_SLICE)
852 
853 #define DWC2_LS_SCHEDULE_FRAMES	1
854 #define DWC2_LS_SCHEDULE_SLICES	(DWC2_LS_SCHEDULE_FRAMES * \
855 				 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
856 
857 /**
858  * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
859  * and periodic schedules
860  *
861  * These are common for both host and peripheral modes:
862  *
863  * @dev:                The struct device pointer
864  * @regs:		Pointer to controller regs
865  * @hw_params:          Parameters that were autodetected from the
866  *                      hardware registers
867  * @params:	Parameters that define how the core should be configured
868  * @op_state:           The operational State, during transitions (a_host=>
869  *                      a_peripheral and b_device=>b_host) this may not match
870  *                      the core, but allows the software to determine
871  *                      transitions
872  * @dr_mode:            Requested mode of operation, one of following:
873  *                      - USB_DR_MODE_PERIPHERAL
874  *                      - USB_DR_MODE_HOST
875  *                      - USB_DR_MODE_OTG
876  * @role_sw:		usb_role_switch handle
877  * @role_sw_default_mode: default operation mode of controller while usb role
878  *			is USB_ROLE_NONE
879  * @hcd_enabled:	Host mode sub-driver initialization indicator.
880  * @gadget_enabled:	Peripheral mode sub-driver initialization indicator.
881  * @ll_hw_enabled:	Status of low-level hardware resources.
882  * @hibernated:		True if core is hibernated
883  * @in_ppd:		True if core is partial power down mode.
884  * @bus_suspended:	True if bus is suspended
885  * @reset_phy_on_wake:	Quirk saying that we should assert PHY reset on a
886  *			remote wakeup.
887  * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
888  * @need_phy_for_wake:	Quirk saying that we should keep the PHY on at
889  *			suspend if we need USB to wake us up.
890  * @frame_number:       Frame number read from the core. For both device
891  *			and host modes. The value ranges are from 0
892  *			to HFNUM_MAX_FRNUM.
893  * @phy:                The otg phy transceiver structure for phy control.
894  * @uphy:               The otg phy transceiver structure for old USB phy
895  *                      control.
896  * @plat:               The platform specific configuration data. This can be
897  *                      removed once all SoCs support usb transceiver.
898  * @supplies:           Definition of USB power supplies
899  * @vbus_supply:        Regulator supplying vbus.
900  * @usb33d:		Optional 3.3v regulator used on some stm32 devices to
901  *			supply ID and VBUS detection hardware.
902  * @lock:		Spinlock that protects all the driver data structures
903  * @priv:		Stores a pointer to the struct usb_hcd
904  * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
905  *                      transfer are in process of being queued
906  * @srp_success:        Stores status of SRP request in the case of a FS PHY
907  *                      with an I2C interface
908  * @wq_otg:             Workqueue object used for handling of some interrupts
909  * @wf_otg:             Work object for handling Connector ID Status Change
910  *                      interrupt
911  * @wkp_timer:          Timer object for handling Wakeup Detected interrupt
912  * @lx_state:           Lx state of connected device
913  * @gr_backup: Backup of global registers during suspend
914  * @dr_backup: Backup of device registers during suspend
915  * @hr_backup: Backup of host registers during suspend
916  * @needs_byte_swap:		Specifies whether the opposite endianness.
917  *
918  * These are for host mode:
919  *
920  * @flags:              Flags for handling root port state changes
921  * @flags.d32:          Contain all root port flags
922  * @flags.b:            Separate root port flags from each other
923  * @flags.b.port_connect_status_change: True if root port connect status
924  *                      changed
925  * @flags.b.port_connect_status: True if device connected to root port
926  * @flags.b.port_reset_change: True if root port reset status changed
927  * @flags.b.port_enable_change: True if root port enable status changed
928  * @flags.b.port_suspend_change: True if root port suspend status changed
929  * @flags.b.port_over_current_change: True if root port over current state
930  *                       changed.
931  * @flags.b.port_l1_change: True if root port l1 status changed
932  * @flags.b.reserved:   Reserved bits of root port register
933  * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
934  *                      Transfers associated with these QHs are not currently
935  *                      assigned to a host channel.
936  * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
937  *                      Transfers associated with these QHs are currently
938  *                      assigned to a host channel.
939  * @non_periodic_qh_ptr: Pointer to next QH to process in the active
940  *                      non-periodic schedule
941  * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
942  *                      Transfers associated with these QHs are not currently
943  *                      assigned to a host channel.
944  * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
945  *                      list of QHs for periodic transfers that are _not_
946  *                      scheduled for the next frame. Each QH in the list has an
947  *                      interval counter that determines when it needs to be
948  *                      scheduled for execution. This scheduling mechanism
949  *                      allows only a simple calculation for periodic bandwidth
950  *                      used (i.e. must assume that all periodic transfers may
951  *                      need to execute in the same frame). However, it greatly
952  *                      simplifies scheduling and should be sufficient for the
953  *                      vast majority of OTG hosts, which need to connect to a
954  *                      small number of peripherals at one time. Items move from
955  *                      this list to periodic_sched_ready when the QH interval
956  *                      counter is 0 at SOF.
957  * @periodic_sched_ready:  List of periodic QHs that are ready for execution in
958  *                      the next frame, but have not yet been assigned to host
959  *                      channels. Items move from this list to
960  *                      periodic_sched_assigned as host channels become
961  *                      available during the current frame.
962  * @periodic_sched_assigned: List of periodic QHs to be executed in the next
963  *                      frame that are assigned to host channels. Items move
964  *                      from this list to periodic_sched_queued as the
965  *                      transactions for the QH are queued to the DWC_otg
966  *                      controller.
967  * @periodic_sched_queued: List of periodic QHs that have been queued for
968  *                      execution. Items move from this list to either
969  *                      periodic_sched_inactive or periodic_sched_ready when the
970  *                      channel associated with the transfer is released. If the
971  *                      interval for the QH is 1, the item moves to
972  *                      periodic_sched_ready because it must be rescheduled for
973  *                      the next frame. Otherwise, the item moves to
974  *                      periodic_sched_inactive.
975  * @split_order:        List keeping track of channels doing splits, in order.
976  * @periodic_usecs:     Total bandwidth claimed so far for periodic transfers.
977  *                      This value is in microseconds per (micro)frame. The
978  *                      assumption is that all periodic transfers may occur in
979  *                      the same (micro)frame.
980  * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
981  *                      host is in high speed mode; low speed schedules are
982  *                      stored elsewhere since we need one per TT.
983  * @periodic_qh_count:  Count of periodic QHs, if using several eps. Used for
984  *                      SOF enable/disable.
985  * @free_hc_list:       Free host channels in the controller. This is a list of
986  *                      struct dwc2_host_chan items.
987  * @periodic_channels:  Number of host channels assigned to periodic transfers.
988  *                      Currently assuming that there is a dedicated host
989  *                      channel for each periodic transaction and at least one
990  *                      host channel is available for non-periodic transactions.
991  * @non_periodic_channels: Number of host channels assigned to non-periodic
992  *                      transfers
993  * @available_host_channels: Number of host channels available for the
994  *			     microframe scheduler to use
995  * @hc_ptr_array:       Array of pointers to the host channel descriptors.
996  *                      Allows accessing a host channel descriptor given the
997  *                      host channel number. This is useful in interrupt
998  *                      handlers.
999  * @status_buf:         Buffer used for data received during the status phase of
1000  *                      a control transfer.
1001  * @status_buf_dma:     DMA address for status_buf
1002  * @start_work:         Delayed work for handling host A-cable connection
1003  * @reset_work:         Delayed work for handling a port reset
1004  * @phy_reset_work:     Work structure for doing a PHY reset
1005  * @otg_port:           OTG port number
1006  * @frame_list:         Frame list
1007  * @frame_list_dma:     Frame list DMA address
1008  * @frame_list_sz:      Frame list size
1009  * @desc_gen_cache:     Kmem cache for generic descriptors
1010  * @desc_hsisoc_cache:  Kmem cache for hs isochronous descriptors
1011  * @unaligned_cache:    Kmem cache for DMA mode to handle non-aligned buf
1012  *
1013  * These are for peripheral mode:
1014  *
1015  * @driver:             USB gadget driver
1016  * @dedicated_fifos:    Set if the hardware has dedicated IN-EP fifos.
1017  * @num_of_eps:         Number of available EPs (excluding EP0)
1018  * @debug_root:         Root directrory for debugfs.
1019  * @ep0_reply:          Request used for ep0 reply.
1020  * @ep0_buff:           Buffer for EP0 reply data, if needed.
1021  * @ctrl_buff:          Buffer for EP0 control requests.
1022  * @ctrl_req:           Request for EP0 control packets.
1023  * @ep0_state:          EP0 control transfers state
1024  * @delayed_status:		true when gadget driver asks for delayed status
1025  * @test_mode:          USB test mode requested by the host
1026  * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1027  *                      remote-wakeup signalling
1028  * @setup_desc_dma:	EP0 setup stage desc chain DMA address
1029  * @setup_desc:		EP0 setup stage desc chain pointer
1030  * @ctrl_in_desc_dma:	EP0 IN data phase desc chain DMA address
1031  * @ctrl_in_desc:	EP0 IN data phase desc chain pointer
1032  * @ctrl_out_desc_dma:	EP0 OUT data phase desc chain DMA address
1033  * @ctrl_out_desc:	EP0 OUT data phase desc chain pointer
1034  * @irq:		Interrupt request line number
1035  * @clk:		Pointer to otg clock
1036  * @reset:		Pointer to dwc2 reset controller
1037  * @reset_ecc:          Pointer to dwc2 optional reset controller in Stratix10.
1038  * @regset:		A pointer to a struct debugfs_regset32, which contains
1039  *			a pointer to an array of register definitions, the
1040  *			array size and the base address where the register bank
1041  *			is to be found.
1042  * @last_frame_num:	Number of last frame. Range from 0 to  32768
1043  * @frame_num_array:    Used only  if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1044  *			defined, for missed SOFs tracking. Array holds that
1045  *			frame numbers, which not equal to last_frame_num +1
1046  * @last_frame_num_array:   Used only  if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1047  *			    defined, for missed SOFs tracking.
1048  *			    If current_frame_number != last_frame_num+1
1049  *			    then last_frame_num added to this array
1050  * @frame_num_idx:	Actual size of frame_num_array and last_frame_num_array
1051  * @dumped_frame_num_array:	1 - if missed SOFs frame numbers dumbed
1052  *				0 - if missed SOFs frame numbers not dumbed
1053  * @fifo_mem:			Total internal RAM for FIFOs (bytes)
1054  * @fifo_map:		Each bit intend for concrete fifo. If that bit is set,
1055  *			then that fifo is used
1056  * @gadget:		Represents a usb gadget device
1057  * @connected:		Used in slave mode. True if device connected with host
1058  * @eps_in:		The IN endpoints being supplied to the gadget framework
1059  * @eps_out:		The OUT endpoints being supplied to the gadget framework
1060  * @new_connection:	Used in host mode. True if there are new connected
1061  *			device
1062  * @enabled:		Indicates the enabling state of controller
1063  *
1064  */
1065 struct dwc2_hsotg {
1066 	struct device *dev;
1067 	void __iomem *regs;
1068 	/** Params detected from hardware */
1069 	struct dwc2_hw_params hw_params;
1070 	/** Params to actually use */
1071 	struct dwc2_core_params params;
1072 	enum usb_otg_state op_state;
1073 	enum usb_dr_mode dr_mode;
1074 	struct usb_role_switch *role_sw;
1075 	enum usb_dr_mode role_sw_default_mode;
1076 	unsigned int hcd_enabled:1;
1077 	unsigned int gadget_enabled:1;
1078 	unsigned int ll_hw_enabled:1;
1079 	unsigned int hibernated:1;
1080 	unsigned int in_ppd:1;
1081 	bool bus_suspended;
1082 	unsigned int reset_phy_on_wake:1;
1083 	unsigned int need_phy_for_wake:1;
1084 	unsigned int phy_off_for_suspend:1;
1085 	u16 frame_number;
1086 
1087 	struct phy *phy;
1088 	struct usb_phy *uphy;
1089 	struct dwc2_hsotg_plat *plat;
1090 	struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1091 	struct regulator *vbus_supply;
1092 	struct regulator *usb33d;
1093 
1094 	spinlock_t lock;
1095 	void *priv;
1096 	int     irq;
1097 	struct clk *clk;
1098 	struct reset_control *reset;
1099 	struct reset_control *reset_ecc;
1100 
1101 	unsigned int queuing_high_bandwidth:1;
1102 	unsigned int srp_success:1;
1103 
1104 	struct workqueue_struct *wq_otg;
1105 	struct work_struct wf_otg;
1106 	struct timer_list wkp_timer;
1107 	enum dwc2_lx_state lx_state;
1108 	struct dwc2_gregs_backup gr_backup;
1109 	struct dwc2_dregs_backup dr_backup;
1110 	struct dwc2_hregs_backup hr_backup;
1111 
1112 	struct dentry *debug_root;
1113 	struct debugfs_regset32 *regset;
1114 	bool needs_byte_swap;
1115 
1116 	/* DWC OTG HW Release versions */
1117 #define DWC2_CORE_REV_2_71a	0x4f54271a
1118 #define DWC2_CORE_REV_2_72a     0x4f54272a
1119 #define DWC2_CORE_REV_2_80a	0x4f54280a
1120 #define DWC2_CORE_REV_2_90a	0x4f54290a
1121 #define DWC2_CORE_REV_2_91a	0x4f54291a
1122 #define DWC2_CORE_REV_2_92a	0x4f54292a
1123 #define DWC2_CORE_REV_2_94a	0x4f54294a
1124 #define DWC2_CORE_REV_3_00a	0x4f54300a
1125 #define DWC2_CORE_REV_3_10a	0x4f54310a
1126 #define DWC2_CORE_REV_4_00a	0x4f54400a
1127 #define DWC2_CORE_REV_4_20a	0x4f54420a
1128 #define DWC2_FS_IOT_REV_1_00a	0x5531100a
1129 #define DWC2_HS_IOT_REV_1_00a	0x5532100a
1130 #define DWC2_CORE_REV_MASK	0x0000ffff
1131 
1132 	/* DWC OTG HW Core ID */
1133 #define DWC2_OTG_ID		0x4f540000
1134 #define DWC2_FS_IOT_ID		0x55310000
1135 #define DWC2_HS_IOT_ID		0x55320000
1136 
1137 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1138 	union dwc2_hcd_internal_flags {
1139 		u32 d32;
1140 		struct {
1141 			unsigned port_connect_status_change:1;
1142 			unsigned port_connect_status:1;
1143 			unsigned port_reset_change:1;
1144 			unsigned port_enable_change:1;
1145 			unsigned port_suspend_change:1;
1146 			unsigned port_over_current_change:1;
1147 			unsigned port_l1_change:1;
1148 			unsigned reserved:25;
1149 		} b;
1150 	} flags;
1151 
1152 	struct list_head non_periodic_sched_inactive;
1153 	struct list_head non_periodic_sched_waiting;
1154 	struct list_head non_periodic_sched_active;
1155 	struct list_head *non_periodic_qh_ptr;
1156 	struct list_head periodic_sched_inactive;
1157 	struct list_head periodic_sched_ready;
1158 	struct list_head periodic_sched_assigned;
1159 	struct list_head periodic_sched_queued;
1160 	struct list_head split_order;
1161 	u16 periodic_usecs;
1162 	DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US);
1163 	u16 periodic_qh_count;
1164 	bool new_connection;
1165 
1166 	u16 last_frame_num;
1167 
1168 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1169 #define FRAME_NUM_ARRAY_SIZE 1000
1170 	u16 *frame_num_array;
1171 	u16 *last_frame_num_array;
1172 	int frame_num_idx;
1173 	int dumped_frame_num_array;
1174 #endif
1175 
1176 	struct list_head free_hc_list;
1177 	int periodic_channels;
1178 	int non_periodic_channels;
1179 	int available_host_channels;
1180 	struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1181 	u8 *status_buf;
1182 	dma_addr_t status_buf_dma;
1183 #define DWC2_HCD_STATUS_BUF_SIZE 64
1184 
1185 	struct delayed_work start_work;
1186 	struct delayed_work reset_work;
1187 	struct work_struct phy_reset_work;
1188 	u8 otg_port;
1189 	u32 *frame_list;
1190 	dma_addr_t frame_list_dma;
1191 	u32 frame_list_sz;
1192 	struct kmem_cache *desc_gen_cache;
1193 	struct kmem_cache *desc_hsisoc_cache;
1194 	struct kmem_cache *unaligned_cache;
1195 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1196 
1197 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1198 
1199 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1200 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1201 	/* Gadget structures */
1202 	struct usb_gadget_driver *driver;
1203 	int fifo_mem;
1204 	unsigned int dedicated_fifos:1;
1205 	unsigned char num_of_eps;
1206 	u32 fifo_map;
1207 
1208 	struct usb_request *ep0_reply;
1209 	struct usb_request *ctrl_req;
1210 	void *ep0_buff;
1211 	void *ctrl_buff;
1212 	enum dwc2_ep0_state ep0_state;
1213 	unsigned delayed_status : 1;
1214 	u8 test_mode;
1215 
1216 	dma_addr_t setup_desc_dma[2];
1217 	struct dwc2_dma_desc *setup_desc[2];
1218 	dma_addr_t ctrl_in_desc_dma;
1219 	struct dwc2_dma_desc *ctrl_in_desc;
1220 	dma_addr_t ctrl_out_desc_dma;
1221 	struct dwc2_dma_desc *ctrl_out_desc;
1222 
1223 	struct usb_gadget gadget;
1224 	unsigned int enabled:1;
1225 	unsigned int connected:1;
1226 	unsigned int remote_wakeup_allowed:1;
1227 	struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1228 	struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1229 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1230 };
1231 
1232 /* Normal architectures just use readl/write */
dwc2_readl(struct dwc2_hsotg * hsotg,u32 offset)1233 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1234 {
1235 	u32 val;
1236 
1237 	val = readl(hsotg->regs + offset);
1238 	if (hsotg->needs_byte_swap)
1239 		return swab32(val);
1240 	else
1241 		return val;
1242 }
1243 
dwc2_writel(struct dwc2_hsotg * hsotg,u32 value,u32 offset)1244 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1245 {
1246 	if (hsotg->needs_byte_swap)
1247 		writel(swab32(value), hsotg->regs + offset);
1248 	else
1249 		writel(value, hsotg->regs + offset);
1250 
1251 #ifdef DWC2_LOG_WRITES
1252 	pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1253 #endif
1254 }
1255 
dwc2_readl_rep(struct dwc2_hsotg * hsotg,u32 offset,void * buffer,unsigned int count)1256 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1257 				  void *buffer, unsigned int count)
1258 {
1259 	if (count) {
1260 		u32 *buf = buffer;
1261 
1262 		do {
1263 			u32 x = dwc2_readl(hsotg, offset);
1264 			*buf++ = x;
1265 		} while (--count);
1266 	}
1267 }
1268 
dwc2_writel_rep(struct dwc2_hsotg * hsotg,u32 offset,const void * buffer,unsigned int count)1269 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1270 				   const void *buffer, unsigned int count)
1271 {
1272 	if (count) {
1273 		const u32 *buf = buffer;
1274 
1275 		do {
1276 			dwc2_writel(hsotg, *buf++, offset);
1277 		} while (--count);
1278 	}
1279 }
1280 
1281 /* Reasons for halting a host channel */
1282 enum dwc2_halt_status {
1283 	DWC2_HC_XFER_NO_HALT_STATUS,
1284 	DWC2_HC_XFER_COMPLETE,
1285 	DWC2_HC_XFER_URB_COMPLETE,
1286 	DWC2_HC_XFER_ACK,
1287 	DWC2_HC_XFER_NAK,
1288 	DWC2_HC_XFER_NYET,
1289 	DWC2_HC_XFER_STALL,
1290 	DWC2_HC_XFER_XACT_ERR,
1291 	DWC2_HC_XFER_FRAME_OVERRUN,
1292 	DWC2_HC_XFER_BABBLE_ERR,
1293 	DWC2_HC_XFER_DATA_TOGGLE_ERR,
1294 	DWC2_HC_XFER_AHB_ERR,
1295 	DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1296 	DWC2_HC_XFER_URB_DEQUEUE,
1297 };
1298 
1299 /* Core version information */
dwc2_is_iot(struct dwc2_hsotg * hsotg)1300 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1301 {
1302 	return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1303 }
1304 
dwc2_is_fs_iot(struct dwc2_hsotg * hsotg)1305 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1306 {
1307 	return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1308 }
1309 
dwc2_is_hs_iot(struct dwc2_hsotg * hsotg)1310 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1311 {
1312 	return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1313 }
1314 
1315 /*
1316  * The following functions support initialization of the core driver component
1317  * and the DWC_otg controller
1318  */
1319 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1320 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1321 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
1322 				 bool restore);
1323 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1324 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1325 		int reset, int is_host);
1326 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1327 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1328 
1329 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1330 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1331 
1332 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1333 
1334 int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1335 
1336 /*
1337  * Common core Functions.
1338  * The following functions support managing the DWC_otg controller in either
1339  * device or host mode.
1340  */
1341 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1342 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1343 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1344 
1345 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1346 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1347 
1348 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1349 			     int is_host);
1350 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1351 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1352 
1353 void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1354 
1355 /* This function should be called on every hardware interrupt. */
1356 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1357 
1358 /* The device ID match table */
1359 extern const struct of_device_id dwc2_of_match_table[];
1360 extern const struct acpi_device_id dwc2_acpi_match[];
1361 
1362 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1363 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1364 
1365 /* Common polling functions */
1366 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1367 			    u32 timeout);
1368 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1369 			      u32 timeout);
1370 /* Parameters */
1371 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1372 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1373 
1374 /*
1375  * The following functions check the controller's OTG operation mode
1376  * capability (GHWCFG2.OTG_MODE).
1377  *
1378  * These functions can be used before the internal hsotg->hw_params
1379  * are read in and cached so they always read directly from the
1380  * GHWCFG2 register.
1381  */
1382 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1383 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1384 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1385 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1386 
1387 /*
1388  * Returns the mode of operation, host or device
1389  */
dwc2_is_host_mode(struct dwc2_hsotg * hsotg)1390 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1391 {
1392 	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1393 }
1394 
dwc2_is_device_mode(struct dwc2_hsotg * hsotg)1395 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1396 {
1397 	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1398 }
1399 
1400 int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1401 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1402 void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1403 void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1404 
1405 /*
1406  * Dump core registers and SPRAM
1407  */
1408 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1409 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1410 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1411 
1412 /* Gadget defines */
1413 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1414 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1415 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1416 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1417 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1418 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1419 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1420 				       bool reset);
1421 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
1422 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1423 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1424 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1425 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1426 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1427 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1428 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1429 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1430 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1431 				 int rem_wakeup, int reset);
1432 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1433 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1434 					bool restore);
1435 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg);
1436 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1437 				   int rem_wakeup);
1438 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1439 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1440 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1441 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1442 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
dwc2_clear_fifo_map(struct dwc2_hsotg * hsotg)1443 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg)
1444 { hsotg->fifo_map = 0; }
1445 #else
dwc2_hsotg_remove(struct dwc2_hsotg * dwc2)1446 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1447 { return 0; }
dwc2_hsotg_suspend(struct dwc2_hsotg * dwc2)1448 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1449 { return 0; }
dwc2_hsotg_resume(struct dwc2_hsotg * dwc2)1450 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1451 { return 0; }
dwc2_gadget_init(struct dwc2_hsotg * hsotg)1452 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1453 { return 0; }
dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg * dwc2,bool reset)1454 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1455 						     bool reset) {}
dwc2_hsotg_core_disconnect(struct dwc2_hsotg * hsotg)1456 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_core_connect(struct dwc2_hsotg * hsotg)1457 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_disconnect(struct dwc2_hsotg * dwc2)1458 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
dwc2_hsotg_set_test_mode(struct dwc2_hsotg * hsotg,int testmode)1459 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1460 					   int testmode)
1461 { return 0; }
1462 #define dwc2_is_device_connected(hsotg) (0)
1463 #define dwc2_is_device_enabled(hsotg) (0)
dwc2_backup_device_registers(struct dwc2_hsotg * hsotg)1464 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1465 { return 0; }
dwc2_restore_device_registers(struct dwc2_hsotg * hsotg,int remote_wakeup)1466 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1467 						int remote_wakeup)
1468 { return 0; }
dwc2_gadget_enter_hibernation(struct dwc2_hsotg * hsotg)1469 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1470 { return 0; }
dwc2_gadget_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1471 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1472 					       int rem_wakeup, int reset)
1473 { return 0; }
dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg * hsotg)1474 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1475 { return 0; }
dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg * hsotg,bool restore)1476 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1477 						      bool restore)
1478 { return 0; }
dwc2_gadget_enter_clock_gating(struct dwc2_hsotg * hsotg)1479 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_exit_clock_gating(struct dwc2_hsotg * hsotg,int rem_wakeup)1480 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1481 						 int rem_wakeup) {}
dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg * hsotg)1482 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1483 { return 0; }
dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg * hsotg)1484 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1485 { return 0; }
dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg * hsotg)1486 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1487 { return 0; }
dwc2_gadget_init_lpm(struct dwc2_hsotg * hsotg)1488 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_program_ref_clk(struct dwc2_hsotg * hsotg)1489 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
dwc2_clear_fifo_map(struct dwc2_hsotg * hsotg)1490 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {}
1491 #endif
1492 
1493 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1494 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1495 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1496 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1497 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1498 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1499 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1500 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex);
1501 int dwc2_port_resume(struct dwc2_hsotg *hsotg);
1502 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1503 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1504 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1505 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1506 			       int rem_wakeup, int reset);
1507 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1508 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1509 				      int rem_wakeup, bool restore);
1510 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg);
1511 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup);
1512 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1513 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1514 { schedule_work(&hsotg->phy_reset_work); }
1515 #else
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)1516 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1517 { return 0; }
dwc2_hcd_get_future_frame_number(struct dwc2_hsotg * hsotg,int us)1518 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1519 						   int us)
1520 { return 0; }
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1521 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1522 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1523 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)1524 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
dwc2_core_init(struct dwc2_hsotg * hsotg,bool initial_setup)1525 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1526 { return 0; }
dwc2_port_suspend(struct dwc2_hsotg * hsotg,u16 windex)1527 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1528 { return 0; }
dwc2_port_resume(struct dwc2_hsotg * hsotg)1529 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg)
1530 { return 0; }
dwc2_hcd_init(struct dwc2_hsotg * hsotg)1531 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1532 { return 0; }
dwc2_backup_host_registers(struct dwc2_hsotg * hsotg)1533 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1534 { return 0; }
dwc2_restore_host_registers(struct dwc2_hsotg * hsotg)1535 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1536 { return 0; }
dwc2_host_enter_hibernation(struct dwc2_hsotg * hsotg)1537 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1538 { return 0; }
dwc2_host_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1539 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1540 					     int rem_wakeup, int reset)
1541 { return 0; }
dwc2_host_enter_partial_power_down(struct dwc2_hsotg * hsotg)1542 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1543 { return 0; }
dwc2_host_exit_partial_power_down(struct dwc2_hsotg * hsotg,int rem_wakeup,bool restore)1544 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1545 						    int rem_wakeup, bool restore)
1546 { return 0; }
dwc2_host_enter_clock_gating(struct dwc2_hsotg * hsotg)1547 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
dwc2_host_exit_clock_gating(struct dwc2_hsotg * hsotg,int rem_wakeup)1548 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg,
1549 					       int rem_wakeup) {}
dwc2_host_can_poweroff_phy(struct dwc2_hsotg * dwc2)1550 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1551 { return false; }
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1552 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1553 
1554 #endif
1555 
1556 #endif /* __DWC2_CORE_H__ */
1557