1 /* 2 * File: mca.h 3 * Purpose: Machine check handling specific defines 4 * 5 * Copyright (C) 1999, 2004 Silicon Graphics, Inc. 6 * Copyright (C) Vijay Chander (vijay@engr.sgi.com) 7 * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com) 8 */ 9 10 #ifndef _ASM_IA64_MCA_H 11 #define _ASM_IA64_MCA_H 12 13 #if !defined(__ASSEMBLY__) 14 #include <linux/types.h> 15 #include <asm/param.h> 16 #include <asm/sal.h> 17 #include <asm/processor.h> 18 #include <asm/mca_asm.h> 19 20 #define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */ 21 22 typedef union cmcv_reg_u { 23 u64 cmcv_regval; 24 struct { 25 u64 cmcr_vector : 8; 26 u64 cmcr_reserved1 : 4; 27 u64 cmcr_ignored1 : 1; 28 u64 cmcr_reserved2 : 3; 29 u64 cmcr_mask : 1; 30 u64 cmcr_ignored2 : 47; 31 } cmcv_reg_s; 32 33 } cmcv_reg_t; 34 35 #define cmcv_mask cmcv_reg_s.cmcr_mask 36 #define cmcv_vector cmcv_reg_s.cmcr_vector 37 38 enum { 39 IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, 40 IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1 41 }; 42 43 /* the following data structure is used for TLB error recovery purposes */ 44 extern struct ia64_mca_tlb_info { 45 u64 cr_lid; 46 u64 percpu_paddr; 47 u64 ptce_base; 48 u32 ptce_count[2]; 49 u32 ptce_stride[2]; 50 u64 pal_paddr; 51 u64 pal_base; 52 } ia64_mca_tlb_list[NR_CPUS]; 53 54 /* Information maintained by the MC infrastructure */ 55 typedef struct ia64_mc_info_s { 56 u64 imi_mca_handler; 57 size_t imi_mca_handler_size; 58 u64 imi_monarch_init_handler; 59 size_t imi_monarch_init_handler_size; 60 u64 imi_slave_init_handler; 61 size_t imi_slave_init_handler_size; 62 u8 imi_rendez_checkin[NR_CPUS]; 63 64 } ia64_mc_info_t; 65 66 typedef struct ia64_mca_sal_to_os_state_s { 67 u64 imsto_os_gp; /* GP of the os registered with the SAL */ 68 u64 imsto_pal_proc; /* PAL_PROC entry point - physical addr */ 69 u64 imsto_sal_proc; /* SAL_PROC entry point - physical addr */ 70 u64 imsto_sal_gp; /* GP of the SAL - physical */ 71 u64 imsto_rendez_state; /* Rendez state information */ 72 u64 imsto_sal_check_ra; /* Return address in SAL_CHECK while going 73 * back to SAL from OS after MCA handling. 74 */ 75 u64 pal_min_state; /* from PAL in r17 */ 76 u64 proc_state_param; /* from PAL in r18. See SDV 2:268 11.3.2.1 */ 77 } ia64_mca_sal_to_os_state_t; 78 79 enum { 80 IA64_MCA_CORRECTED = 0x0, /* Error has been corrected by OS_MCA */ 81 IA64_MCA_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ 82 IA64_MCA_COLD_BOOT = -2, /* Cold boot of the system need from SAL */ 83 IA64_MCA_HALT = -3 /* System to be halted by SAL */ 84 }; 85 86 enum { 87 IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */ 88 IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ 89 }; 90 91 typedef struct ia64_mca_os_to_sal_state_s { 92 u64 imots_os_status; /* OS status to SAL as to what happened 93 * with the MCA handling. 94 */ 95 u64 imots_sal_gp; /* GP of the SAL - physical */ 96 u64 imots_context; /* 0 if return to same context 97 1 if return to new context */ 98 u64 *imots_new_min_state; /* Pointer to structure containing 99 * new values of registers in the min state 100 * save area. 101 */ 102 u64 imots_sal_check_ra; /* Return address in SAL_CHECK while going 103 * back to SAL from OS after MCA handling. 104 */ 105 } ia64_mca_os_to_sal_state_t; 106 107 extern void ia64_mca_init(void); 108 extern void ia64_os_mca_dispatch(void); 109 extern void ia64_os_mca_dispatch_end(void); 110 extern void ia64_mca_ucmc_handler(void); 111 extern void ia64_monarch_init_handler(void); 112 extern void ia64_slave_init_handler(void); 113 extern void ia64_mca_cmc_vector_setup(void); 114 115 #endif /* !__ASSEMBLY__ */ 116 #endif /* _ASM_IA64_MCA_H */ 117