1 /*
2 * Cell Internal Interrupt Controller
3 *
4 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * IBM, Corp.
6 *
7 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
8 *
9 * Author: Arnd Bergmann <arndb@de.ibm.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * TODO:
26 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
27 * vs node numbers in the setup code
28 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
29 * a non-active node to the active node)
30 */
31
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/export.h>
35 #include <linux/percpu.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/kernel_stat.h>
39
40 #include <asm/io.h>
41 #include <asm/pgtable.h>
42 #include <asm/prom.h>
43 #include <asm/ptrace.h>
44 #include <asm/machdep.h>
45 #include <asm/cell-regs.h>
46
47 #include "interrupt.h"
48
49 struct iic {
50 struct cbe_iic_thread_regs __iomem *regs;
51 u8 target_id;
52 u8 eoi_stack[16];
53 int eoi_ptr;
54 struct device_node *node;
55 };
56
57 static DEFINE_PER_CPU(struct iic, cpu_iic);
58 #define IIC_NODE_COUNT 2
59 static struct irq_domain *iic_host;
60
61 /* Convert between "pending" bits and hw irq number */
iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)62 static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
63 {
64 unsigned char unit = bits.source & 0xf;
65 unsigned char node = bits.source >> 4;
66 unsigned char class = bits.class & 3;
67
68 /* Decode IPIs */
69 if (bits.flags & CBE_IIC_IRQ_IPI)
70 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
71 else
72 return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
73 }
74
iic_mask(struct irq_data * d)75 static void iic_mask(struct irq_data *d)
76 {
77 }
78
iic_unmask(struct irq_data * d)79 static void iic_unmask(struct irq_data *d)
80 {
81 }
82
iic_eoi(struct irq_data * d)83 static void iic_eoi(struct irq_data *d)
84 {
85 struct iic *iic = &__get_cpu_var(cpu_iic);
86 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
87 BUG_ON(iic->eoi_ptr < 0);
88 }
89
90 static struct irq_chip iic_chip = {
91 .name = "CELL-IIC",
92 .irq_mask = iic_mask,
93 .irq_unmask = iic_unmask,
94 .irq_eoi = iic_eoi,
95 };
96
97
iic_ioexc_eoi(struct irq_data * d)98 static void iic_ioexc_eoi(struct irq_data *d)
99 {
100 }
101
iic_ioexc_cascade(unsigned int irq,struct irq_desc * desc)102 static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
103 {
104 struct irq_chip *chip = irq_desc_get_chip(desc);
105 struct cbe_iic_regs __iomem *node_iic =
106 (void __iomem *)irq_desc_get_handler_data(desc);
107 unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
108 unsigned long bits, ack;
109 int cascade;
110
111 for (;;) {
112 bits = in_be64(&node_iic->iic_is);
113 if (bits == 0)
114 break;
115 /* pre-ack edge interrupts */
116 ack = bits & IIC_ISR_EDGE_MASK;
117 if (ack)
118 out_be64(&node_iic->iic_is, ack);
119 /* handle them */
120 for (cascade = 63; cascade >= 0; cascade--)
121 if (bits & (0x8000000000000000UL >> cascade)) {
122 unsigned int cirq =
123 irq_linear_revmap(iic_host,
124 base | cascade);
125 if (cirq != NO_IRQ)
126 generic_handle_irq(cirq);
127 }
128 /* post-ack level interrupts */
129 ack = bits & ~IIC_ISR_EDGE_MASK;
130 if (ack)
131 out_be64(&node_iic->iic_is, ack);
132 }
133 chip->irq_eoi(&desc->irq_data);
134 }
135
136
137 static struct irq_chip iic_ioexc_chip = {
138 .name = "CELL-IOEX",
139 .irq_mask = iic_mask,
140 .irq_unmask = iic_unmask,
141 .irq_eoi = iic_ioexc_eoi,
142 };
143
144 /* Get an IRQ number from the pending state register of the IIC */
iic_get_irq(void)145 static unsigned int iic_get_irq(void)
146 {
147 struct cbe_iic_pending_bits pending;
148 struct iic *iic;
149 unsigned int virq;
150
151 iic = &__get_cpu_var(cpu_iic);
152 *(unsigned long *) &pending =
153 in_be64((u64 __iomem *) &iic->regs->pending_destr);
154 if (!(pending.flags & CBE_IIC_IRQ_VALID))
155 return NO_IRQ;
156 virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
157 if (virq == NO_IRQ)
158 return NO_IRQ;
159 iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
160 BUG_ON(iic->eoi_ptr > 15);
161 return virq;
162 }
163
iic_setup_cpu(void)164 void iic_setup_cpu(void)
165 {
166 out_be64(&__get_cpu_var(cpu_iic).regs->prio, 0xff);
167 }
168
iic_get_target_id(int cpu)169 u8 iic_get_target_id(int cpu)
170 {
171 return per_cpu(cpu_iic, cpu).target_id;
172 }
173
174 EXPORT_SYMBOL_GPL(iic_get_target_id);
175
176 #ifdef CONFIG_SMP
177
178 /* Use the highest interrupt priorities for IPI */
iic_msg_to_irq(int msg)179 static inline int iic_msg_to_irq(int msg)
180 {
181 return IIC_IRQ_TYPE_IPI + 0xf - msg;
182 }
183
iic_message_pass(int cpu,int msg)184 void iic_message_pass(int cpu, int msg)
185 {
186 out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
187 }
188
iic_get_irq_host(int node)189 struct irq_domain *iic_get_irq_host(int node)
190 {
191 return iic_host;
192 }
193 EXPORT_SYMBOL_GPL(iic_get_irq_host);
194
iic_request_ipi(int msg)195 static void iic_request_ipi(int msg)
196 {
197 int virq;
198
199 virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
200 if (virq == NO_IRQ) {
201 printk(KERN_ERR
202 "iic: failed to map IPI %s\n", smp_ipi_name[msg]);
203 return;
204 }
205
206 /*
207 * If smp_request_message_ipi encounters an error it will notify
208 * the error. If a message is not needed it will return non-zero.
209 */
210 if (smp_request_message_ipi(virq, msg))
211 irq_dispose_mapping(virq);
212 }
213
iic_request_IPIs(void)214 void iic_request_IPIs(void)
215 {
216 iic_request_ipi(PPC_MSG_CALL_FUNCTION);
217 iic_request_ipi(PPC_MSG_RESCHEDULE);
218 iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE);
219 iic_request_ipi(PPC_MSG_DEBUGGER_BREAK);
220 }
221
222 #endif /* CONFIG_SMP */
223
224
iic_host_match(struct irq_domain * h,struct device_node * node)225 static int iic_host_match(struct irq_domain *h, struct device_node *node)
226 {
227 return of_device_is_compatible(node,
228 "IBM,CBEA-Internal-Interrupt-Controller");
229 }
230
iic_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)231 static int iic_host_map(struct irq_domain *h, unsigned int virq,
232 irq_hw_number_t hw)
233 {
234 switch (hw & IIC_IRQ_TYPE_MASK) {
235 case IIC_IRQ_TYPE_IPI:
236 irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
237 break;
238 case IIC_IRQ_TYPE_IOEXC:
239 irq_set_chip_and_handler(virq, &iic_ioexc_chip,
240 handle_edge_eoi_irq);
241 break;
242 default:
243 irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
244 }
245 return 0;
246 }
247
iic_host_xlate(struct irq_domain * h,struct device_node * ct,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)248 static int iic_host_xlate(struct irq_domain *h, struct device_node *ct,
249 const u32 *intspec, unsigned int intsize,
250 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
251
252 {
253 unsigned int node, ext, unit, class;
254 const u32 *val;
255
256 if (!of_device_is_compatible(ct,
257 "IBM,CBEA-Internal-Interrupt-Controller"))
258 return -ENODEV;
259 if (intsize != 1)
260 return -ENODEV;
261 val = of_get_property(ct, "#interrupt-cells", NULL);
262 if (val == NULL || *val != 1)
263 return -ENODEV;
264
265 node = intspec[0] >> 24;
266 ext = (intspec[0] >> 16) & 0xff;
267 class = (intspec[0] >> 8) & 0xff;
268 unit = intspec[0] & 0xff;
269
270 /* Check if node is in supported range */
271 if (node > 1)
272 return -EINVAL;
273
274 /* Build up interrupt number, special case for IO exceptions */
275 *out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
276 if (unit == IIC_UNIT_IIC && class == 1)
277 *out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
278 else
279 *out_hwirq |= IIC_IRQ_TYPE_NORMAL |
280 (class << IIC_IRQ_CLASS_SHIFT) | unit;
281
282 /* Dummy flags, ignored by iic code */
283 *out_flags = IRQ_TYPE_EDGE_RISING;
284
285 return 0;
286 }
287
288 static const struct irq_domain_ops iic_host_ops = {
289 .match = iic_host_match,
290 .map = iic_host_map,
291 .xlate = iic_host_xlate,
292 };
293
init_one_iic(unsigned int hw_cpu,unsigned long addr,struct device_node * node)294 static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
295 struct device_node *node)
296 {
297 /* XXX FIXME: should locate the linux CPU number from the HW cpu
298 * number properly. We are lucky for now
299 */
300 struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
301
302 iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
303 BUG_ON(iic->regs == NULL);
304
305 iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
306 iic->eoi_stack[0] = 0xff;
307 iic->node = of_node_get(node);
308 out_be64(&iic->regs->prio, 0);
309
310 printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
311 hw_cpu, iic->target_id, node->full_name);
312 }
313
setup_iic(void)314 static int __init setup_iic(void)
315 {
316 struct device_node *dn;
317 struct resource r0, r1;
318 unsigned int node, cascade, found = 0;
319 struct cbe_iic_regs __iomem *node_iic;
320 const u32 *np;
321
322 for (dn = NULL;
323 (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
324 if (!of_device_is_compatible(dn,
325 "IBM,CBEA-Internal-Interrupt-Controller"))
326 continue;
327 np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
328 if (np == NULL) {
329 printk(KERN_WARNING "IIC: CPU association not found\n");
330 of_node_put(dn);
331 return -ENODEV;
332 }
333 if (of_address_to_resource(dn, 0, &r0) ||
334 of_address_to_resource(dn, 1, &r1)) {
335 printk(KERN_WARNING "IIC: Can't resolve addresses\n");
336 of_node_put(dn);
337 return -ENODEV;
338 }
339 found++;
340 init_one_iic(np[0], r0.start, dn);
341 init_one_iic(np[1], r1.start, dn);
342
343 /* Setup cascade for IO exceptions. XXX cleanup tricks to get
344 * node vs CPU etc...
345 * Note that we configure the IIC_IRR here with a hard coded
346 * priority of 1. We might want to improve that later.
347 */
348 node = np[0] >> 1;
349 node_iic = cbe_get_cpu_iic_regs(np[0]);
350 cascade = node << IIC_IRQ_NODE_SHIFT;
351 cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
352 cascade |= IIC_UNIT_IIC;
353 cascade = irq_create_mapping(iic_host, cascade);
354 if (cascade == NO_IRQ)
355 continue;
356 /*
357 * irq_data is a generic pointer that gets passed back
358 * to us later, so the forced cast is fine.
359 */
360 irq_set_handler_data(cascade, (void __force *)node_iic);
361 irq_set_chained_handler(cascade, iic_ioexc_cascade);
362 out_be64(&node_iic->iic_ir,
363 (1 << 12) /* priority */ |
364 (node << 4) /* dest node */ |
365 IIC_UNIT_THREAD_0 /* route them to thread 0 */);
366 /* Flush pending (make sure it triggers if there is
367 * anything pending
368 */
369 out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
370 }
371
372 if (found)
373 return 0;
374 else
375 return -ENODEV;
376 }
377
iic_init_IRQ(void)378 void __init iic_init_IRQ(void)
379 {
380 /* Setup an irq host data structure */
381 iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops,
382 NULL);
383 BUG_ON(iic_host == NULL);
384 irq_set_default_host(iic_host);
385
386 /* Discover and initialize iics */
387 if (setup_iic() < 0)
388 panic("IIC: Failed to initialize !\n");
389
390 /* Set master interrupt handling function */
391 ppc_md.get_irq = iic_get_irq;
392
393 /* Enable on current CPU */
394 iic_setup_cpu();
395 }
396
iic_set_interrupt_routing(int cpu,int thread,int priority)397 void iic_set_interrupt_routing(int cpu, int thread, int priority)
398 {
399 struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
400 u64 iic_ir = 0;
401 int node = cpu >> 1;
402
403 /* Set which node and thread will handle the next interrupt */
404 iic_ir |= CBE_IIC_IR_PRIO(priority) |
405 CBE_IIC_IR_DEST_NODE(node);
406 if (thread == 0)
407 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
408 else
409 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
410 out_be64(&iic_regs->iic_ir, iic_ir);
411 }
412