1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
3
4 #include "igc.h"
5
6 #include <linux/module.h>
7 #include <linux/device.h>
8 #include <linux/pci.h>
9 #include <linux/ptp_classify.h>
10 #include <linux/clocksource.h>
11 #include <linux/ktime.h>
12 #include <linux/delay.h>
13 #include <linux/iopoll.h>
14
15 #define INCVALUE_MASK 0x7fffffff
16 #define ISGN 0x80000000
17
18 #define IGC_PTP_TX_TIMEOUT (HZ * 15)
19
20 #define IGC_PTM_STAT_SLEEP 2
21 #define IGC_PTM_STAT_TIMEOUT 100
22
23 /* SYSTIM read access for I225 */
igc_ptp_read(struct igc_adapter * adapter,struct timespec64 * ts)24 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
25 {
26 struct igc_hw *hw = &adapter->hw;
27 u32 sec, nsec;
28
29 /* The timestamp is latched when SYSTIML is read. */
30 nsec = rd32(IGC_SYSTIML);
31 sec = rd32(IGC_SYSTIMH);
32
33 ts->tv_sec = sec;
34 ts->tv_nsec = nsec;
35 }
36
igc_ptp_write_i225(struct igc_adapter * adapter,const struct timespec64 * ts)37 static void igc_ptp_write_i225(struct igc_adapter *adapter,
38 const struct timespec64 *ts)
39 {
40 struct igc_hw *hw = &adapter->hw;
41
42 wr32(IGC_SYSTIML, ts->tv_nsec);
43 wr32(IGC_SYSTIMH, ts->tv_sec);
44 }
45
igc_ptp_adjfine_i225(struct ptp_clock_info * ptp,long scaled_ppm)46 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
47 {
48 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
49 ptp_caps);
50 struct igc_hw *hw = &igc->hw;
51 int neg_adj = 0;
52 u64 rate;
53 u32 inca;
54
55 if (scaled_ppm < 0) {
56 neg_adj = 1;
57 scaled_ppm = -scaled_ppm;
58 }
59 rate = scaled_ppm;
60 rate <<= 14;
61 rate = div_u64(rate, 78125);
62
63 inca = rate & INCVALUE_MASK;
64 if (neg_adj)
65 inca |= ISGN;
66
67 wr32(IGC_TIMINCA, inca);
68
69 return 0;
70 }
71
igc_ptp_adjtime_i225(struct ptp_clock_info * ptp,s64 delta)72 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
73 {
74 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
75 ptp_caps);
76 struct timespec64 now, then = ns_to_timespec64(delta);
77 unsigned long flags;
78
79 spin_lock_irqsave(&igc->tmreg_lock, flags);
80
81 igc_ptp_read(igc, &now);
82 now = timespec64_add(now, then);
83 igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
84
85 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
86
87 return 0;
88 }
89
igc_ptp_gettimex64_i225(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)90 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
91 struct timespec64 *ts,
92 struct ptp_system_timestamp *sts)
93 {
94 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
95 ptp_caps);
96 struct igc_hw *hw = &igc->hw;
97 unsigned long flags;
98
99 spin_lock_irqsave(&igc->tmreg_lock, flags);
100
101 ptp_read_system_prets(sts);
102 ts->tv_nsec = rd32(IGC_SYSTIML);
103 ts->tv_sec = rd32(IGC_SYSTIMH);
104 ptp_read_system_postts(sts);
105
106 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
107
108 return 0;
109 }
110
igc_ptp_settime_i225(struct ptp_clock_info * ptp,const struct timespec64 * ts)111 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
112 const struct timespec64 *ts)
113 {
114 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
115 ptp_caps);
116 unsigned long flags;
117
118 spin_lock_irqsave(&igc->tmreg_lock, flags);
119
120 igc_ptp_write_i225(igc, ts);
121
122 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
123
124 return 0;
125 }
126
igc_pin_direction(int pin,int input,u32 * ctrl,u32 * ctrl_ext)127 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
128 {
129 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
130 static const u32 mask[IGC_N_SDP] = {
131 IGC_CTRL_SDP0_DIR,
132 IGC_CTRL_SDP1_DIR,
133 IGC_CTRL_EXT_SDP2_DIR,
134 IGC_CTRL_EXT_SDP3_DIR,
135 };
136
137 if (input)
138 *ptr &= ~mask[pin];
139 else
140 *ptr |= mask[pin];
141 }
142
igc_pin_perout(struct igc_adapter * igc,int chan,int pin,int freq)143 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
144 {
145 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
146 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
147 };
148 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
149 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
150 };
151 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
152 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
153 };
154 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
155 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
156 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
157 };
158 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
159 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
160 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
161 };
162 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
163 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
164 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
165 };
166 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
167 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
168 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
169 };
170 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
171 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
172 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
173 };
174 struct igc_hw *hw = &igc->hw;
175 u32 ctrl, ctrl_ext, tssdp = 0;
176
177 ctrl = rd32(IGC_CTRL);
178 ctrl_ext = rd32(IGC_CTRL_EXT);
179 tssdp = rd32(IGC_TSSDP);
180
181 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
182
183 /* Make sure this pin is not enabled as an input. */
184 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
185 tssdp &= ~IGC_AUX0_TS_SDP_EN;
186
187 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
188 tssdp &= ~IGC_AUX1_TS_SDP_EN;
189
190 tssdp &= ~igc_ts_sdp_sel_clr[pin];
191 if (freq) {
192 if (chan == 1)
193 tssdp |= igc_ts_sdp_sel_fc1[pin];
194 else
195 tssdp |= igc_ts_sdp_sel_fc0[pin];
196 } else {
197 if (chan == 1)
198 tssdp |= igc_ts_sdp_sel_tt1[pin];
199 else
200 tssdp |= igc_ts_sdp_sel_tt0[pin];
201 }
202 tssdp |= igc_ts_sdp_en[pin];
203
204 wr32(IGC_TSSDP, tssdp);
205 wr32(IGC_CTRL, ctrl);
206 wr32(IGC_CTRL_EXT, ctrl_ext);
207 }
208
igc_pin_extts(struct igc_adapter * igc,int chan,int pin)209 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
210 {
211 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
212 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
213 };
214 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
215 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
216 };
217 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
218 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
219 };
220 struct igc_hw *hw = &igc->hw;
221 u32 ctrl, ctrl_ext, tssdp = 0;
222
223 ctrl = rd32(IGC_CTRL);
224 ctrl_ext = rd32(IGC_CTRL_EXT);
225 tssdp = rd32(IGC_TSSDP);
226
227 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
228
229 /* Make sure this pin is not enabled as an output. */
230 tssdp &= ~igc_ts_sdp_en[pin];
231
232 if (chan == 1) {
233 tssdp &= ~IGC_AUX1_SEL_SDP3;
234 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
235 } else {
236 tssdp &= ~IGC_AUX0_SEL_SDP3;
237 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
238 }
239
240 wr32(IGC_TSSDP, tssdp);
241 wr32(IGC_CTRL, ctrl);
242 wr32(IGC_CTRL_EXT, ctrl_ext);
243 }
244
igc_ptp_feature_enable_i225(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)245 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
246 struct ptp_clock_request *rq, int on)
247 {
248 struct igc_adapter *igc =
249 container_of(ptp, struct igc_adapter, ptp_caps);
250 struct igc_hw *hw = &igc->hw;
251 unsigned long flags;
252 struct timespec64 ts;
253 int use_freq = 0, pin = -1;
254 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
255 s64 ns;
256
257 switch (rq->type) {
258 case PTP_CLK_REQ_EXTTS:
259 /* Reject requests with unsupported flags */
260 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
261 PTP_RISING_EDGE |
262 PTP_FALLING_EDGE |
263 PTP_STRICT_FLAGS))
264 return -EOPNOTSUPP;
265
266 /* Reject requests failing to enable both edges. */
267 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
268 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
269 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
270 return -EOPNOTSUPP;
271
272 if (on) {
273 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
274 rq->extts.index);
275 if (pin < 0)
276 return -EBUSY;
277 }
278 if (rq->extts.index == 1) {
279 tsauxc_mask = IGC_TSAUXC_EN_TS1;
280 tsim_mask = IGC_TSICR_AUTT1;
281 } else {
282 tsauxc_mask = IGC_TSAUXC_EN_TS0;
283 tsim_mask = IGC_TSICR_AUTT0;
284 }
285 spin_lock_irqsave(&igc->tmreg_lock, flags);
286 tsauxc = rd32(IGC_TSAUXC);
287 tsim = rd32(IGC_TSIM);
288 if (on) {
289 igc_pin_extts(igc, rq->extts.index, pin);
290 tsauxc |= tsauxc_mask;
291 tsim |= tsim_mask;
292 } else {
293 tsauxc &= ~tsauxc_mask;
294 tsim &= ~tsim_mask;
295 }
296 wr32(IGC_TSAUXC, tsauxc);
297 wr32(IGC_TSIM, tsim);
298 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
299 return 0;
300
301 case PTP_CLK_REQ_PEROUT:
302 /* Reject requests with unsupported flags */
303 if (rq->perout.flags)
304 return -EOPNOTSUPP;
305
306 if (on) {
307 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
308 rq->perout.index);
309 if (pin < 0)
310 return -EBUSY;
311 }
312 ts.tv_sec = rq->perout.period.sec;
313 ts.tv_nsec = rq->perout.period.nsec;
314 ns = timespec64_to_ns(&ts);
315 ns = ns >> 1;
316 if (on && (ns <= 70000000LL || ns == 125000000LL ||
317 ns == 250000000LL || ns == 500000000LL)) {
318 if (ns < 8LL)
319 return -EINVAL;
320 use_freq = 1;
321 }
322 ts = ns_to_timespec64(ns);
323 if (rq->perout.index == 1) {
324 if (use_freq) {
325 tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1;
326 tsim_mask = 0;
327 } else {
328 tsauxc_mask = IGC_TSAUXC_EN_TT1;
329 tsim_mask = IGC_TSICR_TT1;
330 }
331 trgttiml = IGC_TRGTTIML1;
332 trgttimh = IGC_TRGTTIMH1;
333 freqout = IGC_FREQOUT1;
334 } else {
335 if (use_freq) {
336 tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0;
337 tsim_mask = 0;
338 } else {
339 tsauxc_mask = IGC_TSAUXC_EN_TT0;
340 tsim_mask = IGC_TSICR_TT0;
341 }
342 trgttiml = IGC_TRGTTIML0;
343 trgttimh = IGC_TRGTTIMH0;
344 freqout = IGC_FREQOUT0;
345 }
346 spin_lock_irqsave(&igc->tmreg_lock, flags);
347 tsauxc = rd32(IGC_TSAUXC);
348 tsim = rd32(IGC_TSIM);
349 if (rq->perout.index == 1) {
350 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 |
351 IGC_TSAUXC_ST1);
352 tsim &= ~IGC_TSICR_TT1;
353 } else {
354 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 |
355 IGC_TSAUXC_ST0);
356 tsim &= ~IGC_TSICR_TT0;
357 }
358 if (on) {
359 int i = rq->perout.index;
360
361 igc_pin_perout(igc, i, pin, use_freq);
362 igc->perout[i].start.tv_sec = rq->perout.start.sec;
363 igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
364 igc->perout[i].period.tv_sec = ts.tv_sec;
365 igc->perout[i].period.tv_nsec = ts.tv_nsec;
366 wr32(trgttimh, rq->perout.start.sec);
367 /* For now, always select timer 0 as source. */
368 wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
369 if (use_freq)
370 wr32(freqout, ns);
371 tsauxc |= tsauxc_mask;
372 tsim |= tsim_mask;
373 }
374 wr32(IGC_TSAUXC, tsauxc);
375 wr32(IGC_TSIM, tsim);
376 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
377 return 0;
378
379 case PTP_CLK_REQ_PPS:
380 spin_lock_irqsave(&igc->tmreg_lock, flags);
381 tsim = rd32(IGC_TSIM);
382 if (on)
383 tsim |= IGC_TSICR_SYS_WRAP;
384 else
385 tsim &= ~IGC_TSICR_SYS_WRAP;
386 igc->pps_sys_wrap_on = on;
387 wr32(IGC_TSIM, tsim);
388 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
389 return 0;
390
391 default:
392 break;
393 }
394
395 return -EOPNOTSUPP;
396 }
397
igc_ptp_verify_pin(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)398 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
399 enum ptp_pin_function func, unsigned int chan)
400 {
401 switch (func) {
402 case PTP_PF_NONE:
403 case PTP_PF_EXTTS:
404 case PTP_PF_PEROUT:
405 break;
406 case PTP_PF_PHYSYNC:
407 return -1;
408 }
409 return 0;
410 }
411
412 /**
413 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
414 * @adapter: board private structure
415 * @hwtstamps: timestamp structure to update
416 * @systim: unsigned 64bit system time value
417 *
418 * We need to convert the system time value stored in the RX/TXSTMP registers
419 * into a hwtstamp which can be used by the upper level timestamping functions.
420 **/
igc_ptp_systim_to_hwtstamp(struct igc_adapter * adapter,struct skb_shared_hwtstamps * hwtstamps,u64 systim)421 static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
422 struct skb_shared_hwtstamps *hwtstamps,
423 u64 systim)
424 {
425 switch (adapter->hw.mac.type) {
426 case igc_i225:
427 memset(hwtstamps, 0, sizeof(*hwtstamps));
428 /* Upper 32 bits contain s, lower 32 bits contain ns. */
429 hwtstamps->hwtstamp = ktime_set(systim >> 32,
430 systim & 0xFFFFFFFF);
431 break;
432 default:
433 break;
434 }
435 }
436
437 /**
438 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
439 * @adapter: Pointer to adapter the packet buffer belongs to
440 * @buf: Pointer to packet buffer
441 *
442 * This function retrieves the timestamp saved in the beginning of packet
443 * buffer. While two timestamps are available, one in timer0 reference and the
444 * other in timer1 reference, this function considers only the timestamp in
445 * timer0 reference.
446 *
447 * Returns timestamp value.
448 */
igc_ptp_rx_pktstamp(struct igc_adapter * adapter,__le32 * buf)449 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
450 {
451 ktime_t timestamp;
452 u32 secs, nsecs;
453 int adjust;
454
455 /* Timestamps are saved in little endian at the beginning of the packet
456 * buffer following the layout:
457 *
458 * DWORD: | 0 | 1 | 2 | 3 |
459 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
460 *
461 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
462 * part of the timestamp.
463 */
464 nsecs = le32_to_cpu(buf[2]);
465 secs = le32_to_cpu(buf[3]);
466
467 timestamp = ktime_set(secs, nsecs);
468
469 /* Adjust timestamp for the RX latency based on link speed */
470 switch (adapter->link_speed) {
471 case SPEED_10:
472 adjust = IGC_I225_RX_LATENCY_10;
473 break;
474 case SPEED_100:
475 adjust = IGC_I225_RX_LATENCY_100;
476 break;
477 case SPEED_1000:
478 adjust = IGC_I225_RX_LATENCY_1000;
479 break;
480 case SPEED_2500:
481 adjust = IGC_I225_RX_LATENCY_2500;
482 break;
483 default:
484 adjust = 0;
485 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
486 break;
487 }
488
489 return ktime_sub_ns(timestamp, adjust);
490 }
491
igc_ptp_disable_rx_timestamp(struct igc_adapter * adapter)492 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
493 {
494 struct igc_hw *hw = &adapter->hw;
495 u32 val;
496 int i;
497
498 wr32(IGC_TSYNCRXCTL, 0);
499
500 for (i = 0; i < adapter->num_rx_queues; i++) {
501 val = rd32(IGC_SRRCTL(i));
502 val &= ~IGC_SRRCTL_TIMESTAMP;
503 wr32(IGC_SRRCTL(i), val);
504 }
505
506 val = rd32(IGC_RXPBS);
507 val &= ~IGC_RXPBS_CFG_TS_EN;
508 wr32(IGC_RXPBS, val);
509 }
510
igc_ptp_enable_rx_timestamp(struct igc_adapter * adapter)511 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
512 {
513 struct igc_hw *hw = &adapter->hw;
514 u32 val;
515 int i;
516
517 val = rd32(IGC_RXPBS);
518 val |= IGC_RXPBS_CFG_TS_EN;
519 wr32(IGC_RXPBS, val);
520
521 for (i = 0; i < adapter->num_rx_queues; i++) {
522 val = rd32(IGC_SRRCTL(i));
523 /* FIXME: For now, only support retrieving RX timestamps from
524 * timer 0.
525 */
526 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
527 IGC_SRRCTL_TIMESTAMP;
528 wr32(IGC_SRRCTL(i), val);
529 }
530
531 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
532 IGC_TSYNCRXCTL_RXSYNSIG;
533 wr32(IGC_TSYNCRXCTL, val);
534 }
535
igc_ptp_disable_tx_timestamp(struct igc_adapter * adapter)536 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
537 {
538 struct igc_hw *hw = &adapter->hw;
539
540 wr32(IGC_TSYNCTXCTL, 0);
541 }
542
igc_ptp_enable_tx_timestamp(struct igc_adapter * adapter)543 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
544 {
545 struct igc_hw *hw = &adapter->hw;
546
547 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
548
549 /* Read TXSTMP registers to discard any timestamp previously stored. */
550 rd32(IGC_TXSTMPL);
551 rd32(IGC_TXSTMPH);
552 }
553
554 /**
555 * igc_ptp_set_timestamp_mode - setup hardware for timestamping
556 * @adapter: networking device structure
557 * @config: hwtstamp configuration
558 *
559 * Return: 0 in case of success, negative errno code otherwise.
560 */
igc_ptp_set_timestamp_mode(struct igc_adapter * adapter,struct hwtstamp_config * config)561 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
562 struct hwtstamp_config *config)
563 {
564 switch (config->tx_type) {
565 case HWTSTAMP_TX_OFF:
566 igc_ptp_disable_tx_timestamp(adapter);
567 break;
568 case HWTSTAMP_TX_ON:
569 igc_ptp_enable_tx_timestamp(adapter);
570 break;
571 default:
572 return -ERANGE;
573 }
574
575 switch (config->rx_filter) {
576 case HWTSTAMP_FILTER_NONE:
577 igc_ptp_disable_rx_timestamp(adapter);
578 break;
579 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
580 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
581 case HWTSTAMP_FILTER_PTP_V2_EVENT:
582 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
583 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
584 case HWTSTAMP_FILTER_PTP_V2_SYNC:
585 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
586 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
587 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
588 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
589 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
590 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
591 case HWTSTAMP_FILTER_NTP_ALL:
592 case HWTSTAMP_FILTER_ALL:
593 igc_ptp_enable_rx_timestamp(adapter);
594 config->rx_filter = HWTSTAMP_FILTER_ALL;
595 break;
596 default:
597 return -ERANGE;
598 }
599
600 return 0;
601 }
602
igc_ptp_tx_timeout(struct igc_adapter * adapter)603 static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
604 {
605 struct igc_hw *hw = &adapter->hw;
606
607 dev_kfree_skb_any(adapter->ptp_tx_skb);
608 adapter->ptp_tx_skb = NULL;
609 adapter->tx_hwtstamp_timeouts++;
610 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
611 /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
612 rd32(IGC_TXSTMPH);
613 netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
614 }
615
igc_ptp_tx_hang(struct igc_adapter * adapter)616 void igc_ptp_tx_hang(struct igc_adapter *adapter)
617 {
618 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
619 IGC_PTP_TX_TIMEOUT);
620
621 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
622 return;
623
624 /* If we haven't received a timestamp within the timeout, it is
625 * reasonable to assume that it will never occur, so we can unlock the
626 * timestamp bit when this occurs.
627 */
628 if (timeout) {
629 cancel_work_sync(&adapter->ptp_tx_work);
630 igc_ptp_tx_timeout(adapter);
631 }
632 }
633
634 /**
635 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
636 * @adapter: Board private structure
637 *
638 * If we were asked to do hardware stamping and such a time stamp is
639 * available, then it must have been for this skb here because we only
640 * allow only one such packet into the queue.
641 */
igc_ptp_tx_hwtstamp(struct igc_adapter * adapter)642 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
643 {
644 struct sk_buff *skb = adapter->ptp_tx_skb;
645 struct skb_shared_hwtstamps shhwtstamps;
646 struct igc_hw *hw = &adapter->hw;
647 int adjust = 0;
648 u64 regval;
649
650 if (WARN_ON_ONCE(!skb))
651 return;
652
653 regval = rd32(IGC_TXSTMPL);
654 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
655 igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
656
657 switch (adapter->link_speed) {
658 case SPEED_10:
659 adjust = IGC_I225_TX_LATENCY_10;
660 break;
661 case SPEED_100:
662 adjust = IGC_I225_TX_LATENCY_100;
663 break;
664 case SPEED_1000:
665 adjust = IGC_I225_TX_LATENCY_1000;
666 break;
667 case SPEED_2500:
668 adjust = IGC_I225_TX_LATENCY_2500;
669 break;
670 }
671
672 shhwtstamps.hwtstamp =
673 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
674
675 /* Clear the lock early before calling skb_tstamp_tx so that
676 * applications are not woken up before the lock bit is clear. We use
677 * a copy of the skb pointer to ensure other threads can't change it
678 * while we're notifying the stack.
679 */
680 adapter->ptp_tx_skb = NULL;
681 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
682
683 /* Notify the stack and free the skb after we've unlocked */
684 skb_tstamp_tx(skb, &shhwtstamps);
685 dev_kfree_skb_any(skb);
686 }
687
688 /**
689 * igc_ptp_tx_work
690 * @work: pointer to work struct
691 *
692 * This work function polls the TSYNCTXCTL valid bit to determine when a
693 * timestamp has been taken for the current stored skb.
694 */
igc_ptp_tx_work(struct work_struct * work)695 static void igc_ptp_tx_work(struct work_struct *work)
696 {
697 struct igc_adapter *adapter = container_of(work, struct igc_adapter,
698 ptp_tx_work);
699 struct igc_hw *hw = &adapter->hw;
700 u32 tsynctxctl;
701
702 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
703 return;
704
705 tsynctxctl = rd32(IGC_TSYNCTXCTL);
706 if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0)))
707 return;
708
709 igc_ptp_tx_hwtstamp(adapter);
710 }
711
712 /**
713 * igc_ptp_set_ts_config - set hardware time stamping config
714 * @netdev: network interface device structure
715 * @ifr: interface request data
716 *
717 **/
igc_ptp_set_ts_config(struct net_device * netdev,struct ifreq * ifr)718 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
719 {
720 struct igc_adapter *adapter = netdev_priv(netdev);
721 struct hwtstamp_config config;
722 int err;
723
724 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
725 return -EFAULT;
726
727 err = igc_ptp_set_timestamp_mode(adapter, &config);
728 if (err)
729 return err;
730
731 /* save these settings for future reference */
732 memcpy(&adapter->tstamp_config, &config,
733 sizeof(adapter->tstamp_config));
734
735 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
736 -EFAULT : 0;
737 }
738
739 /**
740 * igc_ptp_get_ts_config - get hardware time stamping config
741 * @netdev: network interface device structure
742 * @ifr: interface request data
743 *
744 * Get the hwtstamp_config settings to return to the user. Rather than attempt
745 * to deconstruct the settings from the registers, just return a shadow copy
746 * of the last known settings.
747 **/
igc_ptp_get_ts_config(struct net_device * netdev,struct ifreq * ifr)748 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
749 {
750 struct igc_adapter *adapter = netdev_priv(netdev);
751 struct hwtstamp_config *config = &adapter->tstamp_config;
752
753 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
754 -EFAULT : 0;
755 }
756
757 /* The two conditions below must be met for cross timestamping via
758 * PCIe PTM:
759 *
760 * 1. We have an way to convert the timestamps in the PTM messages
761 * to something related to the system clocks (right now, only
762 * X86 systems with support for the Always Running Timer allow that);
763 *
764 * 2. We have PTM enabled in the path from the device to the PCIe root port.
765 */
igc_is_crosststamp_supported(struct igc_adapter * adapter)766 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
767 {
768 if (!IS_ENABLED(CONFIG_X86_TSC))
769 return false;
770
771 /* FIXME: it was noticed that enabling support for PCIe PTM in
772 * some i225-V models could cause lockups when bringing the
773 * interface up/down. There should be no downsides to
774 * disabling crosstimestamping support for i225-V, as it
775 * doesn't have any PTP support. That way we gain some time
776 * while root causing the issue.
777 */
778 if (adapter->pdev->device == IGC_DEV_ID_I225_V)
779 return false;
780
781 return pcie_ptm_enabled(adapter->pdev);
782 }
783
igc_device_tstamp_to_system(u64 tstamp)784 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
785 {
786 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
787 return convert_art_ns_to_tsc(tstamp);
788 #else
789 return (struct system_counterval_t) { };
790 #endif
791 }
792
igc_ptm_log_error(struct igc_adapter * adapter,u32 ptm_stat)793 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
794 {
795 struct net_device *netdev = adapter->netdev;
796
797 switch (ptm_stat) {
798 case IGC_PTM_STAT_RET_ERR:
799 netdev_err(netdev, "PTM Error: Root port timeout\n");
800 break;
801 case IGC_PTM_STAT_BAD_PTM_RES:
802 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
803 break;
804 case IGC_PTM_STAT_T4M1_OVFL:
805 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
806 break;
807 case IGC_PTM_STAT_ADJUST_1ST:
808 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
809 break;
810 case IGC_PTM_STAT_ADJUST_CYC:
811 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
812 break;
813 default:
814 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
815 break;
816 }
817 }
818
igc_phc_get_syncdevicetime(ktime_t * device,struct system_counterval_t * system,void * ctx)819 static int igc_phc_get_syncdevicetime(ktime_t *device,
820 struct system_counterval_t *system,
821 void *ctx)
822 {
823 u32 stat, t2_curr_h, t2_curr_l, ctrl;
824 struct igc_adapter *adapter = ctx;
825 struct igc_hw *hw = &adapter->hw;
826 int err, count = 100;
827 ktime_t t1, t2_curr;
828
829 /* Get a snapshot of system clocks to use as historic value. */
830 ktime_get_snapshot(&adapter->snapshot);
831
832 do {
833 /* Doing this in a loop because in the event of a
834 * badly timed (ha!) system clock adjustment, we may
835 * get PTM errors from the PCI root, but these errors
836 * are transitory. Repeating the process returns valid
837 * data eventually.
838 */
839
840 /* To "manually" start the PTM cycle we need to clear and
841 * then set again the TRIG bit.
842 */
843 ctrl = rd32(IGC_PTM_CTRL);
844 ctrl &= ~IGC_PTM_CTRL_TRIG;
845 wr32(IGC_PTM_CTRL, ctrl);
846 ctrl |= IGC_PTM_CTRL_TRIG;
847 wr32(IGC_PTM_CTRL, ctrl);
848
849 /* The cycle only starts "for real" when software notifies
850 * that it has read the registers, this is done by setting
851 * VALID bit.
852 */
853 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
854
855 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
856 stat, IGC_PTM_STAT_SLEEP,
857 IGC_PTM_STAT_TIMEOUT);
858 if (err < 0) {
859 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
860 return err;
861 }
862
863 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
864 break;
865
866 if (stat & ~IGC_PTM_STAT_VALID) {
867 /* An error occurred, log it. */
868 igc_ptm_log_error(adapter, stat);
869 /* The STAT register is write-1-to-clear (W1C),
870 * so write the previous error status to clear it.
871 */
872 wr32(IGC_PTM_STAT, stat);
873 continue;
874 }
875 } while (--count);
876
877 if (!count) {
878 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
879 return -ETIMEDOUT;
880 }
881
882 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
883
884 t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
885 t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
886
887 /* FIXME: When the register that tells the endianness of the
888 * PTM registers are implemented, check them here and add the
889 * appropriate conversion.
890 */
891 t2_curr_h = swab32(t2_curr_h);
892
893 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
894
895 *device = t1;
896 *system = igc_device_tstamp_to_system(t2_curr);
897
898 return 0;
899 }
900
igc_ptp_getcrosststamp(struct ptp_clock_info * ptp,struct system_device_crosststamp * cts)901 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
902 struct system_device_crosststamp *cts)
903 {
904 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
905 ptp_caps);
906
907 return get_device_system_crosststamp(igc_phc_get_syncdevicetime,
908 adapter, &adapter->snapshot, cts);
909 }
910
911 /**
912 * igc_ptp_init - Initialize PTP functionality
913 * @adapter: Board private structure
914 *
915 * This function is called at device probe to initialize the PTP
916 * functionality.
917 */
igc_ptp_init(struct igc_adapter * adapter)918 void igc_ptp_init(struct igc_adapter *adapter)
919 {
920 struct net_device *netdev = adapter->netdev;
921 struct igc_hw *hw = &adapter->hw;
922 int i;
923
924 switch (hw->mac.type) {
925 case igc_i225:
926 for (i = 0; i < IGC_N_SDP; i++) {
927 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
928
929 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
930 ppd->index = i;
931 ppd->func = PTP_PF_NONE;
932 }
933 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
934 adapter->ptp_caps.owner = THIS_MODULE;
935 adapter->ptp_caps.max_adj = 62499999;
936 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
937 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
938 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
939 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
940 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
941 adapter->ptp_caps.pps = 1;
942 adapter->ptp_caps.pin_config = adapter->sdp_config;
943 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
944 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
945 adapter->ptp_caps.n_pins = IGC_N_SDP;
946 adapter->ptp_caps.verify = igc_ptp_verify_pin;
947
948 if (!igc_is_crosststamp_supported(adapter))
949 break;
950
951 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
952 break;
953 default:
954 adapter->ptp_clock = NULL;
955 return;
956 }
957
958 spin_lock_init(&adapter->tmreg_lock);
959 INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work);
960
961 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
962 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
963
964 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
965 adapter->ptp_reset_start = ktime_get();
966
967 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
968 &adapter->pdev->dev);
969 if (IS_ERR(adapter->ptp_clock)) {
970 adapter->ptp_clock = NULL;
971 netdev_err(netdev, "ptp_clock_register failed\n");
972 } else if (adapter->ptp_clock) {
973 netdev_info(netdev, "PHC added\n");
974 adapter->ptp_flags |= IGC_PTP_ENABLED;
975 }
976 }
977
igc_ptp_time_save(struct igc_adapter * adapter)978 static void igc_ptp_time_save(struct igc_adapter *adapter)
979 {
980 igc_ptp_read(adapter, &adapter->prev_ptp_time);
981 adapter->ptp_reset_start = ktime_get();
982 }
983
igc_ptp_time_restore(struct igc_adapter * adapter)984 static void igc_ptp_time_restore(struct igc_adapter *adapter)
985 {
986 struct timespec64 ts = adapter->prev_ptp_time;
987 ktime_t delta;
988
989 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
990
991 timespec64_add_ns(&ts, ktime_to_ns(delta));
992
993 igc_ptp_write_i225(adapter, &ts);
994 }
995
igc_ptm_stop(struct igc_adapter * adapter)996 static void igc_ptm_stop(struct igc_adapter *adapter)
997 {
998 struct igc_hw *hw = &adapter->hw;
999 u32 ctrl;
1000
1001 ctrl = rd32(IGC_PTM_CTRL);
1002 ctrl &= ~IGC_PTM_CTRL_EN;
1003
1004 wr32(IGC_PTM_CTRL, ctrl);
1005 }
1006
1007 /**
1008 * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1009 * @adapter: Board private structure
1010 *
1011 * This function stops the overflow check work and PTP Tx timestamp work, and
1012 * will prepare the device for OS suspend.
1013 */
igc_ptp_suspend(struct igc_adapter * adapter)1014 void igc_ptp_suspend(struct igc_adapter *adapter)
1015 {
1016 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1017 return;
1018
1019 cancel_work_sync(&adapter->ptp_tx_work);
1020 dev_kfree_skb_any(adapter->ptp_tx_skb);
1021 adapter->ptp_tx_skb = NULL;
1022 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
1023
1024 if (pci_device_is_present(adapter->pdev)) {
1025 igc_ptp_time_save(adapter);
1026 igc_ptm_stop(adapter);
1027 }
1028 }
1029
1030 /**
1031 * igc_ptp_stop - Disable PTP device and stop the overflow check.
1032 * @adapter: Board private structure.
1033 *
1034 * This function stops the PTP support and cancels the delayed work.
1035 **/
igc_ptp_stop(struct igc_adapter * adapter)1036 void igc_ptp_stop(struct igc_adapter *adapter)
1037 {
1038 igc_ptp_suspend(adapter);
1039
1040 if (adapter->ptp_clock) {
1041 ptp_clock_unregister(adapter->ptp_clock);
1042 netdev_info(adapter->netdev, "PHC removed\n");
1043 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1044 }
1045 }
1046
1047 /**
1048 * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1049 * @adapter: Board private structure.
1050 *
1051 * This function handles the reset work required to re-enable the PTP device.
1052 **/
igc_ptp_reset(struct igc_adapter * adapter)1053 void igc_ptp_reset(struct igc_adapter *adapter)
1054 {
1055 struct igc_hw *hw = &adapter->hw;
1056 u32 cycle_ctrl, ctrl;
1057 unsigned long flags;
1058 u32 timadj;
1059
1060 /* reset the tstamp_config */
1061 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1062
1063 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1064
1065 switch (adapter->hw.mac.type) {
1066 case igc_i225:
1067 timadj = rd32(IGC_TIMADJ);
1068 timadj |= IGC_TIMADJ_ADJUST_METH;
1069 wr32(IGC_TIMADJ, timadj);
1070
1071 wr32(IGC_TSAUXC, 0x0);
1072 wr32(IGC_TSSDP, 0x0);
1073 wr32(IGC_TSIM,
1074 IGC_TSICR_INTERRUPTS |
1075 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1076 wr32(IGC_IMS, IGC_IMS_TS);
1077
1078 if (!igc_is_crosststamp_supported(adapter))
1079 break;
1080
1081 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1082 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1083
1084 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1085
1086 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1087
1088 ctrl = IGC_PTM_CTRL_EN |
1089 IGC_PTM_CTRL_START_NOW |
1090 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1091 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1092 IGC_PTM_CTRL_TRIG;
1093
1094 wr32(IGC_PTM_CTRL, ctrl);
1095
1096 /* Force the first cycle to run. */
1097 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1098
1099 break;
1100 default:
1101 /* No work to do. */
1102 goto out;
1103 }
1104
1105 /* Re-initialize the timer. */
1106 if (hw->mac.type == igc_i225) {
1107 igc_ptp_time_restore(adapter);
1108 } else {
1109 timecounter_init(&adapter->tc, &adapter->cc,
1110 ktime_to_ns(ktime_get_real()));
1111 }
1112 out:
1113 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1114
1115 wrfl();
1116 }
1117