1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30
31 #include "e1000_mac.h"
32 #include "e1000_nvm.h"
33
34 /**
35 * igb_raise_eec_clk - Raise EEPROM clock
36 * @hw: pointer to the HW structure
37 * @eecd: pointer to the EEPROM
38 *
39 * Enable/Raise the EEPROM clock bit.
40 **/
igb_raise_eec_clk(struct e1000_hw * hw,u32 * eecd)41 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
42 {
43 *eecd = *eecd | E1000_EECD_SK;
44 wr32(E1000_EECD, *eecd);
45 wrfl();
46 udelay(hw->nvm.delay_usec);
47 }
48
49 /**
50 * igb_lower_eec_clk - Lower EEPROM clock
51 * @hw: pointer to the HW structure
52 * @eecd: pointer to the EEPROM
53 *
54 * Clear/Lower the EEPROM clock bit.
55 **/
igb_lower_eec_clk(struct e1000_hw * hw,u32 * eecd)56 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
57 {
58 *eecd = *eecd & ~E1000_EECD_SK;
59 wr32(E1000_EECD, *eecd);
60 wrfl();
61 udelay(hw->nvm.delay_usec);
62 }
63
64 /**
65 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
66 * @hw: pointer to the HW structure
67 * @data: data to send to the EEPROM
68 * @count: number of bits to shift out
69 *
70 * We need to shift 'count' bits out to the EEPROM. So, the value in the
71 * "data" parameter will be shifted out to the EEPROM one bit at a time.
72 * In order to do this, "data" must be broken down into bits.
73 **/
igb_shift_out_eec_bits(struct e1000_hw * hw,u16 data,u16 count)74 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
75 {
76 struct e1000_nvm_info *nvm = &hw->nvm;
77 u32 eecd = rd32(E1000_EECD);
78 u32 mask;
79
80 mask = 0x01 << (count - 1);
81 if (nvm->type == e1000_nvm_eeprom_spi)
82 eecd |= E1000_EECD_DO;
83
84 do {
85 eecd &= ~E1000_EECD_DI;
86
87 if (data & mask)
88 eecd |= E1000_EECD_DI;
89
90 wr32(E1000_EECD, eecd);
91 wrfl();
92
93 udelay(nvm->delay_usec);
94
95 igb_raise_eec_clk(hw, &eecd);
96 igb_lower_eec_clk(hw, &eecd);
97
98 mask >>= 1;
99 } while (mask);
100
101 eecd &= ~E1000_EECD_DI;
102 wr32(E1000_EECD, eecd);
103 }
104
105 /**
106 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM
107 * @hw: pointer to the HW structure
108 * @count: number of bits to shift in
109 *
110 * In order to read a register from the EEPROM, we need to shift 'count' bits
111 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
112 * the EEPROM (setting the SK bit), and then reading the value of the data out
113 * "DO" bit. During this "shifting in" process the data in "DI" bit should
114 * always be clear.
115 **/
igb_shift_in_eec_bits(struct e1000_hw * hw,u16 count)116 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
117 {
118 u32 eecd;
119 u32 i;
120 u16 data;
121
122 eecd = rd32(E1000_EECD);
123
124 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
125 data = 0;
126
127 for (i = 0; i < count; i++) {
128 data <<= 1;
129 igb_raise_eec_clk(hw, &eecd);
130
131 eecd = rd32(E1000_EECD);
132
133 eecd &= ~E1000_EECD_DI;
134 if (eecd & E1000_EECD_DO)
135 data |= 1;
136
137 igb_lower_eec_clk(hw, &eecd);
138 }
139
140 return data;
141 }
142
143 /**
144 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
145 * @hw: pointer to the HW structure
146 * @ee_reg: EEPROM flag for polling
147 *
148 * Polls the EEPROM status bit for either read or write completion based
149 * upon the value of 'ee_reg'.
150 **/
igb_poll_eerd_eewr_done(struct e1000_hw * hw,int ee_reg)151 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
152 {
153 u32 attempts = 100000;
154 u32 i, reg = 0;
155 s32 ret_val = -E1000_ERR_NVM;
156
157 for (i = 0; i < attempts; i++) {
158 if (ee_reg == E1000_NVM_POLL_READ)
159 reg = rd32(E1000_EERD);
160 else
161 reg = rd32(E1000_EEWR);
162
163 if (reg & E1000_NVM_RW_REG_DONE) {
164 ret_val = 0;
165 break;
166 }
167
168 udelay(5);
169 }
170
171 return ret_val;
172 }
173
174 /**
175 * igb_acquire_nvm - Generic request for access to EEPROM
176 * @hw: pointer to the HW structure
177 *
178 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
179 * Return successful if access grant bit set, else clear the request for
180 * EEPROM access and return -E1000_ERR_NVM (-1).
181 **/
igb_acquire_nvm(struct e1000_hw * hw)182 s32 igb_acquire_nvm(struct e1000_hw *hw)
183 {
184 u32 eecd = rd32(E1000_EECD);
185 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
186 s32 ret_val = 0;
187
188
189 wr32(E1000_EECD, eecd | E1000_EECD_REQ);
190 eecd = rd32(E1000_EECD);
191
192 while (timeout) {
193 if (eecd & E1000_EECD_GNT)
194 break;
195 udelay(5);
196 eecd = rd32(E1000_EECD);
197 timeout--;
198 }
199
200 if (!timeout) {
201 eecd &= ~E1000_EECD_REQ;
202 wr32(E1000_EECD, eecd);
203 hw_dbg("Could not acquire NVM grant\n");
204 ret_val = -E1000_ERR_NVM;
205 }
206
207 return ret_val;
208 }
209
210 /**
211 * igb_standby_nvm - Return EEPROM to standby state
212 * @hw: pointer to the HW structure
213 *
214 * Return the EEPROM to a standby state.
215 **/
igb_standby_nvm(struct e1000_hw * hw)216 static void igb_standby_nvm(struct e1000_hw *hw)
217 {
218 struct e1000_nvm_info *nvm = &hw->nvm;
219 u32 eecd = rd32(E1000_EECD);
220
221 if (nvm->type == e1000_nvm_eeprom_spi) {
222 /* Toggle CS to flush commands */
223 eecd |= E1000_EECD_CS;
224 wr32(E1000_EECD, eecd);
225 wrfl();
226 udelay(nvm->delay_usec);
227 eecd &= ~E1000_EECD_CS;
228 wr32(E1000_EECD, eecd);
229 wrfl();
230 udelay(nvm->delay_usec);
231 }
232 }
233
234 /**
235 * e1000_stop_nvm - Terminate EEPROM command
236 * @hw: pointer to the HW structure
237 *
238 * Terminates the current command by inverting the EEPROM's chip select pin.
239 **/
e1000_stop_nvm(struct e1000_hw * hw)240 static void e1000_stop_nvm(struct e1000_hw *hw)
241 {
242 u32 eecd;
243
244 eecd = rd32(E1000_EECD);
245 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
246 /* Pull CS high */
247 eecd |= E1000_EECD_CS;
248 igb_lower_eec_clk(hw, &eecd);
249 }
250 }
251
252 /**
253 * igb_release_nvm - Release exclusive access to EEPROM
254 * @hw: pointer to the HW structure
255 *
256 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
257 **/
igb_release_nvm(struct e1000_hw * hw)258 void igb_release_nvm(struct e1000_hw *hw)
259 {
260 u32 eecd;
261
262 e1000_stop_nvm(hw);
263
264 eecd = rd32(E1000_EECD);
265 eecd &= ~E1000_EECD_REQ;
266 wr32(E1000_EECD, eecd);
267 }
268
269 /**
270 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write
271 * @hw: pointer to the HW structure
272 *
273 * Setups the EEPROM for reading and writing.
274 **/
igb_ready_nvm_eeprom(struct e1000_hw * hw)275 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
276 {
277 struct e1000_nvm_info *nvm = &hw->nvm;
278 u32 eecd = rd32(E1000_EECD);
279 s32 ret_val = 0;
280 u16 timeout = 0;
281 u8 spi_stat_reg;
282
283
284 if (nvm->type == e1000_nvm_eeprom_spi) {
285 /* Clear SK and CS */
286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
287 wr32(E1000_EECD, eecd);
288 udelay(1);
289 timeout = NVM_MAX_RETRY_SPI;
290
291 /*
292 * Read "Status Register" repeatedly until the LSB is cleared.
293 * The EEPROM will signal that the command has been completed
294 * by clearing bit 0 of the internal status register. If it's
295 * not cleared within 'timeout', then error out.
296 */
297 while (timeout) {
298 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
299 hw->nvm.opcode_bits);
300 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
301 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
302 break;
303
304 udelay(5);
305 igb_standby_nvm(hw);
306 timeout--;
307 }
308
309 if (!timeout) {
310 hw_dbg("SPI NVM Status error\n");
311 ret_val = -E1000_ERR_NVM;
312 goto out;
313 }
314 }
315
316 out:
317 return ret_val;
318 }
319
320 /**
321 * igb_read_nvm_spi - Read EEPROM's using SPI
322 * @hw: pointer to the HW structure
323 * @offset: offset of word in the EEPROM to read
324 * @words: number of words to read
325 * @data: word read from the EEPROM
326 *
327 * Reads a 16 bit word from the EEPROM.
328 **/
igb_read_nvm_spi(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)329 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
330 {
331 struct e1000_nvm_info *nvm = &hw->nvm;
332 u32 i = 0;
333 s32 ret_val;
334 u16 word_in;
335 u8 read_opcode = NVM_READ_OPCODE_SPI;
336
337 /*
338 * A check for invalid values: offset too large, too many words,
339 * and not enough words.
340 */
341 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
342 (words == 0)) {
343 hw_dbg("nvm parameter(s) out of bounds\n");
344 ret_val = -E1000_ERR_NVM;
345 goto out;
346 }
347
348 ret_val = nvm->ops.acquire(hw);
349 if (ret_val)
350 goto out;
351
352 ret_val = igb_ready_nvm_eeprom(hw);
353 if (ret_val)
354 goto release;
355
356 igb_standby_nvm(hw);
357
358 if ((nvm->address_bits == 8) && (offset >= 128))
359 read_opcode |= NVM_A8_OPCODE_SPI;
360
361 /* Send the READ command (opcode + addr) */
362 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
363 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
364
365 /*
366 * Read the data. SPI NVMs increment the address with each byte
367 * read and will roll over if reading beyond the end. This allows
368 * us to read the whole NVM from any offset
369 */
370 for (i = 0; i < words; i++) {
371 word_in = igb_shift_in_eec_bits(hw, 16);
372 data[i] = (word_in >> 8) | (word_in << 8);
373 }
374
375 release:
376 nvm->ops.release(hw);
377
378 out:
379 return ret_val;
380 }
381
382 /**
383 * igb_read_nvm_eerd - Reads EEPROM using EERD register
384 * @hw: pointer to the HW structure
385 * @offset: offset of word in the EEPROM to read
386 * @words: number of words to read
387 * @data: word read from the EEPROM
388 *
389 * Reads a 16 bit word from the EEPROM using the EERD register.
390 **/
igb_read_nvm_eerd(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)391 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
392 {
393 struct e1000_nvm_info *nvm = &hw->nvm;
394 u32 i, eerd = 0;
395 s32 ret_val = 0;
396
397 /*
398 * A check for invalid values: offset too large, too many words,
399 * and not enough words.
400 */
401 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
402 (words == 0)) {
403 hw_dbg("nvm parameter(s) out of bounds\n");
404 ret_val = -E1000_ERR_NVM;
405 goto out;
406 }
407
408 for (i = 0; i < words; i++) {
409 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
410 E1000_NVM_RW_REG_START;
411
412 wr32(E1000_EERD, eerd);
413 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
414 if (ret_val)
415 break;
416
417 data[i] = (rd32(E1000_EERD) >>
418 E1000_NVM_RW_REG_DATA);
419 }
420
421 out:
422 return ret_val;
423 }
424
425 /**
426 * igb_write_nvm_spi - Write to EEPROM using SPI
427 * @hw: pointer to the HW structure
428 * @offset: offset within the EEPROM to be written to
429 * @words: number of words to write
430 * @data: 16 bit word(s) to be written to the EEPROM
431 *
432 * Writes data to EEPROM at offset using SPI interface.
433 *
434 * If e1000_update_nvm_checksum is not called after this function , the
435 * EEPROM will most likley contain an invalid checksum.
436 **/
igb_write_nvm_spi(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)437 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
438 {
439 struct e1000_nvm_info *nvm = &hw->nvm;
440 s32 ret_val;
441 u16 widx = 0;
442
443 /*
444 * A check for invalid values: offset too large, too many words,
445 * and not enough words.
446 */
447 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
448 (words == 0)) {
449 hw_dbg("nvm parameter(s) out of bounds\n");
450 ret_val = -E1000_ERR_NVM;
451 goto out;
452 }
453
454 ret_val = hw->nvm.ops.acquire(hw);
455 if (ret_val)
456 goto out;
457
458 msleep(10);
459
460 while (widx < words) {
461 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
462
463 ret_val = igb_ready_nvm_eeprom(hw);
464 if (ret_val)
465 goto release;
466
467 igb_standby_nvm(hw);
468
469 /* Send the WRITE ENABLE command (8 bit opcode) */
470 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
471 nvm->opcode_bits);
472
473 igb_standby_nvm(hw);
474
475 /*
476 * Some SPI eeproms use the 8th address bit embedded in the
477 * opcode
478 */
479 if ((nvm->address_bits == 8) && (offset >= 128))
480 write_opcode |= NVM_A8_OPCODE_SPI;
481
482 /* Send the Write command (8-bit opcode + addr) */
483 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
484 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
485 nvm->address_bits);
486
487 /* Loop to allow for up to whole page write of eeprom */
488 while (widx < words) {
489 u16 word_out = data[widx];
490 word_out = (word_out >> 8) | (word_out << 8);
491 igb_shift_out_eec_bits(hw, word_out, 16);
492 widx++;
493
494 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
495 igb_standby_nvm(hw);
496 break;
497 }
498 }
499 }
500
501 msleep(10);
502 release:
503 hw->nvm.ops.release(hw);
504
505 out:
506 return ret_val;
507 }
508
509 /**
510 * igb_read_part_string - Read device part number
511 * @hw: pointer to the HW structure
512 * @part_num: pointer to device part number
513 * @part_num_size: size of part number buffer
514 *
515 * Reads the product board assembly (PBA) number from the EEPROM and stores
516 * the value in part_num.
517 **/
igb_read_part_string(struct e1000_hw * hw,u8 * part_num,u32 part_num_size)518 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
519 {
520 s32 ret_val;
521 u16 nvm_data;
522 u16 pointer;
523 u16 offset;
524 u16 length;
525
526 if (part_num == NULL) {
527 hw_dbg("PBA string buffer was null\n");
528 ret_val = E1000_ERR_INVALID_ARGUMENT;
529 goto out;
530 }
531
532 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
533 if (ret_val) {
534 hw_dbg("NVM Read Error\n");
535 goto out;
536 }
537
538 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
539 if (ret_val) {
540 hw_dbg("NVM Read Error\n");
541 goto out;
542 }
543
544 /*
545 * if nvm_data is not ptr guard the PBA must be in legacy format which
546 * means pointer is actually our second data word for the PBA number
547 * and we can decode it into an ascii string
548 */
549 if (nvm_data != NVM_PBA_PTR_GUARD) {
550 hw_dbg("NVM PBA number is not stored as string\n");
551
552 /* we will need 11 characters to store the PBA */
553 if (part_num_size < 11) {
554 hw_dbg("PBA string buffer too small\n");
555 return E1000_ERR_NO_SPACE;
556 }
557
558 /* extract hex string from data and pointer */
559 part_num[0] = (nvm_data >> 12) & 0xF;
560 part_num[1] = (nvm_data >> 8) & 0xF;
561 part_num[2] = (nvm_data >> 4) & 0xF;
562 part_num[3] = nvm_data & 0xF;
563 part_num[4] = (pointer >> 12) & 0xF;
564 part_num[5] = (pointer >> 8) & 0xF;
565 part_num[6] = '-';
566 part_num[7] = 0;
567 part_num[8] = (pointer >> 4) & 0xF;
568 part_num[9] = pointer & 0xF;
569
570 /* put a null character on the end of our string */
571 part_num[10] = '\0';
572
573 /* switch all the data but the '-' to hex char */
574 for (offset = 0; offset < 10; offset++) {
575 if (part_num[offset] < 0xA)
576 part_num[offset] += '0';
577 else if (part_num[offset] < 0x10)
578 part_num[offset] += 'A' - 0xA;
579 }
580
581 goto out;
582 }
583
584 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
585 if (ret_val) {
586 hw_dbg("NVM Read Error\n");
587 goto out;
588 }
589
590 if (length == 0xFFFF || length == 0) {
591 hw_dbg("NVM PBA number section invalid length\n");
592 ret_val = E1000_ERR_NVM_PBA_SECTION;
593 goto out;
594 }
595 /* check if part_num buffer is big enough */
596 if (part_num_size < (((u32)length * 2) - 1)) {
597 hw_dbg("PBA string buffer too small\n");
598 ret_val = E1000_ERR_NO_SPACE;
599 goto out;
600 }
601
602 /* trim pba length from start of string */
603 pointer++;
604 length--;
605
606 for (offset = 0; offset < length; offset++) {
607 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
608 if (ret_val) {
609 hw_dbg("NVM Read Error\n");
610 goto out;
611 }
612 part_num[offset * 2] = (u8)(nvm_data >> 8);
613 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
614 }
615 part_num[offset * 2] = '\0';
616
617 out:
618 return ret_val;
619 }
620
621 /**
622 * igb_read_mac_addr - Read device MAC address
623 * @hw: pointer to the HW structure
624 *
625 * Reads the device MAC address from the EEPROM and stores the value.
626 * Since devices with two ports use the same EEPROM, we increment the
627 * last bit in the MAC address for the second port.
628 **/
igb_read_mac_addr(struct e1000_hw * hw)629 s32 igb_read_mac_addr(struct e1000_hw *hw)
630 {
631 u32 rar_high;
632 u32 rar_low;
633 u16 i;
634
635 rar_high = rd32(E1000_RAH(0));
636 rar_low = rd32(E1000_RAL(0));
637
638 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
639 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
640
641 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
642 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
643
644 for (i = 0; i < ETH_ALEN; i++)
645 hw->mac.addr[i] = hw->mac.perm_addr[i];
646
647 return 0;
648 }
649
650 /**
651 * igb_validate_nvm_checksum - Validate EEPROM checksum
652 * @hw: pointer to the HW structure
653 *
654 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
655 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
656 **/
igb_validate_nvm_checksum(struct e1000_hw * hw)657 s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
658 {
659 s32 ret_val = 0;
660 u16 checksum = 0;
661 u16 i, nvm_data;
662
663 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
664 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
665 if (ret_val) {
666 hw_dbg("NVM Read Error\n");
667 goto out;
668 }
669 checksum += nvm_data;
670 }
671
672 if (checksum != (u16) NVM_SUM) {
673 hw_dbg("NVM Checksum Invalid\n");
674 ret_val = -E1000_ERR_NVM;
675 goto out;
676 }
677
678 out:
679 return ret_val;
680 }
681
682 /**
683 * igb_update_nvm_checksum - Update EEPROM checksum
684 * @hw: pointer to the HW structure
685 *
686 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
687 * up to the checksum. Then calculates the EEPROM checksum and writes the
688 * value to the EEPROM.
689 **/
igb_update_nvm_checksum(struct e1000_hw * hw)690 s32 igb_update_nvm_checksum(struct e1000_hw *hw)
691 {
692 s32 ret_val;
693 u16 checksum = 0;
694 u16 i, nvm_data;
695
696 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
697 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
698 if (ret_val) {
699 hw_dbg("NVM Read Error while updating checksum.\n");
700 goto out;
701 }
702 checksum += nvm_data;
703 }
704 checksum = (u16) NVM_SUM - checksum;
705 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
706 if (ret_val)
707 hw_dbg("NVM Write Error while updating checksum.\n");
708
709 out:
710 return ret_val;
711 }
712
713