1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Contains CPU feature definitions
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  *
7  * A note for the weary kernel hacker: the code here is confusing and hard to
8  * follow! That's partly because it's solving a nasty problem, but also because
9  * there's a little bit of over-abstraction that tends to obscure what's going
10  * on behind a maze of helper functions and macros.
11  *
12  * The basic problem is that hardware folks have started gluing together CPUs
13  * with distinct architectural features; in some cases even creating SoCs where
14  * user-visible instructions are available only on a subset of the available
15  * cores. We try to address this by snapshotting the feature registers of the
16  * boot CPU and comparing these with the feature registers of each secondary
17  * CPU when bringing them up. If there is a mismatch, then we update the
18  * snapshot state to indicate the lowest-common denominator of the feature,
19  * known as the "safe" value. This snapshot state can be queried to view the
20  * "sanitised" value of a feature register.
21  *
22  * The sanitised register values are used to decide which capabilities we
23  * have in the system. These may be in the form of traditional "hwcaps"
24  * advertised to userspace or internal "cpucaps" which are used to configure
25  * things like alternative patching and static keys. While a feature mismatch
26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27  * may prevent a CPU from being onlined at all.
28  *
29  * Some implementation details worth remembering:
30  *
31  * - Mismatched features are *always* sanitised to a "safe" value, which
32  *   usually indicates that the feature is not supported.
33  *
34  * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35  *   warning when onlining an offending CPU and the kernel will be tainted
36  *   with TAINT_CPU_OUT_OF_SPEC.
37  *
38  * - Features marked as FTR_VISIBLE have their sanitised value visible to
39  *   userspace. FTR_VISIBLE features in registers that are only visible
40  *   to EL0 by trapping *must* have a corresponding HWCAP so that late
41  *   onlining of CPUs cannot lead to features disappearing at runtime.
42  *
43  * - A "feature" is typically a 4-bit register field. A "capability" is the
44  *   high-level description derived from the sanitised field value.
45  *
46  * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47  *   scheme for fields in ID registers") to understand when feature fields
48  *   may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49  *
50  * - KVM exposes its own view of the feature registers to guest operating
51  *   systems regardless of FTR_VISIBLE. This is typically driven from the
52  *   sanitised register values to allow virtual CPUs to be migrated between
53  *   arbitrary physical CPUs, but some features not present on the host are
54  *   also advertised and emulated. Look at sys_reg_descs[] for the gory
55  *   details.
56  *
57  * - If the arm64_ftr_bits[] for a register has a missing field, then this
58  *   field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59  *   This is stronger than FTR_HIDDEN and can be used to hide features from
60  *   KVM guests.
61  */
62 
63 #define pr_fmt(fmt) "CPU features: " fmt
64 
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
73 #include <linux/mm.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <linux/percpu.h>
77 
78 #include <asm/cpu.h>
79 #include <asm/cpufeature.h>
80 #include <asm/cpu_ops.h>
81 #include <asm/fpsimd.h>
82 #include <asm/hwcap.h>
83 #include <asm/insn.h>
84 #include <asm/kvm_host.h>
85 #include <asm/mmu_context.h>
86 #include <asm/mte.h>
87 #include <asm/processor.h>
88 #include <asm/smp.h>
89 #include <asm/sysreg.h>
90 #include <asm/traps.h>
91 #include <asm/vectors.h>
92 #include <asm/virt.h>
93 
94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
95 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
96 
97 #ifdef CONFIG_COMPAT
98 #define COMPAT_ELF_HWCAP_DEFAULT	\
99 				(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
100 				 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
101 				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
102 				 COMPAT_HWCAP_LPAE)
103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
104 unsigned int compat_elf_hwcap2 __read_mostly;
105 #endif
106 
107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
108 EXPORT_SYMBOL(cpu_hwcaps);
109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
110 
111 DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS);
112 
113 bool arm64_use_ng_mappings = false;
114 EXPORT_SYMBOL(arm64_use_ng_mappings);
115 
116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
117 
118 /*
119  * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
120  * support it?
121  */
122 static bool __read_mostly allow_mismatched_32bit_el0;
123 
124 /*
125  * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
126  * seen at least one CPU capable of 32-bit EL0.
127  */
128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
129 
130 /*
131  * Mask of CPUs supporting 32-bit EL0.
132  * Only valid if arm64_mismatched_32bit_el0 is enabled.
133  */
134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
135 
dump_cpu_features(void)136 void dump_cpu_features(void)
137 {
138 	/* file-wide pr_fmt adds "CPU features: " prefix */
139 	pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
140 }
141 
142 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
143 	{						\
144 		.sign = SIGNED,				\
145 		.visible = VISIBLE,			\
146 		.strict = STRICT,			\
147 		.type = TYPE,				\
148 		.shift = SHIFT,				\
149 		.width = WIDTH,				\
150 		.safe_val = SAFE_VAL,			\
151 	}
152 
153 /* Define a feature with unsigned values */
154 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
155 	__ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
156 
157 /* Define a feature with a signed value */
158 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
159 	__ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
160 
161 #define ARM64_FTR_END					\
162 	{						\
163 		.width = 0,				\
164 	}
165 
166 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
167 
168 static bool __system_matches_cap(unsigned int n);
169 
170 /*
171  * NOTE: Any changes to the visibility of features should be kept in
172  * sync with the documentation of the CPU feature register ABI.
173  */
174 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
175 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
176 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
177 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
178 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
179 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
180 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
181 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
182 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
183 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
184 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
185 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
186 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
187 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
188 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
189 	ARM64_FTR_END,
190 };
191 
192 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
193 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
194 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
195 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
196 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
197 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
198 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
199 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
200 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
201 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
202 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
203 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
204 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
205 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
206 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
207 		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
208 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
209 		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
210 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
211 	ARM64_FTR_END,
212 };
213 
214 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
215 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
216 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
217 		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
218 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
219 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
220 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
221 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
222 	ARM64_FTR_END,
223 };
224 
225 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
226 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
227 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
228 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
229 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
230 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
231 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
232 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
233 				   FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
234 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
235 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
236 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
237 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
238 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
239 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
240 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
241 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
242 	ARM64_FTR_END,
243 };
244 
245 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
246 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
247 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
248 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
249 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
250 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
251 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
252 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),
253 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
254 				    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
255 	ARM64_FTR_END,
256 };
257 
258 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
259 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
260 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
261 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
262 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
263 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
264 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
265 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
266 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
267 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
268 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
269 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
270 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
271 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
272 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
273 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
274 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
275 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
276 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
277 	ARM64_FTR_END,
278 };
279 
280 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
281 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
282 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
283 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
284 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
285 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
286 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
287 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
288 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
289 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
290 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
291 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
292 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
293 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
294 		       FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
295 	ARM64_FTR_END,
296 };
297 
298 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
299 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
300 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
301 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
302 	/*
303 	 * Page size not being supported at Stage-2 is not fatal. You
304 	 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
305 	 * your favourite nesting hypervisor.
306 	 *
307 	 * There is a small corner case where the hypervisor explicitly
308 	 * advertises a given granule size at Stage-2 (value 2) on some
309 	 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
310 	 * vCPUs. Although this is not forbidden by the architecture, it
311 	 * indicates that the hypervisor is being silly (or buggy).
312 	 *
313 	 * We make no effort to cope with this and pretend that if these
314 	 * fields are inconsistent across vCPUs, then it isn't worth
315 	 * trying to bring KVM up.
316 	 */
317 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
318 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
319 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
320 	/*
321 	 * We already refuse to boot CPUs that don't support our configured
322 	 * page size, so we can only detect mismatches for a page size other
323 	 * than the one we're currently using. Unfortunately, SoCs like this
324 	 * exist in the wild so, even though we don't like it, we'll have to go
325 	 * along with it and treat them as non-strict.
326 	 */
327 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
328 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
329 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
330 
331 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
332 	/* Linux shouldn't care about secure memory */
333 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
334 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
335 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
336 	/*
337 	 * Differing PARange is fine as long as all peripherals and memory are mapped
338 	 * within the minimum PARange of all CPUs
339 	 */
340 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
341 	ARM64_FTR_END,
342 };
343 
344 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
345 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
346 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
347 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
348 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
349 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
350 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
351 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
352 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
353 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
354 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
355 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
356 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
357 	ARM64_FTR_END,
358 };
359 
360 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
361 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
362 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
363 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
364 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
365 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
366 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
367 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
368 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
369 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
370 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
371 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
372 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
373 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
374 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
375 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
376 	ARM64_FTR_END,
377 };
378 
379 static const struct arm64_ftr_bits ftr_ctr[] = {
380 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
381 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
382 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
383 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
384 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
385 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
386 	/*
387 	 * Linux can handle differing I-cache policies. Userspace JITs will
388 	 * make use of *minLine.
389 	 * If we have differing I-cache policies, report it as the weakest - VIPT.
390 	 */
391 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT),	/* L1Ip */
392 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
393 	ARM64_FTR_END,
394 };
395 
396 static struct arm64_ftr_override __ro_after_init no_override = { };
397 
398 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
399 	.name		= "SYS_CTR_EL0",
400 	.ftr_bits	= ftr_ctr,
401 	.override	= &no_override,
402 };
403 
404 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
405 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
406 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
407 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
408 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
409 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
410 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
411 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
412 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
413 	ARM64_FTR_END,
414 };
415 
416 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
417 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
418 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
419 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
420 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
421 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
422 	/*
423 	 * We can instantiate multiple PMU instances with different levels
424 	 * of support.
425 	 */
426 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
427 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
428 	ARM64_FTR_END,
429 };
430 
431 static const struct arm64_ftr_bits ftr_mvfr0[] = {
432 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
433 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
434 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
435 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
436 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
437 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
438 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
439 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
440 	ARM64_FTR_END,
441 };
442 
443 static const struct arm64_ftr_bits ftr_mvfr1[] = {
444 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
445 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
446 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
447 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
448 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
449 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
450 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
451 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
452 	ARM64_FTR_END,
453 };
454 
455 static const struct arm64_ftr_bits ftr_mvfr2[] = {
456 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
457 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
458 	ARM64_FTR_END,
459 };
460 
461 static const struct arm64_ftr_bits ftr_dczid[] = {
462 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
463 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
464 	ARM64_FTR_END,
465 };
466 
467 static const struct arm64_ftr_bits ftr_gmid[] = {
468 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
469 	ARM64_FTR_END,
470 };
471 
472 static const struct arm64_ftr_bits ftr_id_isar0[] = {
473 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
474 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
475 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
476 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
477 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
478 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
479 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
480 	ARM64_FTR_END,
481 };
482 
483 static const struct arm64_ftr_bits ftr_id_isar5[] = {
484 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
485 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
486 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
487 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
488 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
489 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
490 	ARM64_FTR_END,
491 };
492 
493 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
494 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
495 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
496 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
497 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
498 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
499 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
500 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
501 
502 	/*
503 	 * SpecSEI = 1 indicates that the PE might generate an SError on an
504 	 * external abort on speculative read. It is safe to assume that an
505 	 * SError might be generated than it will not be. Hence it has been
506 	 * classified as FTR_HIGHER_SAFE.
507 	 */
508 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
509 	ARM64_FTR_END,
510 };
511 
512 static const struct arm64_ftr_bits ftr_id_isar4[] = {
513 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
514 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
515 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
516 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
517 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
518 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
519 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
520 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
521 	ARM64_FTR_END,
522 };
523 
524 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
525 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
526 	ARM64_FTR_END,
527 };
528 
529 static const struct arm64_ftr_bits ftr_id_isar6[] = {
530 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
531 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
532 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
533 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
534 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
535 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
536 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
537 	ARM64_FTR_END,
538 };
539 
540 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
541 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
542 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
543 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
544 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
545 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
546 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
547 	ARM64_FTR_END,
548 };
549 
550 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
551 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
552 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
553 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
554 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
555 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
556 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
557 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
558 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
559 	ARM64_FTR_END,
560 };
561 
562 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
563 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
564 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
565 	ARM64_FTR_END,
566 };
567 
568 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
569 	/* [31:28] TraceFilt */
570 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
571 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
572 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
573 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
574 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
575 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
576 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
577 	ARM64_FTR_END,
578 };
579 
580 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
581 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
582 	ARM64_FTR_END,
583 };
584 
585 static const struct arm64_ftr_bits ftr_zcr[] = {
586 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
587 		ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0),	/* LEN */
588 	ARM64_FTR_END,
589 };
590 
591 static const struct arm64_ftr_bits ftr_smcr[] = {
592 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
593 		SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0),	/* LEN */
594 	ARM64_FTR_END,
595 };
596 
597 /*
598  * Common ftr bits for a 32bit register with all hidden, strict
599  * attributes, with 4bit feature fields and a default safe value of
600  * 0. Covers the following 32bit registers:
601  * id_isar[1-3], id_mmfr[1-3]
602  */
603 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
604 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
605 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
606 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
607 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
608 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
609 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
610 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
611 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
612 	ARM64_FTR_END,
613 };
614 
615 /* Table for a single 32bit feature value */
616 static const struct arm64_ftr_bits ftr_single32[] = {
617 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
618 	ARM64_FTR_END,
619 };
620 
621 static const struct arm64_ftr_bits ftr_raz[] = {
622 	ARM64_FTR_END,
623 };
624 
625 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) {	\
626 		.sys_id = id,					\
627 		.reg = 	&(struct arm64_ftr_reg){		\
628 			.name = id_str,				\
629 			.override = (ovr),			\
630 			.ftr_bits = &((table)[0]),		\
631 	}}
632 
633 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr)	\
634 	__ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
635 
636 #define ARM64_FTR_REG(id, table)		\
637 	__ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
638 
639 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
640 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override;
641 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
642 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override;
643 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override;
644 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
645 struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
646 
647 static const struct __ftr_reg_entry {
648 	u32			sys_id;
649 	struct arm64_ftr_reg 	*reg;
650 } arm64_ftr_regs[] = {
651 
652 	/* Op1 = 0, CRn = 0, CRm = 1 */
653 	ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
654 	ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
655 	ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
656 	ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
657 	ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
658 	ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
659 	ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
660 
661 	/* Op1 = 0, CRn = 0, CRm = 2 */
662 	ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
663 	ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
664 	ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
665 	ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
666 	ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
667 	ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
668 	ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
669 	ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
670 
671 	/* Op1 = 0, CRn = 0, CRm = 3 */
672 	ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
673 	ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
674 	ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
675 	ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
676 	ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
677 	ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
678 
679 	/* Op1 = 0, CRn = 0, CRm = 4 */
680 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
681 			       &id_aa64pfr0_override),
682 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
683 			       &id_aa64pfr1_override),
684 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
685 			       &id_aa64zfr0_override),
686 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
687 			       &id_aa64smfr0_override),
688 
689 	/* Op1 = 0, CRn = 0, CRm = 5 */
690 	ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
691 	ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
692 
693 	/* Op1 = 0, CRn = 0, CRm = 6 */
694 	ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
695 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
696 			       &id_aa64isar1_override),
697 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
698 			       &id_aa64isar2_override),
699 
700 	/* Op1 = 0, CRn = 0, CRm = 7 */
701 	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
702 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
703 			       &id_aa64mmfr1_override),
704 	ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
705 
706 	/* Op1 = 0, CRn = 1, CRm = 2 */
707 	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
708 	ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
709 
710 	/* Op1 = 1, CRn = 0, CRm = 0 */
711 	ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
712 
713 	/* Op1 = 3, CRn = 0, CRm = 0 */
714 	{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
715 	ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
716 
717 	/* Op1 = 3, CRn = 14, CRm = 0 */
718 	ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
719 };
720 
search_cmp_ftr_reg(const void * id,const void * regp)721 static int search_cmp_ftr_reg(const void *id, const void *regp)
722 {
723 	return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
724 }
725 
726 /*
727  * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
728  * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
729  * ascending order of sys_id, we use binary search to find a matching
730  * entry.
731  *
732  * returns - Upon success,  matching ftr_reg entry for id.
733  *         - NULL on failure. It is upto the caller to decide
734  *	     the impact of a failure.
735  */
get_arm64_ftr_reg_nowarn(u32 sys_id)736 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
737 {
738 	const struct __ftr_reg_entry *ret;
739 
740 	ret = bsearch((const void *)(unsigned long)sys_id,
741 			arm64_ftr_regs,
742 			ARRAY_SIZE(arm64_ftr_regs),
743 			sizeof(arm64_ftr_regs[0]),
744 			search_cmp_ftr_reg);
745 	if (ret)
746 		return ret->reg;
747 	return NULL;
748 }
749 
750 /*
751  * get_arm64_ftr_reg - Looks up a feature register entry using
752  * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
753  *
754  * returns - Upon success,  matching ftr_reg entry for id.
755  *         - NULL on failure but with an WARN_ON().
756  */
get_arm64_ftr_reg(u32 sys_id)757 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
758 {
759 	struct arm64_ftr_reg *reg;
760 
761 	reg = get_arm64_ftr_reg_nowarn(sys_id);
762 
763 	/*
764 	 * Requesting a non-existent register search is an error. Warn
765 	 * and let the caller handle it.
766 	 */
767 	WARN_ON(!reg);
768 	return reg;
769 }
770 
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)771 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
772 			       s64 ftr_val)
773 {
774 	u64 mask = arm64_ftr_mask(ftrp);
775 
776 	reg &= ~mask;
777 	reg |= (ftr_val << ftrp->shift) & mask;
778 	return reg;
779 }
780 
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)781 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
782 				s64 cur)
783 {
784 	s64 ret = 0;
785 
786 	switch (ftrp->type) {
787 	case FTR_EXACT:
788 		ret = ftrp->safe_val;
789 		break;
790 	case FTR_LOWER_SAFE:
791 		ret = min(new, cur);
792 		break;
793 	case FTR_HIGHER_OR_ZERO_SAFE:
794 		if (!cur || !new)
795 			break;
796 		fallthrough;
797 	case FTR_HIGHER_SAFE:
798 		ret = max(new, cur);
799 		break;
800 	default:
801 		BUG();
802 	}
803 
804 	return ret;
805 }
806 
sort_ftr_regs(void)807 static void __init sort_ftr_regs(void)
808 {
809 	unsigned int i;
810 
811 	for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
812 		const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
813 		const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
814 		unsigned int j = 0;
815 
816 		/*
817 		 * Features here must be sorted in descending order with respect
818 		 * to their shift values and should not overlap with each other.
819 		 */
820 		for (; ftr_bits->width != 0; ftr_bits++, j++) {
821 			unsigned int width = ftr_reg->ftr_bits[j].width;
822 			unsigned int shift = ftr_reg->ftr_bits[j].shift;
823 			unsigned int prev_shift;
824 
825 			WARN((shift  + width) > 64,
826 				"%s has invalid feature at shift %d\n",
827 				ftr_reg->name, shift);
828 
829 			/*
830 			 * Skip the first feature. There is nothing to
831 			 * compare against for now.
832 			 */
833 			if (j == 0)
834 				continue;
835 
836 			prev_shift = ftr_reg->ftr_bits[j - 1].shift;
837 			WARN((shift + width) > prev_shift,
838 				"%s has feature overlap at shift %d\n",
839 				ftr_reg->name, shift);
840 		}
841 
842 		/*
843 		 * Skip the first register. There is nothing to
844 		 * compare against for now.
845 		 */
846 		if (i == 0)
847 			continue;
848 		/*
849 		 * Registers here must be sorted in ascending order with respect
850 		 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
851 		 * to work correctly.
852 		 */
853 		BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
854 	}
855 }
856 
857 /*
858  * Initialise the CPU feature register from Boot CPU values.
859  * Also initiliases the strict_mask for the register.
860  * Any bits that are not covered by an arm64_ftr_bits entry are considered
861  * RES0 for the system-wide value, and must strictly match.
862  */
init_cpu_ftr_reg(u32 sys_reg,u64 new)863 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
864 {
865 	u64 val = 0;
866 	u64 strict_mask = ~0x0ULL;
867 	u64 user_mask = 0;
868 	u64 valid_mask = 0;
869 
870 	const struct arm64_ftr_bits *ftrp;
871 	struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
872 
873 	if (!reg)
874 		return;
875 
876 	for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
877 		u64 ftr_mask = arm64_ftr_mask(ftrp);
878 		s64 ftr_new = arm64_ftr_value(ftrp, new);
879 		s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
880 
881 		if ((ftr_mask & reg->override->mask) == ftr_mask) {
882 			s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
883 			char *str = NULL;
884 
885 			if (ftr_ovr != tmp) {
886 				/* Unsafe, remove the override */
887 				reg->override->mask &= ~ftr_mask;
888 				reg->override->val &= ~ftr_mask;
889 				tmp = ftr_ovr;
890 				str = "ignoring override";
891 			} else if (ftr_new != tmp) {
892 				/* Override was valid */
893 				ftr_new = tmp;
894 				str = "forced";
895 			} else if (ftr_ovr == tmp) {
896 				/* Override was the safe value */
897 				str = "already set";
898 			}
899 
900 			if (str)
901 				pr_warn("%s[%d:%d]: %s to %llx\n",
902 					reg->name,
903 					ftrp->shift + ftrp->width - 1,
904 					ftrp->shift, str, tmp);
905 		} else if ((ftr_mask & reg->override->val) == ftr_mask) {
906 			reg->override->val &= ~ftr_mask;
907 			pr_warn("%s[%d:%d]: impossible override, ignored\n",
908 				reg->name,
909 				ftrp->shift + ftrp->width - 1,
910 				ftrp->shift);
911 		}
912 
913 		val = arm64_ftr_set_value(ftrp, val, ftr_new);
914 
915 		valid_mask |= ftr_mask;
916 		if (!ftrp->strict)
917 			strict_mask &= ~ftr_mask;
918 		if (ftrp->visible)
919 			user_mask |= ftr_mask;
920 		else
921 			reg->user_val = arm64_ftr_set_value(ftrp,
922 							    reg->user_val,
923 							    ftrp->safe_val);
924 	}
925 
926 	val &= valid_mask;
927 
928 	reg->sys_val = val;
929 	reg->strict_mask = strict_mask;
930 	reg->user_mask = user_mask;
931 }
932 
933 extern const struct arm64_cpu_capabilities arm64_errata[];
934 static const struct arm64_cpu_capabilities arm64_features[];
935 
936 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)937 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
938 {
939 	for (; caps->matches; caps++) {
940 		if (WARN(caps->capability >= ARM64_NCAPS,
941 			"Invalid capability %d\n", caps->capability))
942 			continue;
943 		if (WARN(cpu_hwcaps_ptrs[caps->capability],
944 			"Duplicate entry for capability %d\n",
945 			caps->capability))
946 			continue;
947 		cpu_hwcaps_ptrs[caps->capability] = caps;
948 	}
949 }
950 
init_cpu_hwcaps_indirect_list(void)951 static void __init init_cpu_hwcaps_indirect_list(void)
952 {
953 	init_cpu_hwcaps_indirect_list_from_array(arm64_features);
954 	init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
955 }
956 
957 static void __init setup_boot_cpu_capabilities(void);
958 
init_32bit_cpu_features(struct cpuinfo_32bit * info)959 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
960 {
961 	init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
962 	init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
963 	init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
964 	init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
965 	init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
966 	init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
967 	init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
968 	init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
969 	init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
970 	init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
971 	init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
972 	init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
973 	init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
974 	init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
975 	init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
976 	init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
977 	init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
978 	init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
979 	init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
980 	init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
981 	init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
982 }
983 
init_cpu_features(struct cpuinfo_arm64 * info)984 void __init init_cpu_features(struct cpuinfo_arm64 *info)
985 {
986 	/* Before we start using the tables, make sure it is sorted */
987 	sort_ftr_regs();
988 
989 	init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
990 	init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
991 	init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
992 	init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
993 	init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
994 	init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
995 	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
996 	init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
997 	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
998 	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
999 	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
1000 	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
1001 	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
1002 	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
1003 	init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1004 
1005 	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1006 		init_32bit_cpu_features(&info->aarch32);
1007 
1008 	if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1009 	    id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1010 		info->reg_zcr = read_zcr_features();
1011 		init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
1012 		vec_init_vq_map(ARM64_VEC_SVE);
1013 	}
1014 
1015 	if (IS_ENABLED(CONFIG_ARM64_SME) &&
1016 	    id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1017 		info->reg_smcr = read_smcr_features();
1018 		/*
1019 		 * We mask out SMPS since even if the hardware
1020 		 * supports priorities the kernel does not at present
1021 		 * and we block access to them.
1022 		 */
1023 		info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1024 		init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
1025 		vec_init_vq_map(ARM64_VEC_SME);
1026 	}
1027 
1028 	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1029 		init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1030 
1031 	/*
1032 	 * Initialize the indirect array of CPU hwcaps capabilities pointers
1033 	 * before we handle the boot CPU below.
1034 	 */
1035 	init_cpu_hwcaps_indirect_list();
1036 
1037 	/*
1038 	 * Detect and enable early CPU capabilities based on the boot CPU,
1039 	 * after we have initialised the CPU feature infrastructure.
1040 	 */
1041 	setup_boot_cpu_capabilities();
1042 }
1043 
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)1044 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1045 {
1046 	const struct arm64_ftr_bits *ftrp;
1047 
1048 	for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1049 		s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1050 		s64 ftr_new = arm64_ftr_value(ftrp, new);
1051 
1052 		if (ftr_cur == ftr_new)
1053 			continue;
1054 		/* Find a safe value */
1055 		ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1056 		reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1057 	}
1058 
1059 }
1060 
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)1061 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1062 {
1063 	struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1064 
1065 	if (!regp)
1066 		return 0;
1067 
1068 	update_cpu_ftr_reg(regp, val);
1069 	if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1070 		return 0;
1071 	pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1072 			regp->name, boot, cpu, val);
1073 	return 1;
1074 }
1075 
relax_cpu_ftr_reg(u32 sys_id,int field)1076 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1077 {
1078 	const struct arm64_ftr_bits *ftrp;
1079 	struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1080 
1081 	if (!regp)
1082 		return;
1083 
1084 	for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1085 		if (ftrp->shift == field) {
1086 			regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1087 			break;
1088 		}
1089 	}
1090 
1091 	/* Bogus field? */
1092 	WARN_ON(!ftrp->width);
1093 }
1094 
lazy_init_32bit_cpu_features(struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1095 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1096 					 struct cpuinfo_arm64 *boot)
1097 {
1098 	static bool boot_cpu_32bit_regs_overridden = false;
1099 
1100 	if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1101 		return;
1102 
1103 	if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1104 		return;
1105 
1106 	boot->aarch32 = info->aarch32;
1107 	init_32bit_cpu_features(&boot->aarch32);
1108 	boot_cpu_32bit_regs_overridden = true;
1109 }
1110 
update_32bit_cpu_features(int cpu,struct cpuinfo_32bit * info,struct cpuinfo_32bit * boot)1111 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1112 				     struct cpuinfo_32bit *boot)
1113 {
1114 	int taint = 0;
1115 	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1116 
1117 	/*
1118 	 * If we don't have AArch32 at EL1, then relax the strictness of
1119 	 * EL1-dependent register fields to avoid spurious sanity check fails.
1120 	 */
1121 	if (!id_aa64pfr0_32bit_el1(pfr0)) {
1122 		relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1123 		relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1124 		relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1125 		relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1126 		relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1127 		relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1128 	}
1129 
1130 	taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1131 				      info->reg_id_dfr0, boot->reg_id_dfr0);
1132 	taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1133 				      info->reg_id_dfr1, boot->reg_id_dfr1);
1134 	taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1135 				      info->reg_id_isar0, boot->reg_id_isar0);
1136 	taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1137 				      info->reg_id_isar1, boot->reg_id_isar1);
1138 	taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1139 				      info->reg_id_isar2, boot->reg_id_isar2);
1140 	taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1141 				      info->reg_id_isar3, boot->reg_id_isar3);
1142 	taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1143 				      info->reg_id_isar4, boot->reg_id_isar4);
1144 	taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1145 				      info->reg_id_isar5, boot->reg_id_isar5);
1146 	taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1147 				      info->reg_id_isar6, boot->reg_id_isar6);
1148 
1149 	/*
1150 	 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1151 	 * ACTLR formats could differ across CPUs and therefore would have to
1152 	 * be trapped for virtualization anyway.
1153 	 */
1154 	taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1155 				      info->reg_id_mmfr0, boot->reg_id_mmfr0);
1156 	taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1157 				      info->reg_id_mmfr1, boot->reg_id_mmfr1);
1158 	taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1159 				      info->reg_id_mmfr2, boot->reg_id_mmfr2);
1160 	taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1161 				      info->reg_id_mmfr3, boot->reg_id_mmfr3);
1162 	taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1163 				      info->reg_id_mmfr4, boot->reg_id_mmfr4);
1164 	taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1165 				      info->reg_id_mmfr5, boot->reg_id_mmfr5);
1166 	taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1167 				      info->reg_id_pfr0, boot->reg_id_pfr0);
1168 	taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1169 				      info->reg_id_pfr1, boot->reg_id_pfr1);
1170 	taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1171 				      info->reg_id_pfr2, boot->reg_id_pfr2);
1172 	taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1173 				      info->reg_mvfr0, boot->reg_mvfr0);
1174 	taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1175 				      info->reg_mvfr1, boot->reg_mvfr1);
1176 	taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1177 				      info->reg_mvfr2, boot->reg_mvfr2);
1178 
1179 	return taint;
1180 }
1181 
1182 /*
1183  * Update system wide CPU feature registers with the values from a
1184  * non-boot CPU. Also performs SANITY checks to make sure that there
1185  * aren't any insane variations from that of the boot CPU.
1186  */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1187 void update_cpu_features(int cpu,
1188 			 struct cpuinfo_arm64 *info,
1189 			 struct cpuinfo_arm64 *boot)
1190 {
1191 	int taint = 0;
1192 
1193 	/*
1194 	 * The kernel can handle differing I-cache policies, but otherwise
1195 	 * caches should look identical. Userspace JITs will make use of
1196 	 * *minLine.
1197 	 */
1198 	taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1199 				      info->reg_ctr, boot->reg_ctr);
1200 
1201 	/*
1202 	 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1203 	 * could result in too much or too little memory being zeroed if a
1204 	 * process is preempted and migrated between CPUs.
1205 	 */
1206 	taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1207 				      info->reg_dczid, boot->reg_dczid);
1208 
1209 	/* If different, timekeeping will be broken (especially with KVM) */
1210 	taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1211 				      info->reg_cntfrq, boot->reg_cntfrq);
1212 
1213 	/*
1214 	 * The kernel uses self-hosted debug features and expects CPUs to
1215 	 * support identical debug features. We presently need CTX_CMPs, WRPs,
1216 	 * and BRPs to be identical.
1217 	 * ID_AA64DFR1 is currently RES0.
1218 	 */
1219 	taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1220 				      info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1221 	taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1222 				      info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1223 	/*
1224 	 * Even in big.LITTLE, processors should be identical instruction-set
1225 	 * wise.
1226 	 */
1227 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1228 				      info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1229 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1230 				      info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1231 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1232 				      info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1233 
1234 	/*
1235 	 * Differing PARange support is fine as long as all peripherals and
1236 	 * memory are mapped within the minimum PARange of all CPUs.
1237 	 * Linux should not care about secure memory.
1238 	 */
1239 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1240 				      info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1241 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1242 				      info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1243 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1244 				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1245 
1246 	taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1247 				      info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1248 	taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1249 				      info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1250 
1251 	taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1252 				      info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1253 
1254 	taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1255 				      info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1256 
1257 	if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1258 	    id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1259 		info->reg_zcr = read_zcr_features();
1260 		taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1261 					info->reg_zcr, boot->reg_zcr);
1262 
1263 		/* Probe vector lengths */
1264 		if (!system_capabilities_finalized())
1265 			vec_update_vq_map(ARM64_VEC_SVE);
1266 	}
1267 
1268 	if (IS_ENABLED(CONFIG_ARM64_SME) &&
1269 	    id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1270 		info->reg_smcr = read_smcr_features();
1271 		/*
1272 		 * We mask out SMPS since even if the hardware
1273 		 * supports priorities the kernel does not at present
1274 		 * and we block access to them.
1275 		 */
1276 		info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1277 		taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
1278 					info->reg_smcr, boot->reg_smcr);
1279 
1280 		/* Probe vector lengths */
1281 		if (!system_capabilities_finalized())
1282 			vec_update_vq_map(ARM64_VEC_SME);
1283 	}
1284 
1285 	/*
1286 	 * The kernel uses the LDGM/STGM instructions and the number of tags
1287 	 * they read/write depends on the GMID_EL1.BS field. Check that the
1288 	 * value is the same on all CPUs.
1289 	 */
1290 	if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1291 	    id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1292 		taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1293 					      info->reg_gmid, boot->reg_gmid);
1294 	}
1295 
1296 	/*
1297 	 * If we don't have AArch32 at all then skip the checks entirely
1298 	 * as the register values may be UNKNOWN and we're not going to be
1299 	 * using them for anything.
1300 	 *
1301 	 * This relies on a sanitised view of the AArch64 ID registers
1302 	 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1303 	 */
1304 	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1305 		lazy_init_32bit_cpu_features(info, boot);
1306 		taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1307 						   &boot->aarch32);
1308 	}
1309 
1310 	/*
1311 	 * Mismatched CPU features are a recipe for disaster. Don't even
1312 	 * pretend to support them.
1313 	 */
1314 	if (taint) {
1315 		pr_warn_once("Unsupported CPU feature variation detected.\n");
1316 		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1317 	}
1318 }
1319 
read_sanitised_ftr_reg(u32 id)1320 u64 read_sanitised_ftr_reg(u32 id)
1321 {
1322 	struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1323 
1324 	if (!regp)
1325 		return 0;
1326 	return regp->sys_val;
1327 }
1328 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1329 
1330 #define read_sysreg_case(r)	\
1331 	case r:		val = read_sysreg_s(r); break;
1332 
1333 /*
1334  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1335  * Read the system register on the current CPU
1336  */
__read_sysreg_by_encoding(u32 sys_id)1337 u64 __read_sysreg_by_encoding(u32 sys_id)
1338 {
1339 	struct arm64_ftr_reg *regp;
1340 	u64 val;
1341 
1342 	switch (sys_id) {
1343 	read_sysreg_case(SYS_ID_PFR0_EL1);
1344 	read_sysreg_case(SYS_ID_PFR1_EL1);
1345 	read_sysreg_case(SYS_ID_PFR2_EL1);
1346 	read_sysreg_case(SYS_ID_DFR0_EL1);
1347 	read_sysreg_case(SYS_ID_DFR1_EL1);
1348 	read_sysreg_case(SYS_ID_MMFR0_EL1);
1349 	read_sysreg_case(SYS_ID_MMFR1_EL1);
1350 	read_sysreg_case(SYS_ID_MMFR2_EL1);
1351 	read_sysreg_case(SYS_ID_MMFR3_EL1);
1352 	read_sysreg_case(SYS_ID_MMFR4_EL1);
1353 	read_sysreg_case(SYS_ID_MMFR5_EL1);
1354 	read_sysreg_case(SYS_ID_ISAR0_EL1);
1355 	read_sysreg_case(SYS_ID_ISAR1_EL1);
1356 	read_sysreg_case(SYS_ID_ISAR2_EL1);
1357 	read_sysreg_case(SYS_ID_ISAR3_EL1);
1358 	read_sysreg_case(SYS_ID_ISAR4_EL1);
1359 	read_sysreg_case(SYS_ID_ISAR5_EL1);
1360 	read_sysreg_case(SYS_ID_ISAR6_EL1);
1361 	read_sysreg_case(SYS_MVFR0_EL1);
1362 	read_sysreg_case(SYS_MVFR1_EL1);
1363 	read_sysreg_case(SYS_MVFR2_EL1);
1364 
1365 	read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1366 	read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1367 	read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1368 	read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1369 	read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1370 	read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1371 	read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1372 	read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1373 	read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1374 	read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1375 	read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1376 	read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1377 
1378 	read_sysreg_case(SYS_CNTFRQ_EL0);
1379 	read_sysreg_case(SYS_CTR_EL0);
1380 	read_sysreg_case(SYS_DCZID_EL0);
1381 
1382 	default:
1383 		BUG();
1384 		return 0;
1385 	}
1386 
1387 	regp  = get_arm64_ftr_reg(sys_id);
1388 	if (regp) {
1389 		val &= ~regp->override->mask;
1390 		val |= (regp->override->val & regp->override->mask);
1391 	}
1392 
1393 	return val;
1394 }
1395 
1396 #include <linux/irqchip/arm-gic-v3.h>
1397 
1398 static bool
has_always(const struct arm64_cpu_capabilities * entry,int scope)1399 has_always(const struct arm64_cpu_capabilities *entry, int scope)
1400 {
1401 	return true;
1402 }
1403 
1404 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)1405 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1406 {
1407 	int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1408 						    entry->field_width,
1409 						    entry->sign);
1410 
1411 	return val >= entry->min_field_value;
1412 }
1413 
1414 static u64
read_scoped_sysreg(const struct arm64_cpu_capabilities * entry,int scope)1415 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)
1416 {
1417 	WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1418 	if (scope == SCOPE_SYSTEM)
1419 		return read_sanitised_ftr_reg(entry->sys_reg);
1420 	else
1421 		return __read_sysreg_by_encoding(entry->sys_reg);
1422 }
1423 
1424 static bool
has_user_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1425 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1426 {
1427 	int mask;
1428 	struct arm64_ftr_reg *regp;
1429 	u64 val = read_scoped_sysreg(entry, scope);
1430 
1431 	regp = get_arm64_ftr_reg(entry->sys_reg);
1432 	if (!regp)
1433 		return false;
1434 
1435 	mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask,
1436 							  entry->field_pos,
1437 							  entry->field_width);
1438 	if (!mask)
1439 		return false;
1440 
1441 	return feature_matches(val, entry);
1442 }
1443 
1444 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1445 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1446 {
1447 	u64 val = read_scoped_sysreg(entry, scope);
1448 	return feature_matches(val, entry);
1449 }
1450 
system_32bit_el0_cpumask(void)1451 const struct cpumask *system_32bit_el0_cpumask(void)
1452 {
1453 	if (!system_supports_32bit_el0())
1454 		return cpu_none_mask;
1455 
1456 	if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1457 		return cpu_32bit_el0_mask;
1458 
1459 	return cpu_possible_mask;
1460 }
1461 
parse_32bit_el0_param(char * str)1462 static int __init parse_32bit_el0_param(char *str)
1463 {
1464 	allow_mismatched_32bit_el0 = true;
1465 	return 0;
1466 }
1467 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1468 
aarch32_el0_show(struct device * dev,struct device_attribute * attr,char * buf)1469 static ssize_t aarch32_el0_show(struct device *dev,
1470 				struct device_attribute *attr, char *buf)
1471 {
1472 	const struct cpumask *mask = system_32bit_el0_cpumask();
1473 
1474 	return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1475 }
1476 static const DEVICE_ATTR_RO(aarch32_el0);
1477 
aarch32_el0_sysfs_init(void)1478 static int __init aarch32_el0_sysfs_init(void)
1479 {
1480 	if (!allow_mismatched_32bit_el0)
1481 		return 0;
1482 
1483 	return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1484 }
1485 device_initcall(aarch32_el0_sysfs_init);
1486 
has_32bit_el0(const struct arm64_cpu_capabilities * entry,int scope)1487 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1488 {
1489 	if (!has_cpuid_feature(entry, scope))
1490 		return allow_mismatched_32bit_el0;
1491 
1492 	if (scope == SCOPE_SYSTEM)
1493 		pr_info("detected: 32-bit EL0 Support\n");
1494 
1495 	return true;
1496 }
1497 
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)1498 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1499 {
1500 	bool has_sre;
1501 
1502 	if (!has_cpuid_feature(entry, scope))
1503 		return false;
1504 
1505 	has_sre = gic_enable_sre();
1506 	if (!has_sre)
1507 		pr_warn_once("%s present but disabled by higher exception level\n",
1508 			     entry->desc);
1509 
1510 	return has_sre;
1511 }
1512 
has_no_hw_prefetch(const struct arm64_cpu_capabilities * entry,int __unused)1513 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1514 {
1515 	u32 midr = read_cpuid_id();
1516 
1517 	/* Cavium ThunderX pass 1.x and 2.x */
1518 	return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1519 		MIDR_CPU_VAR_REV(0, 0),
1520 		MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1521 }
1522 
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)1523 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1524 {
1525 	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1526 
1527 	return cpuid_feature_extract_signed_field(pfr0,
1528 					ID_AA64PFR0_EL1_FP_SHIFT) < 0;
1529 }
1530 
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)1531 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1532 			  int scope)
1533 {
1534 	u64 ctr;
1535 
1536 	if (scope == SCOPE_SYSTEM)
1537 		ctr = arm64_ftr_reg_ctrel0.sys_val;
1538 	else
1539 		ctr = read_cpuid_effective_cachetype();
1540 
1541 	return ctr & BIT(CTR_EL0_IDC_SHIFT);
1542 }
1543 
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)1544 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1545 {
1546 	/*
1547 	 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1548 	 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1549 	 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1550 	 * value.
1551 	 */
1552 	if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1553 		sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1554 }
1555 
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)1556 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1557 			  int scope)
1558 {
1559 	u64 ctr;
1560 
1561 	if (scope == SCOPE_SYSTEM)
1562 		ctr = arm64_ftr_reg_ctrel0.sys_val;
1563 	else
1564 		ctr = read_cpuid_cachetype();
1565 
1566 	return ctr & BIT(CTR_EL0_DIC_SHIFT);
1567 }
1568 
1569 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)1570 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1571 {
1572 	/*
1573 	 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1574 	 * may share TLB entries with a CPU stuck in the crashed
1575 	 * kernel.
1576 	 */
1577 	if (is_kdump_kernel())
1578 		return false;
1579 
1580 	if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1581 		return false;
1582 
1583 	return has_cpuid_feature(entry, scope);
1584 }
1585 
1586 /*
1587  * This check is triggered during the early boot before the cpufeature
1588  * is initialised. Checking the status on the local CPU allows the boot
1589  * CPU to detect the need for non-global mappings and thus avoiding a
1590  * pagetable re-write after all the CPUs are booted. This check will be
1591  * anyway run on individual CPUs, allowing us to get the consistent
1592  * state once the SMP CPUs are up and thus make the switch to non-global
1593  * mappings if required.
1594  */
kaslr_requires_kpti(void)1595 bool kaslr_requires_kpti(void)
1596 {
1597 	if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1598 		return false;
1599 
1600 	/*
1601 	 * E0PD does a similar job to KPTI so can be used instead
1602 	 * where available.
1603 	 */
1604 	if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1605 		u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1606 		if (cpuid_feature_extract_unsigned_field(mmfr2,
1607 						ID_AA64MMFR2_EL1_E0PD_SHIFT))
1608 			return false;
1609 	}
1610 
1611 	/*
1612 	 * Systems affected by Cavium erratum 24756 are incompatible
1613 	 * with KPTI.
1614 	 */
1615 	if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1616 		extern const struct midr_range cavium_erratum_27456_cpus[];
1617 
1618 		if (is_midr_in_range_list(read_cpuid_id(),
1619 					  cavium_erratum_27456_cpus))
1620 			return false;
1621 	}
1622 
1623 	return kaslr_offset() > 0;
1624 }
1625 
1626 static bool __meltdown_safe = true;
1627 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1628 
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)1629 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1630 				int scope)
1631 {
1632 	/* List of CPUs that are not vulnerable and don't need KPTI */
1633 	static const struct midr_range kpti_safe_list[] = {
1634 		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1635 		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1636 		MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1637 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1638 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1639 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1640 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1641 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1642 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1643 		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1644 		MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1645 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1646 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1647 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1648 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1649 		{ /* sentinel */ }
1650 	};
1651 	char const *str = "kpti command line option";
1652 	bool meltdown_safe;
1653 
1654 	meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1655 
1656 	/* Defer to CPU feature registers */
1657 	if (has_cpuid_feature(entry, scope))
1658 		meltdown_safe = true;
1659 
1660 	if (!meltdown_safe)
1661 		__meltdown_safe = false;
1662 
1663 	/*
1664 	 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1665 	 * ThunderX leads to apparent I-cache corruption of kernel text, which
1666 	 * ends as well as you might imagine. Don't even try. We cannot rely
1667 	 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1668 	 * because cpucap detection order may change. However, since we know
1669 	 * affected CPUs are always in a homogeneous configuration, it is
1670 	 * safe to rely on this_cpu_has_cap() here.
1671 	 */
1672 	if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1673 		str = "ARM64_WORKAROUND_CAVIUM_27456";
1674 		__kpti_forced = -1;
1675 	}
1676 
1677 	/* Useful for KASLR robustness */
1678 	if (kaslr_requires_kpti()) {
1679 		if (!__kpti_forced) {
1680 			str = "KASLR";
1681 			__kpti_forced = 1;
1682 		}
1683 	}
1684 
1685 	if (cpu_mitigations_off() && !__kpti_forced) {
1686 		str = "mitigations=off";
1687 		__kpti_forced = -1;
1688 	}
1689 
1690 	if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1691 		pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1692 		return false;
1693 	}
1694 
1695 	/* Forced? */
1696 	if (__kpti_forced) {
1697 		pr_info_once("kernel page table isolation forced %s by %s\n",
1698 			     __kpti_forced > 0 ? "ON" : "OFF", str);
1699 		return __kpti_forced > 0;
1700 	}
1701 
1702 	return !meltdown_safe;
1703 }
1704 
1705 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1706 #define KPTI_NG_TEMP_VA		(-(1UL << PMD_SHIFT))
1707 
1708 extern
1709 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1710 			     phys_addr_t size, pgprot_t prot,
1711 			     phys_addr_t (*pgtable_alloc)(int), int flags);
1712 
1713 static phys_addr_t kpti_ng_temp_alloc;
1714 
kpti_ng_pgd_alloc(int shift)1715 static phys_addr_t kpti_ng_pgd_alloc(int shift)
1716 {
1717 	kpti_ng_temp_alloc -= PAGE_SIZE;
1718 	return kpti_ng_temp_alloc;
1719 }
1720 
1721 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1722 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1723 {
1724 	typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1725 	extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1726 	kpti_remap_fn *remap_fn;
1727 
1728 	int cpu = smp_processor_id();
1729 	int levels = CONFIG_PGTABLE_LEVELS;
1730 	int order = order_base_2(levels);
1731 	u64 kpti_ng_temp_pgd_pa = 0;
1732 	pgd_t *kpti_ng_temp_pgd;
1733 	u64 alloc = 0;
1734 
1735 	if (__this_cpu_read(this_cpu_vector) == vectors) {
1736 		const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1737 
1738 		__this_cpu_write(this_cpu_vector, v);
1739 	}
1740 
1741 	/*
1742 	 * We don't need to rewrite the page-tables if either we've done
1743 	 * it already or we have KASLR enabled and therefore have not
1744 	 * created any global mappings at all.
1745 	 */
1746 	if (arm64_use_ng_mappings)
1747 		return;
1748 
1749 	remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1750 
1751 	if (!cpu) {
1752 		alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1753 		kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1754 		kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1755 
1756 		//
1757 		// Create a minimal page table hierarchy that permits us to map
1758 		// the swapper page tables temporarily as we traverse them.
1759 		//
1760 		// The physical pages are laid out as follows:
1761 		//
1762 		// +--------+-/-------+-/------ +-\\--------+
1763 		// :  PTE[] : | PMD[] : | PUD[] : || PGD[]  :
1764 		// +--------+-\-------+-\------ +-//--------+
1765 		//      ^
1766 		// The first page is mapped into this hierarchy at a PMD_SHIFT
1767 		// aligned virtual address, so that we can manipulate the PTE
1768 		// level entries while the mapping is active. The first entry
1769 		// covers the PTE[] page itself, the remaining entries are free
1770 		// to be used as a ad-hoc fixmap.
1771 		//
1772 		create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1773 					KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1774 					kpti_ng_pgd_alloc, 0);
1775 	}
1776 
1777 	cpu_install_idmap();
1778 	remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1779 	cpu_uninstall_idmap();
1780 
1781 	if (!cpu) {
1782 		free_pages(alloc, order);
1783 		arm64_use_ng_mappings = true;
1784 	}
1785 }
1786 #else
1787 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1788 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1789 {
1790 }
1791 #endif	/* CONFIG_UNMAP_KERNEL_AT_EL0 */
1792 
parse_kpti(char * str)1793 static int __init parse_kpti(char *str)
1794 {
1795 	bool enabled;
1796 	int ret = strtobool(str, &enabled);
1797 
1798 	if (ret)
1799 		return ret;
1800 
1801 	__kpti_forced = enabled ? 1 : -1;
1802 	return 0;
1803 }
1804 early_param("kpti", parse_kpti);
1805 
1806 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1807 static inline void __cpu_enable_hw_dbm(void)
1808 {
1809 	u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1810 
1811 	write_sysreg(tcr, tcr_el1);
1812 	isb();
1813 	local_flush_tlb_all();
1814 }
1815 
cpu_has_broken_dbm(void)1816 static bool cpu_has_broken_dbm(void)
1817 {
1818 	/* List of CPUs which have broken DBM support. */
1819 	static const struct midr_range cpus[] = {
1820 #ifdef CONFIG_ARM64_ERRATUM_1024718
1821 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1822 		/* Kryo4xx Silver (rdpe => r1p0) */
1823 		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1824 #endif
1825 #ifdef CONFIG_ARM64_ERRATUM_2051678
1826 		MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1827 #endif
1828 		{},
1829 	};
1830 
1831 	return is_midr_in_range_list(read_cpuid_id(), cpus);
1832 }
1833 
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1834 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1835 {
1836 	return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1837 	       !cpu_has_broken_dbm();
1838 }
1839 
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1840 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1841 {
1842 	if (cpu_can_use_dbm(cap))
1843 		__cpu_enable_hw_dbm();
1844 }
1845 
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1846 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1847 		       int __unused)
1848 {
1849 	static bool detected = false;
1850 	/*
1851 	 * DBM is a non-conflicting feature. i.e, the kernel can safely
1852 	 * run a mix of CPUs with and without the feature. So, we
1853 	 * unconditionally enable the capability to allow any late CPU
1854 	 * to use the feature. We only enable the control bits on the
1855 	 * CPU, if it actually supports.
1856 	 *
1857 	 * We have to make sure we print the "feature" detection only
1858 	 * when at least one CPU actually uses it. So check if this CPU
1859 	 * can actually use it and print the message exactly once.
1860 	 *
1861 	 * This is safe as all CPUs (including secondary CPUs - due to the
1862 	 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1863 	 * goes through the "matches" check exactly once. Also if a CPU
1864 	 * matches the criteria, it is guaranteed that the CPU will turn
1865 	 * the DBM on, as the capability is unconditionally enabled.
1866 	 */
1867 	if (!detected && cpu_can_use_dbm(cap)) {
1868 		detected = true;
1869 		pr_info("detected: Hardware dirty bit management\n");
1870 	}
1871 
1872 	return true;
1873 }
1874 
1875 #endif
1876 
1877 #ifdef CONFIG_ARM64_AMU_EXTN
1878 
1879 /*
1880  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1881  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1882  * information regarding all the events that it supports. When a CPU bit is
1883  * set in the cpumask, the user of this feature can only rely on the presence
1884  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1885  * counters are enabled or access to these counters is enabled by code
1886  * executed at higher exception levels (firmware).
1887  */
1888 static struct cpumask amu_cpus __read_mostly;
1889 
cpu_has_amu_feat(int cpu)1890 bool cpu_has_amu_feat(int cpu)
1891 {
1892 	return cpumask_test_cpu(cpu, &amu_cpus);
1893 }
1894 
get_cpu_with_amu_feat(void)1895 int get_cpu_with_amu_feat(void)
1896 {
1897 	return cpumask_any(&amu_cpus);
1898 }
1899 
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)1900 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1901 {
1902 	if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1903 		pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1904 			smp_processor_id());
1905 		cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1906 
1907 		/* 0 reference values signal broken/disabled counters */
1908 		if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1909 			update_freq_counters_refs();
1910 	}
1911 }
1912 
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)1913 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1914 		    int __unused)
1915 {
1916 	/*
1917 	 * The AMU extension is a non-conflicting feature: the kernel can
1918 	 * safely run a mix of CPUs with and without support for the
1919 	 * activity monitors extension. Therefore, unconditionally enable
1920 	 * the capability to allow any late CPU to use the feature.
1921 	 *
1922 	 * With this feature unconditionally enabled, the cpu_enable
1923 	 * function will be called for all CPUs that match the criteria,
1924 	 * including secondary and hotplugged, marking this feature as
1925 	 * present on that respective CPU. The enable function will also
1926 	 * print a detection message.
1927 	 */
1928 
1929 	return true;
1930 }
1931 #else
get_cpu_with_amu_feat(void)1932 int get_cpu_with_amu_feat(void)
1933 {
1934 	return nr_cpu_ids;
1935 }
1936 #endif
1937 
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1938 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1939 {
1940 	return is_kernel_in_hyp_mode();
1941 }
1942 
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1943 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1944 {
1945 	/*
1946 	 * Copy register values that aren't redirected by hardware.
1947 	 *
1948 	 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1949 	 * this value to tpidr_el2 before we patch the code. Once we've done
1950 	 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1951 	 * do anything here.
1952 	 */
1953 	if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1954 		write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1955 }
1956 
1957 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1958 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1959 {
1960 	/*
1961 	 * We modify PSTATE. This won't work from irq context as the PSTATE
1962 	 * is discarded once we return from the exception.
1963 	 */
1964 	WARN_ON_ONCE(in_interrupt());
1965 
1966 	sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1967 	set_pstate_pan(1);
1968 }
1969 #endif /* CONFIG_ARM64_PAN */
1970 
1971 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1972 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1973 {
1974 	/* Firmware may have left a deferred SError in this register. */
1975 	write_sysreg_s(0, SYS_DISR_EL1);
1976 }
1977 #endif /* CONFIG_ARM64_RAS_EXTN */
1978 
1979 #ifdef CONFIG_ARM64_PTR_AUTH
has_address_auth_cpucap(const struct arm64_cpu_capabilities * entry,int scope)1980 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1981 {
1982 	int boot_val, sec_val;
1983 
1984 	/* We don't expect to be called with SCOPE_SYSTEM */
1985 	WARN_ON(scope == SCOPE_SYSTEM);
1986 	/*
1987 	 * The ptr-auth feature levels are not intercompatible with lower
1988 	 * levels. Hence we must match ptr-auth feature level of the secondary
1989 	 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1990 	 * from the sanitised register whereas direct register read is done for
1991 	 * the secondary CPUs.
1992 	 * The sanitised feature state is guaranteed to match that of the
1993 	 * boot CPU as a mismatched secondary CPU is parked before it gets
1994 	 * a chance to update the state, with the capability.
1995 	 */
1996 	boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1997 					       entry->field_pos, entry->sign);
1998 	if (scope & SCOPE_BOOT_CPU)
1999 		return boot_val >= entry->min_field_value;
2000 	/* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
2001 	sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
2002 					      entry->field_pos, entry->sign);
2003 	return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
2004 }
2005 
has_address_auth_metacap(const struct arm64_cpu_capabilities * entry,int scope)2006 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
2007 				     int scope)
2008 {
2009 	bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
2010 	bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
2011 	bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
2012 
2013 	return apa || apa3 || api;
2014 }
2015 
has_generic_auth(const struct arm64_cpu_capabilities * entry,int __unused)2016 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
2017 			     int __unused)
2018 {
2019 	bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
2020 	bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
2021 	bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
2022 
2023 	return gpa || gpa3 || gpi;
2024 }
2025 #endif /* CONFIG_ARM64_PTR_AUTH */
2026 
2027 #ifdef CONFIG_ARM64_E0PD
cpu_enable_e0pd(struct arm64_cpu_capabilities const * cap)2028 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2029 {
2030 	if (this_cpu_has_cap(ARM64_HAS_E0PD))
2031 		sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2032 }
2033 #endif /* CONFIG_ARM64_E0PD */
2034 
2035 #ifdef CONFIG_ARM64_PSEUDO_NMI
2036 static bool enable_pseudo_nmi;
2037 
early_enable_pseudo_nmi(char * p)2038 static int __init early_enable_pseudo_nmi(char *p)
2039 {
2040 	return strtobool(p, &enable_pseudo_nmi);
2041 }
2042 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
2043 
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)2044 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2045 				   int scope)
2046 {
2047 	return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
2048 }
2049 #endif
2050 
2051 #ifdef CONFIG_ARM64_BTI
bti_enable(const struct arm64_cpu_capabilities * __unused)2052 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2053 {
2054 	/*
2055 	 * Use of X16/X17 for tail-calls and trampolines that jump to
2056 	 * function entry points using BR is a requirement for
2057 	 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2058 	 * So, be strict and forbid other BRs using other registers to
2059 	 * jump onto a PACIxSP instruction:
2060 	 */
2061 	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2062 	isb();
2063 }
2064 #endif /* CONFIG_ARM64_BTI */
2065 
2066 #ifdef CONFIG_ARM64_MTE
cpu_enable_mte(struct arm64_cpu_capabilities const * cap)2067 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2068 {
2069 	sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2070 
2071 	mte_cpu_setup();
2072 
2073 	/*
2074 	 * Clear the tags in the zero page. This needs to be done via the
2075 	 * linear map which has the Tagged attribute.
2076 	 */
2077 	if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
2078 		mte_clear_page_tags(lm_alias(empty_zero_page));
2079 
2080 	kasan_init_hw_tags_cpu();
2081 }
2082 #endif /* CONFIG_ARM64_MTE */
2083 
elf_hwcap_fixup(void)2084 static void elf_hwcap_fixup(void)
2085 {
2086 #ifdef CONFIG_ARM64_ERRATUM_1742098
2087 	if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
2088 		compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2089 #endif /* ARM64_ERRATUM_1742098 */
2090 }
2091 
2092 #ifdef CONFIG_KVM
is_kvm_protected_mode(const struct arm64_cpu_capabilities * entry,int __unused)2093 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2094 {
2095 	return kvm_get_mode() == KVM_MODE_PROTECTED;
2096 }
2097 #endif /* CONFIG_KVM */
2098 
cpu_trap_el0_impdef(const struct arm64_cpu_capabilities * __unused)2099 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2100 {
2101 	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2102 }
2103 
2104 /* Internal helper functions to match cpu capability type */
2105 static bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)2106 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2107 {
2108 	return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2109 }
2110 
2111 static bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)2112 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2113 {
2114 	return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2115 }
2116 
2117 static bool
cpucap_panic_on_conflict(const struct arm64_cpu_capabilities * cap)2118 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2119 {
2120 	return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2121 }
2122 
2123 static const struct arm64_cpu_capabilities arm64_features[] = {
2124 	{
2125 		.capability = ARM64_ALWAYS_BOOT,
2126 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2127 		.matches = has_always,
2128 	},
2129 	{
2130 		.capability = ARM64_ALWAYS_SYSTEM,
2131 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2132 		.matches = has_always,
2133 	},
2134 	{
2135 		.desc = "GIC system register CPU interface",
2136 		.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
2137 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2138 		.matches = has_useable_gicv3_cpuif,
2139 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2140 		.field_pos = ID_AA64PFR0_EL1_GIC_SHIFT,
2141 		.field_width = 4,
2142 		.sign = FTR_UNSIGNED,
2143 		.min_field_value = 1,
2144 	},
2145 	{
2146 		.desc = "Enhanced Counter Virtualization",
2147 		.capability = ARM64_HAS_ECV,
2148 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2149 		.matches = has_cpuid_feature,
2150 		.sys_reg = SYS_ID_AA64MMFR0_EL1,
2151 		.field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT,
2152 		.field_width = 4,
2153 		.sign = FTR_UNSIGNED,
2154 		.min_field_value = 1,
2155 	},
2156 #ifdef CONFIG_ARM64_PAN
2157 	{
2158 		.desc = "Privileged Access Never",
2159 		.capability = ARM64_HAS_PAN,
2160 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2161 		.matches = has_cpuid_feature,
2162 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
2163 		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
2164 		.field_width = 4,
2165 		.sign = FTR_UNSIGNED,
2166 		.min_field_value = 1,
2167 		.cpu_enable = cpu_enable_pan,
2168 	},
2169 #endif /* CONFIG_ARM64_PAN */
2170 #ifdef CONFIG_ARM64_EPAN
2171 	{
2172 		.desc = "Enhanced Privileged Access Never",
2173 		.capability = ARM64_HAS_EPAN,
2174 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2175 		.matches = has_cpuid_feature,
2176 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
2177 		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
2178 		.field_width = 4,
2179 		.sign = FTR_UNSIGNED,
2180 		.min_field_value = 3,
2181 	},
2182 #endif /* CONFIG_ARM64_EPAN */
2183 #ifdef CONFIG_ARM64_LSE_ATOMICS
2184 	{
2185 		.desc = "LSE atomic instructions",
2186 		.capability = ARM64_HAS_LSE_ATOMICS,
2187 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2188 		.matches = has_cpuid_feature,
2189 		.sys_reg = SYS_ID_AA64ISAR0_EL1,
2190 		.field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
2191 		.field_width = 4,
2192 		.sign = FTR_UNSIGNED,
2193 		.min_field_value = 2,
2194 	},
2195 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2196 	{
2197 		.desc = "Software prefetching using PRFM",
2198 		.capability = ARM64_HAS_NO_HW_PREFETCH,
2199 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2200 		.matches = has_no_hw_prefetch,
2201 	},
2202 	{
2203 		.desc = "Virtualization Host Extensions",
2204 		.capability = ARM64_HAS_VIRT_HOST_EXTN,
2205 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2206 		.matches = runs_at_el2,
2207 		.cpu_enable = cpu_copy_el2regs,
2208 	},
2209 	{
2210 		.capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2211 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2212 		.matches = has_32bit_el0,
2213 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2214 		.sign = FTR_UNSIGNED,
2215 		.field_pos = ID_AA64PFR0_EL1_EL0_SHIFT,
2216 		.field_width = 4,
2217 		.min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT,
2218 	},
2219 #ifdef CONFIG_KVM
2220 	{
2221 		.desc = "32-bit EL1 Support",
2222 		.capability = ARM64_HAS_32BIT_EL1,
2223 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2224 		.matches = has_cpuid_feature,
2225 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2226 		.sign = FTR_UNSIGNED,
2227 		.field_pos = ID_AA64PFR0_EL1_EL1_SHIFT,
2228 		.field_width = 4,
2229 		.min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT,
2230 	},
2231 	{
2232 		.desc = "Protected KVM",
2233 		.capability = ARM64_KVM_PROTECTED_MODE,
2234 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2235 		.matches = is_kvm_protected_mode,
2236 	},
2237 #endif
2238 	{
2239 		.desc = "Kernel page table isolation (KPTI)",
2240 		.capability = ARM64_UNMAP_KERNEL_AT_EL0,
2241 		.type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2242 		/*
2243 		 * The ID feature fields below are used to indicate that
2244 		 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2245 		 * more details.
2246 		 */
2247 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2248 		.field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT,
2249 		.field_width = 4,
2250 		.min_field_value = 1,
2251 		.matches = unmap_kernel_at_el0,
2252 		.cpu_enable = kpti_install_ng_mappings,
2253 	},
2254 	{
2255 		/* FP/SIMD is not implemented */
2256 		.capability = ARM64_HAS_NO_FPSIMD,
2257 		.type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2258 		.min_field_value = 0,
2259 		.matches = has_no_fpsimd,
2260 	},
2261 #ifdef CONFIG_ARM64_PMEM
2262 	{
2263 		.desc = "Data cache clean to Point of Persistence",
2264 		.capability = ARM64_HAS_DCPOP,
2265 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2266 		.matches = has_cpuid_feature,
2267 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2268 		.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
2269 		.field_width = 4,
2270 		.min_field_value = 1,
2271 	},
2272 	{
2273 		.desc = "Data cache clean to Point of Deep Persistence",
2274 		.capability = ARM64_HAS_DCPODP,
2275 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2276 		.matches = has_cpuid_feature,
2277 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2278 		.sign = FTR_UNSIGNED,
2279 		.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
2280 		.field_width = 4,
2281 		.min_field_value = 2,
2282 	},
2283 #endif
2284 #ifdef CONFIG_ARM64_SVE
2285 	{
2286 		.desc = "Scalable Vector Extension",
2287 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2288 		.capability = ARM64_SVE,
2289 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2290 		.sign = FTR_UNSIGNED,
2291 		.field_pos = ID_AA64PFR0_EL1_SVE_SHIFT,
2292 		.field_width = 4,
2293 		.min_field_value = ID_AA64PFR0_EL1_SVE_IMP,
2294 		.matches = has_cpuid_feature,
2295 		.cpu_enable = sve_kernel_enable,
2296 	},
2297 #endif /* CONFIG_ARM64_SVE */
2298 #ifdef CONFIG_ARM64_RAS_EXTN
2299 	{
2300 		.desc = "RAS Extension Support",
2301 		.capability = ARM64_HAS_RAS_EXTN,
2302 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2303 		.matches = has_cpuid_feature,
2304 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2305 		.sign = FTR_UNSIGNED,
2306 		.field_pos = ID_AA64PFR0_EL1_RAS_SHIFT,
2307 		.field_width = 4,
2308 		.min_field_value = ID_AA64PFR0_EL1_RAS_IMP,
2309 		.cpu_enable = cpu_clear_disr,
2310 	},
2311 #endif /* CONFIG_ARM64_RAS_EXTN */
2312 #ifdef CONFIG_ARM64_AMU_EXTN
2313 	{
2314 		/*
2315 		 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2316 		 * Therefore, don't provide .desc as we don't want the detection
2317 		 * message to be shown until at least one CPU is detected to
2318 		 * support the feature.
2319 		 */
2320 		.capability = ARM64_HAS_AMU_EXTN,
2321 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2322 		.matches = has_amu,
2323 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2324 		.sign = FTR_UNSIGNED,
2325 		.field_pos = ID_AA64PFR0_EL1_AMU_SHIFT,
2326 		.field_width = 4,
2327 		.min_field_value = ID_AA64PFR0_EL1_AMU_IMP,
2328 		.cpu_enable = cpu_amu_enable,
2329 	},
2330 #endif /* CONFIG_ARM64_AMU_EXTN */
2331 	{
2332 		.desc = "Data cache clean to the PoU not required for I/D coherence",
2333 		.capability = ARM64_HAS_CACHE_IDC,
2334 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2335 		.matches = has_cache_idc,
2336 		.cpu_enable = cpu_emulate_effective_ctr,
2337 	},
2338 	{
2339 		.desc = "Instruction cache invalidation not required for I/D coherence",
2340 		.capability = ARM64_HAS_CACHE_DIC,
2341 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2342 		.matches = has_cache_dic,
2343 	},
2344 	{
2345 		.desc = "Stage-2 Force Write-Back",
2346 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2347 		.capability = ARM64_HAS_STAGE2_FWB,
2348 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
2349 		.sign = FTR_UNSIGNED,
2350 		.field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT,
2351 		.field_width = 4,
2352 		.min_field_value = 1,
2353 		.matches = has_cpuid_feature,
2354 	},
2355 	{
2356 		.desc = "ARMv8.4 Translation Table Level",
2357 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2358 		.capability = ARM64_HAS_ARMv8_4_TTL,
2359 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
2360 		.sign = FTR_UNSIGNED,
2361 		.field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT,
2362 		.field_width = 4,
2363 		.min_field_value = 1,
2364 		.matches = has_cpuid_feature,
2365 	},
2366 	{
2367 		.desc = "TLB range maintenance instructions",
2368 		.capability = ARM64_HAS_TLB_RANGE,
2369 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2370 		.matches = has_cpuid_feature,
2371 		.sys_reg = SYS_ID_AA64ISAR0_EL1,
2372 		.field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT,
2373 		.field_width = 4,
2374 		.sign = FTR_UNSIGNED,
2375 		.min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE,
2376 	},
2377 #ifdef CONFIG_ARM64_HW_AFDBM
2378 	{
2379 		/*
2380 		 * Since we turn this on always, we don't want the user to
2381 		 * think that the feature is available when it may not be.
2382 		 * So hide the description.
2383 		 *
2384 		 * .desc = "Hardware pagetable Dirty Bit Management",
2385 		 *
2386 		 */
2387 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2388 		.capability = ARM64_HW_DBM,
2389 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
2390 		.sign = FTR_UNSIGNED,
2391 		.field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
2392 		.field_width = 4,
2393 		.min_field_value = 2,
2394 		.matches = has_hw_dbm,
2395 		.cpu_enable = cpu_enable_hw_dbm,
2396 	},
2397 #endif
2398 	{
2399 		.desc = "CRC32 instructions",
2400 		.capability = ARM64_HAS_CRC32,
2401 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2402 		.matches = has_cpuid_feature,
2403 		.sys_reg = SYS_ID_AA64ISAR0_EL1,
2404 		.field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
2405 		.field_width = 4,
2406 		.min_field_value = 1,
2407 	},
2408 	{
2409 		.desc = "Speculative Store Bypassing Safe (SSBS)",
2410 		.capability = ARM64_SSBS,
2411 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2412 		.matches = has_cpuid_feature,
2413 		.sys_reg = SYS_ID_AA64PFR1_EL1,
2414 		.field_pos = ID_AA64PFR1_EL1_SSBS_SHIFT,
2415 		.field_width = 4,
2416 		.sign = FTR_UNSIGNED,
2417 		.min_field_value = ID_AA64PFR1_EL1_SSBS_IMP,
2418 	},
2419 #ifdef CONFIG_ARM64_CNP
2420 	{
2421 		.desc = "Common not Private translations",
2422 		.capability = ARM64_HAS_CNP,
2423 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2424 		.matches = has_useable_cnp,
2425 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
2426 		.sign = FTR_UNSIGNED,
2427 		.field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT,
2428 		.field_width = 4,
2429 		.min_field_value = 1,
2430 		.cpu_enable = cpu_enable_cnp,
2431 	},
2432 #endif
2433 	{
2434 		.desc = "Speculation barrier (SB)",
2435 		.capability = ARM64_HAS_SB,
2436 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2437 		.matches = has_cpuid_feature,
2438 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2439 		.field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,
2440 		.field_width = 4,
2441 		.sign = FTR_UNSIGNED,
2442 		.min_field_value = 1,
2443 	},
2444 #ifdef CONFIG_ARM64_PTR_AUTH
2445 	{
2446 		.desc = "Address authentication (architected QARMA5 algorithm)",
2447 		.capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2448 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2449 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2450 		.sign = FTR_UNSIGNED,
2451 		.field_pos = ID_AA64ISAR1_EL1_APA_SHIFT,
2452 		.field_width = 4,
2453 		.min_field_value = ID_AA64ISAR1_EL1_APA_PAuth,
2454 		.matches = has_address_auth_cpucap,
2455 	},
2456 	{
2457 		.desc = "Address authentication (architected QARMA3 algorithm)",
2458 		.capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2459 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2460 		.sys_reg = SYS_ID_AA64ISAR2_EL1,
2461 		.sign = FTR_UNSIGNED,
2462 		.field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT,
2463 		.field_width = 4,
2464 		.min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth,
2465 		.matches = has_address_auth_cpucap,
2466 	},
2467 	{
2468 		.desc = "Address authentication (IMP DEF algorithm)",
2469 		.capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2470 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2471 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2472 		.sign = FTR_UNSIGNED,
2473 		.field_pos = ID_AA64ISAR1_EL1_API_SHIFT,
2474 		.field_width = 4,
2475 		.min_field_value = ID_AA64ISAR1_EL1_API_PAuth,
2476 		.matches = has_address_auth_cpucap,
2477 	},
2478 	{
2479 		.capability = ARM64_HAS_ADDRESS_AUTH,
2480 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2481 		.matches = has_address_auth_metacap,
2482 	},
2483 	{
2484 		.desc = "Generic authentication (architected QARMA5 algorithm)",
2485 		.capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2486 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2487 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2488 		.sign = FTR_UNSIGNED,
2489 		.field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT,
2490 		.field_width = 4,
2491 		.min_field_value = ID_AA64ISAR1_EL1_GPA_IMP,
2492 		.matches = has_cpuid_feature,
2493 	},
2494 	{
2495 		.desc = "Generic authentication (architected QARMA3 algorithm)",
2496 		.capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2497 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2498 		.sys_reg = SYS_ID_AA64ISAR2_EL1,
2499 		.sign = FTR_UNSIGNED,
2500 		.field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT,
2501 		.field_width = 4,
2502 		.min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP,
2503 		.matches = has_cpuid_feature,
2504 	},
2505 	{
2506 		.desc = "Generic authentication (IMP DEF algorithm)",
2507 		.capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2508 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2509 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2510 		.sign = FTR_UNSIGNED,
2511 		.field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT,
2512 		.field_width = 4,
2513 		.min_field_value = ID_AA64ISAR1_EL1_GPI_IMP,
2514 		.matches = has_cpuid_feature,
2515 	},
2516 	{
2517 		.capability = ARM64_HAS_GENERIC_AUTH,
2518 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2519 		.matches = has_generic_auth,
2520 	},
2521 #endif /* CONFIG_ARM64_PTR_AUTH */
2522 #ifdef CONFIG_ARM64_PSEUDO_NMI
2523 	{
2524 		/*
2525 		 * Depends on having GICv3
2526 		 */
2527 		.desc = "IRQ priority masking",
2528 		.capability = ARM64_HAS_IRQ_PRIO_MASKING,
2529 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2530 		.matches = can_use_gic_priorities,
2531 		.sys_reg = SYS_ID_AA64PFR0_EL1,
2532 		.field_pos = ID_AA64PFR0_EL1_GIC_SHIFT,
2533 		.field_width = 4,
2534 		.sign = FTR_UNSIGNED,
2535 		.min_field_value = 1,
2536 	},
2537 #endif
2538 #ifdef CONFIG_ARM64_E0PD
2539 	{
2540 		.desc = "E0PD",
2541 		.capability = ARM64_HAS_E0PD,
2542 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2543 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
2544 		.sign = FTR_UNSIGNED,
2545 		.field_width = 4,
2546 		.field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT,
2547 		.matches = has_cpuid_feature,
2548 		.min_field_value = 1,
2549 		.cpu_enable = cpu_enable_e0pd,
2550 	},
2551 #endif
2552 	{
2553 		.desc = "Random Number Generator",
2554 		.capability = ARM64_HAS_RNG,
2555 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2556 		.matches = has_cpuid_feature,
2557 		.sys_reg = SYS_ID_AA64ISAR0_EL1,
2558 		.field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
2559 		.field_width = 4,
2560 		.sign = FTR_UNSIGNED,
2561 		.min_field_value = 1,
2562 	},
2563 #ifdef CONFIG_ARM64_BTI
2564 	{
2565 		.desc = "Branch Target Identification",
2566 		.capability = ARM64_BTI,
2567 #ifdef CONFIG_ARM64_BTI_KERNEL
2568 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2569 #else
2570 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2571 #endif
2572 		.matches = has_cpuid_feature,
2573 		.cpu_enable = bti_enable,
2574 		.sys_reg = SYS_ID_AA64PFR1_EL1,
2575 		.field_pos = ID_AA64PFR1_EL1_BT_SHIFT,
2576 		.field_width = 4,
2577 		.min_field_value = ID_AA64PFR1_EL1_BT_IMP,
2578 		.sign = FTR_UNSIGNED,
2579 	},
2580 #endif
2581 #ifdef CONFIG_ARM64_MTE
2582 	{
2583 		.desc = "Memory Tagging Extension",
2584 		.capability = ARM64_MTE,
2585 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2586 		.matches = has_cpuid_feature,
2587 		.sys_reg = SYS_ID_AA64PFR1_EL1,
2588 		.field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
2589 		.field_width = 4,
2590 		.min_field_value = ID_AA64PFR1_EL1_MTE_MTE2,
2591 		.sign = FTR_UNSIGNED,
2592 		.cpu_enable = cpu_enable_mte,
2593 	},
2594 	{
2595 		.desc = "Asymmetric MTE Tag Check Fault",
2596 		.capability = ARM64_MTE_ASYMM,
2597 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2598 		.matches = has_cpuid_feature,
2599 		.sys_reg = SYS_ID_AA64PFR1_EL1,
2600 		.field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
2601 		.field_width = 4,
2602 		.min_field_value = ID_AA64PFR1_EL1_MTE_MTE3,
2603 		.sign = FTR_UNSIGNED,
2604 	},
2605 #endif /* CONFIG_ARM64_MTE */
2606 	{
2607 		.desc = "RCpc load-acquire (LDAPR)",
2608 		.capability = ARM64_HAS_LDAPR,
2609 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2610 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
2611 		.sign = FTR_UNSIGNED,
2612 		.field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,
2613 		.field_width = 4,
2614 		.matches = has_cpuid_feature,
2615 		.min_field_value = 1,
2616 	},
2617 #ifdef CONFIG_ARM64_SME
2618 	{
2619 		.desc = "Scalable Matrix Extension",
2620 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2621 		.capability = ARM64_SME,
2622 		.sys_reg = SYS_ID_AA64PFR1_EL1,
2623 		.sign = FTR_UNSIGNED,
2624 		.field_pos = ID_AA64PFR1_EL1_SME_SHIFT,
2625 		.field_width = 4,
2626 		.min_field_value = ID_AA64PFR1_EL1_SME_IMP,
2627 		.matches = has_cpuid_feature,
2628 		.cpu_enable = sme_kernel_enable,
2629 	},
2630 	/* FA64 should be sorted after the base SME capability */
2631 	{
2632 		.desc = "FA64",
2633 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2634 		.capability = ARM64_SME_FA64,
2635 		.sys_reg = SYS_ID_AA64SMFR0_EL1,
2636 		.sign = FTR_UNSIGNED,
2637 		.field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT,
2638 		.field_width = 1,
2639 		.min_field_value = ID_AA64SMFR0_EL1_FA64_IMP,
2640 		.matches = has_cpuid_feature,
2641 		.cpu_enable = fa64_kernel_enable,
2642 	},
2643 #endif /* CONFIG_ARM64_SME */
2644 	{
2645 		.desc = "WFx with timeout",
2646 		.capability = ARM64_HAS_WFXT,
2647 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2648 		.sys_reg = SYS_ID_AA64ISAR2_EL1,
2649 		.sign = FTR_UNSIGNED,
2650 		.field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT,
2651 		.field_width = 4,
2652 		.matches = has_cpuid_feature,
2653 		.min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP,
2654 	},
2655 	{
2656 		.desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2657 		.capability = ARM64_HAS_TIDCP1,
2658 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2659 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
2660 		.sign = FTR_UNSIGNED,
2661 		.field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT,
2662 		.field_width = 4,
2663 		.min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP,
2664 		.matches = has_cpuid_feature,
2665 		.cpu_enable = cpu_trap_el0_impdef,
2666 	},
2667 	{},
2668 };
2669 
2670 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value)			\
2671 		.matches = has_user_cpuid_feature,					\
2672 		.sys_reg = reg,							\
2673 		.field_pos = field,						\
2674 		.field_width = width,						\
2675 		.sign = s,							\
2676 		.min_field_value = min_value,
2677 
2678 #define __HWCAP_CAP(name, cap_type, cap)					\
2679 		.desc = name,							\
2680 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,				\
2681 		.hwcap_type = cap_type,						\
2682 		.hwcap = cap,							\
2683 
2684 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap)		\
2685 	{									\
2686 		__HWCAP_CAP(#cap, cap_type, cap)				\
2687 		HWCAP_CPUID_MATCH(reg, field, width, s, min_value) 		\
2688 	}
2689 
2690 #define HWCAP_MULTI_CAP(list, cap_type, cap)					\
2691 	{									\
2692 		__HWCAP_CAP(#cap, cap_type, cap)				\
2693 		.matches = cpucap_multi_entry_cap_matches,			\
2694 		.match_list = list,						\
2695 	}
2696 
2697 #define HWCAP_CAP_MATCH(match, cap_type, cap)					\
2698 	{									\
2699 		__HWCAP_CAP(#cap, cap_type, cap)				\
2700 		.matches = match,						\
2701 	}
2702 
2703 #ifdef CONFIG_ARM64_PTR_AUTH
2704 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2705 	{
2706 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT,
2707 				  4, FTR_UNSIGNED,
2708 				  ID_AA64ISAR1_EL1_APA_PAuth)
2709 	},
2710 	{
2711 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT,
2712 				  4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth)
2713 	},
2714 	{
2715 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT,
2716 				  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth)
2717 	},
2718 	{},
2719 };
2720 
2721 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2722 	{
2723 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT,
2724 				  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)
2725 	},
2726 	{
2727 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT,
2728 				  4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP)
2729 	},
2730 	{
2731 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT,
2732 				  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP)
2733 	},
2734 	{},
2735 };
2736 #endif
2737 
2738 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2739 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2740 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2741 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2742 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2743 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2744 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2745 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2746 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2747 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2748 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2749 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2750 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2751 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2752 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2753 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2754 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2755 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2756 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2757 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2758 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2759 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2760 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2761 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2762 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2763 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2764 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2765 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2766 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2767 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2768 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2769 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2770 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2771 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2772 	HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2773 #ifdef CONFIG_ARM64_SVE
2774 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
2775 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2776 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2777 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2778 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2779 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2780 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
2781 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2782 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2783 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2784 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2785 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2786 #endif
2787 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SSBS_SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2788 #ifdef CONFIG_ARM64_BTI
2789 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_BT_IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
2790 #endif
2791 #ifdef CONFIG_ARM64_PTR_AUTH
2792 	HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2793 	HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2794 #endif
2795 #ifdef CONFIG_ARM64_MTE
2796 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
2797 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2798 #endif /* CONFIG_ARM64_MTE */
2799 	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2800 	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2801 	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2802 	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2803 #ifdef CONFIG_ARM64_SME
2804 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME_IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
2805 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2806 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2807 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2808 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2809 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2810 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2811 	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2812 #endif /* CONFIG_ARM64_SME */
2813 	{},
2814 };
2815 
2816 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)2817 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2818 {
2819 	/*
2820 	 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2821 	 * in line with that of arm32 as in vfp_init(). We make sure that the
2822 	 * check is future proof, by making sure value is non-zero.
2823 	 */
2824 	u32 mvfr1;
2825 
2826 	WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2827 	if (scope == SCOPE_SYSTEM)
2828 		mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2829 	else
2830 		mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2831 
2832 	return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2833 		cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2834 		cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2835 }
2836 #endif
2837 
2838 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2839 #ifdef CONFIG_COMPAT
2840 	HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2841 	HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2842 	/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2843 	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2844 	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2845 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2846 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2847 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2848 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2849 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2850 #endif
2851 	{},
2852 };
2853 
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)2854 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2855 {
2856 	switch (cap->hwcap_type) {
2857 	case CAP_HWCAP:
2858 		cpu_set_feature(cap->hwcap);
2859 		break;
2860 #ifdef CONFIG_COMPAT
2861 	case CAP_COMPAT_HWCAP:
2862 		compat_elf_hwcap |= (u32)cap->hwcap;
2863 		break;
2864 	case CAP_COMPAT_HWCAP2:
2865 		compat_elf_hwcap2 |= (u32)cap->hwcap;
2866 		break;
2867 #endif
2868 	default:
2869 		WARN_ON(1);
2870 		break;
2871 	}
2872 }
2873 
2874 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)2875 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2876 {
2877 	bool rc;
2878 
2879 	switch (cap->hwcap_type) {
2880 	case CAP_HWCAP:
2881 		rc = cpu_have_feature(cap->hwcap);
2882 		break;
2883 #ifdef CONFIG_COMPAT
2884 	case CAP_COMPAT_HWCAP:
2885 		rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2886 		break;
2887 	case CAP_COMPAT_HWCAP2:
2888 		rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2889 		break;
2890 #endif
2891 	default:
2892 		WARN_ON(1);
2893 		rc = false;
2894 	}
2895 
2896 	return rc;
2897 }
2898 
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)2899 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2900 {
2901 	/* We support emulation of accesses to CPU ID feature registers */
2902 	cpu_set_named_feature(CPUID);
2903 	for (; hwcaps->matches; hwcaps++)
2904 		if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2905 			cap_set_elf_hwcap(hwcaps);
2906 }
2907 
update_cpu_capabilities(u16 scope_mask)2908 static void update_cpu_capabilities(u16 scope_mask)
2909 {
2910 	int i;
2911 	const struct arm64_cpu_capabilities *caps;
2912 
2913 	scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2914 	for (i = 0; i < ARM64_NCAPS; i++) {
2915 		caps = cpu_hwcaps_ptrs[i];
2916 		if (!caps || !(caps->type & scope_mask) ||
2917 		    cpus_have_cap(caps->capability) ||
2918 		    !caps->matches(caps, cpucap_default_scope(caps)))
2919 			continue;
2920 
2921 		if (caps->desc)
2922 			pr_info("detected: %s\n", caps->desc);
2923 		cpus_set_cap(caps->capability);
2924 
2925 		if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2926 			set_bit(caps->capability, boot_capabilities);
2927 	}
2928 }
2929 
2930 /*
2931  * Enable all the available capabilities on this CPU. The capabilities
2932  * with BOOT_CPU scope are handled separately and hence skipped here.
2933  */
cpu_enable_non_boot_scope_capabilities(void * __unused)2934 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2935 {
2936 	int i;
2937 	u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2938 
2939 	for_each_available_cap(i) {
2940 		const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2941 
2942 		if (WARN_ON(!cap))
2943 			continue;
2944 
2945 		if (!(cap->type & non_boot_scope))
2946 			continue;
2947 
2948 		if (cap->cpu_enable)
2949 			cap->cpu_enable(cap);
2950 	}
2951 	return 0;
2952 }
2953 
2954 /*
2955  * Run through the enabled capabilities and enable() it on all active
2956  * CPUs
2957  */
enable_cpu_capabilities(u16 scope_mask)2958 static void __init enable_cpu_capabilities(u16 scope_mask)
2959 {
2960 	int i;
2961 	const struct arm64_cpu_capabilities *caps;
2962 	bool boot_scope;
2963 
2964 	scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2965 	boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2966 
2967 	for (i = 0; i < ARM64_NCAPS; i++) {
2968 		unsigned int num;
2969 
2970 		caps = cpu_hwcaps_ptrs[i];
2971 		if (!caps || !(caps->type & scope_mask))
2972 			continue;
2973 		num = caps->capability;
2974 		if (!cpus_have_cap(num))
2975 			continue;
2976 
2977 		if (boot_scope && caps->cpu_enable)
2978 			/*
2979 			 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2980 			 * before any secondary CPU boots. Thus, each secondary
2981 			 * will enable the capability as appropriate via
2982 			 * check_local_cpu_capabilities(). The only exception is
2983 			 * the boot CPU, for which the capability must be
2984 			 * enabled here. This approach avoids costly
2985 			 * stop_machine() calls for this case.
2986 			 */
2987 			caps->cpu_enable(caps);
2988 	}
2989 
2990 	/*
2991 	 * For all non-boot scope capabilities, use stop_machine()
2992 	 * as it schedules the work allowing us to modify PSTATE,
2993 	 * instead of on_each_cpu() which uses an IPI, giving us a
2994 	 * PSTATE that disappears when we return.
2995 	 */
2996 	if (!boot_scope)
2997 		stop_machine(cpu_enable_non_boot_scope_capabilities,
2998 			     NULL, cpu_online_mask);
2999 }
3000 
3001 /*
3002  * Run through the list of capabilities to check for conflicts.
3003  * If the system has already detected a capability, take necessary
3004  * action on this CPU.
3005  */
verify_local_cpu_caps(u16 scope_mask)3006 static void verify_local_cpu_caps(u16 scope_mask)
3007 {
3008 	int i;
3009 	bool cpu_has_cap, system_has_cap;
3010 	const struct arm64_cpu_capabilities *caps;
3011 
3012 	scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3013 
3014 	for (i = 0; i < ARM64_NCAPS; i++) {
3015 		caps = cpu_hwcaps_ptrs[i];
3016 		if (!caps || !(caps->type & scope_mask))
3017 			continue;
3018 
3019 		cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
3020 		system_has_cap = cpus_have_cap(caps->capability);
3021 
3022 		if (system_has_cap) {
3023 			/*
3024 			 * Check if the new CPU misses an advertised feature,
3025 			 * which is not safe to miss.
3026 			 */
3027 			if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
3028 				break;
3029 			/*
3030 			 * We have to issue cpu_enable() irrespective of
3031 			 * whether the CPU has it or not, as it is enabeld
3032 			 * system wide. It is upto the call back to take
3033 			 * appropriate action on this CPU.
3034 			 */
3035 			if (caps->cpu_enable)
3036 				caps->cpu_enable(caps);
3037 		} else {
3038 			/*
3039 			 * Check if the CPU has this capability if it isn't
3040 			 * safe to have when the system doesn't.
3041 			 */
3042 			if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3043 				break;
3044 		}
3045 	}
3046 
3047 	if (i < ARM64_NCAPS) {
3048 		pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3049 			smp_processor_id(), caps->capability,
3050 			caps->desc, system_has_cap, cpu_has_cap);
3051 
3052 		if (cpucap_panic_on_conflict(caps))
3053 			cpu_panic_kernel();
3054 		else
3055 			cpu_die_early();
3056 	}
3057 }
3058 
3059 /*
3060  * Check for CPU features that are used in early boot
3061  * based on the Boot CPU value.
3062  */
check_early_cpu_features(void)3063 static void check_early_cpu_features(void)
3064 {
3065 	verify_cpu_asid_bits();
3066 
3067 	verify_local_cpu_caps(SCOPE_BOOT_CPU);
3068 }
3069 
3070 static void
__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)3071 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3072 {
3073 
3074 	for (; caps->matches; caps++)
3075 		if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3076 			pr_crit("CPU%d: missing HWCAP: %s\n",
3077 					smp_processor_id(), caps->desc);
3078 			cpu_die_early();
3079 		}
3080 }
3081 
verify_local_elf_hwcaps(void)3082 static void verify_local_elf_hwcaps(void)
3083 {
3084 	__verify_local_elf_hwcaps(arm64_elf_hwcaps);
3085 
3086 	if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3087 		__verify_local_elf_hwcaps(compat_elf_hwcaps);
3088 }
3089 
verify_sve_features(void)3090 static void verify_sve_features(void)
3091 {
3092 	u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
3093 	u64 zcr = read_zcr_features();
3094 
3095 	unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
3096 	unsigned int len = zcr & ZCR_ELx_LEN_MASK;
3097 
3098 	if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
3099 		pr_crit("CPU%d: SVE: vector length support mismatch\n",
3100 			smp_processor_id());
3101 		cpu_die_early();
3102 	}
3103 
3104 	/* Add checks on other ZCR bits here if necessary */
3105 }
3106 
verify_sme_features(void)3107 static void verify_sme_features(void)
3108 {
3109 	u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
3110 	u64 smcr = read_smcr_features();
3111 
3112 	unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
3113 	unsigned int len = smcr & SMCR_ELx_LEN_MASK;
3114 
3115 	if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
3116 		pr_crit("CPU%d: SME: vector length support mismatch\n",
3117 			smp_processor_id());
3118 		cpu_die_early();
3119 	}
3120 
3121 	/* Add checks on other SMCR bits here if necessary */
3122 }
3123 
verify_hyp_capabilities(void)3124 static void verify_hyp_capabilities(void)
3125 {
3126 	u64 safe_mmfr1, mmfr0, mmfr1;
3127 	int parange, ipa_max;
3128 	unsigned int safe_vmid_bits, vmid_bits;
3129 
3130 	if (!IS_ENABLED(CONFIG_KVM))
3131 		return;
3132 
3133 	safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3134 	mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3135 	mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3136 
3137 	/* Verify VMID bits */
3138 	safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3139 	vmid_bits = get_vmid_bits(mmfr1);
3140 	if (vmid_bits < safe_vmid_bits) {
3141 		pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3142 		cpu_die_early();
3143 	}
3144 
3145 	/* Verify IPA range */
3146 	parange = cpuid_feature_extract_unsigned_field(mmfr0,
3147 				ID_AA64MMFR0_EL1_PARANGE_SHIFT);
3148 	ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3149 	if (ipa_max < get_kvm_ipa_limit()) {
3150 		pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3151 		cpu_die_early();
3152 	}
3153 }
3154 
3155 /*
3156  * Run through the enabled system capabilities and enable() it on this CPU.
3157  * The capabilities were decided based on the available CPUs at the boot time.
3158  * Any new CPU should match the system wide status of the capability. If the
3159  * new CPU doesn't have a capability which the system now has enabled, we
3160  * cannot do anything to fix it up and could cause unexpected failures. So
3161  * we park the CPU.
3162  */
verify_local_cpu_capabilities(void)3163 static void verify_local_cpu_capabilities(void)
3164 {
3165 	/*
3166 	 * The capabilities with SCOPE_BOOT_CPU are checked from
3167 	 * check_early_cpu_features(), as they need to be verified
3168 	 * on all secondary CPUs.
3169 	 */
3170 	verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3171 	verify_local_elf_hwcaps();
3172 
3173 	if (system_supports_sve())
3174 		verify_sve_features();
3175 
3176 	if (system_supports_sme())
3177 		verify_sme_features();
3178 
3179 	if (is_hyp_mode_available())
3180 		verify_hyp_capabilities();
3181 }
3182 
check_local_cpu_capabilities(void)3183 void check_local_cpu_capabilities(void)
3184 {
3185 	/*
3186 	 * All secondary CPUs should conform to the early CPU features
3187 	 * in use by the kernel based on boot CPU.
3188 	 */
3189 	check_early_cpu_features();
3190 
3191 	/*
3192 	 * If we haven't finalised the system capabilities, this CPU gets
3193 	 * a chance to update the errata work arounds and local features.
3194 	 * Otherwise, this CPU should verify that it has all the system
3195 	 * advertised capabilities.
3196 	 */
3197 	if (!system_capabilities_finalized())
3198 		update_cpu_capabilities(SCOPE_LOCAL_CPU);
3199 	else
3200 		verify_local_cpu_capabilities();
3201 }
3202 
setup_boot_cpu_capabilities(void)3203 static void __init setup_boot_cpu_capabilities(void)
3204 {
3205 	/* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
3206 	update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3207 	/* Enable the SCOPE_BOOT_CPU capabilities alone right away */
3208 	enable_cpu_capabilities(SCOPE_BOOT_CPU);
3209 }
3210 
this_cpu_has_cap(unsigned int n)3211 bool this_cpu_has_cap(unsigned int n)
3212 {
3213 	if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3214 		const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3215 
3216 		if (cap)
3217 			return cap->matches(cap, SCOPE_LOCAL_CPU);
3218 	}
3219 
3220 	return false;
3221 }
3222 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3223 
3224 /*
3225  * This helper function is used in a narrow window when,
3226  * - The system wide safe registers are set with all the SMP CPUs and,
3227  * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
3228  * In all other cases cpus_have_{const_}cap() should be used.
3229  */
__system_matches_cap(unsigned int n)3230 static bool __maybe_unused __system_matches_cap(unsigned int n)
3231 {
3232 	if (n < ARM64_NCAPS) {
3233 		const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3234 
3235 		if (cap)
3236 			return cap->matches(cap, SCOPE_SYSTEM);
3237 	}
3238 	return false;
3239 }
3240 
cpu_set_feature(unsigned int num)3241 void cpu_set_feature(unsigned int num)
3242 {
3243 	set_bit(num, elf_hwcap);
3244 }
3245 
cpu_have_feature(unsigned int num)3246 bool cpu_have_feature(unsigned int num)
3247 {
3248 	return test_bit(num, elf_hwcap);
3249 }
3250 EXPORT_SYMBOL_GPL(cpu_have_feature);
3251 
cpu_get_elf_hwcap(void)3252 unsigned long cpu_get_elf_hwcap(void)
3253 {
3254 	/*
3255 	 * We currently only populate the first 32 bits of AT_HWCAP. Please
3256 	 * note that for userspace compatibility we guarantee that bits 62
3257 	 * and 63 will always be returned as 0.
3258 	 */
3259 	return elf_hwcap[0];
3260 }
3261 
cpu_get_elf_hwcap2(void)3262 unsigned long cpu_get_elf_hwcap2(void)
3263 {
3264 	return elf_hwcap[1];
3265 }
3266 
setup_system_capabilities(void)3267 static void __init setup_system_capabilities(void)
3268 {
3269 	/*
3270 	 * We have finalised the system-wide safe feature
3271 	 * registers, finalise the capabilities that depend
3272 	 * on it. Also enable all the available capabilities,
3273 	 * that are not enabled already.
3274 	 */
3275 	update_cpu_capabilities(SCOPE_SYSTEM);
3276 	enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3277 }
3278 
setup_cpu_features(void)3279 void __init setup_cpu_features(void)
3280 {
3281 	u32 cwg;
3282 
3283 	setup_system_capabilities();
3284 	setup_elf_hwcaps(arm64_elf_hwcaps);
3285 
3286 	if (system_supports_32bit_el0()) {
3287 		setup_elf_hwcaps(compat_elf_hwcaps);
3288 		elf_hwcap_fixup();
3289 	}
3290 
3291 	if (system_uses_ttbr0_pan())
3292 		pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3293 
3294 	sve_setup();
3295 	sme_setup();
3296 	minsigstksz_setup();
3297 
3298 	/*
3299 	 * Check for sane CTR_EL0.CWG value.
3300 	 */
3301 	cwg = cache_type_cwg();
3302 	if (!cwg)
3303 		pr_warn("No Cache Writeback Granule information, assuming %d\n",
3304 			ARCH_DMA_MINALIGN);
3305 }
3306 
enable_mismatched_32bit_el0(unsigned int cpu)3307 static int enable_mismatched_32bit_el0(unsigned int cpu)
3308 {
3309 	/*
3310 	 * The first 32-bit-capable CPU we detected and so can no longer
3311 	 * be offlined by userspace. -1 indicates we haven't yet onlined
3312 	 * a 32-bit-capable CPU.
3313 	 */
3314 	static int lucky_winner = -1;
3315 
3316 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3317 	bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3318 
3319 	if (cpu_32bit) {
3320 		cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3321 		static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3322 	}
3323 
3324 	if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3325 		return 0;
3326 
3327 	if (lucky_winner >= 0)
3328 		return 0;
3329 
3330 	/*
3331 	 * We've detected a mismatch. We need to keep one of our CPUs with
3332 	 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3333 	 * every CPU in the system for a 32-bit task.
3334 	 */
3335 	lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3336 							 cpu_active_mask);
3337 	get_cpu_device(lucky_winner)->offline_disabled = true;
3338 	setup_elf_hwcaps(compat_elf_hwcaps);
3339 	elf_hwcap_fixup();
3340 	pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3341 		cpu, lucky_winner);
3342 	return 0;
3343 }
3344 
init_32bit_el0_mask(void)3345 static int __init init_32bit_el0_mask(void)
3346 {
3347 	if (!allow_mismatched_32bit_el0)
3348 		return 0;
3349 
3350 	if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3351 		return -ENOMEM;
3352 
3353 	return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3354 				 "arm64/mismatched_32bit_el0:online",
3355 				 enable_mismatched_32bit_el0, NULL);
3356 }
3357 subsys_initcall_sync(init_32bit_el0_mask);
3358 
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)3359 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3360 {
3361 	cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir);
3362 }
3363 
3364 /*
3365  * We emulate only the following system register space.
3366  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3367  * See Table C5-6 System instruction encodings for System register accesses,
3368  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3369  */
is_emulated(u32 id)3370 static inline bool __attribute_const__ is_emulated(u32 id)
3371 {
3372 	return (sys_reg_Op0(id) == 0x3 &&
3373 		sys_reg_CRn(id) == 0x0 &&
3374 		sys_reg_Op1(id) == 0x0 &&
3375 		(sys_reg_CRm(id) == 0 ||
3376 		 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
3377 }
3378 
3379 /*
3380  * With CRm == 0, reg should be one of :
3381  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3382  */
emulate_id_reg(u32 id,u64 * valp)3383 static inline int emulate_id_reg(u32 id, u64 *valp)
3384 {
3385 	switch (id) {
3386 	case SYS_MIDR_EL1:
3387 		*valp = read_cpuid_id();
3388 		break;
3389 	case SYS_MPIDR_EL1:
3390 		*valp = SYS_MPIDR_SAFE_VAL;
3391 		break;
3392 	case SYS_REVIDR_EL1:
3393 		/* IMPLEMENTATION DEFINED values are emulated with 0 */
3394 		*valp = 0;
3395 		break;
3396 	default:
3397 		return -EINVAL;
3398 	}
3399 
3400 	return 0;
3401 }
3402 
emulate_sys_reg(u32 id,u64 * valp)3403 static int emulate_sys_reg(u32 id, u64 *valp)
3404 {
3405 	struct arm64_ftr_reg *regp;
3406 
3407 	if (!is_emulated(id))
3408 		return -EINVAL;
3409 
3410 	if (sys_reg_CRm(id) == 0)
3411 		return emulate_id_reg(id, valp);
3412 
3413 	regp = get_arm64_ftr_reg_nowarn(id);
3414 	if (regp)
3415 		*valp = arm64_ftr_reg_user_value(regp);
3416 	else
3417 		/*
3418 		 * The untracked registers are either IMPLEMENTATION DEFINED
3419 		 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3420 		 */
3421 		*valp = 0;
3422 	return 0;
3423 }
3424 
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)3425 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3426 {
3427 	int rc;
3428 	u64 val;
3429 
3430 	rc = emulate_sys_reg(sys_reg, &val);
3431 	if (!rc) {
3432 		pt_regs_write_reg(regs, rt, val);
3433 		arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3434 	}
3435 	return rc;
3436 }
3437 
emulate_mrs(struct pt_regs * regs,u32 insn)3438 static int emulate_mrs(struct pt_regs *regs, u32 insn)
3439 {
3440 	u32 sys_reg, rt;
3441 
3442 	/*
3443 	 * sys_reg values are defined as used in mrs/msr instruction.
3444 	 * shift the imm value to get the encoding.
3445 	 */
3446 	sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3447 	rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3448 	return do_emulate_mrs(regs, sys_reg, rt);
3449 }
3450 
3451 static struct undef_hook mrs_hook = {
3452 	.instr_mask = 0xffff0000,
3453 	.instr_val  = 0xd5380000,
3454 	.pstate_mask = PSR_AA32_MODE_MASK,
3455 	.pstate_val = PSR_MODE_EL0t,
3456 	.fn = emulate_mrs,
3457 };
3458 
enable_mrs_emulation(void)3459 static int __init enable_mrs_emulation(void)
3460 {
3461 	register_undef_hook(&mrs_hook);
3462 	return 0;
3463 }
3464 
3465 core_initcall(enable_mrs_emulation);
3466 
arm64_get_meltdown_state(void)3467 enum mitigation_state arm64_get_meltdown_state(void)
3468 {
3469 	if (__meltdown_safe)
3470 		return SPECTRE_UNAFFECTED;
3471 
3472 	if (arm64_kernel_unmapped_at_el0())
3473 		return SPECTRE_MITIGATED;
3474 
3475 	return SPECTRE_VULNERABLE;
3476 }
3477 
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)3478 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3479 			  char *buf)
3480 {
3481 	switch (arm64_get_meltdown_state()) {
3482 	case SPECTRE_UNAFFECTED:
3483 		return sprintf(buf, "Not affected\n");
3484 
3485 	case SPECTRE_MITIGATED:
3486 		return sprintf(buf, "Mitigation: PTI\n");
3487 
3488 	default:
3489 		return sprintf(buf, "Vulnerable\n");
3490 	}
3491 }
3492