1 /*
2  * Copyright (c) 2011 Broadcom Corporation
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef	_BRCM_AIUTILS_H_
18 #define	_BRCM_AIUTILS_H_
19 
20 #include <linux/bcma/bcma.h>
21 
22 #include "types.h"
23 
24 /*
25  * SOC Interconnect Address Map.
26  * All regions may not exist on all chips.
27  */
28 /* each core gets 4Kbytes for registers */
29 #define SI_CORE_SIZE		0x1000
30 /*
31  * Max cores (this is arbitrary, for software
32  * convenience and could be changed if we
33  * make any larger chips
34  */
35 #define	SI_MAXCORES		16
36 
37 /* Client Mode sb2pcitranslation2 size in bytes */
38 #define SI_PCI_DMA_SZ		0x40000000
39 
40 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
41 #define SI_PCIE_DMA_H32		0x80000000
42 
43 /* chipcommon being the first core: */
44 #define	SI_CC_IDX		0
45 
46 /* SOC Interconnect types (aka chip types) */
47 #define	SOCI_AI			1
48 
49 /* A register that is common to all cores to
50  * communicate w/PMU regarding clock control.
51  */
52 #define SI_CLK_CTL_ST		0x1e0	/* clock control and status */
53 
54 /* clk_ctl_st register */
55 #define	CCS_FORCEALP		0x00000001	/* force ALP request */
56 #define	CCS_FORCEHT		0x00000002	/* force HT request */
57 #define	CCS_FORCEILP		0x00000004	/* force ILP request */
58 #define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
59 #define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
60 #define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
61 #define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
62 #define CCS_ERSRC_REQ_SHIFT	8
63 #define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
64 #define	CCS_HTAVAIL		0x00020000	/* HT is available */
65 #define CCS_BP_ON_APL		0x00040000	/* RO: running on ALP clock */
66 #define CCS_BP_ON_HT		0x00080000	/* RO: running on HT clock */
67 #define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
68 #define CCS_ERSRC_STS_SHIFT	24
69 
70 /* HT avail in chipc and pcmcia on 4328a0 */
71 #define	CCS0_HTAVAIL		0x00010000
72 /* ALP avail in chipc and pcmcia on 4328a0 */
73 #define	CCS0_ALPAVAIL		0x00020000
74 
75 /* Not really related to SOC Interconnect, but a couple of software
76  * conventions for the use the flash space:
77  */
78 
79 /* Minumum amount of flash we support */
80 #define FLASH_MIN		0x00020000	/* Minimum flash size */
81 
82 #define	CC_SROM_OTP		0x800	/* SROM/OTP address space */
83 
84 /* gpiotimerval */
85 #define GPIO_ONTIME_SHIFT	16
86 
87 /* Fields in clkdiv */
88 #define	CLKD_OTP		0x000f0000
89 #define	CLKD_OTP_SHIFT		16
90 
91 /* Package IDs */
92 #define	BCM4717_PKG_ID		9	/* 4717 package id */
93 #define	BCM4718_PKG_ID		10	/* 4718 package id */
94 #define BCM43224_FAB_SMIC	0xa	/* the chip is manufactured by SMIC */
95 
96 /* these are router chips */
97 #define	BCM4716_CHIP_ID		0x4716	/* 4716 chipcommon chipid */
98 #define	BCM47162_CHIP_ID	47162	/* 47162 chipcommon chipid */
99 #define	BCM4748_CHIP_ID		0x4748	/* 4716 chipcommon chipid (OTP, RBBU) */
100 
101 /* dynamic clock control defines */
102 #define	LPOMINFREQ		25000	/* low power oscillator min */
103 #define	LPOMAXFREQ		43000	/* low power oscillator max */
104 #define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
105 #define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
106 #define	PCIMINFREQ		25000000	/* 25 MHz */
107 #define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */
108 
109 #define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
110 #define	ILP_DIV_1MHZ		4	/* ILP = 1 MHz */
111 
112 /* clkctl xtal what flags */
113 #define	XTAL			0x1	/* primary crystal oscillator (2050) */
114 #define	PLL			0x2	/* main chip pll */
115 
116 /* clkctl clk mode */
117 #define	CLK_FAST		0	/* force fast (pll) clock */
118 #define	CLK_DYNAMIC		2	/* enable dynamic clock control */
119 
120 /* GPIO usage priorities */
121 #define GPIO_DRV_PRIORITY	0	/* Driver */
122 #define GPIO_APP_PRIORITY	1	/* Application */
123 #define GPIO_HI_PRIORITY	2	/* Highest priority. Ignore GPIO
124 					 * reservation
125 					 */
126 
127 /* GPIO pull up/down */
128 #define GPIO_PULLUP		0
129 #define GPIO_PULLDN		1
130 
131 /* GPIO event regtype */
132 #define GPIO_REGEVT		0	/* GPIO register event */
133 #define GPIO_REGEVT_INTMSK	1	/* GPIO register event int mask */
134 #define GPIO_REGEVT_INTPOL	2	/* GPIO register event int polarity */
135 
136 /* device path */
137 #define SI_DEVPATH_BUFSZ	16	/* min buffer size in bytes */
138 
139 /* SI routine enumeration: to be used by update function with multiple hooks */
140 #define	SI_DOATTACH	1
141 #define SI_PCIDOWN	2
142 #define SI_PCIUP	3
143 
144 /*
145  * Data structure to export all chip specific common variables
146  *   public (read-only) portion of aiutils handle returned by si_attach()
147  */
148 struct si_pub {
149 	int ccrev;		/* chip common core rev */
150 	u32 cccaps;		/* chip common capabilities */
151 	int pmurev;		/* pmu core rev */
152 	u32 pmucaps;		/* pmu capabilities */
153 	uint boardtype;		/* board type */
154 	uint boardvendor;	/* board vendor */
155 	uint chip;		/* chip number */
156 	uint chiprev;		/* chip revision */
157 	uint chippkg;		/* chip package option */
158 };
159 
160 struct pci_dev;
161 
162 struct gpioh_item {
163 	void *arg;
164 	bool level;
165 	void (*handler) (u32 stat, void *arg);
166 	u32 event;
167 	struct gpioh_item *next;
168 };
169 
170 /* misc si info needed by some of the routines */
171 struct si_info {
172 	struct si_pub pub;	/* back plane public state (must be first) */
173 	struct bcma_bus *icbus;	/* handle to soc interconnect bus */
174 	struct pci_dev *pcibus;	/* handle to pci bus */
175 	struct pcicore_info *pch; /* PCI/E core handle */
176 	struct bcma_device *buscore;
177 	struct list_head var_list; /* list of srom variables */
178 
179 	u32 chipst;		/* chip status */
180 };
181 
182 /*
183  * Many of the routines below take an 'sih' handle as their first arg.
184  * Allocate this by calling si_attach().  Free it by calling si_detach().
185  * At any one time, the sih is logically focused on one particular si core
186  * (the "current core").
187  * Use si_setcore() or si_setcoreidx() to change the association to another core
188  */
189 
190 
191 /* AMBA Interconnect exported externs */
192 extern struct bcma_device *ai_findcore(struct si_pub *sih,
193 				       u16 coreid, u16 coreunit);
194 extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
195 
196 /* === exported functions === */
197 extern struct si_pub *ai_attach(struct bcma_bus *pbus);
198 extern void ai_detach(struct si_pub *sih);
199 extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
200 extern void ai_pci_setup(struct si_pub *sih, uint coremask);
201 extern void ai_clkctl_init(struct si_pub *sih);
202 extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
203 extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
204 extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
205 extern bool ai_deviceremoved(struct si_pub *sih);
206 extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
207 			     u8 priority);
208 
209 /* OTP status */
210 extern bool ai_is_otp_disabled(struct si_pub *sih);
211 
212 /* SPROM availability */
213 extern bool ai_is_sprom_available(struct si_pub *sih);
214 
215 extern void ai_pci_sleep(struct si_pub *sih);
216 extern void ai_pci_down(struct si_pub *sih);
217 extern void ai_pci_up(struct si_pub *sih);
218 extern int ai_pci_fixcfg(struct si_pub *sih);
219 
220 extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
221 /* Enable Ex-PA for 4313 */
222 extern void ai_epa_4313war(struct si_pub *sih);
223 
224 extern uint ai_get_buscoretype(struct si_pub *sih);
225 extern uint ai_get_buscorerev(struct si_pub *sih);
226 
ai_get_ccrev(struct si_pub * sih)227 static inline int ai_get_ccrev(struct si_pub *sih)
228 {
229 	return sih->ccrev;
230 }
231 
ai_get_cccaps(struct si_pub * sih)232 static inline u32 ai_get_cccaps(struct si_pub *sih)
233 {
234 	return sih->cccaps;
235 }
236 
ai_get_pmurev(struct si_pub * sih)237 static inline int ai_get_pmurev(struct si_pub *sih)
238 {
239 	return sih->pmurev;
240 }
241 
ai_get_pmucaps(struct si_pub * sih)242 static inline u32 ai_get_pmucaps(struct si_pub *sih)
243 {
244 	return sih->pmucaps;
245 }
246 
ai_get_boardtype(struct si_pub * sih)247 static inline uint ai_get_boardtype(struct si_pub *sih)
248 {
249 	return sih->boardtype;
250 }
251 
ai_get_boardvendor(struct si_pub * sih)252 static inline uint ai_get_boardvendor(struct si_pub *sih)
253 {
254 	return sih->boardvendor;
255 }
256 
ai_get_chip_id(struct si_pub * sih)257 static inline uint ai_get_chip_id(struct si_pub *sih)
258 {
259 	return sih->chip;
260 }
261 
ai_get_chiprev(struct si_pub * sih)262 static inline uint ai_get_chiprev(struct si_pub *sih)
263 {
264 	return sih->chiprev;
265 }
266 
ai_get_chippkg(struct si_pub * sih)267 static inline uint ai_get_chippkg(struct si_pub *sih)
268 {
269 	return sih->chippkg;
270 }
271 
272 #endif				/* _BRCM_AIUTILS_H_ */
273