1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_IA64_HW_IRQ_H
3 #define _ASM_IA64_HW_IRQ_H
4 
5 /*
6  * Copyright (C) 2001-2003 Hewlett-Packard Co
7  *	David Mosberger-Tang <davidm@hpl.hp.com>
8  */
9 
10 #include <linux/interrupt.h>
11 #include <linux/sched.h>
12 #include <linux/types.h>
13 #include <linux/profile.h>
14 
15 #include <asm/ptrace.h>
16 #include <asm/smp.h>
17 
18 typedef u8 ia64_vector;
19 
20 /*
21  * 0 special
22  *
23  * 1,3-14 are reserved from firmware
24  *
25  * 16-255 (vectored external interrupts) are available
26  *
27  * 15 spurious interrupt (see IVR)
28  *
29  * 16 lowest priority, 255 highest priority
30  *
31  * 15 classes of 16 interrupts each.
32  */
33 #define IA64_MIN_VECTORED_IRQ		 16
34 #define IA64_MAX_VECTORED_IRQ		255
35 #define IA64_NUM_VECTORS		256
36 
37 #define AUTO_ASSIGN			-1
38 
39 #define IA64_SPURIOUS_INT_VECTOR	0x0f
40 
41 /*
42  * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
43  */
44 #define IA64_CPEP_VECTOR		0x1c	/* corrected platform error polling vector */
45 #define IA64_CMCP_VECTOR		0x1d	/* corrected machine-check polling vector */
46 #define IA64_CPE_VECTOR			0x1e	/* corrected platform error interrupt vector */
47 #define IA64_CMC_VECTOR			0x1f	/* corrected machine-check interrupt vector */
48 /*
49  * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
50  * Use vectors 0x30-0xe7 as the default device vector range for ia64.
51  * Platforms may choose to reduce this range in platform_irq_setup, but the
52  * platform range must fall within
53  *	[IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR]
54  */
55 extern int ia64_first_device_vector;
56 extern int ia64_last_device_vector;
57 
58 #ifdef CONFIG_SMP
59 /* Reserve the lower priority vector than device vectors for "move IRQ" IPI */
60 #define IA64_IRQ_MOVE_VECTOR		0x30	/* "move IRQ" IPI */
61 #define IA64_DEF_FIRST_DEVICE_VECTOR	0x31
62 #else
63 #define IA64_DEF_FIRST_DEVICE_VECTOR	0x30
64 #endif
65 #define IA64_DEF_LAST_DEVICE_VECTOR	0xe7
66 #define IA64_FIRST_DEVICE_VECTOR	ia64_first_device_vector
67 #define IA64_LAST_DEVICE_VECTOR		ia64_last_device_vector
68 #define IA64_MAX_DEVICE_VECTORS		(IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1)
69 #define IA64_NUM_DEVICE_VECTORS		(IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
70 
71 #define IA64_MCA_RENDEZ_VECTOR		0xe8	/* MCA rendez interrupt */
72 #define IA64_TIMER_VECTOR		0xef	/* use highest-prio group 15 interrupt for timer */
73 #define	IA64_MCA_WAKEUP_VECTOR		0xf0	/* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
74 #define IA64_IPI_LOCAL_TLB_FLUSH	0xfc	/* SMP flush local TLB */
75 #define IA64_IPI_RESCHEDULE		0xfd	/* SMP reschedule */
76 #define IA64_IPI_VECTOR			0xfe	/* inter-processor interrupt vector */
77 
78 /* Used for encoding redirected irqs */
79 
80 #define IA64_IRQ_REDIRECTED		(1 << 31)
81 
82 /* IA64 inter-cpu interrupt related definitions */
83 
84 #define IA64_IPI_DEFAULT_BASE_ADDR	0xfee00000
85 
86 /* Delivery modes for inter-cpu interrupts */
87 enum {
88         IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
89         IA64_IPI_DM_PMI =       0x2,    /* pend a PMI */
90         IA64_IPI_DM_NMI =       0x4,    /* pend an NMI (vector 2) */
91         IA64_IPI_DM_INIT =      0x5,    /* pend an INIT interrupt */
92         IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
93 };
94 
95 extern __u8 isa_irq_to_vector_map[16];
96 #define isa_irq_to_vector(x)	isa_irq_to_vector_map[(x)]
97 
98 struct irq_cfg {
99 	ia64_vector vector;
100 	cpumask_t domain;
101 	cpumask_t old_domain;
102 	unsigned move_cleanup_count;
103 	u8 move_in_progress : 1;
104 };
105 extern spinlock_t vector_lock;
106 extern struct irq_cfg irq_cfg[NR_IRQS];
107 #define irq_to_domain(x)	irq_cfg[(x)].domain
108 DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq);
109 
110 extern struct irq_chip irq_type_ia64_lsapic;	/* CPU-internal interrupt controller */
111 
112 #define ia64_register_ipi	ia64_native_register_ipi
113 #define assign_irq_vector	ia64_native_assign_irq_vector
114 #define free_irq_vector		ia64_native_free_irq_vector
115 #define ia64_resend_irq		ia64_native_resend_irq
116 
117 extern void ia64_native_register_ipi(void);
118 extern int bind_irq_vector(int irq, int vector, cpumask_t domain);
119 extern int ia64_native_assign_irq_vector (int irq);	/* allocate a free vector */
120 extern void ia64_native_free_irq_vector (int vector);
121 extern int reserve_irq_vector (int vector);
122 extern void __setup_vector_irq(int cpu);
123 extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
124 extern void destroy_and_reserve_irq (unsigned int irq);
125 
126 #ifdef CONFIG_SMP
127 extern int irq_prepare_move(int irq, int cpu);
128 extern void irq_complete_move(unsigned int irq);
129 #else
irq_prepare_move(int irq,int cpu)130 static inline int irq_prepare_move(int irq, int cpu) { return 0; }
irq_complete_move(unsigned int irq)131 static inline void irq_complete_move(unsigned int irq) {}
132 #endif
133 
ia64_native_resend_irq(unsigned int vector)134 static inline void ia64_native_resend_irq(unsigned int vector)
135 {
136 	ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
137 }
138 
139 /*
140  * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
141  * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
142  * vectors and the Linux irq numbers.  However, larger systems may have multiple interrupt
143  * domains meaning that the translation from vector number to irq number depends on the
144  * interrupt domain that a CPU belongs to.  This API abstracts such platform-dependent
145  * differences and provides a uniform means to translate between vector and irq numbers
146  * and to obtain the irq descriptor for a given irq number.
147  */
148 
149 /* Extract the IA-64 vector that corresponds to IRQ.  */
150 static inline ia64_vector
irq_to_vector(int irq)151 irq_to_vector (int irq)
152 {
153 	return irq_cfg[irq].vector;
154 }
155 
156 /*
157  * Convert the local IA-64 vector to the corresponding irq number.  This translation is
158  * done in the context of the interrupt domain that the currently executing CPU belongs
159  * to.
160  */
161 static inline unsigned int
local_vector_to_irq(ia64_vector vec)162 local_vector_to_irq (ia64_vector vec)
163 {
164 	return __this_cpu_read(vector_irq[vec]);
165 }
166 
167 #endif /* _ASM_IA64_HW_IRQ_H */
168