1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #include "i40e.h"
5 #include <linux/ptp_classify.h>
6 #include <linux/posix-clock.h>
7
8 /* The XL710 timesync is very much like Intel's 82599 design when it comes to
9 * the fundamental clock design. However, the clock operations are much simpler
10 * in the XL710 because the device supports a full 64 bits of nanoseconds.
11 * Because the field is so wide, we can forgo the cycle counter and just
12 * operate with the nanosecond field directly without fear of overflow.
13 *
14 * Much like the 82599, the update period is dependent upon the link speed:
15 * At 40Gb, 25Gb, or no link, the period is 1.6ns.
16 * At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns)
17 * At 1Gb link, the period is multiplied by 20. (32ns)
18 * 1588 functionality is not supported at 100Mbps.
19 */
20 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
21 #define I40E_PTP_10GB_INCVAL_MULT 2
22 #define I40E_PTP_5GB_INCVAL_MULT 2
23 #define I40E_PTP_1GB_INCVAL_MULT 20
24 #define I40E_ISGN 0x80000000
25
26 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
27 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
28 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
29 #define I40E_SUBDEV_ID_25G_PTP_PIN 0xB
30
31 enum i40e_ptp_pin {
32 SDP3_2 = 0,
33 SDP3_3,
34 GPIO_4
35 };
36
37 enum i40e_can_set_pins_t {
38 CANT_DO_PINS = -1,
39 CAN_SET_PINS,
40 CAN_DO_PINS
41 };
42
43 static struct ptp_pin_desc sdp_desc[] = {
44 /* name idx func chan */
45 {"SDP3_2", SDP3_2, PTP_PF_NONE, 0},
46 {"SDP3_3", SDP3_3, PTP_PF_NONE, 1},
47 {"GPIO_4", GPIO_4, PTP_PF_NONE, 1},
48 };
49
50 enum i40e_ptp_gpio_pin_state {
51 end = -2,
52 invalid,
53 off,
54 in_A,
55 in_B,
56 out_A,
57 out_B,
58 };
59
60 static const char * const i40e_ptp_gpio_pin_state2str[] = {
61 "off", "in_A", "in_B", "out_A", "out_B"
62 };
63
64 enum i40e_ptp_led_pin_state {
65 led_end = -2,
66 low = 0,
67 high,
68 };
69
70 struct i40e_ptp_pins_settings {
71 enum i40e_ptp_gpio_pin_state sdp3_2;
72 enum i40e_ptp_gpio_pin_state sdp3_3;
73 enum i40e_ptp_gpio_pin_state gpio_4;
74 enum i40e_ptp_led_pin_state led2_0;
75 enum i40e_ptp_led_pin_state led2_1;
76 enum i40e_ptp_led_pin_state led3_0;
77 enum i40e_ptp_led_pin_state led3_1;
78 };
79
80 static const struct i40e_ptp_pins_settings
81 i40e_ptp_pin_led_allowed_states[] = {
82 {off, off, off, high, high, high, high},
83 {off, in_A, off, high, high, high, low},
84 {off, out_A, off, high, low, high, high},
85 {off, in_B, off, high, high, high, low},
86 {off, out_B, off, high, low, high, high},
87 {in_A, off, off, high, high, high, low},
88 {in_A, in_B, off, high, high, high, low},
89 {in_A, out_B, off, high, low, high, high},
90 {out_A, off, off, high, low, high, high},
91 {out_A, in_B, off, high, low, high, high},
92 {in_B, off, off, high, high, high, low},
93 {in_B, in_A, off, high, high, high, low},
94 {in_B, out_A, off, high, low, high, high},
95 {out_B, off, off, high, low, high, high},
96 {out_B, in_A, off, high, low, high, high},
97 {off, off, in_A, high, high, low, high},
98 {off, out_A, in_A, high, low, low, high},
99 {off, in_B, in_A, high, high, low, low},
100 {off, out_B, in_A, high, low, low, high},
101 {out_A, off, in_A, high, low, low, high},
102 {out_A, in_B, in_A, high, low, low, high},
103 {in_B, off, in_A, high, high, low, low},
104 {in_B, out_A, in_A, high, low, low, high},
105 {out_B, off, in_A, high, low, low, high},
106 {off, off, out_A, low, high, high, high},
107 {off, in_A, out_A, low, high, high, low},
108 {off, in_B, out_A, low, high, high, low},
109 {off, out_B, out_A, low, low, high, high},
110 {in_A, off, out_A, low, high, high, low},
111 {in_A, in_B, out_A, low, high, high, low},
112 {in_A, out_B, out_A, low, low, high, high},
113 {in_B, off, out_A, low, high, high, low},
114 {in_B, in_A, out_A, low, high, high, low},
115 {out_B, off, out_A, low, low, high, high},
116 {out_B, in_A, out_A, low, low, high, high},
117 {off, off, in_B, high, high, low, high},
118 {off, in_A, in_B, high, high, low, low},
119 {off, out_A, in_B, high, low, low, high},
120 {off, out_B, in_B, high, low, low, high},
121 {in_A, off, in_B, high, high, low, low},
122 {in_A, out_B, in_B, high, low, low, high},
123 {out_A, off, in_B, high, low, low, high},
124 {out_B, off, in_B, high, low, low, high},
125 {out_B, in_A, in_B, high, low, low, high},
126 {off, off, out_B, low, high, high, high},
127 {off, in_A, out_B, low, high, high, low},
128 {off, out_A, out_B, low, low, high, high},
129 {off, in_B, out_B, low, high, high, low},
130 {in_A, off, out_B, low, high, high, low},
131 {in_A, in_B, out_B, low, high, high, low},
132 {out_A, off, out_B, low, low, high, high},
133 {out_A, in_B, out_B, low, low, high, high},
134 {in_B, off, out_B, low, high, high, low},
135 {in_B, in_A, out_B, low, high, high, low},
136 {in_B, out_A, out_B, low, low, high, high},
137 {end, end, end, led_end, led_end, led_end, led_end}
138 };
139
140 static int i40e_ptp_set_pins(struct i40e_pf *pf,
141 struct i40e_ptp_pins_settings *pins);
142
143 /**
144 * i40e_ptp_extts0_work - workqueue task function
145 * @work: workqueue task structure
146 *
147 * Service for PTP external clock event
148 **/
i40e_ptp_extts0_work(struct work_struct * work)149 static void i40e_ptp_extts0_work(struct work_struct *work)
150 {
151 struct i40e_pf *pf = container_of(work, struct i40e_pf,
152 ptp_extts0_work);
153 struct i40e_hw *hw = &pf->hw;
154 struct ptp_clock_event event;
155 u32 hi, lo;
156
157 /* Event time is captured by one of the two matched registers
158 * PRTTSYN_EVNT_L: 32 LSB of sampled time event
159 * PRTTSYN_EVNT_H: 32 MSB of sampled time event
160 * Event is defined in PRTTSYN_EVNT_0 register
161 */
162 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0));
163 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0));
164
165 event.timestamp = (((u64)hi) << 32) | lo;
166
167 event.type = PTP_CLOCK_EXTTS;
168 event.index = hw->pf_id;
169
170 /* fire event */
171 ptp_clock_event(pf->ptp_clock, &event);
172 }
173
174 /**
175 * i40e_is_ptp_pin_dev - check if device supports PTP pins
176 * @hw: pointer to the hardware structure
177 *
178 * Return true if device supports PTP pins, false otherwise.
179 **/
i40e_is_ptp_pin_dev(struct i40e_hw * hw)180 static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw)
181 {
182 return hw->device_id == I40E_DEV_ID_25G_SFP28 &&
183 hw->subsystem_device_id == I40E_SUBDEV_ID_25G_PTP_PIN;
184 }
185
186 /**
187 * i40e_can_set_pins - check possibility of manipulating the pins
188 * @pf: board private structure
189 *
190 * Check if all conditions are satisfied to manipulate PTP pins.
191 * Return CAN_SET_PINS if pins can be set on a specific PF or
192 * return CAN_DO_PINS if pins can be manipulated within a NIC or
193 * return CANT_DO_PINS otherwise.
194 **/
i40e_can_set_pins(struct i40e_pf * pf)195 static enum i40e_can_set_pins_t i40e_can_set_pins(struct i40e_pf *pf)
196 {
197 if (!i40e_is_ptp_pin_dev(&pf->hw)) {
198 dev_warn(&pf->pdev->dev,
199 "PTP external clock not supported.\n");
200 return CANT_DO_PINS;
201 }
202
203 if (!pf->ptp_pins) {
204 dev_warn(&pf->pdev->dev,
205 "PTP PIN manipulation not allowed.\n");
206 return CANT_DO_PINS;
207 }
208
209 if (pf->hw.pf_id) {
210 dev_warn(&pf->pdev->dev,
211 "PTP PINs should be accessed via PF0.\n");
212 return CAN_DO_PINS;
213 }
214
215 return CAN_SET_PINS;
216 }
217
218 /**
219 * i40_ptp_reset_timing_events - Reset PTP timing events
220 * @pf: Board private structure
221 *
222 * This function resets timing events for pf.
223 **/
i40_ptp_reset_timing_events(struct i40e_pf * pf)224 static void i40_ptp_reset_timing_events(struct i40e_pf *pf)
225 {
226 u32 i;
227
228 spin_lock_bh(&pf->ptp_rx_lock);
229 for (i = 0; i <= I40E_PRTTSYN_RXTIME_L_MAX_INDEX; i++) {
230 /* reading and automatically clearing timing events registers */
231 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i));
232 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i));
233 pf->latch_events[i] = 0;
234 }
235 /* reading and automatically clearing timing events registers */
236 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L);
237 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H);
238
239 pf->tx_hwtstamp_timeouts = 0;
240 pf->tx_hwtstamp_skipped = 0;
241 pf->rx_hwtstamp_cleared = 0;
242 pf->latch_event_flags = 0;
243 spin_unlock_bh(&pf->ptp_rx_lock);
244 }
245
246 /**
247 * i40e_ptp_verify - check pins
248 * @ptp: ptp clock
249 * @pin: pin index
250 * @func: assigned function
251 * @chan: channel
252 *
253 * Check pins consistency.
254 * Return 0 on success or error on failure.
255 **/
i40e_ptp_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)256 static int i40e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
257 enum ptp_pin_function func, unsigned int chan)
258 {
259 switch (func) {
260 case PTP_PF_NONE:
261 case PTP_PF_EXTTS:
262 case PTP_PF_PEROUT:
263 break;
264 case PTP_PF_PHYSYNC:
265 return -EOPNOTSUPP;
266 }
267 return 0;
268 }
269
270 /**
271 * i40e_ptp_read - Read the PHC time from the device
272 * @pf: Board private structure
273 * @ts: timespec structure to hold the current time value
274 * @sts: structure to hold the system time before and after reading the PHC
275 *
276 * This function reads the PRTTSYN_TIME registers and stores them in a
277 * timespec. However, since the registers are 64 bits of nanoseconds, we must
278 * convert the result to a timespec before we can return.
279 **/
i40e_ptp_read(struct i40e_pf * pf,struct timespec64 * ts,struct ptp_system_timestamp * sts)280 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts,
281 struct ptp_system_timestamp *sts)
282 {
283 struct i40e_hw *hw = &pf->hw;
284 u32 hi, lo;
285 u64 ns;
286
287 /* The timer latches on the lowest register read. */
288 ptp_read_system_prets(sts);
289 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
290 ptp_read_system_postts(sts);
291 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
292
293 ns = (((u64)hi) << 32) | lo;
294
295 *ts = ns_to_timespec64(ns);
296 }
297
298 /**
299 * i40e_ptp_write - Write the PHC time to the device
300 * @pf: Board private structure
301 * @ts: timespec structure that holds the new time value
302 *
303 * This function writes the PRTTSYN_TIME registers with the user value. Since
304 * we receive a timespec from the stack, we must convert that timespec into
305 * nanoseconds before programming the registers.
306 **/
i40e_ptp_write(struct i40e_pf * pf,const struct timespec64 * ts)307 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
308 {
309 struct i40e_hw *hw = &pf->hw;
310 u64 ns = timespec64_to_ns(ts);
311
312 /* The timer will not update until the high register is written, so
313 * write the low register first.
314 */
315 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
316 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
317 }
318
319 /**
320 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
321 * @hwtstamps: Timestamp structure to update
322 * @timestamp: Timestamp from the hardware
323 *
324 * We need to convert the NIC clock value into a hwtstamp which can be used by
325 * the upper level timestamping functions. Since the timestamp is simply a 64-
326 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
327 **/
i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps * hwtstamps,u64 timestamp)328 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
329 u64 timestamp)
330 {
331 memset(hwtstamps, 0, sizeof(*hwtstamps));
332
333 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
334 }
335
336 /**
337 * i40e_ptp_adjfine - Adjust the PHC frequency
338 * @ptp: The PTP clock structure
339 * @scaled_ppm: Scaled parts per million adjustment from base
340 *
341 * Adjust the frequency of the PHC by the indicated delta from the base
342 * frequency.
343 *
344 * Scaled parts per million is ppm with a 16 bit binary fractional field.
345 **/
i40e_ptp_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)346 static int i40e_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
347 {
348 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
349 struct i40e_hw *hw = &pf->hw;
350 u64 adj, freq, diff;
351 int neg_adj = 0;
352
353 if (scaled_ppm < 0) {
354 neg_adj = 1;
355 scaled_ppm = -scaled_ppm;
356 }
357
358 smp_mb(); /* Force any pending update before accessing. */
359 freq = I40E_PTP_40GB_INCVAL * READ_ONCE(pf->ptp_adj_mult);
360 diff = mul_u64_u64_div_u64(freq, (u64)scaled_ppm,
361 1000000ULL << 16);
362
363 if (neg_adj)
364 adj = I40E_PTP_40GB_INCVAL - diff;
365 else
366 adj = I40E_PTP_40GB_INCVAL + diff;
367
368 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
369 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
370
371 return 0;
372 }
373
374 /**
375 * i40e_ptp_set_1pps_signal_hw - configure 1PPS PTP signal for pins
376 * @pf: the PF private data structure
377 *
378 * Configure 1PPS signal used for PTP pins
379 **/
i40e_ptp_set_1pps_signal_hw(struct i40e_pf * pf)380 static void i40e_ptp_set_1pps_signal_hw(struct i40e_pf *pf)
381 {
382 struct i40e_hw *hw = &pf->hw;
383 struct timespec64 now;
384 u64 ns;
385
386 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0);
387 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT);
388 wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE);
389
390 i40e_ptp_read(pf, &now, NULL);
391 now.tv_sec += I40E_PTP_2_SEC_DELAY;
392 now.tv_nsec = 0;
393 ns = timespec64_to_ns(&now);
394
395 /* I40E_PRTTSYN_TGT_L(1) */
396 wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF);
397 /* I40E_PRTTSYN_TGT_H(1) */
398 wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32);
399 wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND);
400 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT);
401 wr32(hw, I40E_PRTTSYN_AUX_0(1),
402 I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD);
403 }
404
405 /**
406 * i40e_ptp_adjtime - Adjust the PHC time
407 * @ptp: The PTP clock structure
408 * @delta: Offset in nanoseconds to adjust the PHC time by
409 *
410 * Adjust the current clock time by a delta specified in nanoseconds.
411 **/
i40e_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)412 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
413 {
414 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
415 struct i40e_hw *hw = &pf->hw;
416
417 mutex_lock(&pf->tmreg_lock);
418
419 if (delta > -999999900LL && delta < 999999900LL) {
420 int neg_adj = 0;
421 u32 timadj;
422 u64 tohw;
423
424 if (delta < 0) {
425 neg_adj = 1;
426 tohw = -delta;
427 } else {
428 tohw = delta;
429 }
430
431 timadj = tohw & 0x3FFFFFFF;
432 if (neg_adj)
433 timadj |= I40E_ISGN;
434 wr32(hw, I40E_PRTTSYN_ADJ, timadj);
435 } else {
436 struct timespec64 then, now;
437
438 then = ns_to_timespec64(delta);
439 i40e_ptp_read(pf, &now, NULL);
440 now = timespec64_add(now, then);
441 i40e_ptp_write(pf, (const struct timespec64 *)&now);
442 i40e_ptp_set_1pps_signal_hw(pf);
443 }
444
445 mutex_unlock(&pf->tmreg_lock);
446
447 return 0;
448 }
449
450 /**
451 * i40e_ptp_gettimex - Get the time of the PHC
452 * @ptp: The PTP clock structure
453 * @ts: timespec structure to hold the current time value
454 * @sts: structure to hold the system time before and after reading the PHC
455 *
456 * Read the device clock and return the correct value on ns, after converting it
457 * into a timespec struct.
458 **/
i40e_ptp_gettimex(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)459 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
460 struct ptp_system_timestamp *sts)
461 {
462 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
463
464 mutex_lock(&pf->tmreg_lock);
465 i40e_ptp_read(pf, ts, sts);
466 mutex_unlock(&pf->tmreg_lock);
467
468 return 0;
469 }
470
471 /**
472 * i40e_ptp_settime - Set the time of the PHC
473 * @ptp: The PTP clock structure
474 * @ts: timespec64 structure that holds the new time value
475 *
476 * Set the device clock to the user input value. The conversion from timespec
477 * to ns happens in the write function.
478 **/
i40e_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)479 static int i40e_ptp_settime(struct ptp_clock_info *ptp,
480 const struct timespec64 *ts)
481 {
482 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
483
484 mutex_lock(&pf->tmreg_lock);
485 i40e_ptp_write(pf, ts);
486 mutex_unlock(&pf->tmreg_lock);
487
488 return 0;
489 }
490
491 /**
492 * i40e_pps_configure - configure PPS events
493 * @ptp: ptp clock
494 * @rq: clock request
495 * @on: status
496 *
497 * Configure PPS events for external clock source.
498 * Return 0 on success or error on failure.
499 **/
i40e_pps_configure(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)500 static int i40e_pps_configure(struct ptp_clock_info *ptp,
501 struct ptp_clock_request *rq,
502 int on)
503 {
504 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
505
506 if (!!on)
507 i40e_ptp_set_1pps_signal_hw(pf);
508
509 return 0;
510 }
511
512 /**
513 * i40e_pin_state - determine PIN state
514 * @index: PIN index
515 * @func: function assigned to PIN
516 *
517 * Determine PIN state based on PIN index and function assigned.
518 * Return PIN state.
519 **/
i40e_pin_state(int index,int func)520 static enum i40e_ptp_gpio_pin_state i40e_pin_state(int index, int func)
521 {
522 enum i40e_ptp_gpio_pin_state state = off;
523
524 if (index == 0 && func == PTP_PF_EXTTS)
525 state = in_A;
526 if (index == 1 && func == PTP_PF_EXTTS)
527 state = in_B;
528 if (index == 0 && func == PTP_PF_PEROUT)
529 state = out_A;
530 if (index == 1 && func == PTP_PF_PEROUT)
531 state = out_B;
532
533 return state;
534 }
535
536 /**
537 * i40e_ptp_enable_pin - enable PINs.
538 * @pf: private board structure
539 * @chan: channel
540 * @func: PIN function
541 * @on: state
542 *
543 * Enable PTP pins for external clock source.
544 * Return 0 on success or error code on failure.
545 **/
i40e_ptp_enable_pin(struct i40e_pf * pf,unsigned int chan,enum ptp_pin_function func,int on)546 static int i40e_ptp_enable_pin(struct i40e_pf *pf, unsigned int chan,
547 enum ptp_pin_function func, int on)
548 {
549 enum i40e_ptp_gpio_pin_state *pin = NULL;
550 struct i40e_ptp_pins_settings pins;
551 int pin_index;
552
553 /* Use PF0 to set pins. Return success for user space tools */
554 if (pf->hw.pf_id)
555 return 0;
556
557 /* Preserve previous state of pins that we don't touch */
558 pins.sdp3_2 = pf->ptp_pins->sdp3_2;
559 pins.sdp3_3 = pf->ptp_pins->sdp3_3;
560 pins.gpio_4 = pf->ptp_pins->gpio_4;
561
562 /* To turn on the pin - find the corresponding one based on
563 * the given index. To to turn the function off - find
564 * which pin had it assigned. Don't use ptp_find_pin here
565 * because it tries to lock the pincfg_mux which is locked by
566 * ptp_pin_store() that calls here.
567 */
568 if (on) {
569 pin_index = ptp_find_pin(pf->ptp_clock, func, chan);
570 if (pin_index < 0)
571 return -EBUSY;
572
573 switch (pin_index) {
574 case SDP3_2:
575 pin = &pins.sdp3_2;
576 break;
577 case SDP3_3:
578 pin = &pins.sdp3_3;
579 break;
580 case GPIO_4:
581 pin = &pins.gpio_4;
582 break;
583 default:
584 return -EINVAL;
585 }
586
587 *pin = i40e_pin_state(chan, func);
588 } else {
589 pins.sdp3_2 = off;
590 pins.sdp3_3 = off;
591 pins.gpio_4 = off;
592 }
593
594 return i40e_ptp_set_pins(pf, &pins) ? -EINVAL : 0;
595 }
596
597 /**
598 * i40e_ptp_feature_enable - Enable external clock pins
599 * @ptp: The PTP clock structure
600 * @rq: The PTP clock request structure
601 * @on: To turn feature on/off
602 *
603 * Setting on/off PTP PPS feature for pin.
604 **/
i40e_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)605 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
606 struct ptp_clock_request *rq,
607 int on)
608 {
609 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
610
611 enum ptp_pin_function func;
612 unsigned int chan;
613
614 /* TODO: Implement flags handling for EXTTS and PEROUT */
615 switch (rq->type) {
616 case PTP_CLK_REQ_EXTTS:
617 func = PTP_PF_EXTTS;
618 chan = rq->extts.index;
619 break;
620 case PTP_CLK_REQ_PEROUT:
621 func = PTP_PF_PEROUT;
622 chan = rq->perout.index;
623 break;
624 case PTP_CLK_REQ_PPS:
625 return i40e_pps_configure(ptp, rq, on);
626 default:
627 return -EOPNOTSUPP;
628 }
629
630 return i40e_ptp_enable_pin(pf, chan, func, on);
631 }
632
633 /**
634 * i40e_ptp_get_rx_events - Read I40E_PRTTSYN_STAT_1 and latch events
635 * @pf: the PF data structure
636 *
637 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers
638 * for noticed latch events. This allows the driver to keep track of the first
639 * time a latch event was noticed which will be used to help clear out Rx
640 * timestamps for packets that got dropped or lost.
641 *
642 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is
643 * expected to be called only while under the ptp_rx_lock.
644 **/
i40e_ptp_get_rx_events(struct i40e_pf * pf)645 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
646 {
647 struct i40e_hw *hw = &pf->hw;
648 u32 prttsyn_stat, new_latch_events;
649 int i;
650
651 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
652 new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
653
654 /* Update the jiffies time for any newly latched timestamp. This
655 * ensures that we store the time that we first discovered a timestamp
656 * was latched by the hardware. The service task will later determine
657 * if we should free the latch and drop that timestamp should too much
658 * time pass. This flow ensures that we only update jiffies for new
659 * events latched since the last time we checked, and not all events
660 * currently latched, so that the service task accounting remains
661 * accurate.
662 */
663 for (i = 0; i < 4; i++) {
664 if (new_latch_events & BIT(i))
665 pf->latch_events[i] = jiffies;
666 }
667
668 /* Finally, we store the current status of the Rx timestamp latches */
669 pf->latch_event_flags = prttsyn_stat;
670
671 return prttsyn_stat;
672 }
673
674 /**
675 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
676 * @pf: The PF private data structure
677 *
678 * This watchdog task is scheduled to detect error case where hardware has
679 * dropped an Rx packet that was timestamped when the ring is full. The
680 * particular error is rare but leaves the device in a state unable to timestamp
681 * any future packets.
682 **/
i40e_ptp_rx_hang(struct i40e_pf * pf)683 void i40e_ptp_rx_hang(struct i40e_pf *pf)
684 {
685 struct i40e_hw *hw = &pf->hw;
686 unsigned int i, cleared = 0;
687
688 /* Since we cannot turn off the Rx timestamp logic if the device is
689 * configured for Tx timestamping, we check if Rx timestamping is
690 * configured. We don't want to spuriously warn about Rx timestamp
691 * hangs if we don't care about the timestamps.
692 */
693 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
694 return;
695
696 spin_lock_bh(&pf->ptp_rx_lock);
697
698 /* Update current latch times for Rx events */
699 i40e_ptp_get_rx_events(pf);
700
701 /* Check all the currently latched Rx events and see whether they have
702 * been latched for over a second. It is assumed that any timestamp
703 * should have been cleared within this time, or else it was captured
704 * for a dropped frame that the driver never received. Thus, we will
705 * clear any timestamp that has been latched for over 1 second.
706 */
707 for (i = 0; i < 4; i++) {
708 if ((pf->latch_event_flags & BIT(i)) &&
709 time_is_before_jiffies(pf->latch_events[i] + HZ)) {
710 rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
711 pf->latch_event_flags &= ~BIT(i);
712 cleared++;
713 }
714 }
715
716 spin_unlock_bh(&pf->ptp_rx_lock);
717
718 /* Log a warning if more than 2 timestamps got dropped in the same
719 * check. We don't want to warn about all drops because it can occur
720 * in normal scenarios such as PTP frames on multicast addresses we
721 * aren't listening to. However, administrator should know if this is
722 * the reason packets aren't receiving timestamps.
723 */
724 if (cleared > 2)
725 dev_dbg(&pf->pdev->dev,
726 "Dropped %d missed RXTIME timestamp events\n",
727 cleared);
728
729 /* Finally, update the rx_hwtstamp_cleared counter */
730 pf->rx_hwtstamp_cleared += cleared;
731 }
732
733 /**
734 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung
735 * @pf: The PF private data structure
736 *
737 * This watchdog task is run periodically to make sure that we clear the Tx
738 * timestamp logic if we don't obtain a timestamp in a reasonable amount of
739 * time. It is unexpected in the normal case but if it occurs it results in
740 * permanently preventing timestamps of future packets.
741 **/
i40e_ptp_tx_hang(struct i40e_pf * pf)742 void i40e_ptp_tx_hang(struct i40e_pf *pf)
743 {
744 struct sk_buff *skb;
745
746 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
747 return;
748
749 /* Nothing to do if we're not already waiting for a timestamp */
750 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
751 return;
752
753 /* We already have a handler routine which is run when we are notified
754 * of a Tx timestamp in the hardware. If we don't get an interrupt
755 * within a second it is reasonable to assume that we never will.
756 */
757 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
758 skb = pf->ptp_tx_skb;
759 pf->ptp_tx_skb = NULL;
760 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
761
762 /* Free the skb after we clear the bitlock */
763 dev_kfree_skb_any(skb);
764 pf->tx_hwtstamp_timeouts++;
765 }
766 }
767
768 /**
769 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
770 * @pf: Board private structure
771 *
772 * Read the value of the Tx timestamp from the registers, convert it into a
773 * value consumable by the stack, and store that result into the shhwtstamps
774 * struct before returning it up the stack.
775 **/
i40e_ptp_tx_hwtstamp(struct i40e_pf * pf)776 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
777 {
778 struct skb_shared_hwtstamps shhwtstamps;
779 struct sk_buff *skb = pf->ptp_tx_skb;
780 struct i40e_hw *hw = &pf->hw;
781 u32 hi, lo;
782 u64 ns;
783
784 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
785 return;
786
787 /* don't attempt to timestamp if we don't have an skb */
788 if (!pf->ptp_tx_skb)
789 return;
790
791 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
792 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
793
794 ns = (((u64)hi) << 32) | lo;
795 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
796
797 /* Clear the bit lock as soon as possible after reading the register,
798 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise
799 * applications might wake up and attempt to request another transmit
800 * timestamp prior to the bit lock being cleared.
801 */
802 pf->ptp_tx_skb = NULL;
803 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
804
805 /* Notify the stack and free the skb after we've unlocked */
806 skb_tstamp_tx(skb, &shhwtstamps);
807 dev_kfree_skb_any(skb);
808 }
809
810 /**
811 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
812 * @pf: Board private structure
813 * @skb: Particular skb to send timestamp with
814 * @index: Index into the receive timestamp registers for the timestamp
815 *
816 * The XL710 receives a notification in the receive descriptor with an offset
817 * into the set of RXTIME registers where the timestamp is for that skb. This
818 * function goes and fetches the receive timestamp from that offset, if a valid
819 * one exists. The RXTIME registers are in ns, so we must convert the result
820 * first.
821 **/
i40e_ptp_rx_hwtstamp(struct i40e_pf * pf,struct sk_buff * skb,u8 index)822 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
823 {
824 u32 prttsyn_stat, hi, lo;
825 struct i40e_hw *hw;
826 u64 ns;
827
828 /* Since we cannot turn off the Rx timestamp logic if the device is
829 * doing Tx timestamping, check if Rx timestamping is configured.
830 */
831 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
832 return;
833
834 hw = &pf->hw;
835
836 spin_lock_bh(&pf->ptp_rx_lock);
837
838 /* Get current Rx events and update latch times */
839 prttsyn_stat = i40e_ptp_get_rx_events(pf);
840
841 /* TODO: Should we warn about missing Rx timestamp event? */
842 if (!(prttsyn_stat & BIT(index))) {
843 spin_unlock_bh(&pf->ptp_rx_lock);
844 return;
845 }
846
847 /* Clear the latched event since we're about to read its register */
848 pf->latch_event_flags &= ~BIT(index);
849
850 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
851 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
852
853 spin_unlock_bh(&pf->ptp_rx_lock);
854
855 ns = (((u64)hi) << 32) | lo;
856
857 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
858 }
859
860 /**
861 * i40e_ptp_set_increment - Utility function to update clock increment rate
862 * @pf: Board private structure
863 *
864 * During a link change, the DMA frequency that drives the 1588 logic will
865 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
866 * we must update the increment value per clock tick.
867 **/
i40e_ptp_set_increment(struct i40e_pf * pf)868 void i40e_ptp_set_increment(struct i40e_pf *pf)
869 {
870 struct i40e_link_status *hw_link_info;
871 struct i40e_hw *hw = &pf->hw;
872 u64 incval;
873 u32 mult;
874
875 hw_link_info = &hw->phy.link_info;
876
877 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
878
879 switch (hw_link_info->link_speed) {
880 case I40E_LINK_SPEED_10GB:
881 mult = I40E_PTP_10GB_INCVAL_MULT;
882 break;
883 case I40E_LINK_SPEED_5GB:
884 mult = I40E_PTP_5GB_INCVAL_MULT;
885 break;
886 case I40E_LINK_SPEED_1GB:
887 mult = I40E_PTP_1GB_INCVAL_MULT;
888 break;
889 case I40E_LINK_SPEED_100MB:
890 {
891 static int warn_once;
892
893 if (!warn_once) {
894 dev_warn(&pf->pdev->dev,
895 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
896 warn_once++;
897 }
898 mult = 0;
899 break;
900 }
901 case I40E_LINK_SPEED_40GB:
902 default:
903 mult = 1;
904 break;
905 }
906
907 /* The increment value is calculated by taking the base 40GbE incvalue
908 * and multiplying it by a factor based on the link speed.
909 */
910 incval = I40E_PTP_40GB_INCVAL * mult;
911
912 /* Write the new increment value into the increment register. The
913 * hardware will not update the clock until both registers have been
914 * written.
915 */
916 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
917 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
918
919 /* Update the base adjustement value. */
920 WRITE_ONCE(pf->ptp_adj_mult, mult);
921 smp_mb(); /* Force the above update. */
922 }
923
924 /**
925 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
926 * @pf: Board private structure
927 * @ifr: ioctl data
928 *
929 * Obtain the current hardware timestamping settigs as requested. To do this,
930 * keep a shadow copy of the timestamp settings rather than attempting to
931 * deconstruct it from the registers.
932 **/
i40e_ptp_get_ts_config(struct i40e_pf * pf,struct ifreq * ifr)933 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
934 {
935 struct hwtstamp_config *config = &pf->tstamp_config;
936
937 if (!(pf->flags & I40E_FLAG_PTP))
938 return -EOPNOTSUPP;
939
940 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
941 -EFAULT : 0;
942 }
943
944 /**
945 * i40e_ptp_free_pins - free memory used by PTP pins
946 * @pf: Board private structure
947 *
948 * Release memory allocated for PTP pins.
949 **/
i40e_ptp_free_pins(struct i40e_pf * pf)950 static void i40e_ptp_free_pins(struct i40e_pf *pf)
951 {
952 if (i40e_is_ptp_pin_dev(&pf->hw)) {
953 kfree(pf->ptp_pins);
954 kfree(pf->ptp_caps.pin_config);
955 pf->ptp_pins = NULL;
956 }
957 }
958
959 /**
960 * i40e_ptp_set_pin_hw - Set HW GPIO pin
961 * @hw: pointer to the hardware structure
962 * @pin: pin index
963 * @state: pin state
964 *
965 * Set status of GPIO pin for external clock handling.
966 **/
i40e_ptp_set_pin_hw(struct i40e_hw * hw,unsigned int pin,enum i40e_ptp_gpio_pin_state state)967 static void i40e_ptp_set_pin_hw(struct i40e_hw *hw,
968 unsigned int pin,
969 enum i40e_ptp_gpio_pin_state state)
970 {
971 switch (state) {
972 case off:
973 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 0);
974 break;
975 case in_A:
976 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
977 I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0);
978 break;
979 case in_B:
980 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
981 I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0);
982 break;
983 case out_A:
984 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
985 I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1);
986 break;
987 case out_B:
988 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
989 I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1);
990 break;
991 default:
992 break;
993 }
994 }
995
996 /**
997 * i40e_ptp_set_led_hw - Set HW GPIO led
998 * @hw: pointer to the hardware structure
999 * @led: led index
1000 * @state: led state
1001 *
1002 * Set status of GPIO led for external clock handling.
1003 **/
i40e_ptp_set_led_hw(struct i40e_hw * hw,unsigned int led,enum i40e_ptp_led_pin_state state)1004 static void i40e_ptp_set_led_hw(struct i40e_hw *hw,
1005 unsigned int led,
1006 enum i40e_ptp_led_pin_state state)
1007 {
1008 switch (state) {
1009 case low:
1010 wr32(hw, I40E_GLGEN_GPIO_SET,
1011 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | led);
1012 break;
1013 case high:
1014 wr32(hw, I40E_GLGEN_GPIO_SET,
1015 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA |
1016 I40E_GLGEN_GPIO_SET_SDP_DATA_HI | led);
1017 break;
1018 default:
1019 break;
1020 }
1021 }
1022
1023 /**
1024 * i40e_ptp_init_leds_hw - init LEDs
1025 * @hw: pointer to a hardware structure
1026 *
1027 * Set initial state of LEDs
1028 **/
i40e_ptp_init_leds_hw(struct i40e_hw * hw)1029 static void i40e_ptp_init_leds_hw(struct i40e_hw *hw)
1030 {
1031 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_0),
1032 I40E_GLGEN_GPIO_CTL_LED_INIT);
1033 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_1),
1034 I40E_GLGEN_GPIO_CTL_LED_INIT);
1035 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_0),
1036 I40E_GLGEN_GPIO_CTL_LED_INIT);
1037 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_1),
1038 I40E_GLGEN_GPIO_CTL_LED_INIT);
1039 }
1040
1041 /**
1042 * i40e_ptp_set_pins_hw - Set HW GPIO pins
1043 * @pf: Board private structure
1044 *
1045 * This function sets GPIO pins for PTP
1046 **/
i40e_ptp_set_pins_hw(struct i40e_pf * pf)1047 static void i40e_ptp_set_pins_hw(struct i40e_pf *pf)
1048 {
1049 const struct i40e_ptp_pins_settings *pins = pf->ptp_pins;
1050 struct i40e_hw *hw = &pf->hw;
1051
1052 /* pin must be disabled before it may be used */
1053 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off);
1054 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off);
1055 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off);
1056
1057 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, pins->sdp3_2);
1058 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, pins->sdp3_3);
1059 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, pins->gpio_4);
1060
1061 i40e_ptp_set_led_hw(hw, I40E_LED2_0, pins->led2_0);
1062 i40e_ptp_set_led_hw(hw, I40E_LED2_1, pins->led2_1);
1063 i40e_ptp_set_led_hw(hw, I40E_LED3_0, pins->led3_0);
1064 i40e_ptp_set_led_hw(hw, I40E_LED3_1, pins->led3_1);
1065
1066 dev_info(&pf->pdev->dev,
1067 "PTP configuration set to: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n",
1068 i40e_ptp_gpio_pin_state2str[pins->sdp3_2],
1069 i40e_ptp_gpio_pin_state2str[pins->sdp3_3],
1070 i40e_ptp_gpio_pin_state2str[pins->gpio_4]);
1071 }
1072
1073 /**
1074 * i40e_ptp_set_pins - set PTP pins in HW
1075 * @pf: Board private structure
1076 * @pins: PTP pins to be applied
1077 *
1078 * Validate and set PTP pins in HW for specific PF.
1079 * Return 0 on success or negative value on error.
1080 **/
i40e_ptp_set_pins(struct i40e_pf * pf,struct i40e_ptp_pins_settings * pins)1081 static int i40e_ptp_set_pins(struct i40e_pf *pf,
1082 struct i40e_ptp_pins_settings *pins)
1083 {
1084 enum i40e_can_set_pins_t pin_caps = i40e_can_set_pins(pf);
1085 int i = 0;
1086
1087 if (pin_caps == CANT_DO_PINS)
1088 return -EOPNOTSUPP;
1089 else if (pin_caps == CAN_DO_PINS)
1090 return 0;
1091
1092 if (pins->sdp3_2 == invalid)
1093 pins->sdp3_2 = pf->ptp_pins->sdp3_2;
1094 if (pins->sdp3_3 == invalid)
1095 pins->sdp3_3 = pf->ptp_pins->sdp3_3;
1096 if (pins->gpio_4 == invalid)
1097 pins->gpio_4 = pf->ptp_pins->gpio_4;
1098 while (i40e_ptp_pin_led_allowed_states[i].sdp3_2 != end) {
1099 if (pins->sdp3_2 == i40e_ptp_pin_led_allowed_states[i].sdp3_2 &&
1100 pins->sdp3_3 == i40e_ptp_pin_led_allowed_states[i].sdp3_3 &&
1101 pins->gpio_4 == i40e_ptp_pin_led_allowed_states[i].gpio_4) {
1102 pins->led2_0 =
1103 i40e_ptp_pin_led_allowed_states[i].led2_0;
1104 pins->led2_1 =
1105 i40e_ptp_pin_led_allowed_states[i].led2_1;
1106 pins->led3_0 =
1107 i40e_ptp_pin_led_allowed_states[i].led3_0;
1108 pins->led3_1 =
1109 i40e_ptp_pin_led_allowed_states[i].led3_1;
1110 break;
1111 }
1112 i++;
1113 }
1114 if (i40e_ptp_pin_led_allowed_states[i].sdp3_2 == end) {
1115 dev_warn(&pf->pdev->dev,
1116 "Unsupported PTP pin configuration: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n",
1117 i40e_ptp_gpio_pin_state2str[pins->sdp3_2],
1118 i40e_ptp_gpio_pin_state2str[pins->sdp3_3],
1119 i40e_ptp_gpio_pin_state2str[pins->gpio_4]);
1120
1121 return -EPERM;
1122 }
1123 memcpy(pf->ptp_pins, pins, sizeof(*pins));
1124 i40e_ptp_set_pins_hw(pf);
1125 i40_ptp_reset_timing_events(pf);
1126
1127 return 0;
1128 }
1129
1130 /**
1131 * i40e_ptp_alloc_pins - allocate PTP pins structure
1132 * @pf: Board private structure
1133 *
1134 * allocate PTP pins structure
1135 **/
i40e_ptp_alloc_pins(struct i40e_pf * pf)1136 int i40e_ptp_alloc_pins(struct i40e_pf *pf)
1137 {
1138 if (!i40e_is_ptp_pin_dev(&pf->hw))
1139 return 0;
1140
1141 pf->ptp_pins =
1142 kzalloc(sizeof(struct i40e_ptp_pins_settings), GFP_KERNEL);
1143
1144 if (!pf->ptp_pins) {
1145 dev_warn(&pf->pdev->dev, "Cannot allocate memory for PTP pins structure.\n");
1146 return -I40E_ERR_NO_MEMORY;
1147 }
1148
1149 pf->ptp_pins->sdp3_2 = off;
1150 pf->ptp_pins->sdp3_3 = off;
1151 pf->ptp_pins->gpio_4 = off;
1152 pf->ptp_pins->led2_0 = high;
1153 pf->ptp_pins->led2_1 = high;
1154 pf->ptp_pins->led3_0 = high;
1155 pf->ptp_pins->led3_1 = high;
1156
1157 /* Use PF0 to set pins in HW. Return success for user space tools */
1158 if (pf->hw.pf_id)
1159 return 0;
1160
1161 i40e_ptp_init_leds_hw(&pf->hw);
1162 i40e_ptp_set_pins_hw(pf);
1163
1164 return 0;
1165 }
1166
1167 /**
1168 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
1169 * @pf: Board private structure
1170 * @config: hwtstamp settings requested or saved
1171 *
1172 * Control hardware registers to enter the specific mode requested by the
1173 * user. Also used during reset path to ensure that timestamp settings are
1174 * maintained.
1175 *
1176 * Note: modifies config in place, and may update the requested mode to be
1177 * more broad if the specific filter is not directly supported.
1178 **/
i40e_ptp_set_timestamp_mode(struct i40e_pf * pf,struct hwtstamp_config * config)1179 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
1180 struct hwtstamp_config *config)
1181 {
1182 struct i40e_hw *hw = &pf->hw;
1183 u32 tsyntype, regval;
1184
1185 /* Selects external trigger to cause event */
1186 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));
1187 /* Bit 17:16 is EVNTLVL, 01B rising edge */
1188 regval &= 0;
1189 regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT);
1190 /* regval: 0001 0000 0000 0000 0000 */
1191 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);
1192
1193 /* Enabel interrupts */
1194 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1195 regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT;
1196 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1197
1198 INIT_WORK(&pf->ptp_extts0_work, i40e_ptp_extts0_work);
1199
1200 switch (config->tx_type) {
1201 case HWTSTAMP_TX_OFF:
1202 pf->ptp_tx = false;
1203 break;
1204 case HWTSTAMP_TX_ON:
1205 pf->ptp_tx = true;
1206 break;
1207 default:
1208 return -ERANGE;
1209 }
1210
1211 switch (config->rx_filter) {
1212 case HWTSTAMP_FILTER_NONE:
1213 pf->ptp_rx = false;
1214 /* We set the type to V1, but do not enable UDP packet
1215 * recognition. In this way, we should be as close to
1216 * disabling PTP Rx timestamps as possible since V1 packets
1217 * are always UDP, since L2 packets are a V2 feature.
1218 */
1219 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
1220 break;
1221 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1222 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1223 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1224 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
1225 return -ERANGE;
1226 pf->ptp_rx = true;
1227 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
1228 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
1229 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
1230 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1231 break;
1232 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1233 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1234 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1235 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1236 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1237 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1238 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
1239 return -ERANGE;
1240 fallthrough;
1241 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1242 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1243 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1244 pf->ptp_rx = true;
1245 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
1246 I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
1247 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
1248 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
1249 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1250 } else {
1251 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1252 }
1253 break;
1254 case HWTSTAMP_FILTER_NTP_ALL:
1255 case HWTSTAMP_FILTER_ALL:
1256 default:
1257 return -ERANGE;
1258 }
1259
1260 /* Clear out all 1588-related registers to clear and unlatch them. */
1261 spin_lock_bh(&pf->ptp_rx_lock);
1262 rd32(hw, I40E_PRTTSYN_STAT_0);
1263 rd32(hw, I40E_PRTTSYN_TXTIME_H);
1264 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
1265 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
1266 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
1267 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
1268 pf->latch_event_flags = 0;
1269 spin_unlock_bh(&pf->ptp_rx_lock);
1270
1271 /* Enable/disable the Tx timestamp interrupt based on user input. */
1272 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1273 if (pf->ptp_tx)
1274 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
1275 else
1276 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
1277 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1278
1279 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
1280 if (pf->ptp_tx)
1281 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
1282 else
1283 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
1284 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
1285
1286 /* Although there is no simple on/off switch for Rx, we "disable" Rx
1287 * timestamps by setting to V1 only mode and clear the UDP
1288 * recognition. This ought to disable all PTP Rx timestamps as V1
1289 * packets are always over UDP. Note that software is configured to
1290 * ignore Rx timestamps via the pf->ptp_rx flag.
1291 */
1292 regval = rd32(hw, I40E_PRTTSYN_CTL1);
1293 /* clear everything but the enable bit */
1294 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
1295 /* now enable bits for desired Rx timestamps */
1296 regval |= tsyntype;
1297 wr32(hw, I40E_PRTTSYN_CTL1, regval);
1298
1299 return 0;
1300 }
1301
1302 /**
1303 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
1304 * @pf: Board private structure
1305 * @ifr: ioctl data
1306 *
1307 * Respond to the user filter requests and make the appropriate hardware
1308 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
1309 * logic, so keep track in software of whether to indicate these timestamps
1310 * or not.
1311 *
1312 * It is permissible to "upgrade" the user request to a broader filter, as long
1313 * as the user receives the timestamps they care about and the user is notified
1314 * the filter has been broadened.
1315 **/
i40e_ptp_set_ts_config(struct i40e_pf * pf,struct ifreq * ifr)1316 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
1317 {
1318 struct hwtstamp_config config;
1319 int err;
1320
1321 if (!(pf->flags & I40E_FLAG_PTP))
1322 return -EOPNOTSUPP;
1323
1324 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1325 return -EFAULT;
1326
1327 err = i40e_ptp_set_timestamp_mode(pf, &config);
1328 if (err)
1329 return err;
1330
1331 /* save these settings for future reference */
1332 pf->tstamp_config = config;
1333
1334 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1335 -EFAULT : 0;
1336 }
1337
1338 /**
1339 * i40e_init_pin_config - initialize pins.
1340 * @pf: private board structure
1341 *
1342 * Initialize pins for external clock source.
1343 * Return 0 on success or error code on failure.
1344 **/
i40e_init_pin_config(struct i40e_pf * pf)1345 static int i40e_init_pin_config(struct i40e_pf *pf)
1346 {
1347 int i;
1348
1349 pf->ptp_caps.n_pins = 3;
1350 pf->ptp_caps.n_ext_ts = 2;
1351 pf->ptp_caps.pps = 1;
1352 pf->ptp_caps.n_per_out = 2;
1353
1354 pf->ptp_caps.pin_config = kcalloc(pf->ptp_caps.n_pins,
1355 sizeof(*pf->ptp_caps.pin_config),
1356 GFP_KERNEL);
1357 if (!pf->ptp_caps.pin_config)
1358 return -ENOMEM;
1359
1360 for (i = 0; i < pf->ptp_caps.n_pins; i++) {
1361 snprintf(pf->ptp_caps.pin_config[i].name,
1362 sizeof(pf->ptp_caps.pin_config[i].name),
1363 "%s", sdp_desc[i].name);
1364 pf->ptp_caps.pin_config[i].index = sdp_desc[i].index;
1365 pf->ptp_caps.pin_config[i].func = PTP_PF_NONE;
1366 pf->ptp_caps.pin_config[i].chan = sdp_desc[i].chan;
1367 }
1368
1369 pf->ptp_caps.verify = i40e_ptp_verify;
1370 pf->ptp_caps.enable = i40e_ptp_feature_enable;
1371
1372 pf->ptp_caps.pps = 1;
1373
1374 return 0;
1375 }
1376
1377 /**
1378 * i40e_ptp_create_clock - Create PTP clock device for userspace
1379 * @pf: Board private structure
1380 *
1381 * This function creates a new PTP clock device. It only creates one if we
1382 * don't already have one, so it is safe to call. Will return error if it
1383 * can't create one, but success if we already have a device. Should be used
1384 * by i40e_ptp_init to create clock initially, and prevent global resets from
1385 * creating new clock devices.
1386 **/
i40e_ptp_create_clock(struct i40e_pf * pf)1387 static long i40e_ptp_create_clock(struct i40e_pf *pf)
1388 {
1389 /* no need to create a clock device if we already have one */
1390 if (!IS_ERR_OR_NULL(pf->ptp_clock))
1391 return 0;
1392
1393 strscpy(pf->ptp_caps.name, i40e_driver_name,
1394 sizeof(pf->ptp_caps.name) - 1);
1395 pf->ptp_caps.owner = THIS_MODULE;
1396 pf->ptp_caps.max_adj = 999999999;
1397 pf->ptp_caps.adjfine = i40e_ptp_adjfine;
1398 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
1399 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex;
1400 pf->ptp_caps.settime64 = i40e_ptp_settime;
1401 if (i40e_is_ptp_pin_dev(&pf->hw)) {
1402 int err = i40e_init_pin_config(pf);
1403
1404 if (err)
1405 return err;
1406 }
1407
1408 /* Attempt to register the clock before enabling the hardware. */
1409 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
1410 if (IS_ERR(pf->ptp_clock))
1411 return PTR_ERR(pf->ptp_clock);
1412
1413 /* clear the hwtstamp settings here during clock create, instead of
1414 * during regular init, so that we can maintain settings across a
1415 * reset or suspend.
1416 */
1417 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1418 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1419
1420 /* Set the previous "reset" time to the current Kernel clock time */
1421 ktime_get_real_ts64(&pf->ptp_prev_hw_time);
1422 pf->ptp_reset_start = ktime_get();
1423
1424 return 0;
1425 }
1426
1427 /**
1428 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time
1429 * @pf: Board private structure
1430 *
1431 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should
1432 * be called at the end of preparing to reset, just before hardware reset
1433 * occurs, in order to preserve the PTP time as close as possible across
1434 * resets.
1435 */
i40e_ptp_save_hw_time(struct i40e_pf * pf)1436 void i40e_ptp_save_hw_time(struct i40e_pf *pf)
1437 {
1438 /* don't try to access the PTP clock if it's not enabled */
1439 if (!(pf->flags & I40E_FLAG_PTP))
1440 return;
1441
1442 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL);
1443 /* Get a monotonic starting time for this reset */
1444 pf->ptp_reset_start = ktime_get();
1445 }
1446
1447 /**
1448 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs
1449 * @pf: Board private structure
1450 *
1451 * Restore the PTP hardware clock registers. We previously cached the PTP
1452 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible,
1453 * update this value based on the time delta since the time was saved, using
1454 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference.
1455 *
1456 * This ensures that the hardware clock is restored to nearly what it should
1457 * have been if a reset had not occurred.
1458 */
i40e_ptp_restore_hw_time(struct i40e_pf * pf)1459 void i40e_ptp_restore_hw_time(struct i40e_pf *pf)
1460 {
1461 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start);
1462
1463 /* Update the previous HW time with the ktime delta */
1464 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta));
1465
1466 /* Restore the hardware clock registers */
1467 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time);
1468 }
1469
1470 /**
1471 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
1472 * @pf: Board private structure
1473 *
1474 * This function sets device up for 1588 support. The first time it is run, it
1475 * will create a PHC clock device. It does not create a clock device if one
1476 * already exists. It also reconfigures the device after a reset.
1477 *
1478 * The first time a clock is created, i40e_ptp_create_clock will set
1479 * pf->ptp_prev_hw_time to the current system time. During resets, it is
1480 * expected that this timespec will be set to the last known PTP clock time,
1481 * in order to preserve the clock time as close as possible across a reset.
1482 **/
i40e_ptp_init(struct i40e_pf * pf)1483 void i40e_ptp_init(struct i40e_pf *pf)
1484 {
1485 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
1486 struct i40e_hw *hw = &pf->hw;
1487 u32 pf_id;
1488 long err;
1489
1490 /* Only one PF is assigned to control 1588 logic per port. Do not
1491 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
1492 */
1493 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
1494 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
1495 if (hw->pf_id != pf_id) {
1496 pf->flags &= ~I40E_FLAG_PTP;
1497 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
1498 __func__,
1499 netdev->name);
1500 return;
1501 }
1502
1503 mutex_init(&pf->tmreg_lock);
1504 spin_lock_init(&pf->ptp_rx_lock);
1505
1506 /* ensure we have a clock device */
1507 err = i40e_ptp_create_clock(pf);
1508 if (err) {
1509 pf->ptp_clock = NULL;
1510 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
1511 __func__);
1512 } else if (pf->ptp_clock) {
1513 u32 regval;
1514
1515 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
1516 dev_info(&pf->pdev->dev, "PHC enabled\n");
1517 pf->flags |= I40E_FLAG_PTP;
1518
1519 /* Ensure the clocks are running. */
1520 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1521 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
1522 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1523 regval = rd32(hw, I40E_PRTTSYN_CTL1);
1524 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
1525 wr32(hw, I40E_PRTTSYN_CTL1, regval);
1526
1527 /* Set the increment value per clock tick. */
1528 i40e_ptp_set_increment(pf);
1529
1530 /* reset timestamping mode */
1531 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
1532
1533 /* Restore the clock time based on last known value */
1534 i40e_ptp_restore_hw_time(pf);
1535 }
1536
1537 i40e_ptp_set_1pps_signal_hw(pf);
1538 }
1539
1540 /**
1541 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
1542 * @pf: Board private structure
1543 *
1544 * This function handles the cleanup work required from the initialization by
1545 * clearing out the important information and unregistering the PHC.
1546 **/
i40e_ptp_stop(struct i40e_pf * pf)1547 void i40e_ptp_stop(struct i40e_pf *pf)
1548 {
1549 struct i40e_hw *hw = &pf->hw;
1550 u32 regval;
1551
1552 pf->flags &= ~I40E_FLAG_PTP;
1553 pf->ptp_tx = false;
1554 pf->ptp_rx = false;
1555
1556 if (pf->ptp_tx_skb) {
1557 struct sk_buff *skb = pf->ptp_tx_skb;
1558
1559 pf->ptp_tx_skb = NULL;
1560 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
1561 dev_kfree_skb_any(skb);
1562 }
1563
1564 if (pf->ptp_clock) {
1565 ptp_clock_unregister(pf->ptp_clock);
1566 pf->ptp_clock = NULL;
1567 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
1568 pf->vsi[pf->lan_vsi]->netdev->name);
1569 }
1570
1571 if (i40e_is_ptp_pin_dev(&pf->hw)) {
1572 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off);
1573 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off);
1574 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off);
1575 }
1576
1577 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));
1578 regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK;
1579 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);
1580
1581 /* Disable interrupts */
1582 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1583 regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK;
1584 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1585
1586 i40e_ptp_free_pins(pf);
1587 }
1588