1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #include "i40e.h"
5 #include <linux/ptp_classify.h>
6 #include <linux/posix-clock.h>
7 
8 /* The XL710 timesync is very much like Intel's 82599 design when it comes to
9  * the fundamental clock design. However, the clock operations are much simpler
10  * in the XL710 because the device supports a full 64 bits of nanoseconds.
11  * Because the field is so wide, we can forgo the cycle counter and just
12  * operate with the nanosecond field directly without fear of overflow.
13  *
14  * Much like the 82599, the update period is dependent upon the link speed:
15  * At 40Gb, 25Gb, or no link, the period is 1.6ns.
16  * At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns)
17  * At 1Gb link, the period is multiplied by 20. (32ns)
18  * 1588 functionality is not supported at 100Mbps.
19  */
20 #define I40E_PTP_40GB_INCVAL		0x0199999999ULL
21 #define I40E_PTP_10GB_INCVAL_MULT	2
22 #define I40E_PTP_5GB_INCVAL_MULT	2
23 #define I40E_PTP_1GB_INCVAL_MULT	20
24 #define I40E_ISGN			0x80000000
25 
26 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1  BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
27 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2  (2 << \
28 					I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
29 #define I40E_SUBDEV_ID_25G_PTP_PIN	0xB
30 #define to_dev(obj) container_of(obj, struct device, kobj)
31 
32 enum i40e_ptp_pin {
33 	SDP3_2 = 0,
34 	SDP3_3,
35 	GPIO_4
36 };
37 
38 enum i40e_can_set_pins_t {
39 	CANT_DO_PINS = -1,
40 	CAN_SET_PINS,
41 	CAN_DO_PINS
42 };
43 
44 static struct ptp_pin_desc sdp_desc[] = {
45 	/* name     idx      func      chan */
46 	{"SDP3_2", SDP3_2, PTP_PF_NONE, 0},
47 	{"SDP3_3", SDP3_3, PTP_PF_NONE, 1},
48 	{"GPIO_4", GPIO_4, PTP_PF_NONE, 1},
49 };
50 
51 enum i40e_ptp_gpio_pin_state {
52 	end = -2,
53 	invalid,
54 	off,
55 	in_A,
56 	in_B,
57 	out_A,
58 	out_B,
59 };
60 
61 static const char * const i40e_ptp_gpio_pin_state2str[] = {
62 	"off", "in_A", "in_B", "out_A", "out_B"
63 };
64 
65 enum i40e_ptp_led_pin_state {
66 	led_end = -2,
67 	low = 0,
68 	high,
69 };
70 
71 struct i40e_ptp_pins_settings {
72 	enum i40e_ptp_gpio_pin_state sdp3_2;
73 	enum i40e_ptp_gpio_pin_state sdp3_3;
74 	enum i40e_ptp_gpio_pin_state gpio_4;
75 	enum i40e_ptp_led_pin_state led2_0;
76 	enum i40e_ptp_led_pin_state led2_1;
77 	enum i40e_ptp_led_pin_state led3_0;
78 	enum i40e_ptp_led_pin_state led3_1;
79 };
80 
81 static const struct i40e_ptp_pins_settings
82 	i40e_ptp_pin_led_allowed_states[] = {
83 	{off,	off,	off,		high,	high,	high,	high},
84 	{off,	in_A,	off,		high,	high,	high,	low},
85 	{off,	out_A,	off,		high,	low,	high,	high},
86 	{off,	in_B,	off,		high,	high,	high,	low},
87 	{off,	out_B,	off,		high,	low,	high,	high},
88 	{in_A,	off,	off,		high,	high,	high,	low},
89 	{in_A,	in_B,	off,		high,	high,	high,	low},
90 	{in_A,	out_B,	off,		high,	low,	high,	high},
91 	{out_A,	off,	off,		high,	low,	high,	high},
92 	{out_A,	in_B,	off,		high,	low,	high,	high},
93 	{in_B,	off,	off,		high,	high,	high,	low},
94 	{in_B,	in_A,	off,		high,	high,	high,	low},
95 	{in_B,	out_A,	off,		high,	low,	high,	high},
96 	{out_B,	off,	off,		high,	low,	high,	high},
97 	{out_B,	in_A,	off,		high,	low,	high,	high},
98 	{off,	off,	in_A,		high,	high,	low,	high},
99 	{off,	out_A,	in_A,		high,	low,	low,	high},
100 	{off,	in_B,	in_A,		high,	high,	low,	low},
101 	{off,	out_B,	in_A,		high,	low,	low,	high},
102 	{out_A,	off,	in_A,		high,	low,	low,	high},
103 	{out_A,	in_B,	in_A,		high,	low,	low,	high},
104 	{in_B,	off,	in_A,		high,	high,	low,	low},
105 	{in_B,	out_A,	in_A,		high,	low,	low,	high},
106 	{out_B,	off,	in_A,		high,	low,	low,	high},
107 	{off,	off,	out_A,		low,	high,	high,	high},
108 	{off,	in_A,	out_A,		low,	high,	high,	low},
109 	{off,	in_B,	out_A,		low,	high,	high,	low},
110 	{off,	out_B,	out_A,		low,	low,	high,	high},
111 	{in_A,	off,	out_A,		low,	high,	high,	low},
112 	{in_A,	in_B,	out_A,		low,	high,	high,	low},
113 	{in_A,	out_B,	out_A,		low,	low,	high,	high},
114 	{in_B,	off,	out_A,		low,	high,	high,	low},
115 	{in_B,	in_A,	out_A,		low,	high,	high,	low},
116 	{out_B,	off,	out_A,		low,	low,	high,	high},
117 	{out_B,	in_A,	out_A,		low,	low,	high,	high},
118 	{off,	off,	in_B,		high,	high,	low,	high},
119 	{off,	in_A,	in_B,		high,	high,	low,	low},
120 	{off,	out_A,	in_B,		high,	low,	low,	high},
121 	{off,	out_B,	in_B,		high,	low,	low,	high},
122 	{in_A,	off,	in_B,		high,	high,	low,	low},
123 	{in_A,	out_B,	in_B,		high,	low,	low,	high},
124 	{out_A,	off,	in_B,		high,	low,	low,	high},
125 	{out_B,	off,	in_B,		high,	low,	low,	high},
126 	{out_B,	in_A,	in_B,		high,	low,	low,	high},
127 	{off,	off,	out_B,		low,	high,	high,	high},
128 	{off,	in_A,	out_B,		low,	high,	high,	low},
129 	{off,	out_A,	out_B,		low,	low,	high,	high},
130 	{off,	in_B,	out_B,		low,	high,	high,	low},
131 	{in_A,	off,	out_B,		low,	high,	high,	low},
132 	{in_A,	in_B,	out_B,		low,	high,	high,	low},
133 	{out_A,	off,	out_B,		low,	low,	high,	high},
134 	{out_A,	in_B,	out_B,		low,	low,	high,	high},
135 	{in_B,	off,	out_B,		low,	high,	high,	low},
136 	{in_B,	in_A,	out_B,		low,	high,	high,	low},
137 	{in_B,	out_A,	out_B,		low,	low,	high,	high},
138 	{end,	end,	end,	led_end, led_end, led_end, led_end}
139 };
140 
141 static int i40e_ptp_set_pins(struct i40e_pf *pf,
142 			     struct i40e_ptp_pins_settings *pins);
143 
144 /**
145  * i40e_ptp_extts0_work - workqueue task function
146  * @work: workqueue task structure
147  *
148  * Service for PTP external clock event
149  **/
i40e_ptp_extts0_work(struct work_struct * work)150 static void i40e_ptp_extts0_work(struct work_struct *work)
151 {
152 	struct i40e_pf *pf = container_of(work, struct i40e_pf,
153 					  ptp_extts0_work);
154 	struct i40e_hw *hw = &pf->hw;
155 	struct ptp_clock_event event;
156 	u32 hi, lo;
157 
158 	/* Event time is captured by one of the two matched registers
159 	 *      PRTTSYN_EVNT_L: 32 LSB of sampled time event
160 	 *      PRTTSYN_EVNT_H: 32 MSB of sampled time event
161 	 * Event is defined in PRTTSYN_EVNT_0 register
162 	 */
163 	lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0));
164 	hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0));
165 
166 	event.timestamp = (((u64)hi) << 32) | lo;
167 
168 	event.type = PTP_CLOCK_EXTTS;
169 	event.index = hw->pf_id;
170 
171 	/* fire event */
172 	ptp_clock_event(pf->ptp_clock, &event);
173 }
174 
175 /**
176  * i40e_is_ptp_pin_dev - check if device supports PTP pins
177  * @hw: pointer to the hardware structure
178  *
179  * Return true if device supports PTP pins, false otherwise.
180  **/
i40e_is_ptp_pin_dev(struct i40e_hw * hw)181 static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw)
182 {
183 	return hw->device_id == I40E_DEV_ID_25G_SFP28 &&
184 	       hw->subsystem_device_id == I40E_SUBDEV_ID_25G_PTP_PIN;
185 }
186 
187 /**
188  * i40e_can_set_pins - check possibility of manipulating the pins
189  * @pf: board private structure
190  *
191  * Check if all conditions are satisfied to manipulate PTP pins.
192  * Return CAN_SET_PINS if pins can be set on a specific PF or
193  * return CAN_DO_PINS if pins can be manipulated within a NIC or
194  * return CANT_DO_PINS otherwise.
195  **/
i40e_can_set_pins(struct i40e_pf * pf)196 static enum i40e_can_set_pins_t i40e_can_set_pins(struct i40e_pf *pf)
197 {
198 	if (!i40e_is_ptp_pin_dev(&pf->hw)) {
199 		dev_warn(&pf->pdev->dev,
200 			 "PTP external clock not supported.\n");
201 		return CANT_DO_PINS;
202 	}
203 
204 	if (!pf->ptp_pins) {
205 		dev_warn(&pf->pdev->dev,
206 			 "PTP PIN manipulation not allowed.\n");
207 		return CANT_DO_PINS;
208 	}
209 
210 	if (pf->hw.pf_id) {
211 		dev_warn(&pf->pdev->dev,
212 			 "PTP PINs should be accessed via PF0.\n");
213 		return CAN_DO_PINS;
214 	}
215 
216 	return CAN_SET_PINS;
217 }
218 
219 /**
220  * i40_ptp_reset_timing_events - Reset PTP timing events
221  * @pf: Board private structure
222  *
223  * This function resets timing events for pf.
224  **/
i40_ptp_reset_timing_events(struct i40e_pf * pf)225 static void i40_ptp_reset_timing_events(struct i40e_pf *pf)
226 {
227 	u32 i;
228 
229 	spin_lock_bh(&pf->ptp_rx_lock);
230 	for (i = 0; i <= I40E_PRTTSYN_RXTIME_L_MAX_INDEX; i++) {
231 		/* reading and automatically clearing timing events registers */
232 		rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i));
233 		rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i));
234 		pf->latch_events[i] = 0;
235 	}
236 	/* reading and automatically clearing timing events registers */
237 	rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L);
238 	rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H);
239 
240 	pf->tx_hwtstamp_timeouts = 0;
241 	pf->tx_hwtstamp_skipped = 0;
242 	pf->rx_hwtstamp_cleared = 0;
243 	pf->latch_event_flags = 0;
244 	spin_unlock_bh(&pf->ptp_rx_lock);
245 }
246 
247 /**
248  * i40e_ptp_verify - check pins
249  * @ptp: ptp clock
250  * @pin: pin index
251  * @func: assigned function
252  * @chan: channel
253  *
254  * Check pins consistency.
255  * Return 0 on success or error on failure.
256  **/
i40e_ptp_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)257 static int i40e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
258 			   enum ptp_pin_function func, unsigned int chan)
259 {
260 	switch (func) {
261 	case PTP_PF_NONE:
262 	case PTP_PF_EXTTS:
263 	case PTP_PF_PEROUT:
264 		break;
265 	case PTP_PF_PHYSYNC:
266 		return -EOPNOTSUPP;
267 	}
268 	return 0;
269 }
270 
271 /**
272  * i40e_ptp_read - Read the PHC time from the device
273  * @pf: Board private structure
274  * @ts: timespec structure to hold the current time value
275  * @sts: structure to hold the system time before and after reading the PHC
276  *
277  * This function reads the PRTTSYN_TIME registers and stores them in a
278  * timespec. However, since the registers are 64 bits of nanoseconds, we must
279  * convert the result to a timespec before we can return.
280  **/
i40e_ptp_read(struct i40e_pf * pf,struct timespec64 * ts,struct ptp_system_timestamp * sts)281 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts,
282 			  struct ptp_system_timestamp *sts)
283 {
284 	struct i40e_hw *hw = &pf->hw;
285 	u32 hi, lo;
286 	u64 ns;
287 
288 	/* The timer latches on the lowest register read. */
289 	ptp_read_system_prets(sts);
290 	lo = rd32(hw, I40E_PRTTSYN_TIME_L);
291 	ptp_read_system_postts(sts);
292 	hi = rd32(hw, I40E_PRTTSYN_TIME_H);
293 
294 	ns = (((u64)hi) << 32) | lo;
295 
296 	*ts = ns_to_timespec64(ns);
297 }
298 
299 /**
300  * i40e_ptp_write - Write the PHC time to the device
301  * @pf: Board private structure
302  * @ts: timespec structure that holds the new time value
303  *
304  * This function writes the PRTTSYN_TIME registers with the user value. Since
305  * we receive a timespec from the stack, we must convert that timespec into
306  * nanoseconds before programming the registers.
307  **/
i40e_ptp_write(struct i40e_pf * pf,const struct timespec64 * ts)308 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
309 {
310 	struct i40e_hw *hw = &pf->hw;
311 	u64 ns = timespec64_to_ns(ts);
312 
313 	/* The timer will not update until the high register is written, so
314 	 * write the low register first.
315 	 */
316 	wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
317 	wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
318 }
319 
320 /**
321  * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
322  * @hwtstamps: Timestamp structure to update
323  * @timestamp: Timestamp from the hardware
324  *
325  * We need to convert the NIC clock value into a hwtstamp which can be used by
326  * the upper level timestamping functions. Since the timestamp is simply a 64-
327  * bit nanosecond value, we can call ns_to_ktime directly to handle this.
328  **/
i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps * hwtstamps,u64 timestamp)329 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
330 					 u64 timestamp)
331 {
332 	memset(hwtstamps, 0, sizeof(*hwtstamps));
333 
334 	hwtstamps->hwtstamp = ns_to_ktime(timestamp);
335 }
336 
337 /**
338  * i40e_ptp_adjfreq - Adjust the PHC frequency
339  * @ptp: The PTP clock structure
340  * @ppb: Parts per billion adjustment from the base
341  *
342  * Adjust the frequency of the PHC by the indicated parts per billion from the
343  * base frequency.
344  **/
i40e_ptp_adjfreq(struct ptp_clock_info * ptp,s32 ppb)345 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
346 {
347 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
348 	struct i40e_hw *hw = &pf->hw;
349 	u64 adj, freq, diff;
350 	int neg_adj = 0;
351 
352 	if (ppb < 0) {
353 		neg_adj = 1;
354 		ppb = -ppb;
355 	}
356 
357 	freq = I40E_PTP_40GB_INCVAL;
358 	freq *= ppb;
359 	diff = div_u64(freq, 1000000000ULL);
360 
361 	if (neg_adj)
362 		adj = I40E_PTP_40GB_INCVAL - diff;
363 	else
364 		adj = I40E_PTP_40GB_INCVAL + diff;
365 
366 	/* At some link speeds, the base incval is so large that directly
367 	 * multiplying by ppb would result in arithmetic overflow even when
368 	 * using a u64. Avoid this by instead calculating the new incval
369 	 * always in terms of the 40GbE clock rate and then multiplying by the
370 	 * link speed factor afterwards. This does result in slightly lower
371 	 * precision at lower link speeds, but it is fairly minor.
372 	 */
373 	smp_mb(); /* Force any pending update before accessing. */
374 	adj *= READ_ONCE(pf->ptp_adj_mult);
375 
376 	wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
377 	wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
378 
379 	return 0;
380 }
381 
382 /**
383  * i40e_ptp_set_1pps_signal_hw - configure 1PPS PTP signal for pins
384  * @pf: the PF private data structure
385  *
386  * Configure 1PPS signal used for PTP pins
387  **/
i40e_ptp_set_1pps_signal_hw(struct i40e_pf * pf)388 static void i40e_ptp_set_1pps_signal_hw(struct i40e_pf *pf)
389 {
390 	struct i40e_hw *hw = &pf->hw;
391 	struct timespec64 now;
392 	u64 ns;
393 
394 	wr32(hw, I40E_PRTTSYN_AUX_0(1), 0);
395 	wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT);
396 	wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE);
397 
398 	i40e_ptp_read(pf, &now, NULL);
399 	now.tv_sec += I40E_PTP_2_SEC_DELAY;
400 	now.tv_nsec = 0;
401 	ns = timespec64_to_ns(&now);
402 
403 	/* I40E_PRTTSYN_TGT_L(1) */
404 	wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF);
405 	/* I40E_PRTTSYN_TGT_H(1) */
406 	wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32);
407 	wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND);
408 	wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT);
409 	wr32(hw, I40E_PRTTSYN_AUX_0(1),
410 	     I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD);
411 }
412 
413 /**
414  * i40e_ptp_adjtime - Adjust the PHC time
415  * @ptp: The PTP clock structure
416  * @delta: Offset in nanoseconds to adjust the PHC time by
417  *
418  * Adjust the current clock time by a delta specified in nanoseconds.
419  **/
i40e_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)420 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
421 {
422 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
423 	struct i40e_hw *hw = &pf->hw;
424 
425 	mutex_lock(&pf->tmreg_lock);
426 
427 	if (delta > -999999900LL && delta < 999999900LL) {
428 		int neg_adj = 0;
429 		u32 timadj;
430 		u64 tohw;
431 
432 		if (delta < 0) {
433 			neg_adj = 1;
434 			tohw = -delta;
435 		} else {
436 			tohw = delta;
437 		}
438 
439 		timadj = tohw & 0x3FFFFFFF;
440 		if (neg_adj)
441 			timadj |= I40E_ISGN;
442 		wr32(hw, I40E_PRTTSYN_ADJ, timadj);
443 	} else {
444 		struct timespec64 then, now;
445 
446 		then = ns_to_timespec64(delta);
447 		i40e_ptp_read(pf, &now, NULL);
448 		now = timespec64_add(now, then);
449 		i40e_ptp_write(pf, (const struct timespec64 *)&now);
450 		i40e_ptp_set_1pps_signal_hw(pf);
451 	}
452 
453 	mutex_unlock(&pf->tmreg_lock);
454 
455 	return 0;
456 }
457 
458 /**
459  * i40e_ptp_gettimex - Get the time of the PHC
460  * @ptp: The PTP clock structure
461  * @ts: timespec structure to hold the current time value
462  * @sts: structure to hold the system time before and after reading the PHC
463  *
464  * Read the device clock and return the correct value on ns, after converting it
465  * into a timespec struct.
466  **/
i40e_ptp_gettimex(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)467 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
468 			     struct ptp_system_timestamp *sts)
469 {
470 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
471 
472 	mutex_lock(&pf->tmreg_lock);
473 	i40e_ptp_read(pf, ts, sts);
474 	mutex_unlock(&pf->tmreg_lock);
475 
476 	return 0;
477 }
478 
479 /**
480  * i40e_ptp_settime - Set the time of the PHC
481  * @ptp: The PTP clock structure
482  * @ts: timespec64 structure that holds the new time value
483  *
484  * Set the device clock to the user input value. The conversion from timespec
485  * to ns happens in the write function.
486  **/
i40e_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)487 static int i40e_ptp_settime(struct ptp_clock_info *ptp,
488 			    const struct timespec64 *ts)
489 {
490 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
491 
492 	mutex_lock(&pf->tmreg_lock);
493 	i40e_ptp_write(pf, ts);
494 	mutex_unlock(&pf->tmreg_lock);
495 
496 	return 0;
497 }
498 
499 /**
500  * i40e_pps_configure - configure PPS events
501  * @ptp: ptp clock
502  * @rq: clock request
503  * @on: status
504  *
505  * Configure PPS events for external clock source.
506  * Return 0 on success or error on failure.
507  **/
i40e_pps_configure(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)508 static int i40e_pps_configure(struct ptp_clock_info *ptp,
509 			      struct ptp_clock_request *rq,
510 			      int on)
511 {
512 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
513 
514 	if (!!on)
515 		i40e_ptp_set_1pps_signal_hw(pf);
516 
517 	return 0;
518 }
519 
520 /**
521  * i40e_pin_state - determine PIN state
522  * @index: PIN index
523  * @func: function assigned to PIN
524  *
525  * Determine PIN state based on PIN index and function assigned.
526  * Return PIN state.
527  **/
i40e_pin_state(int index,int func)528 static enum i40e_ptp_gpio_pin_state i40e_pin_state(int index, int func)
529 {
530 	enum i40e_ptp_gpio_pin_state state = off;
531 
532 	if (index == 0 && func == PTP_PF_EXTTS)
533 		state = in_A;
534 	if (index == 1 && func == PTP_PF_EXTTS)
535 		state = in_B;
536 	if (index == 0 && func == PTP_PF_PEROUT)
537 		state = out_A;
538 	if (index == 1 && func == PTP_PF_PEROUT)
539 		state = out_B;
540 
541 	return state;
542 }
543 
544 /**
545  * i40e_ptp_enable_pin - enable PINs.
546  * @pf: private board structure
547  * @chan: channel
548  * @func: PIN function
549  * @on: state
550  *
551  * Enable PTP pins for external clock source.
552  * Return 0 on success or error code on failure.
553  **/
i40e_ptp_enable_pin(struct i40e_pf * pf,unsigned int chan,enum ptp_pin_function func,int on)554 static int i40e_ptp_enable_pin(struct i40e_pf *pf, unsigned int chan,
555 			       enum ptp_pin_function func, int on)
556 {
557 	enum i40e_ptp_gpio_pin_state *pin = NULL;
558 	struct i40e_ptp_pins_settings pins;
559 	int pin_index;
560 
561 	/* Use PF0 to set pins. Return success for user space tools */
562 	if (pf->hw.pf_id)
563 		return 0;
564 
565 	/* Preserve previous state of pins that we don't touch */
566 	pins.sdp3_2 = pf->ptp_pins->sdp3_2;
567 	pins.sdp3_3 = pf->ptp_pins->sdp3_3;
568 	pins.gpio_4 = pf->ptp_pins->gpio_4;
569 
570 	/* To turn on the pin - find the corresponding one based on
571 	 * the given index. To to turn the function off - find
572 	 * which pin had it assigned. Don't use ptp_find_pin here
573 	 * because it tries to lock the pincfg_mux which is locked by
574 	 * ptp_pin_store() that calls here.
575 	 */
576 	if (on) {
577 		pin_index = ptp_find_pin(pf->ptp_clock, func, chan);
578 		if (pin_index < 0)
579 			return -EBUSY;
580 
581 		switch (pin_index) {
582 		case SDP3_2:
583 			pin = &pins.sdp3_2;
584 			break;
585 		case SDP3_3:
586 			pin = &pins.sdp3_3;
587 			break;
588 		case GPIO_4:
589 			pin = &pins.gpio_4;
590 			break;
591 		default:
592 			return -EINVAL;
593 		}
594 
595 		*pin = i40e_pin_state(chan, func);
596 	} else {
597 		pins.sdp3_2 = off;
598 		pins.sdp3_3 = off;
599 		pins.gpio_4 = off;
600 	}
601 
602 	return i40e_ptp_set_pins(pf, &pins) ? -EINVAL : 0;
603 }
604 
605 /**
606  * i40e_ptp_feature_enable - Enable external clock pins
607  * @ptp: The PTP clock structure
608  * @rq: The PTP clock request structure
609  * @on: To turn feature on/off
610  *
611  * Setting on/off PTP PPS feature for pin.
612  **/
i40e_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)613 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
614 				   struct ptp_clock_request *rq,
615 				   int on)
616 {
617 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
618 
619 	enum ptp_pin_function func;
620 	unsigned int chan;
621 
622 	/* TODO: Implement flags handling for EXTTS and PEROUT */
623 	switch (rq->type) {
624 	case PTP_CLK_REQ_EXTTS:
625 		func = PTP_PF_EXTTS;
626 		chan = rq->extts.index;
627 		break;
628 	case PTP_CLK_REQ_PEROUT:
629 		func = PTP_PF_PEROUT;
630 		chan = rq->perout.index;
631 		break;
632 	case PTP_CLK_REQ_PPS:
633 		return i40e_pps_configure(ptp, rq, on);
634 	default:
635 		return -EOPNOTSUPP;
636 	}
637 
638 	return i40e_ptp_enable_pin(pf, chan, func, on);
639 }
640 
641 /**
642  * i40e_ptp_get_rx_events - Read I40E_PRTTSYN_STAT_1 and latch events
643  * @pf: the PF data structure
644  *
645  * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers
646  * for noticed latch events. This allows the driver to keep track of the first
647  * time a latch event was noticed which will be used to help clear out Rx
648  * timestamps for packets that got dropped or lost.
649  *
650  * This function will return the current value of I40E_PRTTSYN_STAT_1 and is
651  * expected to be called only while under the ptp_rx_lock.
652  **/
i40e_ptp_get_rx_events(struct i40e_pf * pf)653 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
654 {
655 	struct i40e_hw *hw = &pf->hw;
656 	u32 prttsyn_stat, new_latch_events;
657 	int  i;
658 
659 	prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
660 	new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
661 
662 	/* Update the jiffies time for any newly latched timestamp. This
663 	 * ensures that we store the time that we first discovered a timestamp
664 	 * was latched by the hardware. The service task will later determine
665 	 * if we should free the latch and drop that timestamp should too much
666 	 * time pass. This flow ensures that we only update jiffies for new
667 	 * events latched since the last time we checked, and not all events
668 	 * currently latched, so that the service task accounting remains
669 	 * accurate.
670 	 */
671 	for (i = 0; i < 4; i++) {
672 		if (new_latch_events & BIT(i))
673 			pf->latch_events[i] = jiffies;
674 	}
675 
676 	/* Finally, we store the current status of the Rx timestamp latches */
677 	pf->latch_event_flags = prttsyn_stat;
678 
679 	return prttsyn_stat;
680 }
681 
682 /**
683  * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
684  * @pf: The PF private data structure
685  *
686  * This watchdog task is scheduled to detect error case where hardware has
687  * dropped an Rx packet that was timestamped when the ring is full. The
688  * particular error is rare but leaves the device in a state unable to timestamp
689  * any future packets.
690  **/
i40e_ptp_rx_hang(struct i40e_pf * pf)691 void i40e_ptp_rx_hang(struct i40e_pf *pf)
692 {
693 	struct i40e_hw *hw = &pf->hw;
694 	unsigned int i, cleared = 0;
695 
696 	/* Since we cannot turn off the Rx timestamp logic if the device is
697 	 * configured for Tx timestamping, we check if Rx timestamping is
698 	 * configured. We don't want to spuriously warn about Rx timestamp
699 	 * hangs if we don't care about the timestamps.
700 	 */
701 	if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
702 		return;
703 
704 	spin_lock_bh(&pf->ptp_rx_lock);
705 
706 	/* Update current latch times for Rx events */
707 	i40e_ptp_get_rx_events(pf);
708 
709 	/* Check all the currently latched Rx events and see whether they have
710 	 * been latched for over a second. It is assumed that any timestamp
711 	 * should have been cleared within this time, or else it was captured
712 	 * for a dropped frame that the driver never received. Thus, we will
713 	 * clear any timestamp that has been latched for over 1 second.
714 	 */
715 	for (i = 0; i < 4; i++) {
716 		if ((pf->latch_event_flags & BIT(i)) &&
717 		    time_is_before_jiffies(pf->latch_events[i] + HZ)) {
718 			rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
719 			pf->latch_event_flags &= ~BIT(i);
720 			cleared++;
721 		}
722 	}
723 
724 	spin_unlock_bh(&pf->ptp_rx_lock);
725 
726 	/* Log a warning if more than 2 timestamps got dropped in the same
727 	 * check. We don't want to warn about all drops because it can occur
728 	 * in normal scenarios such as PTP frames on multicast addresses we
729 	 * aren't listening to. However, administrator should know if this is
730 	 * the reason packets aren't receiving timestamps.
731 	 */
732 	if (cleared > 2)
733 		dev_dbg(&pf->pdev->dev,
734 			"Dropped %d missed RXTIME timestamp events\n",
735 			cleared);
736 
737 	/* Finally, update the rx_hwtstamp_cleared counter */
738 	pf->rx_hwtstamp_cleared += cleared;
739 }
740 
741 /**
742  * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung
743  * @pf: The PF private data structure
744  *
745  * This watchdog task is run periodically to make sure that we clear the Tx
746  * timestamp logic if we don't obtain a timestamp in a reasonable amount of
747  * time. It is unexpected in the normal case but if it occurs it results in
748  * permanently preventing timestamps of future packets.
749  **/
i40e_ptp_tx_hang(struct i40e_pf * pf)750 void i40e_ptp_tx_hang(struct i40e_pf *pf)
751 {
752 	struct sk_buff *skb;
753 
754 	if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
755 		return;
756 
757 	/* Nothing to do if we're not already waiting for a timestamp */
758 	if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
759 		return;
760 
761 	/* We already have a handler routine which is run when we are notified
762 	 * of a Tx timestamp in the hardware. If we don't get an interrupt
763 	 * within a second it is reasonable to assume that we never will.
764 	 */
765 	if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
766 		skb = pf->ptp_tx_skb;
767 		pf->ptp_tx_skb = NULL;
768 		clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
769 
770 		/* Free the skb after we clear the bitlock */
771 		dev_kfree_skb_any(skb);
772 		pf->tx_hwtstamp_timeouts++;
773 	}
774 }
775 
776 /**
777  * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
778  * @pf: Board private structure
779  *
780  * Read the value of the Tx timestamp from the registers, convert it into a
781  * value consumable by the stack, and store that result into the shhwtstamps
782  * struct before returning it up the stack.
783  **/
i40e_ptp_tx_hwtstamp(struct i40e_pf * pf)784 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
785 {
786 	struct skb_shared_hwtstamps shhwtstamps;
787 	struct sk_buff *skb = pf->ptp_tx_skb;
788 	struct i40e_hw *hw = &pf->hw;
789 	u32 hi, lo;
790 	u64 ns;
791 
792 	if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
793 		return;
794 
795 	/* don't attempt to timestamp if we don't have an skb */
796 	if (!pf->ptp_tx_skb)
797 		return;
798 
799 	lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
800 	hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
801 
802 	ns = (((u64)hi) << 32) | lo;
803 	i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
804 
805 	/* Clear the bit lock as soon as possible after reading the register,
806 	 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise
807 	 * applications might wake up and attempt to request another transmit
808 	 * timestamp prior to the bit lock being cleared.
809 	 */
810 	pf->ptp_tx_skb = NULL;
811 	clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
812 
813 	/* Notify the stack and free the skb after we've unlocked */
814 	skb_tstamp_tx(skb, &shhwtstamps);
815 	dev_kfree_skb_any(skb);
816 }
817 
818 /**
819  * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
820  * @pf: Board private structure
821  * @skb: Particular skb to send timestamp with
822  * @index: Index into the receive timestamp registers for the timestamp
823  *
824  * The XL710 receives a notification in the receive descriptor with an offset
825  * into the set of RXTIME registers where the timestamp is for that skb. This
826  * function goes and fetches the receive timestamp from that offset, if a valid
827  * one exists. The RXTIME registers are in ns, so we must convert the result
828  * first.
829  **/
i40e_ptp_rx_hwtstamp(struct i40e_pf * pf,struct sk_buff * skb,u8 index)830 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
831 {
832 	u32 prttsyn_stat, hi, lo;
833 	struct i40e_hw *hw;
834 	u64 ns;
835 
836 	/* Since we cannot turn off the Rx timestamp logic if the device is
837 	 * doing Tx timestamping, check if Rx timestamping is configured.
838 	 */
839 	if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
840 		return;
841 
842 	hw = &pf->hw;
843 
844 	spin_lock_bh(&pf->ptp_rx_lock);
845 
846 	/* Get current Rx events and update latch times */
847 	prttsyn_stat = i40e_ptp_get_rx_events(pf);
848 
849 	/* TODO: Should we warn about missing Rx timestamp event? */
850 	if (!(prttsyn_stat & BIT(index))) {
851 		spin_unlock_bh(&pf->ptp_rx_lock);
852 		return;
853 	}
854 
855 	/* Clear the latched event since we're about to read its register */
856 	pf->latch_event_flags &= ~BIT(index);
857 
858 	lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
859 	hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
860 
861 	spin_unlock_bh(&pf->ptp_rx_lock);
862 
863 	ns = (((u64)hi) << 32) | lo;
864 
865 	i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
866 }
867 
868 /**
869  * i40e_ptp_set_increment - Utility function to update clock increment rate
870  * @pf: Board private structure
871  *
872  * During a link change, the DMA frequency that drives the 1588 logic will
873  * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
874  * we must update the increment value per clock tick.
875  **/
i40e_ptp_set_increment(struct i40e_pf * pf)876 void i40e_ptp_set_increment(struct i40e_pf *pf)
877 {
878 	struct i40e_link_status *hw_link_info;
879 	struct i40e_hw *hw = &pf->hw;
880 	u64 incval;
881 	u32 mult;
882 
883 	hw_link_info = &hw->phy.link_info;
884 
885 	i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
886 
887 	switch (hw_link_info->link_speed) {
888 	case I40E_LINK_SPEED_10GB:
889 		mult = I40E_PTP_10GB_INCVAL_MULT;
890 		break;
891 	case I40E_LINK_SPEED_5GB:
892 		mult = I40E_PTP_5GB_INCVAL_MULT;
893 		break;
894 	case I40E_LINK_SPEED_1GB:
895 		mult = I40E_PTP_1GB_INCVAL_MULT;
896 		break;
897 	case I40E_LINK_SPEED_100MB:
898 	{
899 		static int warn_once;
900 
901 		if (!warn_once) {
902 			dev_warn(&pf->pdev->dev,
903 				 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
904 			warn_once++;
905 		}
906 		mult = 0;
907 		break;
908 	}
909 	case I40E_LINK_SPEED_40GB:
910 	default:
911 		mult = 1;
912 		break;
913 	}
914 
915 	/* The increment value is calculated by taking the base 40GbE incvalue
916 	 * and multiplying it by a factor based on the link speed.
917 	 */
918 	incval = I40E_PTP_40GB_INCVAL * mult;
919 
920 	/* Write the new increment value into the increment register. The
921 	 * hardware will not update the clock until both registers have been
922 	 * written.
923 	 */
924 	wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
925 	wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
926 
927 	/* Update the base adjustement value. */
928 	WRITE_ONCE(pf->ptp_adj_mult, mult);
929 	smp_mb(); /* Force the above update. */
930 }
931 
932 /**
933  * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
934  * @pf: Board private structure
935  * @ifr: ioctl data
936  *
937  * Obtain the current hardware timestamping settigs as requested. To do this,
938  * keep a shadow copy of the timestamp settings rather than attempting to
939  * deconstruct it from the registers.
940  **/
i40e_ptp_get_ts_config(struct i40e_pf * pf,struct ifreq * ifr)941 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
942 {
943 	struct hwtstamp_config *config = &pf->tstamp_config;
944 
945 	if (!(pf->flags & I40E_FLAG_PTP))
946 		return -EOPNOTSUPP;
947 
948 	return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
949 		-EFAULT : 0;
950 }
951 
952 /**
953  * i40e_ptp_free_pins - free memory used by PTP pins
954  * @pf: Board private structure
955  *
956  * Release memory allocated for PTP pins.
957  **/
i40e_ptp_free_pins(struct i40e_pf * pf)958 static void i40e_ptp_free_pins(struct i40e_pf *pf)
959 {
960 	if (i40e_is_ptp_pin_dev(&pf->hw)) {
961 		kfree(pf->ptp_pins);
962 		kfree(pf->ptp_caps.pin_config);
963 		pf->ptp_pins = NULL;
964 	}
965 }
966 
967 /**
968  * i40e_ptp_set_pin_hw - Set HW GPIO pin
969  * @hw: pointer to the hardware structure
970  * @pin: pin index
971  * @state: pin state
972  *
973  * Set status of GPIO pin for external clock handling.
974  **/
i40e_ptp_set_pin_hw(struct i40e_hw * hw,unsigned int pin,enum i40e_ptp_gpio_pin_state state)975 static void i40e_ptp_set_pin_hw(struct i40e_hw *hw,
976 				unsigned int pin,
977 				enum i40e_ptp_gpio_pin_state state)
978 {
979 	switch (state) {
980 	case off:
981 		wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 0);
982 		break;
983 	case in_A:
984 		wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
985 		     I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0);
986 		break;
987 	case in_B:
988 		wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
989 		     I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0);
990 		break;
991 	case out_A:
992 		wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
993 		     I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1);
994 		break;
995 	case out_B:
996 		wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
997 		     I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1);
998 		break;
999 	default:
1000 		break;
1001 	}
1002 }
1003 
1004 /**
1005  * i40e_ptp_set_led_hw - Set HW GPIO led
1006  * @hw: pointer to the hardware structure
1007  * @led: led index
1008  * @state: led state
1009  *
1010  * Set status of GPIO led for external clock handling.
1011  **/
i40e_ptp_set_led_hw(struct i40e_hw * hw,unsigned int led,enum i40e_ptp_led_pin_state state)1012 static void i40e_ptp_set_led_hw(struct i40e_hw *hw,
1013 				unsigned int led,
1014 				enum i40e_ptp_led_pin_state state)
1015 {
1016 	switch (state) {
1017 	case low:
1018 		wr32(hw, I40E_GLGEN_GPIO_SET,
1019 		     I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | led);
1020 		break;
1021 	case high:
1022 		wr32(hw, I40E_GLGEN_GPIO_SET,
1023 		     I40E_GLGEN_GPIO_SET_DRV_SDP_DATA |
1024 		     I40E_GLGEN_GPIO_SET_SDP_DATA_HI | led);
1025 		break;
1026 	default:
1027 		break;
1028 	}
1029 }
1030 
1031 /**
1032  * i40e_ptp_init_leds_hw - init LEDs
1033  * @hw: pointer to a hardware structure
1034  *
1035  * Set initial state of LEDs
1036  **/
i40e_ptp_init_leds_hw(struct i40e_hw * hw)1037 static void i40e_ptp_init_leds_hw(struct i40e_hw *hw)
1038 {
1039 	wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_0),
1040 	     I40E_GLGEN_GPIO_CTL_LED_INIT);
1041 	wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_1),
1042 	     I40E_GLGEN_GPIO_CTL_LED_INIT);
1043 	wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_0),
1044 	     I40E_GLGEN_GPIO_CTL_LED_INIT);
1045 	wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_1),
1046 	     I40E_GLGEN_GPIO_CTL_LED_INIT);
1047 }
1048 
1049 /**
1050  * i40e_ptp_set_pins_hw - Set HW GPIO pins
1051  * @pf: Board private structure
1052  *
1053  * This function sets GPIO pins for PTP
1054  **/
i40e_ptp_set_pins_hw(struct i40e_pf * pf)1055 static void i40e_ptp_set_pins_hw(struct i40e_pf *pf)
1056 {
1057 	const struct i40e_ptp_pins_settings *pins = pf->ptp_pins;
1058 	struct i40e_hw *hw = &pf->hw;
1059 
1060 	/* pin must be disabled before it may be used */
1061 	i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off);
1062 	i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off);
1063 	i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off);
1064 
1065 	i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, pins->sdp3_2);
1066 	i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, pins->sdp3_3);
1067 	i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, pins->gpio_4);
1068 
1069 	i40e_ptp_set_led_hw(hw, I40E_LED2_0, pins->led2_0);
1070 	i40e_ptp_set_led_hw(hw, I40E_LED2_1, pins->led2_1);
1071 	i40e_ptp_set_led_hw(hw, I40E_LED3_0, pins->led3_0);
1072 	i40e_ptp_set_led_hw(hw, I40E_LED3_1, pins->led3_1);
1073 
1074 	dev_info(&pf->pdev->dev,
1075 		 "PTP configuration set to: SDP3_2: %s,  SDP3_3: %s,  GPIO_4: %s.\n",
1076 		 i40e_ptp_gpio_pin_state2str[pins->sdp3_2],
1077 		 i40e_ptp_gpio_pin_state2str[pins->sdp3_3],
1078 		 i40e_ptp_gpio_pin_state2str[pins->gpio_4]);
1079 }
1080 
1081 /**
1082  * i40e_ptp_set_pins - set PTP pins in HW
1083  * @pf: Board private structure
1084  * @pins: PTP pins to be applied
1085  *
1086  * Validate and set PTP pins in HW for specific PF.
1087  * Return 0 on success or negative value on error.
1088  **/
i40e_ptp_set_pins(struct i40e_pf * pf,struct i40e_ptp_pins_settings * pins)1089 static int i40e_ptp_set_pins(struct i40e_pf *pf,
1090 			     struct i40e_ptp_pins_settings *pins)
1091 {
1092 	enum i40e_can_set_pins_t pin_caps = i40e_can_set_pins(pf);
1093 	int i = 0;
1094 
1095 	if (pin_caps == CANT_DO_PINS)
1096 		return -EOPNOTSUPP;
1097 	else if (pin_caps == CAN_DO_PINS)
1098 		return 0;
1099 
1100 	if (pins->sdp3_2 == invalid)
1101 		pins->sdp3_2 = pf->ptp_pins->sdp3_2;
1102 	if (pins->sdp3_3 == invalid)
1103 		pins->sdp3_3 = pf->ptp_pins->sdp3_3;
1104 	if (pins->gpio_4 == invalid)
1105 		pins->gpio_4 = pf->ptp_pins->gpio_4;
1106 	while (i40e_ptp_pin_led_allowed_states[i].sdp3_2 != end) {
1107 		if (pins->sdp3_2 == i40e_ptp_pin_led_allowed_states[i].sdp3_2 &&
1108 		    pins->sdp3_3 == i40e_ptp_pin_led_allowed_states[i].sdp3_3 &&
1109 		    pins->gpio_4 == i40e_ptp_pin_led_allowed_states[i].gpio_4) {
1110 			pins->led2_0 =
1111 				i40e_ptp_pin_led_allowed_states[i].led2_0;
1112 			pins->led2_1 =
1113 				i40e_ptp_pin_led_allowed_states[i].led2_1;
1114 			pins->led3_0 =
1115 				i40e_ptp_pin_led_allowed_states[i].led3_0;
1116 			pins->led3_1 =
1117 				i40e_ptp_pin_led_allowed_states[i].led3_1;
1118 			break;
1119 		}
1120 		i++;
1121 	}
1122 	if (i40e_ptp_pin_led_allowed_states[i].sdp3_2 == end) {
1123 		dev_warn(&pf->pdev->dev,
1124 			 "Unsupported PTP pin configuration: SDP3_2: %s,  SDP3_3: %s,  GPIO_4: %s.\n",
1125 			 i40e_ptp_gpio_pin_state2str[pins->sdp3_2],
1126 			 i40e_ptp_gpio_pin_state2str[pins->sdp3_3],
1127 			 i40e_ptp_gpio_pin_state2str[pins->gpio_4]);
1128 
1129 		return -EPERM;
1130 	}
1131 	memcpy(pf->ptp_pins, pins, sizeof(*pins));
1132 	i40e_ptp_set_pins_hw(pf);
1133 	i40_ptp_reset_timing_events(pf);
1134 
1135 	return 0;
1136 }
1137 
1138 /**
1139  * i40e_ptp_alloc_pins - allocate PTP pins structure
1140  * @pf: Board private structure
1141  *
1142  * allocate PTP pins structure
1143  **/
i40e_ptp_alloc_pins(struct i40e_pf * pf)1144 int i40e_ptp_alloc_pins(struct i40e_pf *pf)
1145 {
1146 	if (!i40e_is_ptp_pin_dev(&pf->hw))
1147 		return 0;
1148 
1149 	pf->ptp_pins =
1150 		kzalloc(sizeof(struct i40e_ptp_pins_settings), GFP_KERNEL);
1151 
1152 	if (!pf->ptp_pins) {
1153 		dev_warn(&pf->pdev->dev, "Cannot allocate memory for PTP pins structure.\n");
1154 		return -I40E_ERR_NO_MEMORY;
1155 	}
1156 
1157 	pf->ptp_pins->sdp3_2 = off;
1158 	pf->ptp_pins->sdp3_3 = off;
1159 	pf->ptp_pins->gpio_4 = off;
1160 	pf->ptp_pins->led2_0 = high;
1161 	pf->ptp_pins->led2_1 = high;
1162 	pf->ptp_pins->led3_0 = high;
1163 	pf->ptp_pins->led3_1 = high;
1164 
1165 	/* Use PF0 to set pins in HW. Return success for user space tools */
1166 	if (pf->hw.pf_id)
1167 		return 0;
1168 
1169 	i40e_ptp_init_leds_hw(&pf->hw);
1170 	i40e_ptp_set_pins_hw(pf);
1171 
1172 	return 0;
1173 }
1174 
1175 /**
1176  * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
1177  * @pf: Board private structure
1178  * @config: hwtstamp settings requested or saved
1179  *
1180  * Control hardware registers to enter the specific mode requested by the
1181  * user. Also used during reset path to ensure that timestamp settings are
1182  * maintained.
1183  *
1184  * Note: modifies config in place, and may update the requested mode to be
1185  * more broad if the specific filter is not directly supported.
1186  **/
i40e_ptp_set_timestamp_mode(struct i40e_pf * pf,struct hwtstamp_config * config)1187 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
1188 				       struct hwtstamp_config *config)
1189 {
1190 	struct i40e_hw *hw = &pf->hw;
1191 	u32 tsyntype, regval;
1192 
1193 	/* Selects external trigger to cause event */
1194 	regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));
1195 	/* Bit 17:16 is EVNTLVL, 01B rising edge */
1196 	regval &= 0;
1197 	regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT);
1198 	/* regval: 0001 0000 0000 0000 0000 */
1199 	wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);
1200 
1201 	/* Enabel interrupts */
1202 	regval = rd32(hw, I40E_PRTTSYN_CTL0);
1203 	regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT;
1204 	wr32(hw, I40E_PRTTSYN_CTL0, regval);
1205 
1206 	INIT_WORK(&pf->ptp_extts0_work, i40e_ptp_extts0_work);
1207 
1208 	switch (config->tx_type) {
1209 	case HWTSTAMP_TX_OFF:
1210 		pf->ptp_tx = false;
1211 		break;
1212 	case HWTSTAMP_TX_ON:
1213 		pf->ptp_tx = true;
1214 		break;
1215 	default:
1216 		return -ERANGE;
1217 	}
1218 
1219 	switch (config->rx_filter) {
1220 	case HWTSTAMP_FILTER_NONE:
1221 		pf->ptp_rx = false;
1222 		/* We set the type to V1, but do not enable UDP packet
1223 		 * recognition. In this way, we should be as close to
1224 		 * disabling PTP Rx timestamps as possible since V1 packets
1225 		 * are always UDP, since L2 packets are a V2 feature.
1226 		 */
1227 		tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
1228 		break;
1229 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1230 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1231 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1232 		if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
1233 			return -ERANGE;
1234 		pf->ptp_rx = true;
1235 		tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
1236 			   I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
1237 			   I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
1238 		config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1239 		break;
1240 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1241 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1242 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1243 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1244 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1245 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1246 		if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
1247 			return -ERANGE;
1248 		fallthrough;
1249 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1250 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1251 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1252 		pf->ptp_rx = true;
1253 		tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
1254 			   I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
1255 		if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
1256 			tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
1257 			config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1258 		} else {
1259 			config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1260 		}
1261 		break;
1262 	case HWTSTAMP_FILTER_NTP_ALL:
1263 	case HWTSTAMP_FILTER_ALL:
1264 	default:
1265 		return -ERANGE;
1266 	}
1267 
1268 	/* Clear out all 1588-related registers to clear and unlatch them. */
1269 	spin_lock_bh(&pf->ptp_rx_lock);
1270 	rd32(hw, I40E_PRTTSYN_STAT_0);
1271 	rd32(hw, I40E_PRTTSYN_TXTIME_H);
1272 	rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
1273 	rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
1274 	rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
1275 	rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
1276 	pf->latch_event_flags = 0;
1277 	spin_unlock_bh(&pf->ptp_rx_lock);
1278 
1279 	/* Enable/disable the Tx timestamp interrupt based on user input. */
1280 	regval = rd32(hw, I40E_PRTTSYN_CTL0);
1281 	if (pf->ptp_tx)
1282 		regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
1283 	else
1284 		regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
1285 	wr32(hw, I40E_PRTTSYN_CTL0, regval);
1286 
1287 	regval = rd32(hw, I40E_PFINT_ICR0_ENA);
1288 	if (pf->ptp_tx)
1289 		regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
1290 	else
1291 		regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
1292 	wr32(hw, I40E_PFINT_ICR0_ENA, regval);
1293 
1294 	/* Although there is no simple on/off switch for Rx, we "disable" Rx
1295 	 * timestamps by setting to V1 only mode and clear the UDP
1296 	 * recognition. This ought to disable all PTP Rx timestamps as V1
1297 	 * packets are always over UDP. Note that software is configured to
1298 	 * ignore Rx timestamps via the pf->ptp_rx flag.
1299 	 */
1300 	regval = rd32(hw, I40E_PRTTSYN_CTL1);
1301 	/* clear everything but the enable bit */
1302 	regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
1303 	/* now enable bits for desired Rx timestamps */
1304 	regval |= tsyntype;
1305 	wr32(hw, I40E_PRTTSYN_CTL1, regval);
1306 
1307 	return 0;
1308 }
1309 
1310 /**
1311  * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
1312  * @pf: Board private structure
1313  * @ifr: ioctl data
1314  *
1315  * Respond to the user filter requests and make the appropriate hardware
1316  * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
1317  * logic, so keep track in software of whether to indicate these timestamps
1318  * or not.
1319  *
1320  * It is permissible to "upgrade" the user request to a broader filter, as long
1321  * as the user receives the timestamps they care about and the user is notified
1322  * the filter has been broadened.
1323  **/
i40e_ptp_set_ts_config(struct i40e_pf * pf,struct ifreq * ifr)1324 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
1325 {
1326 	struct hwtstamp_config config;
1327 	int err;
1328 
1329 	if (!(pf->flags & I40E_FLAG_PTP))
1330 		return -EOPNOTSUPP;
1331 
1332 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1333 		return -EFAULT;
1334 
1335 	err = i40e_ptp_set_timestamp_mode(pf, &config);
1336 	if (err)
1337 		return err;
1338 
1339 	/* save these settings for future reference */
1340 	pf->tstamp_config = config;
1341 
1342 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1343 		-EFAULT : 0;
1344 }
1345 
1346 /**
1347  * i40e_init_pin_config - initialize pins.
1348  * @pf: private board structure
1349  *
1350  * Initialize pins for external clock source.
1351  * Return 0 on success or error code on failure.
1352  **/
i40e_init_pin_config(struct i40e_pf * pf)1353 static int i40e_init_pin_config(struct i40e_pf *pf)
1354 {
1355 	int i;
1356 
1357 	pf->ptp_caps.n_pins = 3;
1358 	pf->ptp_caps.n_ext_ts = 2;
1359 	pf->ptp_caps.pps = 1;
1360 	pf->ptp_caps.n_per_out = 2;
1361 
1362 	pf->ptp_caps.pin_config = kcalloc(pf->ptp_caps.n_pins,
1363 					  sizeof(*pf->ptp_caps.pin_config),
1364 					  GFP_KERNEL);
1365 	if (!pf->ptp_caps.pin_config)
1366 		return -ENOMEM;
1367 
1368 	for (i = 0; i < pf->ptp_caps.n_pins; i++) {
1369 		snprintf(pf->ptp_caps.pin_config[i].name,
1370 			 sizeof(pf->ptp_caps.pin_config[i].name),
1371 			 "%s", sdp_desc[i].name);
1372 		pf->ptp_caps.pin_config[i].index = sdp_desc[i].index;
1373 		pf->ptp_caps.pin_config[i].func = PTP_PF_NONE;
1374 		pf->ptp_caps.pin_config[i].chan = sdp_desc[i].chan;
1375 	}
1376 
1377 	pf->ptp_caps.verify = i40e_ptp_verify;
1378 	pf->ptp_caps.enable = i40e_ptp_feature_enable;
1379 
1380 	pf->ptp_caps.pps = 1;
1381 
1382 	return 0;
1383 }
1384 
1385 /**
1386  * i40e_ptp_create_clock - Create PTP clock device for userspace
1387  * @pf: Board private structure
1388  *
1389  * This function creates a new PTP clock device. It only creates one if we
1390  * don't already have one, so it is safe to call. Will return error if it
1391  * can't create one, but success if we already have a device. Should be used
1392  * by i40e_ptp_init to create clock initially, and prevent global resets from
1393  * creating new clock devices.
1394  **/
i40e_ptp_create_clock(struct i40e_pf * pf)1395 static long i40e_ptp_create_clock(struct i40e_pf *pf)
1396 {
1397 	/* no need to create a clock device if we already have one */
1398 	if (!IS_ERR_OR_NULL(pf->ptp_clock))
1399 		return 0;
1400 
1401 	strlcpy(pf->ptp_caps.name, i40e_driver_name,
1402 		sizeof(pf->ptp_caps.name) - 1);
1403 	pf->ptp_caps.owner = THIS_MODULE;
1404 	pf->ptp_caps.max_adj = 999999999;
1405 	pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
1406 	pf->ptp_caps.adjtime = i40e_ptp_adjtime;
1407 	pf->ptp_caps.gettimex64 = i40e_ptp_gettimex;
1408 	pf->ptp_caps.settime64 = i40e_ptp_settime;
1409 	if (i40e_is_ptp_pin_dev(&pf->hw)) {
1410 		int err = i40e_init_pin_config(pf);
1411 
1412 		if (err)
1413 			return err;
1414 	}
1415 
1416 	/* Attempt to register the clock before enabling the hardware. */
1417 	pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
1418 	if (IS_ERR(pf->ptp_clock))
1419 		return PTR_ERR(pf->ptp_clock);
1420 
1421 	/* clear the hwtstamp settings here during clock create, instead of
1422 	 * during regular init, so that we can maintain settings across a
1423 	 * reset or suspend.
1424 	 */
1425 	pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1426 	pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1427 
1428 	/* Set the previous "reset" time to the current Kernel clock time */
1429 	ktime_get_real_ts64(&pf->ptp_prev_hw_time);
1430 	pf->ptp_reset_start = ktime_get();
1431 
1432 	return 0;
1433 }
1434 
1435 /**
1436  * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time
1437  * @pf: Board private structure
1438  *
1439  * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should
1440  * be called at the end of preparing to reset, just before hardware reset
1441  * occurs, in order to preserve the PTP time as close as possible across
1442  * resets.
1443  */
i40e_ptp_save_hw_time(struct i40e_pf * pf)1444 void i40e_ptp_save_hw_time(struct i40e_pf *pf)
1445 {
1446 	/* don't try to access the PTP clock if it's not enabled */
1447 	if (!(pf->flags & I40E_FLAG_PTP))
1448 		return;
1449 
1450 	i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL);
1451 	/* Get a monotonic starting time for this reset */
1452 	pf->ptp_reset_start = ktime_get();
1453 }
1454 
1455 /**
1456  * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs
1457  * @pf: Board private structure
1458  *
1459  * Restore the PTP hardware clock registers. We previously cached the PTP
1460  * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible,
1461  * update this value based on the time delta since the time was saved, using
1462  * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference.
1463  *
1464  * This ensures that the hardware clock is restored to nearly what it should
1465  * have been if a reset had not occurred.
1466  */
i40e_ptp_restore_hw_time(struct i40e_pf * pf)1467 void i40e_ptp_restore_hw_time(struct i40e_pf *pf)
1468 {
1469 	ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start);
1470 
1471 	/* Update the previous HW time with the ktime delta */
1472 	timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta));
1473 
1474 	/* Restore the hardware clock registers */
1475 	i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time);
1476 }
1477 
1478 /**
1479  * i40e_ptp_init - Initialize the 1588 support after device probe or reset
1480  * @pf: Board private structure
1481  *
1482  * This function sets device up for 1588 support. The first time it is run, it
1483  * will create a PHC clock device. It does not create a clock device if one
1484  * already exists. It also reconfigures the device after a reset.
1485  *
1486  * The first time a clock is created, i40e_ptp_create_clock will set
1487  * pf->ptp_prev_hw_time to the current system time. During resets, it is
1488  * expected that this timespec will be set to the last known PTP clock time,
1489  * in order to preserve the clock time as close as possible across a reset.
1490  **/
i40e_ptp_init(struct i40e_pf * pf)1491 void i40e_ptp_init(struct i40e_pf *pf)
1492 {
1493 	struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
1494 	struct i40e_hw *hw = &pf->hw;
1495 	u32 pf_id;
1496 	long err;
1497 
1498 	/* Only one PF is assigned to control 1588 logic per port. Do not
1499 	 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
1500 	 */
1501 	pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
1502 		I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
1503 	if (hw->pf_id != pf_id) {
1504 		pf->flags &= ~I40E_FLAG_PTP;
1505 		dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
1506 			 __func__,
1507 			 netdev->name);
1508 		return;
1509 	}
1510 
1511 	mutex_init(&pf->tmreg_lock);
1512 	spin_lock_init(&pf->ptp_rx_lock);
1513 
1514 	/* ensure we have a clock device */
1515 	err = i40e_ptp_create_clock(pf);
1516 	if (err) {
1517 		pf->ptp_clock = NULL;
1518 		dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
1519 			__func__);
1520 	} else if (pf->ptp_clock) {
1521 		u32 regval;
1522 
1523 		if (pf->hw.debug_mask & I40E_DEBUG_LAN)
1524 			dev_info(&pf->pdev->dev, "PHC enabled\n");
1525 		pf->flags |= I40E_FLAG_PTP;
1526 
1527 		/* Ensure the clocks are running. */
1528 		regval = rd32(hw, I40E_PRTTSYN_CTL0);
1529 		regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
1530 		wr32(hw, I40E_PRTTSYN_CTL0, regval);
1531 		regval = rd32(hw, I40E_PRTTSYN_CTL1);
1532 		regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
1533 		wr32(hw, I40E_PRTTSYN_CTL1, regval);
1534 
1535 		/* Set the increment value per clock tick. */
1536 		i40e_ptp_set_increment(pf);
1537 
1538 		/* reset timestamping mode */
1539 		i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
1540 
1541 		/* Restore the clock time based on last known value */
1542 		i40e_ptp_restore_hw_time(pf);
1543 	}
1544 
1545 	i40e_ptp_set_1pps_signal_hw(pf);
1546 }
1547 
1548 /**
1549  * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
1550  * @pf: Board private structure
1551  *
1552  * This function handles the cleanup work required from the initialization by
1553  * clearing out the important information and unregistering the PHC.
1554  **/
i40e_ptp_stop(struct i40e_pf * pf)1555 void i40e_ptp_stop(struct i40e_pf *pf)
1556 {
1557 	struct i40e_hw *hw = &pf->hw;
1558 	u32 regval;
1559 
1560 	pf->flags &= ~I40E_FLAG_PTP;
1561 	pf->ptp_tx = false;
1562 	pf->ptp_rx = false;
1563 
1564 	if (pf->ptp_tx_skb) {
1565 		struct sk_buff *skb = pf->ptp_tx_skb;
1566 
1567 		pf->ptp_tx_skb = NULL;
1568 		clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
1569 		dev_kfree_skb_any(skb);
1570 	}
1571 
1572 	if (pf->ptp_clock) {
1573 		ptp_clock_unregister(pf->ptp_clock);
1574 		pf->ptp_clock = NULL;
1575 		dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
1576 			 pf->vsi[pf->lan_vsi]->netdev->name);
1577 	}
1578 
1579 	if (i40e_is_ptp_pin_dev(&pf->hw)) {
1580 		i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off);
1581 		i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off);
1582 		i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off);
1583 	}
1584 
1585 	regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));
1586 	regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK;
1587 	wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);
1588 
1589 	/* Disable interrupts */
1590 	regval = rd32(hw, I40E_PRTTSYN_CTL0);
1591 	regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK;
1592 	wr32(hw, I40E_PRTTSYN_CTL0, regval);
1593 
1594 	i40e_ptp_free_pins(pf);
1595 }
1596