1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #include <linux/prefetch.h>
5 #include <linux/bpf_trace.h>
6 #include <net/mpls.h>
7 #include <net/xdp.h>
8 #include "i40e.h"
9 #include "i40e_trace.h"
10 #include "i40e_prototype.h"
11 #include "i40e_txrx_common.h"
12 #include "i40e_xsk.h"
13 
14 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
15 /**
16  * i40e_fdir - Generate a Flow Director descriptor based on fdata
17  * @tx_ring: Tx ring to send buffer on
18  * @fdata: Flow director filter data
19  * @add: Indicate if we are adding a rule or deleting one
20  *
21  **/
i40e_fdir(struct i40e_ring * tx_ring,struct i40e_fdir_filter * fdata,bool add)22 static void i40e_fdir(struct i40e_ring *tx_ring,
23 		      struct i40e_fdir_filter *fdata, bool add)
24 {
25 	struct i40e_filter_program_desc *fdir_desc;
26 	struct i40e_pf *pf = tx_ring->vsi->back;
27 	u32 flex_ptype, dtype_cmd;
28 	u16 i;
29 
30 	/* grab the next descriptor */
31 	i = tx_ring->next_to_use;
32 	fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
33 
34 	i++;
35 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
36 
37 	flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
38 		     (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
39 
40 	flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
41 		      (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
42 
43 	flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
44 		      (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
45 
46 	/* Use LAN VSI Id if not programmed by user */
47 	flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
48 		      ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
49 		       I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
50 
51 	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
52 
53 	dtype_cmd |= add ?
54 		     I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
55 		     I40E_TXD_FLTR_QW1_PCMD_SHIFT :
56 		     I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
57 		     I40E_TXD_FLTR_QW1_PCMD_SHIFT;
58 
59 	dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
60 		     (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
61 
62 	dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
63 		     (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
64 
65 	if (fdata->cnt_index) {
66 		dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
67 		dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
68 			     ((u32)fdata->cnt_index <<
69 			      I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
70 	}
71 
72 	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
73 	fdir_desc->rsvd = cpu_to_le32(0);
74 	fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
75 	fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
76 }
77 
78 #define I40E_FD_CLEAN_DELAY 10
79 /**
80  * i40e_program_fdir_filter - Program a Flow Director filter
81  * @fdir_data: Packet data that will be filter parameters
82  * @raw_packet: the pre-allocated packet buffer for FDir
83  * @pf: The PF pointer
84  * @add: True for add/update, False for remove
85  **/
i40e_program_fdir_filter(struct i40e_fdir_filter * fdir_data,u8 * raw_packet,struct i40e_pf * pf,bool add)86 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
87 				    u8 *raw_packet, struct i40e_pf *pf,
88 				    bool add)
89 {
90 	struct i40e_tx_buffer *tx_buf, *first;
91 	struct i40e_tx_desc *tx_desc;
92 	struct i40e_ring *tx_ring;
93 	struct i40e_vsi *vsi;
94 	struct device *dev;
95 	dma_addr_t dma;
96 	u32 td_cmd = 0;
97 	u16 i;
98 
99 	/* find existing FDIR VSI */
100 	vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
101 	if (!vsi)
102 		return -ENOENT;
103 
104 	tx_ring = vsi->tx_rings[0];
105 	dev = tx_ring->dev;
106 
107 	/* we need two descriptors to add/del a filter and we can wait */
108 	for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
109 		if (!i)
110 			return -EAGAIN;
111 		msleep_interruptible(1);
112 	}
113 
114 	dma = dma_map_single(dev, raw_packet,
115 			     I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
116 	if (dma_mapping_error(dev, dma))
117 		goto dma_fail;
118 
119 	/* grab the next descriptor */
120 	i = tx_ring->next_to_use;
121 	first = &tx_ring->tx_bi[i];
122 	i40e_fdir(tx_ring, fdir_data, add);
123 
124 	/* Now program a dummy descriptor */
125 	i = tx_ring->next_to_use;
126 	tx_desc = I40E_TX_DESC(tx_ring, i);
127 	tx_buf = &tx_ring->tx_bi[i];
128 
129 	tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
130 
131 	memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
132 
133 	/* record length, and DMA address */
134 	dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
135 	dma_unmap_addr_set(tx_buf, dma, dma);
136 
137 	tx_desc->buffer_addr = cpu_to_le64(dma);
138 	td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
139 
140 	tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
141 	tx_buf->raw_buf = (void *)raw_packet;
142 
143 	tx_desc->cmd_type_offset_bsz =
144 		build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
145 
146 	/* Force memory writes to complete before letting h/w
147 	 * know there are new descriptors to fetch.
148 	 */
149 	wmb();
150 
151 	/* Mark the data descriptor to be watched */
152 	first->next_to_watch = tx_desc;
153 
154 	writel(tx_ring->next_to_use, tx_ring->tail);
155 	return 0;
156 
157 dma_fail:
158 	return -1;
159 }
160 
161 /**
162  * i40e_create_dummy_packet - Constructs dummy packet for HW
163  * @dummy_packet: preallocated space for dummy packet
164  * @ipv4: is layer 3 packet of version 4 or 6
165  * @l4proto: next level protocol used in data portion of l3
166  * @data: filter data
167  *
168  * Returns address of layer 4 protocol dummy packet.
169  **/
i40e_create_dummy_packet(u8 * dummy_packet,bool ipv4,u8 l4proto,struct i40e_fdir_filter * data)170 static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto,
171 				      struct i40e_fdir_filter *data)
172 {
173 	bool is_vlan = !!data->vlan_tag;
174 	struct vlan_hdr vlan;
175 	struct ipv6hdr ipv6;
176 	struct ethhdr eth;
177 	struct iphdr ip;
178 	u8 *tmp;
179 
180 	if (ipv4) {
181 		eth.h_proto = cpu_to_be16(ETH_P_IP);
182 		ip.protocol = l4proto;
183 		ip.version = 0x4;
184 		ip.ihl = 0x5;
185 
186 		ip.daddr = data->dst_ip;
187 		ip.saddr = data->src_ip;
188 	} else {
189 		eth.h_proto = cpu_to_be16(ETH_P_IPV6);
190 		ipv6.nexthdr = l4proto;
191 		ipv6.version = 0x6;
192 
193 		memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6,
194 		       sizeof(__be32) * 4);
195 		memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6,
196 		       sizeof(__be32) * 4);
197 	}
198 
199 	if (is_vlan) {
200 		vlan.h_vlan_TCI = data->vlan_tag;
201 		vlan.h_vlan_encapsulated_proto = eth.h_proto;
202 		eth.h_proto = data->vlan_etype;
203 	}
204 
205 	tmp = dummy_packet;
206 	memcpy(tmp, &eth, sizeof(eth));
207 	tmp += sizeof(eth);
208 
209 	if (is_vlan) {
210 		memcpy(tmp, &vlan, sizeof(vlan));
211 		tmp += sizeof(vlan);
212 	}
213 
214 	if (ipv4) {
215 		memcpy(tmp, &ip, sizeof(ip));
216 		tmp += sizeof(ip);
217 	} else {
218 		memcpy(tmp, &ipv6, sizeof(ipv6));
219 		tmp += sizeof(ipv6);
220 	}
221 
222 	return tmp;
223 }
224 
225 /**
226  * i40e_create_dummy_udp_packet - helper function to create UDP packet
227  * @raw_packet: preallocated space for dummy packet
228  * @ipv4: is layer 3 packet of version 4 or 6
229  * @l4proto: next level protocol used in data portion of l3
230  * @data: filter data
231  *
232  * Helper function to populate udp fields.
233  **/
i40e_create_dummy_udp_packet(u8 * raw_packet,bool ipv4,u8 l4proto,struct i40e_fdir_filter * data)234 static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
235 					 struct i40e_fdir_filter *data)
236 {
237 	struct udphdr *udp;
238 	u8 *tmp;
239 
240 	tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data);
241 	udp = (struct udphdr *)(tmp);
242 	udp->dest = data->dst_port;
243 	udp->source = data->src_port;
244 }
245 
246 /**
247  * i40e_create_dummy_tcp_packet - helper function to create TCP packet
248  * @raw_packet: preallocated space for dummy packet
249  * @ipv4: is layer 3 packet of version 4 or 6
250  * @l4proto: next level protocol used in data portion of l3
251  * @data: filter data
252  *
253  * Helper function to populate tcp fields.
254  **/
i40e_create_dummy_tcp_packet(u8 * raw_packet,bool ipv4,u8 l4proto,struct i40e_fdir_filter * data)255 static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
256 					 struct i40e_fdir_filter *data)
257 {
258 	struct tcphdr *tcp;
259 	u8 *tmp;
260 	/* Dummy tcp packet */
261 	static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 		0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0};
263 
264 	tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data);
265 
266 	tcp = (struct tcphdr *)tmp;
267 	memcpy(tcp, tcp_packet, sizeof(tcp_packet));
268 	tcp->dest = data->dst_port;
269 	tcp->source = data->src_port;
270 }
271 
272 /**
273  * i40e_create_dummy_sctp_packet - helper function to create SCTP packet
274  * @raw_packet: preallocated space for dummy packet
275  * @ipv4: is layer 3 packet of version 4 or 6
276  * @l4proto: next level protocol used in data portion of l3
277  * @data: filter data
278  *
279  * Helper function to populate sctp fields.
280  **/
i40e_create_dummy_sctp_packet(u8 * raw_packet,bool ipv4,u8 l4proto,struct i40e_fdir_filter * data)281 static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4,
282 					  u8 l4proto,
283 					  struct i40e_fdir_filter *data)
284 {
285 	struct sctphdr *sctp;
286 	u8 *tmp;
287 
288 	tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data);
289 
290 	sctp = (struct sctphdr *)tmp;
291 	sctp->dest = data->dst_port;
292 	sctp->source = data->src_port;
293 }
294 
295 /**
296  * i40e_prepare_fdir_filter - Prepare and program fdir filter
297  * @pf: physical function to attach filter to
298  * @fd_data: filter data
299  * @add: add or delete filter
300  * @packet_addr: address of dummy packet, used in filtering
301  * @payload_offset: offset from dummy packet address to user defined data
302  * @pctype: Packet type for which filter is used
303  *
304  * Helper function to offset data of dummy packet, program it and
305  * handle errors.
306  **/
i40e_prepare_fdir_filter(struct i40e_pf * pf,struct i40e_fdir_filter * fd_data,bool add,char * packet_addr,int payload_offset,u8 pctype)307 static int i40e_prepare_fdir_filter(struct i40e_pf *pf,
308 				    struct i40e_fdir_filter *fd_data,
309 				    bool add, char *packet_addr,
310 				    int payload_offset, u8 pctype)
311 {
312 	int ret;
313 
314 	if (fd_data->flex_filter) {
315 		u8 *payload;
316 		__be16 pattern = fd_data->flex_word;
317 		u16 off = fd_data->flex_offset;
318 
319 		payload = packet_addr + payload_offset;
320 
321 		/* If user provided vlan, offset payload by vlan header length */
322 		if (!!fd_data->vlan_tag)
323 			payload += VLAN_HLEN;
324 
325 		*((__force __be16 *)(payload + off)) = pattern;
326 	}
327 
328 	fd_data->pctype = pctype;
329 	ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add);
330 	if (ret) {
331 		dev_info(&pf->pdev->dev,
332 			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
333 			 fd_data->pctype, fd_data->fd_id, ret);
334 		/* Free the packet buffer since it wasn't added to the ring */
335 		return -EOPNOTSUPP;
336 	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
337 		if (add)
338 			dev_info(&pf->pdev->dev,
339 				 "Filter OK for PCTYPE %d loc = %d\n",
340 				 fd_data->pctype, fd_data->fd_id);
341 		else
342 			dev_info(&pf->pdev->dev,
343 				 "Filter deleted for PCTYPE %d loc = %d\n",
344 				 fd_data->pctype, fd_data->fd_id);
345 	}
346 
347 	return ret;
348 }
349 
350 /**
351  * i40e_change_filter_num - Prepare and program fdir filter
352  * @ipv4: is layer 3 packet of version 4 or 6
353  * @add: add or delete filter
354  * @ipv4_filter_num: field to update
355  * @ipv6_filter_num: field to update
356  *
357  * Update filter number field for pf.
358  **/
i40e_change_filter_num(bool ipv4,bool add,u16 * ipv4_filter_num,u16 * ipv6_filter_num)359 static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num,
360 				   u16 *ipv6_filter_num)
361 {
362 	if (add) {
363 		if (ipv4)
364 			(*ipv4_filter_num)++;
365 		else
366 			(*ipv6_filter_num)++;
367 	} else {
368 		if (ipv4)
369 			(*ipv4_filter_num)--;
370 		else
371 			(*ipv6_filter_num)--;
372 	}
373 }
374 
375 #define IP_HEADER_OFFSET		14
376 #define I40E_UDPIP_DUMMY_PACKET_LEN	42
377 #define I40E_UDPIP6_DUMMY_PACKET_LEN	62
378 /**
379  * i40e_add_del_fdir_udp - Add/Remove UDP filters
380  * @vsi: pointer to the targeted VSI
381  * @fd_data: the flow director data required for the FDir descriptor
382  * @add: true adds a filter, false removes it
383  * @ipv4: true is v4, false is v6
384  *
385  * Returns 0 if the filters were successfully added or removed
386  **/
i40e_add_del_fdir_udp(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add,bool ipv4)387 static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi,
388 				 struct i40e_fdir_filter *fd_data,
389 				 bool add,
390 				 bool ipv4)
391 {
392 	struct i40e_pf *pf = vsi->back;
393 	u8 *raw_packet;
394 	int ret;
395 
396 	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
397 	if (!raw_packet)
398 		return -ENOMEM;
399 
400 	i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data);
401 
402 	if (ipv4)
403 		ret = i40e_prepare_fdir_filter
404 			(pf, fd_data, add, raw_packet,
405 			 I40E_UDPIP_DUMMY_PACKET_LEN,
406 			 I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
407 	else
408 		ret = i40e_prepare_fdir_filter
409 			(pf, fd_data, add, raw_packet,
410 			 I40E_UDPIP6_DUMMY_PACKET_LEN,
411 			 I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
412 
413 	if (ret) {
414 		kfree(raw_packet);
415 		return ret;
416 	}
417 
418 	i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt,
419 			       &pf->fd_udp6_filter_cnt);
420 
421 	return 0;
422 }
423 
424 #define I40E_TCPIP_DUMMY_PACKET_LEN	54
425 #define I40E_TCPIP6_DUMMY_PACKET_LEN	74
426 /**
427  * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters
428  * @vsi: pointer to the targeted VSI
429  * @fd_data: the flow director data required for the FDir descriptor
430  * @add: true adds a filter, false removes it
431  * @ipv4: true is v4, false is v6
432  *
433  * Returns 0 if the filters were successfully added or removed
434  **/
i40e_add_del_fdir_tcp(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add,bool ipv4)435 static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi,
436 				 struct i40e_fdir_filter *fd_data,
437 				 bool add,
438 				 bool ipv4)
439 {
440 	struct i40e_pf *pf = vsi->back;
441 	u8 *raw_packet;
442 	int ret;
443 
444 	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
445 	if (!raw_packet)
446 		return -ENOMEM;
447 
448 	i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data);
449 	if (ipv4)
450 		ret = i40e_prepare_fdir_filter
451 			(pf, fd_data, add, raw_packet,
452 			 I40E_TCPIP_DUMMY_PACKET_LEN,
453 			 I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
454 	else
455 		ret = i40e_prepare_fdir_filter
456 			(pf, fd_data, add, raw_packet,
457 			 I40E_TCPIP6_DUMMY_PACKET_LEN,
458 			 I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
459 
460 	if (ret) {
461 		kfree(raw_packet);
462 		return ret;
463 	}
464 
465 	i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt,
466 			       &pf->fd_tcp6_filter_cnt);
467 
468 	if (add) {
469 		if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
470 		    I40E_DEBUG_FD & pf->hw.debug_mask)
471 			dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
472 		set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
473 	}
474 	return 0;
475 }
476 
477 #define I40E_SCTPIP_DUMMY_PACKET_LEN	46
478 #define I40E_SCTPIP6_DUMMY_PACKET_LEN	66
479 /**
480  * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for
481  * a specific flow spec
482  * @vsi: pointer to the targeted VSI
483  * @fd_data: the flow director data required for the FDir descriptor
484  * @add: true adds a filter, false removes it
485  * @ipv4: true is v4, false is v6
486  *
487  * Returns 0 if the filters were successfully added or removed
488  **/
i40e_add_del_fdir_sctp(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add,bool ipv4)489 static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi,
490 				  struct i40e_fdir_filter *fd_data,
491 				  bool add,
492 				  bool ipv4)
493 {
494 	struct i40e_pf *pf = vsi->back;
495 	u8 *raw_packet;
496 	int ret;
497 
498 	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
499 	if (!raw_packet)
500 		return -ENOMEM;
501 
502 	i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data);
503 
504 	if (ipv4)
505 		ret = i40e_prepare_fdir_filter
506 			(pf, fd_data, add, raw_packet,
507 			 I40E_SCTPIP_DUMMY_PACKET_LEN,
508 			 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
509 	else
510 		ret = i40e_prepare_fdir_filter
511 			(pf, fd_data, add, raw_packet,
512 			 I40E_SCTPIP6_DUMMY_PACKET_LEN,
513 			 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
514 
515 	if (ret) {
516 		kfree(raw_packet);
517 		return ret;
518 	}
519 
520 	i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt,
521 			       &pf->fd_sctp6_filter_cnt);
522 
523 	return 0;
524 }
525 
526 #define I40E_IP_DUMMY_PACKET_LEN	34
527 #define I40E_IP6_DUMMY_PACKET_LEN	54
528 /**
529  * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for
530  * a specific flow spec
531  * @vsi: pointer to the targeted VSI
532  * @fd_data: the flow director data required for the FDir descriptor
533  * @add: true adds a filter, false removes it
534  * @ipv4: true is v4, false is v6
535  *
536  * Returns 0 if the filters were successfully added or removed
537  **/
i40e_add_del_fdir_ip(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add,bool ipv4)538 static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi,
539 				struct i40e_fdir_filter *fd_data,
540 				bool add,
541 				bool ipv4)
542 {
543 	struct i40e_pf *pf = vsi->back;
544 	int payload_offset;
545 	u8 *raw_packet;
546 	int iter_start;
547 	int iter_end;
548 	int ret;
549 	int i;
550 
551 	if (ipv4) {
552 		iter_start = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
553 		iter_end = I40E_FILTER_PCTYPE_FRAG_IPV4;
554 	} else {
555 		iter_start = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
556 		iter_end = I40E_FILTER_PCTYPE_FRAG_IPV6;
557 	}
558 
559 	for (i = iter_start; i <= iter_end; i++) {
560 		raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
561 		if (!raw_packet)
562 			return -ENOMEM;
563 
564 		/* IPv6 no header option differs from IPv4 */
565 		(void)i40e_create_dummy_packet
566 			(raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE,
567 			 fd_data);
568 
569 		payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN :
570 			I40E_IP6_DUMMY_PACKET_LEN;
571 		ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet,
572 					       payload_offset, i);
573 		if (ret)
574 			goto err;
575 	}
576 
577 	i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt,
578 			       &pf->fd_ip6_filter_cnt);
579 
580 	return 0;
581 err:
582 	kfree(raw_packet);
583 	return ret;
584 }
585 
586 /**
587  * i40e_add_del_fdir - Build raw packets to add/del fdir filter
588  * @vsi: pointer to the targeted VSI
589  * @input: filter to add or delete
590  * @add: true adds a filter, false removes it
591  *
592  **/
i40e_add_del_fdir(struct i40e_vsi * vsi,struct i40e_fdir_filter * input,bool add)593 int i40e_add_del_fdir(struct i40e_vsi *vsi,
594 		      struct i40e_fdir_filter *input, bool add)
595 {
596 	enum ip_ver { ipv6 = 0, ipv4 = 1 };
597 	struct i40e_pf *pf = vsi->back;
598 	int ret;
599 
600 	switch (input->flow_type & ~FLOW_EXT) {
601 	case TCP_V4_FLOW:
602 		ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
603 		break;
604 	case UDP_V4_FLOW:
605 		ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
606 		break;
607 	case SCTP_V4_FLOW:
608 		ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
609 		break;
610 	case TCP_V6_FLOW:
611 		ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
612 		break;
613 	case UDP_V6_FLOW:
614 		ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
615 		break;
616 	case SCTP_V6_FLOW:
617 		ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
618 		break;
619 	case IP_USER_FLOW:
620 		switch (input->ipl4_proto) {
621 		case IPPROTO_TCP:
622 			ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
623 			break;
624 		case IPPROTO_UDP:
625 			ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
626 			break;
627 		case IPPROTO_SCTP:
628 			ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
629 			break;
630 		case IPPROTO_IP:
631 			ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4);
632 			break;
633 		default:
634 			/* We cannot support masking based on protocol */
635 			dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
636 				 input->ipl4_proto);
637 			return -EINVAL;
638 		}
639 		break;
640 	case IPV6_USER_FLOW:
641 		switch (input->ipl4_proto) {
642 		case IPPROTO_TCP:
643 			ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
644 			break;
645 		case IPPROTO_UDP:
646 			ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
647 			break;
648 		case IPPROTO_SCTP:
649 			ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
650 			break;
651 		case IPPROTO_IP:
652 			ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6);
653 			break;
654 		default:
655 			/* We cannot support masking based on protocol */
656 			dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n",
657 				 input->ipl4_proto);
658 			return -EINVAL;
659 		}
660 		break;
661 	default:
662 		dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
663 			 input->flow_type);
664 		return -EINVAL;
665 	}
666 
667 	/* The buffer allocated here will be normally be freed by
668 	 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
669 	 * completion. In the event of an error adding the buffer to the FDIR
670 	 * ring, it will immediately be freed. It may also be freed by
671 	 * i40e_clean_tx_ring() when closing the VSI.
672 	 */
673 	return ret;
674 }
675 
676 /**
677  * i40e_fd_handle_status - check the Programming Status for FD
678  * @rx_ring: the Rx ring for this descriptor
679  * @qword0_raw: qword0
680  * @qword1: qword1 after le_to_cpu
681  * @prog_id: the id originally used for programming
682  *
683  * This is used to verify if the FD programming or invalidation
684  * requested by SW to the HW is successful or not and take actions accordingly.
685  **/
i40e_fd_handle_status(struct i40e_ring * rx_ring,u64 qword0_raw,u64 qword1,u8 prog_id)686 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
687 				  u64 qword1, u8 prog_id)
688 {
689 	struct i40e_pf *pf = rx_ring->vsi->back;
690 	struct pci_dev *pdev = pf->pdev;
691 	struct i40e_16b_rx_wb_qw0 *qw0;
692 	u32 fcnt_prog, fcnt_avail;
693 	u32 error;
694 
695 	qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw;
696 	error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
697 		I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
698 
699 	if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
700 		pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
701 		if (qw0->hi_dword.fd_id != 0 ||
702 		    (I40E_DEBUG_FD & pf->hw.debug_mask))
703 			dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
704 				 pf->fd_inv);
705 
706 		/* Check if the programming error is for ATR.
707 		 * If so, auto disable ATR and set a state for
708 		 * flush in progress. Next time we come here if flush is in
709 		 * progress do nothing, once flush is complete the state will
710 		 * be cleared.
711 		 */
712 		if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
713 			return;
714 
715 		pf->fd_add_err++;
716 		/* store the current atr filter count */
717 		pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
718 
719 		if (qw0->hi_dword.fd_id == 0 &&
720 		    test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
721 			/* These set_bit() calls aren't atomic with the
722 			 * test_bit() here, but worse case we potentially
723 			 * disable ATR and queue a flush right after SB
724 			 * support is re-enabled. That shouldn't cause an
725 			 * issue in practice
726 			 */
727 			set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
728 			set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
729 		}
730 
731 		/* filter programming failed most likely due to table full */
732 		fcnt_prog = i40e_get_global_fd_count(pf);
733 		fcnt_avail = pf->fdir_pf_filter_count;
734 		/* If ATR is running fcnt_prog can quickly change,
735 		 * if we are very close to full, it makes sense to disable
736 		 * FD ATR/SB and then re-enable it when there is room.
737 		 */
738 		if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
739 			if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
740 			    !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
741 					      pf->state))
742 				if (I40E_DEBUG_FD & pf->hw.debug_mask)
743 					dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
744 		}
745 	} else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
746 		if (I40E_DEBUG_FD & pf->hw.debug_mask)
747 			dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
748 				 qw0->hi_dword.fd_id);
749 	}
750 }
751 
752 /**
753  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
754  * @ring:      the ring that owns the buffer
755  * @tx_buffer: the buffer to free
756  **/
i40e_unmap_and_free_tx_resource(struct i40e_ring * ring,struct i40e_tx_buffer * tx_buffer)757 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
758 					    struct i40e_tx_buffer *tx_buffer)
759 {
760 	if (tx_buffer->skb) {
761 		if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
762 			kfree(tx_buffer->raw_buf);
763 		else if (ring_is_xdp(ring))
764 			xdp_return_frame(tx_buffer->xdpf);
765 		else
766 			dev_kfree_skb_any(tx_buffer->skb);
767 		if (dma_unmap_len(tx_buffer, len))
768 			dma_unmap_single(ring->dev,
769 					 dma_unmap_addr(tx_buffer, dma),
770 					 dma_unmap_len(tx_buffer, len),
771 					 DMA_TO_DEVICE);
772 	} else if (dma_unmap_len(tx_buffer, len)) {
773 		dma_unmap_page(ring->dev,
774 			       dma_unmap_addr(tx_buffer, dma),
775 			       dma_unmap_len(tx_buffer, len),
776 			       DMA_TO_DEVICE);
777 	}
778 
779 	tx_buffer->next_to_watch = NULL;
780 	tx_buffer->skb = NULL;
781 	dma_unmap_len_set(tx_buffer, len, 0);
782 	/* tx_buffer must be completely set up in the transmit path */
783 }
784 
785 /**
786  * i40e_clean_tx_ring - Free any empty Tx buffers
787  * @tx_ring: ring to be cleaned
788  **/
i40e_clean_tx_ring(struct i40e_ring * tx_ring)789 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
790 {
791 	unsigned long bi_size;
792 	u16 i;
793 
794 	if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) {
795 		i40e_xsk_clean_tx_ring(tx_ring);
796 	} else {
797 		/* ring already cleared, nothing to do */
798 		if (!tx_ring->tx_bi)
799 			return;
800 
801 		/* Free all the Tx ring sk_buffs */
802 		for (i = 0; i < tx_ring->count; i++)
803 			i40e_unmap_and_free_tx_resource(tx_ring,
804 							&tx_ring->tx_bi[i]);
805 	}
806 
807 	bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
808 	memset(tx_ring->tx_bi, 0, bi_size);
809 
810 	/* Zero out the descriptor ring */
811 	memset(tx_ring->desc, 0, tx_ring->size);
812 
813 	tx_ring->next_to_use = 0;
814 	tx_ring->next_to_clean = 0;
815 
816 	if (!tx_ring->netdev)
817 		return;
818 
819 	/* cleanup Tx queue statistics */
820 	netdev_tx_reset_queue(txring_txq(tx_ring));
821 }
822 
823 /**
824  * i40e_free_tx_resources - Free Tx resources per queue
825  * @tx_ring: Tx descriptor ring for a specific queue
826  *
827  * Free all transmit software resources
828  **/
i40e_free_tx_resources(struct i40e_ring * tx_ring)829 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
830 {
831 	i40e_clean_tx_ring(tx_ring);
832 	kfree(tx_ring->tx_bi);
833 	tx_ring->tx_bi = NULL;
834 
835 	if (tx_ring->desc) {
836 		dma_free_coherent(tx_ring->dev, tx_ring->size,
837 				  tx_ring->desc, tx_ring->dma);
838 		tx_ring->desc = NULL;
839 	}
840 }
841 
842 /**
843  * i40e_get_tx_pending - how many tx descriptors not processed
844  * @ring: the ring of descriptors
845  * @in_sw: use SW variables
846  *
847  * Since there is no access to the ring head register
848  * in XL710, we need to use our local copies
849  **/
i40e_get_tx_pending(struct i40e_ring * ring,bool in_sw)850 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
851 {
852 	u32 head, tail;
853 
854 	if (!in_sw) {
855 		head = i40e_get_head(ring);
856 		tail = readl(ring->tail);
857 	} else {
858 		head = ring->next_to_clean;
859 		tail = ring->next_to_use;
860 	}
861 
862 	if (head != tail)
863 		return (head < tail) ?
864 			tail - head : (tail + ring->count - head);
865 
866 	return 0;
867 }
868 
869 /**
870  * i40e_detect_recover_hung - Function to detect and recover hung_queues
871  * @vsi:  pointer to vsi struct with tx queues
872  *
873  * VSI has netdev and netdev has TX queues. This function is to check each of
874  * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
875  **/
i40e_detect_recover_hung(struct i40e_vsi * vsi)876 void i40e_detect_recover_hung(struct i40e_vsi *vsi)
877 {
878 	struct i40e_ring *tx_ring = NULL;
879 	struct net_device *netdev;
880 	unsigned int i;
881 	int packets;
882 
883 	if (!vsi)
884 		return;
885 
886 	if (test_bit(__I40E_VSI_DOWN, vsi->state))
887 		return;
888 
889 	netdev = vsi->netdev;
890 	if (!netdev)
891 		return;
892 
893 	if (!netif_carrier_ok(netdev))
894 		return;
895 
896 	for (i = 0; i < vsi->num_queue_pairs; i++) {
897 		tx_ring = vsi->tx_rings[i];
898 		if (tx_ring && tx_ring->desc) {
899 			/* If packet counter has not changed the queue is
900 			 * likely stalled, so force an interrupt for this
901 			 * queue.
902 			 *
903 			 * prev_pkt_ctr would be negative if there was no
904 			 * pending work.
905 			 */
906 			packets = tx_ring->stats.packets & INT_MAX;
907 			if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
908 				i40e_force_wb(vsi, tx_ring->q_vector);
909 				continue;
910 			}
911 
912 			/* Memory barrier between read of packet count and call
913 			 * to i40e_get_tx_pending()
914 			 */
915 			smp_rmb();
916 			tx_ring->tx_stats.prev_pkt_ctr =
917 			    i40e_get_tx_pending(tx_ring, true) ? packets : -1;
918 		}
919 	}
920 }
921 
922 /**
923  * i40e_clean_tx_irq - Reclaim resources after transmit completes
924  * @vsi: the VSI we care about
925  * @tx_ring: Tx ring to clean
926  * @napi_budget: Used to determine if we are in netpoll
927  *
928  * Returns true if there's any budget left (e.g. the clean is finished)
929  **/
i40e_clean_tx_irq(struct i40e_vsi * vsi,struct i40e_ring * tx_ring,int napi_budget)930 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
931 			      struct i40e_ring *tx_ring, int napi_budget)
932 {
933 	int i = tx_ring->next_to_clean;
934 	struct i40e_tx_buffer *tx_buf;
935 	struct i40e_tx_desc *tx_head;
936 	struct i40e_tx_desc *tx_desc;
937 	unsigned int total_bytes = 0, total_packets = 0;
938 	unsigned int budget = vsi->work_limit;
939 
940 	tx_buf = &tx_ring->tx_bi[i];
941 	tx_desc = I40E_TX_DESC(tx_ring, i);
942 	i -= tx_ring->count;
943 
944 	tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
945 
946 	do {
947 		struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
948 
949 		/* if next_to_watch is not set then there is no work pending */
950 		if (!eop_desc)
951 			break;
952 
953 		/* prevent any other reads prior to eop_desc */
954 		smp_rmb();
955 
956 		i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
957 		/* we have caught up to head, no work left to do */
958 		if (tx_head == tx_desc)
959 			break;
960 
961 		/* clear next_to_watch to prevent false hangs */
962 		tx_buf->next_to_watch = NULL;
963 
964 		/* update the statistics for this packet */
965 		total_bytes += tx_buf->bytecount;
966 		total_packets += tx_buf->gso_segs;
967 
968 		/* free the skb/XDP data */
969 		if (ring_is_xdp(tx_ring))
970 			xdp_return_frame(tx_buf->xdpf);
971 		else
972 			napi_consume_skb(tx_buf->skb, napi_budget);
973 
974 		/* unmap skb header data */
975 		dma_unmap_single(tx_ring->dev,
976 				 dma_unmap_addr(tx_buf, dma),
977 				 dma_unmap_len(tx_buf, len),
978 				 DMA_TO_DEVICE);
979 
980 		/* clear tx_buffer data */
981 		tx_buf->skb = NULL;
982 		dma_unmap_len_set(tx_buf, len, 0);
983 
984 		/* unmap remaining buffers */
985 		while (tx_desc != eop_desc) {
986 			i40e_trace(clean_tx_irq_unmap,
987 				   tx_ring, tx_desc, tx_buf);
988 
989 			tx_buf++;
990 			tx_desc++;
991 			i++;
992 			if (unlikely(!i)) {
993 				i -= tx_ring->count;
994 				tx_buf = tx_ring->tx_bi;
995 				tx_desc = I40E_TX_DESC(tx_ring, 0);
996 			}
997 
998 			/* unmap any remaining paged data */
999 			if (dma_unmap_len(tx_buf, len)) {
1000 				dma_unmap_page(tx_ring->dev,
1001 					       dma_unmap_addr(tx_buf, dma),
1002 					       dma_unmap_len(tx_buf, len),
1003 					       DMA_TO_DEVICE);
1004 				dma_unmap_len_set(tx_buf, len, 0);
1005 			}
1006 		}
1007 
1008 		/* move us one more past the eop_desc for start of next pkt */
1009 		tx_buf++;
1010 		tx_desc++;
1011 		i++;
1012 		if (unlikely(!i)) {
1013 			i -= tx_ring->count;
1014 			tx_buf = tx_ring->tx_bi;
1015 			tx_desc = I40E_TX_DESC(tx_ring, 0);
1016 		}
1017 
1018 		prefetch(tx_desc);
1019 
1020 		/* update budget accounting */
1021 		budget--;
1022 	} while (likely(budget));
1023 
1024 	i += tx_ring->count;
1025 	tx_ring->next_to_clean = i;
1026 	i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
1027 	i40e_arm_wb(tx_ring, vsi, budget);
1028 
1029 	if (ring_is_xdp(tx_ring))
1030 		return !!budget;
1031 
1032 	/* notify netdev of completed buffers */
1033 	netdev_tx_completed_queue(txring_txq(tx_ring),
1034 				  total_packets, total_bytes);
1035 
1036 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
1037 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1038 		     (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
1039 		/* Make sure that anybody stopping the queue after this
1040 		 * sees the new next_to_clean.
1041 		 */
1042 		smp_mb();
1043 		if (__netif_subqueue_stopped(tx_ring->netdev,
1044 					     tx_ring->queue_index) &&
1045 		   !test_bit(__I40E_VSI_DOWN, vsi->state)) {
1046 			netif_wake_subqueue(tx_ring->netdev,
1047 					    tx_ring->queue_index);
1048 			++tx_ring->tx_stats.restart_queue;
1049 		}
1050 	}
1051 
1052 	return !!budget;
1053 }
1054 
1055 /**
1056  * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
1057  * @vsi: the VSI we care about
1058  * @q_vector: the vector on which to enable writeback
1059  *
1060  **/
i40e_enable_wb_on_itr(struct i40e_vsi * vsi,struct i40e_q_vector * q_vector)1061 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
1062 				  struct i40e_q_vector *q_vector)
1063 {
1064 	u16 flags = q_vector->tx.ring[0].flags;
1065 	u32 val;
1066 
1067 	if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
1068 		return;
1069 
1070 	if (q_vector->arm_wb_state)
1071 		return;
1072 
1073 	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1074 		val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
1075 		      I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
1076 
1077 		wr32(&vsi->back->hw,
1078 		     I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
1079 		     val);
1080 	} else {
1081 		val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
1082 		      I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
1083 
1084 		wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1085 	}
1086 	q_vector->arm_wb_state = true;
1087 }
1088 
1089 /**
1090  * i40e_force_wb - Issue SW Interrupt so HW does a wb
1091  * @vsi: the VSI we care about
1092  * @q_vector: the vector  on which to force writeback
1093  *
1094  **/
i40e_force_wb(struct i40e_vsi * vsi,struct i40e_q_vector * q_vector)1095 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
1096 {
1097 	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1098 		u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1099 			  I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
1100 			  I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
1101 			  I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
1102 			  /* allow 00 to be written to the index */
1103 
1104 		wr32(&vsi->back->hw,
1105 		     I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
1106 	} else {
1107 		u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
1108 			  I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
1109 			  I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
1110 			  I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
1111 			/* allow 00 to be written to the index */
1112 
1113 		wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1114 	}
1115 }
1116 
i40e_container_is_rx(struct i40e_q_vector * q_vector,struct i40e_ring_container * rc)1117 static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
1118 					struct i40e_ring_container *rc)
1119 {
1120 	return &q_vector->rx == rc;
1121 }
1122 
i40e_itr_divisor(struct i40e_q_vector * q_vector)1123 static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
1124 {
1125 	unsigned int divisor;
1126 
1127 	switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
1128 	case I40E_LINK_SPEED_40GB:
1129 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
1130 		break;
1131 	case I40E_LINK_SPEED_25GB:
1132 	case I40E_LINK_SPEED_20GB:
1133 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
1134 		break;
1135 	default:
1136 	case I40E_LINK_SPEED_10GB:
1137 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
1138 		break;
1139 	case I40E_LINK_SPEED_1GB:
1140 	case I40E_LINK_SPEED_100MB:
1141 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
1142 		break;
1143 	}
1144 
1145 	return divisor;
1146 }
1147 
1148 /**
1149  * i40e_update_itr - update the dynamic ITR value based on statistics
1150  * @q_vector: structure containing interrupt and ring information
1151  * @rc: structure containing ring performance data
1152  *
1153  * Stores a new ITR value based on packets and byte
1154  * counts during the last interrupt.  The advantage of per interrupt
1155  * computation is faster updates and more accurate ITR for the current
1156  * traffic pattern.  Constants in this function were computed
1157  * based on theoretical maximum wire speed and thresholds were set based
1158  * on testing data as well as attempting to minimize response time
1159  * while increasing bulk throughput.
1160  **/
i40e_update_itr(struct i40e_q_vector * q_vector,struct i40e_ring_container * rc)1161 static void i40e_update_itr(struct i40e_q_vector *q_vector,
1162 			    struct i40e_ring_container *rc)
1163 {
1164 	unsigned int avg_wire_size, packets, bytes, itr;
1165 	unsigned long next_update = jiffies;
1166 
1167 	/* If we don't have any rings just leave ourselves set for maximum
1168 	 * possible latency so we take ourselves out of the equation.
1169 	 */
1170 	if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1171 		return;
1172 
1173 	/* For Rx we want to push the delay up and default to low latency.
1174 	 * for Tx we want to pull the delay down and default to high latency.
1175 	 */
1176 	itr = i40e_container_is_rx(q_vector, rc) ?
1177 	      I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1178 	      I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1179 
1180 	/* If we didn't update within up to 1 - 2 jiffies we can assume
1181 	 * that either packets are coming in so slow there hasn't been
1182 	 * any work, or that there is so much work that NAPI is dealing
1183 	 * with interrupt moderation and we don't need to do anything.
1184 	 */
1185 	if (time_after(next_update, rc->next_update))
1186 		goto clear_counts;
1187 
1188 	/* If itr_countdown is set it means we programmed an ITR within
1189 	 * the last 4 interrupt cycles. This has a side effect of us
1190 	 * potentially firing an early interrupt. In order to work around
1191 	 * this we need to throw out any data received for a few
1192 	 * interrupts following the update.
1193 	 */
1194 	if (q_vector->itr_countdown) {
1195 		itr = rc->target_itr;
1196 		goto clear_counts;
1197 	}
1198 
1199 	packets = rc->total_packets;
1200 	bytes = rc->total_bytes;
1201 
1202 	if (i40e_container_is_rx(q_vector, rc)) {
1203 		/* If Rx there are 1 to 4 packets and bytes are less than
1204 		 * 9000 assume insufficient data to use bulk rate limiting
1205 		 * approach unless Tx is already in bulk rate limiting. We
1206 		 * are likely latency driven.
1207 		 */
1208 		if (packets && packets < 4 && bytes < 9000 &&
1209 		    (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1210 			itr = I40E_ITR_ADAPTIVE_LATENCY;
1211 			goto adjust_by_size;
1212 		}
1213 	} else if (packets < 4) {
1214 		/* If we have Tx and Rx ITR maxed and Tx ITR is running in
1215 		 * bulk mode and we are receiving 4 or fewer packets just
1216 		 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1217 		 * that the Rx can relax.
1218 		 */
1219 		if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1220 		    (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1221 		     I40E_ITR_ADAPTIVE_MAX_USECS)
1222 			goto clear_counts;
1223 	} else if (packets > 32) {
1224 		/* If we have processed over 32 packets in a single interrupt
1225 		 * for Tx assume we need to switch over to "bulk" mode.
1226 		 */
1227 		rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1228 	}
1229 
1230 	/* We have no packets to actually measure against. This means
1231 	 * either one of the other queues on this vector is active or
1232 	 * we are a Tx queue doing TSO with too high of an interrupt rate.
1233 	 *
1234 	 * Between 4 and 56 we can assume that our current interrupt delay
1235 	 * is only slightly too low. As such we should increase it by a small
1236 	 * fixed amount.
1237 	 */
1238 	if (packets < 56) {
1239 		itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1240 		if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1241 			itr &= I40E_ITR_ADAPTIVE_LATENCY;
1242 			itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1243 		}
1244 		goto clear_counts;
1245 	}
1246 
1247 	if (packets <= 256) {
1248 		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1249 		itr &= I40E_ITR_MASK;
1250 
1251 		/* Between 56 and 112 is our "goldilocks" zone where we are
1252 		 * working out "just right". Just report that our current
1253 		 * ITR is good for us.
1254 		 */
1255 		if (packets <= 112)
1256 			goto clear_counts;
1257 
1258 		/* If packet count is 128 or greater we are likely looking
1259 		 * at a slight overrun of the delay we want. Try halving
1260 		 * our delay to see if that will cut the number of packets
1261 		 * in half per interrupt.
1262 		 */
1263 		itr /= 2;
1264 		itr &= I40E_ITR_MASK;
1265 		if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1266 			itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1267 
1268 		goto clear_counts;
1269 	}
1270 
1271 	/* The paths below assume we are dealing with a bulk ITR since
1272 	 * number of packets is greater than 256. We are just going to have
1273 	 * to compute a value and try to bring the count under control,
1274 	 * though for smaller packet sizes there isn't much we can do as
1275 	 * NAPI polling will likely be kicking in sooner rather than later.
1276 	 */
1277 	itr = I40E_ITR_ADAPTIVE_BULK;
1278 
1279 adjust_by_size:
1280 	/* If packet counts are 256 or greater we can assume we have a gross
1281 	 * overestimation of what the rate should be. Instead of trying to fine
1282 	 * tune it just use the formula below to try and dial in an exact value
1283 	 * give the current packet size of the frame.
1284 	 */
1285 	avg_wire_size = bytes / packets;
1286 
1287 	/* The following is a crude approximation of:
1288 	 *  wmem_default / (size + overhead) = desired_pkts_per_int
1289 	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1290 	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1291 	 *
1292 	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1293 	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1294 	 * formula down to
1295 	 *
1296 	 *  (170 * (size + 24)) / (size + 640) = ITR
1297 	 *
1298 	 * We first do some math on the packet size and then finally bitshift
1299 	 * by 8 after rounding up. We also have to account for PCIe link speed
1300 	 * difference as ITR scales based on this.
1301 	 */
1302 	if (avg_wire_size <= 60) {
1303 		/* Start at 250k ints/sec */
1304 		avg_wire_size = 4096;
1305 	} else if (avg_wire_size <= 380) {
1306 		/* 250K ints/sec to 60K ints/sec */
1307 		avg_wire_size *= 40;
1308 		avg_wire_size += 1696;
1309 	} else if (avg_wire_size <= 1084) {
1310 		/* 60K ints/sec to 36K ints/sec */
1311 		avg_wire_size *= 15;
1312 		avg_wire_size += 11452;
1313 	} else if (avg_wire_size <= 1980) {
1314 		/* 36K ints/sec to 30K ints/sec */
1315 		avg_wire_size *= 5;
1316 		avg_wire_size += 22420;
1317 	} else {
1318 		/* plateau at a limit of 30K ints/sec */
1319 		avg_wire_size = 32256;
1320 	}
1321 
1322 	/* If we are in low latency mode halve our delay which doubles the
1323 	 * rate to somewhere between 100K to 16K ints/sec
1324 	 */
1325 	if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1326 		avg_wire_size /= 2;
1327 
1328 	/* Resultant value is 256 times larger than it needs to be. This
1329 	 * gives us room to adjust the value as needed to either increase
1330 	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1331 	 *
1332 	 * Use addition as we have already recorded the new latency flag
1333 	 * for the ITR value.
1334 	 */
1335 	itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1336 	       I40E_ITR_ADAPTIVE_MIN_INC;
1337 
1338 	if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1339 		itr &= I40E_ITR_ADAPTIVE_LATENCY;
1340 		itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1341 	}
1342 
1343 clear_counts:
1344 	/* write back value */
1345 	rc->target_itr = itr;
1346 
1347 	/* next update should occur within next jiffy */
1348 	rc->next_update = next_update + 1;
1349 
1350 	rc->total_bytes = 0;
1351 	rc->total_packets = 0;
1352 }
1353 
i40e_rx_bi(struct i40e_ring * rx_ring,u32 idx)1354 static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1355 {
1356 	return &rx_ring->rx_bi[idx];
1357 }
1358 
1359 /**
1360  * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1361  * @rx_ring: rx descriptor ring to store buffers on
1362  * @old_buff: donor buffer to have page reused
1363  *
1364  * Synchronizes page for reuse by the adapter
1365  **/
i40e_reuse_rx_page(struct i40e_ring * rx_ring,struct i40e_rx_buffer * old_buff)1366 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1367 			       struct i40e_rx_buffer *old_buff)
1368 {
1369 	struct i40e_rx_buffer *new_buff;
1370 	u16 nta = rx_ring->next_to_alloc;
1371 
1372 	new_buff = i40e_rx_bi(rx_ring, nta);
1373 
1374 	/* update, and store next to alloc */
1375 	nta++;
1376 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1377 
1378 	/* transfer page from old buffer to new buffer */
1379 	new_buff->dma		= old_buff->dma;
1380 	new_buff->page		= old_buff->page;
1381 	new_buff->page_offset	= old_buff->page_offset;
1382 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
1383 
1384 	/* clear contents of buffer_info */
1385 	old_buff->page = NULL;
1386 }
1387 
1388 /**
1389  * i40e_clean_programming_status - clean the programming status descriptor
1390  * @rx_ring: the rx ring that has this descriptor
1391  * @qword0_raw: qword0
1392  * @qword1: qword1 representing status_error_len in CPU ordering
1393  *
1394  * Flow director should handle FD_FILTER_STATUS to check its filter programming
1395  * status being successful or not and take actions accordingly. FCoE should
1396  * handle its context/filter programming/invalidation status and take actions.
1397  *
1398  * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1399  **/
i40e_clean_programming_status(struct i40e_ring * rx_ring,u64 qword0_raw,u64 qword1)1400 void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1401 				   u64 qword1)
1402 {
1403 	u8 id;
1404 
1405 	id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1406 		  I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1407 
1408 	if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1409 		i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1410 }
1411 
1412 /**
1413  * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1414  * @tx_ring: the tx ring to set up
1415  *
1416  * Return 0 on success, negative on error
1417  **/
i40e_setup_tx_descriptors(struct i40e_ring * tx_ring)1418 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1419 {
1420 	struct device *dev = tx_ring->dev;
1421 	int bi_size;
1422 
1423 	if (!dev)
1424 		return -ENOMEM;
1425 
1426 	/* warn if we are about to overwrite the pointer */
1427 	WARN_ON(tx_ring->tx_bi);
1428 	bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1429 	tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1430 	if (!tx_ring->tx_bi)
1431 		goto err;
1432 
1433 	u64_stats_init(&tx_ring->syncp);
1434 
1435 	/* round up to nearest 4K */
1436 	tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1437 	/* add u32 for head writeback, align after this takes care of
1438 	 * guaranteeing this is at least one cache line in size
1439 	 */
1440 	tx_ring->size += sizeof(u32);
1441 	tx_ring->size = ALIGN(tx_ring->size, 4096);
1442 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1443 					   &tx_ring->dma, GFP_KERNEL);
1444 	if (!tx_ring->desc) {
1445 		dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1446 			 tx_ring->size);
1447 		goto err;
1448 	}
1449 
1450 	tx_ring->next_to_use = 0;
1451 	tx_ring->next_to_clean = 0;
1452 	tx_ring->tx_stats.prev_pkt_ctr = -1;
1453 	return 0;
1454 
1455 err:
1456 	kfree(tx_ring->tx_bi);
1457 	tx_ring->tx_bi = NULL;
1458 	return -ENOMEM;
1459 }
1460 
i40e_alloc_rx_bi(struct i40e_ring * rx_ring)1461 int i40e_alloc_rx_bi(struct i40e_ring *rx_ring)
1462 {
1463 	unsigned long sz = sizeof(*rx_ring->rx_bi) * rx_ring->count;
1464 
1465 	rx_ring->rx_bi = kzalloc(sz, GFP_KERNEL);
1466 	return rx_ring->rx_bi ? 0 : -ENOMEM;
1467 }
1468 
i40e_clear_rx_bi(struct i40e_ring * rx_ring)1469 static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1470 {
1471 	memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1472 }
1473 
1474 /**
1475  * i40e_clean_rx_ring - Free Rx buffers
1476  * @rx_ring: ring to be cleaned
1477  **/
i40e_clean_rx_ring(struct i40e_ring * rx_ring)1478 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1479 {
1480 	u16 i;
1481 
1482 	/* ring already cleared, nothing to do */
1483 	if (!rx_ring->rx_bi)
1484 		return;
1485 
1486 	if (rx_ring->skb) {
1487 		dev_kfree_skb(rx_ring->skb);
1488 		rx_ring->skb = NULL;
1489 	}
1490 
1491 	if (rx_ring->xsk_pool) {
1492 		i40e_xsk_clean_rx_ring(rx_ring);
1493 		goto skip_free;
1494 	}
1495 
1496 	/* Free all the Rx ring sk_buffs */
1497 	for (i = 0; i < rx_ring->count; i++) {
1498 		struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1499 
1500 		if (!rx_bi->page)
1501 			continue;
1502 
1503 		/* Invalidate cache lines that may have been written to by
1504 		 * device so that we avoid corrupting memory.
1505 		 */
1506 		dma_sync_single_range_for_cpu(rx_ring->dev,
1507 					      rx_bi->dma,
1508 					      rx_bi->page_offset,
1509 					      rx_ring->rx_buf_len,
1510 					      DMA_FROM_DEVICE);
1511 
1512 		/* free resources associated with mapping */
1513 		dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1514 				     i40e_rx_pg_size(rx_ring),
1515 				     DMA_FROM_DEVICE,
1516 				     I40E_RX_DMA_ATTR);
1517 
1518 		__page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1519 
1520 		rx_bi->page = NULL;
1521 		rx_bi->page_offset = 0;
1522 	}
1523 
1524 skip_free:
1525 	if (rx_ring->xsk_pool)
1526 		i40e_clear_rx_bi_zc(rx_ring);
1527 	else
1528 		i40e_clear_rx_bi(rx_ring);
1529 
1530 	/* Zero out the descriptor ring */
1531 	memset(rx_ring->desc, 0, rx_ring->size);
1532 
1533 	rx_ring->next_to_alloc = 0;
1534 	rx_ring->next_to_clean = 0;
1535 	rx_ring->next_to_use = 0;
1536 }
1537 
1538 /**
1539  * i40e_free_rx_resources - Free Rx resources
1540  * @rx_ring: ring to clean the resources from
1541  *
1542  * Free all receive software resources
1543  **/
i40e_free_rx_resources(struct i40e_ring * rx_ring)1544 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1545 {
1546 	i40e_clean_rx_ring(rx_ring);
1547 	if (rx_ring->vsi->type == I40E_VSI_MAIN)
1548 		xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1549 	rx_ring->xdp_prog = NULL;
1550 	kfree(rx_ring->rx_bi);
1551 	rx_ring->rx_bi = NULL;
1552 
1553 	if (rx_ring->desc) {
1554 		dma_free_coherent(rx_ring->dev, rx_ring->size,
1555 				  rx_ring->desc, rx_ring->dma);
1556 		rx_ring->desc = NULL;
1557 	}
1558 }
1559 
1560 /**
1561  * i40e_setup_rx_descriptors - Allocate Rx descriptors
1562  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1563  *
1564  * Returns 0 on success, negative on failure
1565  **/
i40e_setup_rx_descriptors(struct i40e_ring * rx_ring)1566 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1567 {
1568 	struct device *dev = rx_ring->dev;
1569 	int err;
1570 
1571 	u64_stats_init(&rx_ring->syncp);
1572 
1573 	/* Round up to nearest 4K */
1574 	rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc);
1575 	rx_ring->size = ALIGN(rx_ring->size, 4096);
1576 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1577 					   &rx_ring->dma, GFP_KERNEL);
1578 
1579 	if (!rx_ring->desc) {
1580 		dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1581 			 rx_ring->size);
1582 		return -ENOMEM;
1583 	}
1584 
1585 	rx_ring->next_to_alloc = 0;
1586 	rx_ring->next_to_clean = 0;
1587 	rx_ring->next_to_use = 0;
1588 
1589 	/* XDP RX-queue info only needed for RX rings exposed to XDP */
1590 	if (rx_ring->vsi->type == I40E_VSI_MAIN) {
1591 		err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
1592 				       rx_ring->queue_index, rx_ring->q_vector->napi.napi_id);
1593 		if (err < 0)
1594 			return err;
1595 	}
1596 
1597 	rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1598 
1599 	return 0;
1600 }
1601 
1602 /**
1603  * i40e_release_rx_desc - Store the new tail and head values
1604  * @rx_ring: ring to bump
1605  * @val: new head index
1606  **/
i40e_release_rx_desc(struct i40e_ring * rx_ring,u32 val)1607 void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1608 {
1609 	rx_ring->next_to_use = val;
1610 
1611 	/* update next to alloc since we have filled the ring */
1612 	rx_ring->next_to_alloc = val;
1613 
1614 	/* Force memory writes to complete before letting h/w
1615 	 * know there are new descriptors to fetch.  (Only
1616 	 * applicable for weak-ordered memory model archs,
1617 	 * such as IA-64).
1618 	 */
1619 	wmb();
1620 	writel(val, rx_ring->tail);
1621 }
1622 
i40e_rx_frame_truesize(struct i40e_ring * rx_ring,unsigned int size)1623 static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1624 					   unsigned int size)
1625 {
1626 	unsigned int truesize;
1627 
1628 #if (PAGE_SIZE < 8192)
1629 	truesize = i40e_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
1630 #else
1631 	truesize = rx_ring->rx_offset ?
1632 		SKB_DATA_ALIGN(size + rx_ring->rx_offset) +
1633 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1634 		SKB_DATA_ALIGN(size);
1635 #endif
1636 	return truesize;
1637 }
1638 
1639 /**
1640  * i40e_alloc_mapped_page - recycle or make a new page
1641  * @rx_ring: ring to use
1642  * @bi: rx_buffer struct to modify
1643  *
1644  * Returns true if the page was successfully allocated or
1645  * reused.
1646  **/
i40e_alloc_mapped_page(struct i40e_ring * rx_ring,struct i40e_rx_buffer * bi)1647 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1648 				   struct i40e_rx_buffer *bi)
1649 {
1650 	struct page *page = bi->page;
1651 	dma_addr_t dma;
1652 
1653 	/* since we are recycling buffers we should seldom need to alloc */
1654 	if (likely(page)) {
1655 		rx_ring->rx_stats.page_reuse_count++;
1656 		return true;
1657 	}
1658 
1659 	/* alloc new page for storage */
1660 	page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1661 	if (unlikely(!page)) {
1662 		rx_ring->rx_stats.alloc_page_failed++;
1663 		return false;
1664 	}
1665 
1666 	rx_ring->rx_stats.page_alloc_count++;
1667 
1668 	/* map page for use */
1669 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1670 				 i40e_rx_pg_size(rx_ring),
1671 				 DMA_FROM_DEVICE,
1672 				 I40E_RX_DMA_ATTR);
1673 
1674 	/* if mapping failed free memory back to system since
1675 	 * there isn't much point in holding memory we can't use
1676 	 */
1677 	if (dma_mapping_error(rx_ring->dev, dma)) {
1678 		__free_pages(page, i40e_rx_pg_order(rx_ring));
1679 		rx_ring->rx_stats.alloc_page_failed++;
1680 		return false;
1681 	}
1682 
1683 	bi->dma = dma;
1684 	bi->page = page;
1685 	bi->page_offset = rx_ring->rx_offset;
1686 	page_ref_add(page, USHRT_MAX - 1);
1687 	bi->pagecnt_bias = USHRT_MAX;
1688 
1689 	return true;
1690 }
1691 
1692 /**
1693  * i40e_alloc_rx_buffers - Replace used receive buffers
1694  * @rx_ring: ring to place buffers on
1695  * @cleaned_count: number of buffers to replace
1696  *
1697  * Returns false if all allocations were successful, true if any fail
1698  **/
i40e_alloc_rx_buffers(struct i40e_ring * rx_ring,u16 cleaned_count)1699 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1700 {
1701 	u16 ntu = rx_ring->next_to_use;
1702 	union i40e_rx_desc *rx_desc;
1703 	struct i40e_rx_buffer *bi;
1704 
1705 	/* do nothing if no valid netdev defined */
1706 	if (!rx_ring->netdev || !cleaned_count)
1707 		return false;
1708 
1709 	rx_desc = I40E_RX_DESC(rx_ring, ntu);
1710 	bi = i40e_rx_bi(rx_ring, ntu);
1711 
1712 	do {
1713 		if (!i40e_alloc_mapped_page(rx_ring, bi))
1714 			goto no_buffers;
1715 
1716 		/* sync the buffer for use by the device */
1717 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1718 						 bi->page_offset,
1719 						 rx_ring->rx_buf_len,
1720 						 DMA_FROM_DEVICE);
1721 
1722 		/* Refresh the desc even if buffer_addrs didn't change
1723 		 * because each write-back erases this info.
1724 		 */
1725 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1726 
1727 		rx_desc++;
1728 		bi++;
1729 		ntu++;
1730 		if (unlikely(ntu == rx_ring->count)) {
1731 			rx_desc = I40E_RX_DESC(rx_ring, 0);
1732 			bi = i40e_rx_bi(rx_ring, 0);
1733 			ntu = 0;
1734 		}
1735 
1736 		/* clear the status bits for the next_to_use descriptor */
1737 		rx_desc->wb.qword1.status_error_len = 0;
1738 
1739 		cleaned_count--;
1740 	} while (cleaned_count);
1741 
1742 	if (rx_ring->next_to_use != ntu)
1743 		i40e_release_rx_desc(rx_ring, ntu);
1744 
1745 	return false;
1746 
1747 no_buffers:
1748 	if (rx_ring->next_to_use != ntu)
1749 		i40e_release_rx_desc(rx_ring, ntu);
1750 
1751 	/* make sure to come back via polling to try again after
1752 	 * allocation failure
1753 	 */
1754 	return true;
1755 }
1756 
1757 /**
1758  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1759  * @vsi: the VSI we care about
1760  * @skb: skb currently being received and modified
1761  * @rx_desc: the receive descriptor
1762  **/
i40e_rx_checksum(struct i40e_vsi * vsi,struct sk_buff * skb,union i40e_rx_desc * rx_desc)1763 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1764 				    struct sk_buff *skb,
1765 				    union i40e_rx_desc *rx_desc)
1766 {
1767 	struct i40e_rx_ptype_decoded decoded;
1768 	u32 rx_error, rx_status;
1769 	bool ipv4, ipv6;
1770 	u8 ptype;
1771 	u64 qword;
1772 
1773 	qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1774 	ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1775 	rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1776 		   I40E_RXD_QW1_ERROR_SHIFT;
1777 	rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1778 		    I40E_RXD_QW1_STATUS_SHIFT;
1779 	decoded = decode_rx_desc_ptype(ptype);
1780 
1781 	skb->ip_summed = CHECKSUM_NONE;
1782 
1783 	skb_checksum_none_assert(skb);
1784 
1785 	/* Rx csum enabled and ip headers found? */
1786 	if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1787 		return;
1788 
1789 	/* did the hardware decode the packet and checksum? */
1790 	if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1791 		return;
1792 
1793 	/* both known and outer_ip must be set for the below code to work */
1794 	if (!(decoded.known && decoded.outer_ip))
1795 		return;
1796 
1797 	ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1798 	       (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1799 	ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1800 	       (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1801 
1802 	if (ipv4 &&
1803 	    (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1804 			 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1805 		goto checksum_fail;
1806 
1807 	/* likely incorrect csum if alternate IP extension headers found */
1808 	if (ipv6 &&
1809 	    rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1810 		/* don't increment checksum err here, non-fatal err */
1811 		return;
1812 
1813 	/* there was some L4 error, count error and punt packet to the stack */
1814 	if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1815 		goto checksum_fail;
1816 
1817 	/* handle packets that were not able to be checksummed due
1818 	 * to arrival speed, in this case the stack can compute
1819 	 * the csum.
1820 	 */
1821 	if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1822 		return;
1823 
1824 	/* If there is an outer header present that might contain a checksum
1825 	 * we need to bump the checksum level by 1 to reflect the fact that
1826 	 * we are indicating we validated the inner checksum.
1827 	 */
1828 	if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1829 		skb->csum_level = 1;
1830 
1831 	/* Only report checksum unnecessary for TCP, UDP, or SCTP */
1832 	switch (decoded.inner_prot) {
1833 	case I40E_RX_PTYPE_INNER_PROT_TCP:
1834 	case I40E_RX_PTYPE_INNER_PROT_UDP:
1835 	case I40E_RX_PTYPE_INNER_PROT_SCTP:
1836 		skb->ip_summed = CHECKSUM_UNNECESSARY;
1837 		fallthrough;
1838 	default:
1839 		break;
1840 	}
1841 
1842 	return;
1843 
1844 checksum_fail:
1845 	vsi->back->hw_csum_rx_error++;
1846 }
1847 
1848 /**
1849  * i40e_ptype_to_htype - get a hash type
1850  * @ptype: the ptype value from the descriptor
1851  *
1852  * Returns a hash type to be used by skb_set_hash
1853  **/
i40e_ptype_to_htype(u8 ptype)1854 static inline int i40e_ptype_to_htype(u8 ptype)
1855 {
1856 	struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1857 
1858 	if (!decoded.known)
1859 		return PKT_HASH_TYPE_NONE;
1860 
1861 	if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1862 	    decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1863 		return PKT_HASH_TYPE_L4;
1864 	else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1865 		 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1866 		return PKT_HASH_TYPE_L3;
1867 	else
1868 		return PKT_HASH_TYPE_L2;
1869 }
1870 
1871 /**
1872  * i40e_rx_hash - set the hash value in the skb
1873  * @ring: descriptor ring
1874  * @rx_desc: specific descriptor
1875  * @skb: skb currently being received and modified
1876  * @rx_ptype: Rx packet type
1877  **/
i40e_rx_hash(struct i40e_ring * ring,union i40e_rx_desc * rx_desc,struct sk_buff * skb,u8 rx_ptype)1878 static inline void i40e_rx_hash(struct i40e_ring *ring,
1879 				union i40e_rx_desc *rx_desc,
1880 				struct sk_buff *skb,
1881 				u8 rx_ptype)
1882 {
1883 	u32 hash;
1884 	const __le64 rss_mask =
1885 		cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1886 			    I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1887 
1888 	if (!(ring->netdev->features & NETIF_F_RXHASH))
1889 		return;
1890 
1891 	if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1892 		hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1893 		skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1894 	}
1895 }
1896 
1897 /**
1898  * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1899  * @rx_ring: rx descriptor ring packet is being transacted on
1900  * @rx_desc: pointer to the EOP Rx descriptor
1901  * @skb: pointer to current skb being populated
1902  *
1903  * This function checks the ring, descriptor, and packet information in
1904  * order to populate the hash, checksum, VLAN, protocol, and
1905  * other fields within the skb.
1906  **/
i40e_process_skb_fields(struct i40e_ring * rx_ring,union i40e_rx_desc * rx_desc,struct sk_buff * skb)1907 void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1908 			     union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1909 {
1910 	u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1911 	u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1912 			I40E_RXD_QW1_STATUS_SHIFT;
1913 	u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1914 	u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1915 		   I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1916 	u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1917 		      I40E_RXD_QW1_PTYPE_SHIFT;
1918 
1919 	if (unlikely(tsynvalid))
1920 		i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1921 
1922 	i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1923 
1924 	i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1925 
1926 	skb_record_rx_queue(skb, rx_ring->queue_index);
1927 
1928 	if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1929 		__le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1930 
1931 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1932 				       le16_to_cpu(vlan_tag));
1933 	}
1934 
1935 	/* modifies the skb - consumes the enet header */
1936 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1937 }
1938 
1939 /**
1940  * i40e_cleanup_headers - Correct empty headers
1941  * @rx_ring: rx descriptor ring packet is being transacted on
1942  * @skb: pointer to current skb being fixed
1943  * @rx_desc: pointer to the EOP Rx descriptor
1944  *
1945  * In addition if skb is not at least 60 bytes we need to pad it so that
1946  * it is large enough to qualify as a valid Ethernet frame.
1947  *
1948  * Returns true if an error was encountered and skb was freed.
1949  **/
i40e_cleanup_headers(struct i40e_ring * rx_ring,struct sk_buff * skb,union i40e_rx_desc * rx_desc)1950 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1951 				 union i40e_rx_desc *rx_desc)
1952 
1953 {
1954 	/* ERR_MASK will only have valid bits if EOP set, and
1955 	 * what we are doing here is actually checking
1956 	 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1957 	 * the error field
1958 	 */
1959 	if (unlikely(i40e_test_staterr(rx_desc,
1960 				       BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1961 		dev_kfree_skb_any(skb);
1962 		return true;
1963 	}
1964 
1965 	/* if eth_skb_pad returns an error the skb was freed */
1966 	if (eth_skb_pad(skb))
1967 		return true;
1968 
1969 	return false;
1970 }
1971 
1972 /**
1973  * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx
1974  * @rx_buffer: buffer containing the page
1975  * @rx_stats: rx stats structure for the rx ring
1976  * @rx_buffer_pgcnt: buffer page refcount pre xdp_do_redirect() call
1977  *
1978  * If page is reusable, we have a green light for calling i40e_reuse_rx_page,
1979  * which will assign the current buffer to the buffer that next_to_alloc is
1980  * pointing to; otherwise, the DMA mapping needs to be destroyed and
1981  * page freed.
1982  *
1983  * rx_stats will be updated to indicate whether the page was waived
1984  * or busy if it could not be reused.
1985  */
i40e_can_reuse_rx_page(struct i40e_rx_buffer * rx_buffer,struct i40e_rx_queue_stats * rx_stats,int rx_buffer_pgcnt)1986 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer,
1987 				   struct i40e_rx_queue_stats *rx_stats,
1988 				   int rx_buffer_pgcnt)
1989 {
1990 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1991 	struct page *page = rx_buffer->page;
1992 
1993 	/* Is any reuse possible? */
1994 	if (!dev_page_is_reusable(page)) {
1995 		rx_stats->page_waive_count++;
1996 		return false;
1997 	}
1998 
1999 #if (PAGE_SIZE < 8192)
2000 	/* if we are only owner of page we can reuse it */
2001 	if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) {
2002 		rx_stats->page_busy_count++;
2003 		return false;
2004 	}
2005 #else
2006 #define I40E_LAST_OFFSET \
2007 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
2008 	if (rx_buffer->page_offset > I40E_LAST_OFFSET) {
2009 		rx_stats->page_busy_count++;
2010 		return false;
2011 	}
2012 #endif
2013 
2014 	/* If we have drained the page fragment pool we need to update
2015 	 * the pagecnt_bias and page count so that we fully restock the
2016 	 * number of references the driver holds.
2017 	 */
2018 	if (unlikely(pagecnt_bias == 1)) {
2019 		page_ref_add(page, USHRT_MAX - 1);
2020 		rx_buffer->pagecnt_bias = USHRT_MAX;
2021 	}
2022 
2023 	return true;
2024 }
2025 
2026 /**
2027  * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
2028  * @rx_ring: rx descriptor ring to transact packets on
2029  * @rx_buffer: buffer containing page to add
2030  * @skb: sk_buff to place the data into
2031  * @size: packet length from rx_desc
2032  *
2033  * This function will add the data contained in rx_buffer->page to the skb.
2034  * It will just attach the page as a frag to the skb.
2035  *
2036  * The function will then update the page offset.
2037  **/
i40e_add_rx_frag(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)2038 static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
2039 			     struct i40e_rx_buffer *rx_buffer,
2040 			     struct sk_buff *skb,
2041 			     unsigned int size)
2042 {
2043 #if (PAGE_SIZE < 8192)
2044 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2045 #else
2046 	unsigned int truesize = SKB_DATA_ALIGN(size + rx_ring->rx_offset);
2047 #endif
2048 
2049 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2050 			rx_buffer->page_offset, size, truesize);
2051 
2052 	/* page is being used so we must update the page offset */
2053 #if (PAGE_SIZE < 8192)
2054 	rx_buffer->page_offset ^= truesize;
2055 #else
2056 	rx_buffer->page_offset += truesize;
2057 #endif
2058 }
2059 
2060 /**
2061  * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
2062  * @rx_ring: rx descriptor ring to transact packets on
2063  * @size: size of buffer to add to skb
2064  * @rx_buffer_pgcnt: buffer page refcount
2065  *
2066  * This function will pull an Rx buffer from the ring and synchronize it
2067  * for use by the CPU.
2068  */
i40e_get_rx_buffer(struct i40e_ring * rx_ring,const unsigned int size,int * rx_buffer_pgcnt)2069 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
2070 						 const unsigned int size,
2071 						 int *rx_buffer_pgcnt)
2072 {
2073 	struct i40e_rx_buffer *rx_buffer;
2074 
2075 	rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2076 	*rx_buffer_pgcnt =
2077 #if (PAGE_SIZE < 8192)
2078 		page_count(rx_buffer->page);
2079 #else
2080 		0;
2081 #endif
2082 	prefetch_page_address(rx_buffer->page);
2083 
2084 	/* we are reusing so sync this buffer for CPU use */
2085 	dma_sync_single_range_for_cpu(rx_ring->dev,
2086 				      rx_buffer->dma,
2087 				      rx_buffer->page_offset,
2088 				      size,
2089 				      DMA_FROM_DEVICE);
2090 
2091 	/* We have pulled a buffer for use, so decrement pagecnt_bias */
2092 	rx_buffer->pagecnt_bias--;
2093 
2094 	return rx_buffer;
2095 }
2096 
2097 /**
2098  * i40e_construct_skb - Allocate skb and populate it
2099  * @rx_ring: rx descriptor ring to transact packets on
2100  * @rx_buffer: rx buffer to pull data from
2101  * @xdp: xdp_buff pointing to the data
2102  *
2103  * This function allocates an skb.  It then populates it with the page
2104  * data from the current receive descriptor, taking care to set up the
2105  * skb correctly.
2106  */
i40e_construct_skb(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,struct xdp_buff * xdp)2107 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
2108 					  struct i40e_rx_buffer *rx_buffer,
2109 					  struct xdp_buff *xdp)
2110 {
2111 	unsigned int size = xdp->data_end - xdp->data;
2112 #if (PAGE_SIZE < 8192)
2113 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2114 #else
2115 	unsigned int truesize = SKB_DATA_ALIGN(size);
2116 #endif
2117 	unsigned int headlen;
2118 	struct sk_buff *skb;
2119 
2120 	/* prefetch first cache line of first page */
2121 	net_prefetch(xdp->data);
2122 
2123 	/* Note, we get here by enabling legacy-rx via:
2124 	 *
2125 	 *    ethtool --set-priv-flags <dev> legacy-rx on
2126 	 *
2127 	 * In this mode, we currently get 0 extra XDP headroom as
2128 	 * opposed to having legacy-rx off, where we process XDP
2129 	 * packets going to stack via i40e_build_skb(). The latter
2130 	 * provides us currently with 192 bytes of headroom.
2131 	 *
2132 	 * For i40e_construct_skb() mode it means that the
2133 	 * xdp->data_meta will always point to xdp->data, since
2134 	 * the helper cannot expand the head. Should this ever
2135 	 * change in future for legacy-rx mode on, then lets also
2136 	 * add xdp->data_meta handling here.
2137 	 */
2138 
2139 	/* allocate a skb to store the frags */
2140 	skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2141 			       I40E_RX_HDR_SIZE,
2142 			       GFP_ATOMIC | __GFP_NOWARN);
2143 	if (unlikely(!skb))
2144 		return NULL;
2145 
2146 	/* Determine available headroom for copy */
2147 	headlen = size;
2148 	if (headlen > I40E_RX_HDR_SIZE)
2149 		headlen = eth_get_headlen(skb->dev, xdp->data,
2150 					  I40E_RX_HDR_SIZE);
2151 
2152 	/* align pull length to size of long to optimize memcpy performance */
2153 	memcpy(__skb_put(skb, headlen), xdp->data,
2154 	       ALIGN(headlen, sizeof(long)));
2155 
2156 	/* update all of the pointers */
2157 	size -= headlen;
2158 	if (size) {
2159 		skb_add_rx_frag(skb, 0, rx_buffer->page,
2160 				rx_buffer->page_offset + headlen,
2161 				size, truesize);
2162 
2163 		/* buffer is used by skb, update page_offset */
2164 #if (PAGE_SIZE < 8192)
2165 		rx_buffer->page_offset ^= truesize;
2166 #else
2167 		rx_buffer->page_offset += truesize;
2168 #endif
2169 	} else {
2170 		/* buffer is unused, reset bias back to rx_buffer */
2171 		rx_buffer->pagecnt_bias++;
2172 	}
2173 
2174 	return skb;
2175 }
2176 
2177 /**
2178  * i40e_build_skb - Build skb around an existing buffer
2179  * @rx_ring: Rx descriptor ring to transact packets on
2180  * @rx_buffer: Rx buffer to pull data from
2181  * @xdp: xdp_buff pointing to the data
2182  *
2183  * This function builds an skb around an existing Rx buffer, taking care
2184  * to set up the skb correctly and avoid any memcpy overhead.
2185  */
i40e_build_skb(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,struct xdp_buff * xdp)2186 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2187 				      struct i40e_rx_buffer *rx_buffer,
2188 				      struct xdp_buff *xdp)
2189 {
2190 	unsigned int metasize = xdp->data - xdp->data_meta;
2191 #if (PAGE_SIZE < 8192)
2192 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2193 #else
2194 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2195 				SKB_DATA_ALIGN(xdp->data_end -
2196 					       xdp->data_hard_start);
2197 #endif
2198 	struct sk_buff *skb;
2199 
2200 	/* Prefetch first cache line of first page. If xdp->data_meta
2201 	 * is unused, this points exactly as xdp->data, otherwise we
2202 	 * likely have a consumer accessing first few bytes of meta
2203 	 * data, and then actual data.
2204 	 */
2205 	net_prefetch(xdp->data_meta);
2206 
2207 	/* build an skb around the page buffer */
2208 	skb = napi_build_skb(xdp->data_hard_start, truesize);
2209 	if (unlikely(!skb))
2210 		return NULL;
2211 
2212 	/* update pointers within the skb to store the data */
2213 	skb_reserve(skb, xdp->data - xdp->data_hard_start);
2214 	__skb_put(skb, xdp->data_end - xdp->data);
2215 	if (metasize)
2216 		skb_metadata_set(skb, metasize);
2217 
2218 	/* buffer is used by skb, update page_offset */
2219 #if (PAGE_SIZE < 8192)
2220 	rx_buffer->page_offset ^= truesize;
2221 #else
2222 	rx_buffer->page_offset += truesize;
2223 #endif
2224 
2225 	return skb;
2226 }
2227 
2228 /**
2229  * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2230  * @rx_ring: rx descriptor ring to transact packets on
2231  * @rx_buffer: rx buffer to pull data from
2232  * @rx_buffer_pgcnt: rx buffer page refcount pre xdp_do_redirect() call
2233  *
2234  * This function will clean up the contents of the rx_buffer.  It will
2235  * either recycle the buffer or unmap it and free the associated resources.
2236  */
i40e_put_rx_buffer(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,int rx_buffer_pgcnt)2237 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2238 			       struct i40e_rx_buffer *rx_buffer,
2239 			       int rx_buffer_pgcnt)
2240 {
2241 	if (i40e_can_reuse_rx_page(rx_buffer, &rx_ring->rx_stats, rx_buffer_pgcnt)) {
2242 		/* hand second half of page back to the ring */
2243 		i40e_reuse_rx_page(rx_ring, rx_buffer);
2244 	} else {
2245 		/* we are not reusing the buffer so unmap it */
2246 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2247 				     i40e_rx_pg_size(rx_ring),
2248 				     DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2249 		__page_frag_cache_drain(rx_buffer->page,
2250 					rx_buffer->pagecnt_bias);
2251 		/* clear contents of buffer_info */
2252 		rx_buffer->page = NULL;
2253 	}
2254 }
2255 
2256 /**
2257  * i40e_is_non_eop - process handling of non-EOP buffers
2258  * @rx_ring: Rx ring being processed
2259  * @rx_desc: Rx descriptor for current buffer
2260  *
2261  * If the buffer is an EOP buffer, this function exits returning false,
2262  * otherwise return true indicating that this is in fact a non-EOP buffer.
2263  */
i40e_is_non_eop(struct i40e_ring * rx_ring,union i40e_rx_desc * rx_desc)2264 static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2265 			    union i40e_rx_desc *rx_desc)
2266 {
2267 	/* if we are the last buffer then there is nothing else to do */
2268 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2269 	if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2270 		return false;
2271 
2272 	rx_ring->rx_stats.non_eop_descs++;
2273 
2274 	return true;
2275 }
2276 
2277 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2278 			      struct i40e_ring *xdp_ring);
2279 
i40e_xmit_xdp_tx_ring(struct xdp_buff * xdp,struct i40e_ring * xdp_ring)2280 int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2281 {
2282 	struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2283 
2284 	if (unlikely(!xdpf))
2285 		return I40E_XDP_CONSUMED;
2286 
2287 	return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2288 }
2289 
2290 /**
2291  * i40e_run_xdp - run an XDP program
2292  * @rx_ring: Rx ring being processed
2293  * @xdp: XDP buffer containing the frame
2294  **/
i40e_run_xdp(struct i40e_ring * rx_ring,struct xdp_buff * xdp)2295 static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp)
2296 {
2297 	int err, result = I40E_XDP_PASS;
2298 	struct i40e_ring *xdp_ring;
2299 	struct bpf_prog *xdp_prog;
2300 	u32 act;
2301 
2302 	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2303 
2304 	if (!xdp_prog)
2305 		goto xdp_out;
2306 
2307 	prefetchw(xdp->data_hard_start); /* xdp_frame write */
2308 
2309 	act = bpf_prog_run_xdp(xdp_prog, xdp);
2310 	switch (act) {
2311 	case XDP_PASS:
2312 		break;
2313 	case XDP_TX:
2314 		xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2315 		result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2316 		if (result == I40E_XDP_CONSUMED)
2317 			goto out_failure;
2318 		break;
2319 	case XDP_REDIRECT:
2320 		err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2321 		if (err)
2322 			goto out_failure;
2323 		result = I40E_XDP_REDIR;
2324 		break;
2325 	default:
2326 		bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act);
2327 		fallthrough;
2328 	case XDP_ABORTED:
2329 out_failure:
2330 		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2331 		fallthrough; /* handle aborts by dropping packet */
2332 	case XDP_DROP:
2333 		result = I40E_XDP_CONSUMED;
2334 		break;
2335 	}
2336 xdp_out:
2337 	return result;
2338 }
2339 
2340 /**
2341  * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2342  * @rx_ring: Rx ring
2343  * @rx_buffer: Rx buffer to adjust
2344  * @size: Size of adjustment
2345  **/
i40e_rx_buffer_flip(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,unsigned int size)2346 static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2347 				struct i40e_rx_buffer *rx_buffer,
2348 				unsigned int size)
2349 {
2350 	unsigned int truesize = i40e_rx_frame_truesize(rx_ring, size);
2351 
2352 #if (PAGE_SIZE < 8192)
2353 	rx_buffer->page_offset ^= truesize;
2354 #else
2355 	rx_buffer->page_offset += truesize;
2356 #endif
2357 }
2358 
2359 /**
2360  * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2361  * @xdp_ring: XDP Tx ring
2362  *
2363  * This function updates the XDP Tx ring tail register.
2364  **/
i40e_xdp_ring_update_tail(struct i40e_ring * xdp_ring)2365 void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2366 {
2367 	/* Force memory writes to complete before letting h/w
2368 	 * know there are new descriptors to fetch.
2369 	 */
2370 	wmb();
2371 	writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2372 }
2373 
2374 /**
2375  * i40e_update_rx_stats - Update Rx ring statistics
2376  * @rx_ring: rx descriptor ring
2377  * @total_rx_bytes: number of bytes received
2378  * @total_rx_packets: number of packets received
2379  *
2380  * This function updates the Rx ring statistics.
2381  **/
i40e_update_rx_stats(struct i40e_ring * rx_ring,unsigned int total_rx_bytes,unsigned int total_rx_packets)2382 void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2383 			  unsigned int total_rx_bytes,
2384 			  unsigned int total_rx_packets)
2385 {
2386 	u64_stats_update_begin(&rx_ring->syncp);
2387 	rx_ring->stats.packets += total_rx_packets;
2388 	rx_ring->stats.bytes += total_rx_bytes;
2389 	u64_stats_update_end(&rx_ring->syncp);
2390 	rx_ring->q_vector->rx.total_packets += total_rx_packets;
2391 	rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2392 }
2393 
2394 /**
2395  * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2396  * @rx_ring: Rx ring
2397  * @xdp_res: Result of the receive batch
2398  *
2399  * This function bumps XDP Tx tail and/or flush redirect map, and
2400  * should be called when a batch of packets has been processed in the
2401  * napi loop.
2402  **/
i40e_finalize_xdp_rx(struct i40e_ring * rx_ring,unsigned int xdp_res)2403 void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2404 {
2405 	if (xdp_res & I40E_XDP_REDIR)
2406 		xdp_do_flush_map();
2407 
2408 	if (xdp_res & I40E_XDP_TX) {
2409 		struct i40e_ring *xdp_ring =
2410 			rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2411 
2412 		i40e_xdp_ring_update_tail(xdp_ring);
2413 	}
2414 }
2415 
2416 /**
2417  * i40e_inc_ntc: Advance the next_to_clean index
2418  * @rx_ring: Rx ring
2419  **/
i40e_inc_ntc(struct i40e_ring * rx_ring)2420 static void i40e_inc_ntc(struct i40e_ring *rx_ring)
2421 {
2422 	u32 ntc = rx_ring->next_to_clean + 1;
2423 
2424 	ntc = (ntc < rx_ring->count) ? ntc : 0;
2425 	rx_ring->next_to_clean = ntc;
2426 	prefetch(I40E_RX_DESC(rx_ring, ntc));
2427 }
2428 
2429 /**
2430  * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2431  * @rx_ring: rx descriptor ring to transact packets on
2432  * @budget: Total limit on number of packets to process
2433  *
2434  * This function provides a "bounce buffer" approach to Rx interrupt
2435  * processing.  The advantage to this is that on systems that have
2436  * expensive overhead for IOMMU access this provides a means of avoiding
2437  * it by maintaining the mapping of the page to the system.
2438  *
2439  * Returns amount of work completed
2440  **/
i40e_clean_rx_irq(struct i40e_ring * rx_ring,int budget)2441 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2442 {
2443 	unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0;
2444 	u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2445 	unsigned int offset = rx_ring->rx_offset;
2446 	struct sk_buff *skb = rx_ring->skb;
2447 	unsigned int xdp_xmit = 0;
2448 	bool failure = false;
2449 	struct xdp_buff xdp;
2450 	int xdp_res = 0;
2451 
2452 #if (PAGE_SIZE < 8192)
2453 	frame_sz = i40e_rx_frame_truesize(rx_ring, 0);
2454 #endif
2455 	xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
2456 
2457 	while (likely(total_rx_packets < (unsigned int)budget)) {
2458 		struct i40e_rx_buffer *rx_buffer;
2459 		union i40e_rx_desc *rx_desc;
2460 		int rx_buffer_pgcnt;
2461 		unsigned int size;
2462 		u64 qword;
2463 
2464 		/* return some buffers to hardware, one at a time is too slow */
2465 		if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2466 			failure = failure ||
2467 				  i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2468 			cleaned_count = 0;
2469 		}
2470 
2471 		rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2472 
2473 		/* status_error_len will always be zero for unused descriptors
2474 		 * because it's cleared in cleanup, and overlaps with hdr_addr
2475 		 * which is always zero because packet split isn't used, if the
2476 		 * hardware wrote DD then the length will be non-zero
2477 		 */
2478 		qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2479 
2480 		/* This memory barrier is needed to keep us from reading
2481 		 * any other fields out of the rx_desc until we have
2482 		 * verified the descriptor has been written back.
2483 		 */
2484 		dma_rmb();
2485 
2486 		if (i40e_rx_is_programming_status(qword)) {
2487 			i40e_clean_programming_status(rx_ring,
2488 						      rx_desc->raw.qword[0],
2489 						      qword);
2490 			rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2491 			i40e_inc_ntc(rx_ring);
2492 			i40e_reuse_rx_page(rx_ring, rx_buffer);
2493 			cleaned_count++;
2494 			continue;
2495 		}
2496 
2497 		size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2498 		       I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2499 		if (!size)
2500 			break;
2501 
2502 		i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2503 		rx_buffer = i40e_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);
2504 
2505 		/* retrieve a buffer from the ring */
2506 		if (!skb) {
2507 			unsigned char *hard_start;
2508 
2509 			hard_start = page_address(rx_buffer->page) +
2510 				     rx_buffer->page_offset - offset;
2511 			xdp_prepare_buff(&xdp, hard_start, offset, size, true);
2512 #if (PAGE_SIZE > 4096)
2513 			/* At larger PAGE_SIZE, frame_sz depend on len size */
2514 			xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2515 #endif
2516 			xdp_res = i40e_run_xdp(rx_ring, &xdp);
2517 		}
2518 
2519 		if (xdp_res) {
2520 			if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2521 				xdp_xmit |= xdp_res;
2522 				i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2523 			} else {
2524 				rx_buffer->pagecnt_bias++;
2525 			}
2526 			total_rx_bytes += size;
2527 			total_rx_packets++;
2528 		} else if (skb) {
2529 			i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2530 		} else if (ring_uses_build_skb(rx_ring)) {
2531 			skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2532 		} else {
2533 			skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2534 		}
2535 
2536 		/* exit if we failed to retrieve a buffer */
2537 		if (!xdp_res && !skb) {
2538 			rx_ring->rx_stats.alloc_buff_failed++;
2539 			rx_buffer->pagecnt_bias++;
2540 			break;
2541 		}
2542 
2543 		i40e_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);
2544 		cleaned_count++;
2545 
2546 		i40e_inc_ntc(rx_ring);
2547 		if (i40e_is_non_eop(rx_ring, rx_desc))
2548 			continue;
2549 
2550 		if (xdp_res || i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2551 			skb = NULL;
2552 			continue;
2553 		}
2554 
2555 		/* probably a little skewed due to removing CRC */
2556 		total_rx_bytes += skb->len;
2557 
2558 		/* populate checksum, VLAN, and protocol */
2559 		i40e_process_skb_fields(rx_ring, rx_desc, skb);
2560 
2561 		i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2562 		napi_gro_receive(&rx_ring->q_vector->napi, skb);
2563 		skb = NULL;
2564 
2565 		/* update budget accounting */
2566 		total_rx_packets++;
2567 	}
2568 
2569 	i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2570 	rx_ring->skb = skb;
2571 
2572 	i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2573 
2574 	/* guarantee a trip back through this routine if there was a failure */
2575 	return failure ? budget : (int)total_rx_packets;
2576 }
2577 
i40e_buildreg_itr(const int type,u16 itr)2578 static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2579 {
2580 	u32 val;
2581 
2582 	/* We don't bother with setting the CLEARPBA bit as the data sheet
2583 	 * points out doing so is "meaningless since it was already
2584 	 * auto-cleared". The auto-clearing happens when the interrupt is
2585 	 * asserted.
2586 	 *
2587 	 * Hardware errata 28 for also indicates that writing to a
2588 	 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2589 	 * an event in the PBA anyway so we need to rely on the automask
2590 	 * to hold pending events for us until the interrupt is re-enabled
2591 	 *
2592 	 * The itr value is reported in microseconds, and the register
2593 	 * value is recorded in 2 microsecond units. For this reason we
2594 	 * only need to shift by the interval shift - 1 instead of the
2595 	 * full value.
2596 	 */
2597 	itr &= I40E_ITR_MASK;
2598 
2599 	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2600 	      (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2601 	      (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2602 
2603 	return val;
2604 }
2605 
2606 /* a small macro to shorten up some long lines */
2607 #define INTREG I40E_PFINT_DYN_CTLN
2608 
2609 /* The act of updating the ITR will cause it to immediately trigger. In order
2610  * to prevent this from throwing off adaptive update statistics we defer the
2611  * update so that it can only happen so often. So after either Tx or Rx are
2612  * updated we make the adaptive scheme wait until either the ITR completely
2613  * expires via the next_update expiration or we have been through at least
2614  * 3 interrupts.
2615  */
2616 #define ITR_COUNTDOWN_START 3
2617 
2618 /**
2619  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2620  * @vsi: the VSI we care about
2621  * @q_vector: q_vector for which itr is being updated and interrupt enabled
2622  *
2623  **/
i40e_update_enable_itr(struct i40e_vsi * vsi,struct i40e_q_vector * q_vector)2624 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2625 					  struct i40e_q_vector *q_vector)
2626 {
2627 	struct i40e_hw *hw = &vsi->back->hw;
2628 	u32 intval;
2629 
2630 	/* If we don't have MSIX, then we only need to re-enable icr0 */
2631 	if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2632 		i40e_irq_dynamic_enable_icr0(vsi->back);
2633 		return;
2634 	}
2635 
2636 	/* These will do nothing if dynamic updates are not enabled */
2637 	i40e_update_itr(q_vector, &q_vector->tx);
2638 	i40e_update_itr(q_vector, &q_vector->rx);
2639 
2640 	/* This block of logic allows us to get away with only updating
2641 	 * one ITR value with each interrupt. The idea is to perform a
2642 	 * pseudo-lazy update with the following criteria.
2643 	 *
2644 	 * 1. Rx is given higher priority than Tx if both are in same state
2645 	 * 2. If we must reduce an ITR that is given highest priority.
2646 	 * 3. We then give priority to increasing ITR based on amount.
2647 	 */
2648 	if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2649 		/* Rx ITR needs to be reduced, this is highest priority */
2650 		intval = i40e_buildreg_itr(I40E_RX_ITR,
2651 					   q_vector->rx.target_itr);
2652 		q_vector->rx.current_itr = q_vector->rx.target_itr;
2653 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2654 	} else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2655 		   ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2656 		    (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2657 		/* Tx ITR needs to be reduced, this is second priority
2658 		 * Tx ITR needs to be increased more than Rx, fourth priority
2659 		 */
2660 		intval = i40e_buildreg_itr(I40E_TX_ITR,
2661 					   q_vector->tx.target_itr);
2662 		q_vector->tx.current_itr = q_vector->tx.target_itr;
2663 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2664 	} else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2665 		/* Rx ITR needs to be increased, third priority */
2666 		intval = i40e_buildreg_itr(I40E_RX_ITR,
2667 					   q_vector->rx.target_itr);
2668 		q_vector->rx.current_itr = q_vector->rx.target_itr;
2669 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2670 	} else {
2671 		/* No ITR update, lowest priority */
2672 		intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2673 		if (q_vector->itr_countdown)
2674 			q_vector->itr_countdown--;
2675 	}
2676 
2677 	if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2678 		wr32(hw, INTREG(q_vector->reg_idx), intval);
2679 }
2680 
2681 /**
2682  * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2683  * @napi: napi struct with our devices info in it
2684  * @budget: amount of work driver is allowed to do this pass, in packets
2685  *
2686  * This function will clean all queues associated with a q_vector.
2687  *
2688  * Returns the amount of work done
2689  **/
i40e_napi_poll(struct napi_struct * napi,int budget)2690 int i40e_napi_poll(struct napi_struct *napi, int budget)
2691 {
2692 	struct i40e_q_vector *q_vector =
2693 			       container_of(napi, struct i40e_q_vector, napi);
2694 	struct i40e_vsi *vsi = q_vector->vsi;
2695 	struct i40e_ring *ring;
2696 	bool clean_complete = true;
2697 	bool arm_wb = false;
2698 	int budget_per_ring;
2699 	int work_done = 0;
2700 
2701 	if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2702 		napi_complete(napi);
2703 		return 0;
2704 	}
2705 
2706 	/* Since the actual Tx work is minimal, we can give the Tx a larger
2707 	 * budget and be more aggressive about cleaning up the Tx descriptors.
2708 	 */
2709 	i40e_for_each_ring(ring, q_vector->tx) {
2710 		bool wd = ring->xsk_pool ?
2711 			  i40e_clean_xdp_tx_irq(vsi, ring) :
2712 			  i40e_clean_tx_irq(vsi, ring, budget);
2713 
2714 		if (!wd) {
2715 			clean_complete = false;
2716 			continue;
2717 		}
2718 		arm_wb |= ring->arm_wb;
2719 		ring->arm_wb = false;
2720 	}
2721 
2722 	/* Handle case where we are called by netpoll with a budget of 0 */
2723 	if (budget <= 0)
2724 		goto tx_only;
2725 
2726 	/* normally we have 1 Rx ring per q_vector */
2727 	if (unlikely(q_vector->num_ringpairs > 1))
2728 		/* We attempt to distribute budget to each Rx queue fairly, but
2729 		 * don't allow the budget to go below 1 because that would exit
2730 		 * polling early.
2731 		 */
2732 		budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2733 	else
2734 		/* Max of 1 Rx ring in this q_vector so give it the budget */
2735 		budget_per_ring = budget;
2736 
2737 	i40e_for_each_ring(ring, q_vector->rx) {
2738 		int cleaned = ring->xsk_pool ?
2739 			      i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2740 			      i40e_clean_rx_irq(ring, budget_per_ring);
2741 
2742 		work_done += cleaned;
2743 		/* if we clean as many as budgeted, we must not be done */
2744 		if (cleaned >= budget_per_ring)
2745 			clean_complete = false;
2746 	}
2747 
2748 	/* If work not completed, return budget and polling will return */
2749 	if (!clean_complete) {
2750 		int cpu_id = smp_processor_id();
2751 
2752 		/* It is possible that the interrupt affinity has changed but,
2753 		 * if the cpu is pegged at 100%, polling will never exit while
2754 		 * traffic continues and the interrupt will be stuck on this
2755 		 * cpu.  We check to make sure affinity is correct before we
2756 		 * continue to poll, otherwise we must stop polling so the
2757 		 * interrupt can move to the correct cpu.
2758 		 */
2759 		if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2760 			/* Tell napi that we are done polling */
2761 			napi_complete_done(napi, work_done);
2762 
2763 			/* Force an interrupt */
2764 			i40e_force_wb(vsi, q_vector);
2765 
2766 			/* Return budget-1 so that polling stops */
2767 			return budget - 1;
2768 		}
2769 tx_only:
2770 		if (arm_wb) {
2771 			q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2772 			i40e_enable_wb_on_itr(vsi, q_vector);
2773 		}
2774 		return budget;
2775 	}
2776 
2777 	if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2778 		q_vector->arm_wb_state = false;
2779 
2780 	/* Exit the polling mode, but don't re-enable interrupts if stack might
2781 	 * poll us due to busy-polling
2782 	 */
2783 	if (likely(napi_complete_done(napi, work_done)))
2784 		i40e_update_enable_itr(vsi, q_vector);
2785 
2786 	return min(work_done, budget - 1);
2787 }
2788 
2789 /**
2790  * i40e_atr - Add a Flow Director ATR filter
2791  * @tx_ring:  ring to add programming descriptor to
2792  * @skb:      send buffer
2793  * @tx_flags: send tx flags
2794  **/
i40e_atr(struct i40e_ring * tx_ring,struct sk_buff * skb,u32 tx_flags)2795 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2796 		     u32 tx_flags)
2797 {
2798 	struct i40e_filter_program_desc *fdir_desc;
2799 	struct i40e_pf *pf = tx_ring->vsi->back;
2800 	union {
2801 		unsigned char *network;
2802 		struct iphdr *ipv4;
2803 		struct ipv6hdr *ipv6;
2804 	} hdr;
2805 	struct tcphdr *th;
2806 	unsigned int hlen;
2807 	u32 flex_ptype, dtype_cmd;
2808 	int l4_proto;
2809 	u16 i;
2810 
2811 	/* make sure ATR is enabled */
2812 	if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2813 		return;
2814 
2815 	if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2816 		return;
2817 
2818 	/* if sampling is disabled do nothing */
2819 	if (!tx_ring->atr_sample_rate)
2820 		return;
2821 
2822 	/* Currently only IPv4/IPv6 with TCP is supported */
2823 	if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2824 		return;
2825 
2826 	/* snag network header to get L4 type and address */
2827 	hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2828 		      skb_inner_network_header(skb) : skb_network_header(skb);
2829 
2830 	/* Note: tx_flags gets modified to reflect inner protocols in
2831 	 * tx_enable_csum function if encap is enabled.
2832 	 */
2833 	if (tx_flags & I40E_TX_FLAGS_IPV4) {
2834 		/* access ihl as u8 to avoid unaligned access on ia64 */
2835 		hlen = (hdr.network[0] & 0x0F) << 2;
2836 		l4_proto = hdr.ipv4->protocol;
2837 	} else {
2838 		/* find the start of the innermost ipv6 header */
2839 		unsigned int inner_hlen = hdr.network - skb->data;
2840 		unsigned int h_offset = inner_hlen;
2841 
2842 		/* this function updates h_offset to the end of the header */
2843 		l4_proto =
2844 		  ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2845 		/* hlen will contain our best estimate of the tcp header */
2846 		hlen = h_offset - inner_hlen;
2847 	}
2848 
2849 	if (l4_proto != IPPROTO_TCP)
2850 		return;
2851 
2852 	th = (struct tcphdr *)(hdr.network + hlen);
2853 
2854 	/* Due to lack of space, no more new filters can be programmed */
2855 	if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2856 		return;
2857 	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2858 		/* HW ATR eviction will take care of removing filters on FIN
2859 		 * and RST packets.
2860 		 */
2861 		if (th->fin || th->rst)
2862 			return;
2863 	}
2864 
2865 	tx_ring->atr_count++;
2866 
2867 	/* sample on all syn/fin/rst packets or once every atr sample rate */
2868 	if (!th->fin &&
2869 	    !th->syn &&
2870 	    !th->rst &&
2871 	    (tx_ring->atr_count < tx_ring->atr_sample_rate))
2872 		return;
2873 
2874 	tx_ring->atr_count = 0;
2875 
2876 	/* grab the next descriptor */
2877 	i = tx_ring->next_to_use;
2878 	fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2879 
2880 	i++;
2881 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2882 
2883 	flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2884 		      I40E_TXD_FLTR_QW0_QINDEX_MASK;
2885 	flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2886 		      (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2887 		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2888 		      (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2889 		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2890 
2891 	flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2892 
2893 	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2894 
2895 	dtype_cmd |= (th->fin || th->rst) ?
2896 		     (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2897 		      I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2898 		     (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2899 		      I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2900 
2901 	dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2902 		     I40E_TXD_FLTR_QW1_DEST_SHIFT;
2903 
2904 	dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2905 		     I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2906 
2907 	dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2908 	if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2909 		dtype_cmd |=
2910 			((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2911 			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2912 			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2913 	else
2914 		dtype_cmd |=
2915 			((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2916 			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2917 			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2918 
2919 	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2920 		dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2921 
2922 	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2923 	fdir_desc->rsvd = cpu_to_le32(0);
2924 	fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2925 	fdir_desc->fd_id = cpu_to_le32(0);
2926 }
2927 
2928 /**
2929  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2930  * @skb:     send buffer
2931  * @tx_ring: ring to send buffer on
2932  * @flags:   the tx flags to be set
2933  *
2934  * Checks the skb and set up correspondingly several generic transmit flags
2935  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2936  *
2937  * Returns error code indicate the frame should be dropped upon error and the
2938  * otherwise  returns 0 to indicate the flags has been set properly.
2939  **/
i40e_tx_prepare_vlan_flags(struct sk_buff * skb,struct i40e_ring * tx_ring,u32 * flags)2940 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2941 					     struct i40e_ring *tx_ring,
2942 					     u32 *flags)
2943 {
2944 	__be16 protocol = skb->protocol;
2945 	u32  tx_flags = 0;
2946 
2947 	if (protocol == htons(ETH_P_8021Q) &&
2948 	    !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2949 		/* When HW VLAN acceleration is turned off by the user the
2950 		 * stack sets the protocol to 8021q so that the driver
2951 		 * can take any steps required to support the SW only
2952 		 * VLAN handling.  In our case the driver doesn't need
2953 		 * to take any further steps so just set the protocol
2954 		 * to the encapsulated ethertype.
2955 		 */
2956 		skb->protocol = vlan_get_protocol(skb);
2957 		goto out;
2958 	}
2959 
2960 	/* if we have a HW VLAN tag being added, default to the HW one */
2961 	if (skb_vlan_tag_present(skb)) {
2962 		tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2963 		tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2964 	/* else if it is a SW VLAN, check the next protocol and store the tag */
2965 	} else if (protocol == htons(ETH_P_8021Q)) {
2966 		struct vlan_hdr *vhdr, _vhdr;
2967 
2968 		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2969 		if (!vhdr)
2970 			return -EINVAL;
2971 
2972 		protocol = vhdr->h_vlan_encapsulated_proto;
2973 		tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2974 		tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2975 	}
2976 
2977 	if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2978 		goto out;
2979 
2980 	/* Insert 802.1p priority into VLAN header */
2981 	if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2982 	    (skb->priority != TC_PRIO_CONTROL)) {
2983 		tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2984 		tx_flags |= (skb->priority & 0x7) <<
2985 				I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2986 		if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2987 			struct vlan_ethhdr *vhdr;
2988 			int rc;
2989 
2990 			rc = skb_cow_head(skb, 0);
2991 			if (rc < 0)
2992 				return rc;
2993 			vhdr = (struct vlan_ethhdr *)skb->data;
2994 			vhdr->h_vlan_TCI = htons(tx_flags >>
2995 						 I40E_TX_FLAGS_VLAN_SHIFT);
2996 		} else {
2997 			tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2998 		}
2999 	}
3000 
3001 out:
3002 	*flags = tx_flags;
3003 	return 0;
3004 }
3005 
3006 /**
3007  * i40e_tso - set up the tso context descriptor
3008  * @first:    pointer to first Tx buffer for xmit
3009  * @hdr_len:  ptr to the size of the packet header
3010  * @cd_type_cmd_tso_mss: Quad Word 1
3011  *
3012  * Returns 0 if no TSO can happen, 1 if tso is going, or error
3013  **/
i40e_tso(struct i40e_tx_buffer * first,u8 * hdr_len,u64 * cd_type_cmd_tso_mss)3014 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
3015 		    u64 *cd_type_cmd_tso_mss)
3016 {
3017 	struct sk_buff *skb = first->skb;
3018 	u64 cd_cmd, cd_tso_len, cd_mss;
3019 	__be16 protocol;
3020 	union {
3021 		struct iphdr *v4;
3022 		struct ipv6hdr *v6;
3023 		unsigned char *hdr;
3024 	} ip;
3025 	union {
3026 		struct tcphdr *tcp;
3027 		struct udphdr *udp;
3028 		unsigned char *hdr;
3029 	} l4;
3030 	u32 paylen, l4_offset;
3031 	u16 gso_size;
3032 	int err;
3033 
3034 	if (skb->ip_summed != CHECKSUM_PARTIAL)
3035 		return 0;
3036 
3037 	if (!skb_is_gso(skb))
3038 		return 0;
3039 
3040 	err = skb_cow_head(skb, 0);
3041 	if (err < 0)
3042 		return err;
3043 
3044 	protocol = vlan_get_protocol(skb);
3045 
3046 	if (eth_p_mpls(protocol))
3047 		ip.hdr = skb_inner_network_header(skb);
3048 	else
3049 		ip.hdr = skb_network_header(skb);
3050 	l4.hdr = skb_checksum_start(skb);
3051 
3052 	/* initialize outer IP header fields */
3053 	if (ip.v4->version == 4) {
3054 		ip.v4->tot_len = 0;
3055 		ip.v4->check = 0;
3056 
3057 		first->tx_flags |= I40E_TX_FLAGS_TSO;
3058 	} else {
3059 		ip.v6->payload_len = 0;
3060 		first->tx_flags |= I40E_TX_FLAGS_TSO;
3061 	}
3062 
3063 	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
3064 					 SKB_GSO_GRE_CSUM |
3065 					 SKB_GSO_IPXIP4 |
3066 					 SKB_GSO_IPXIP6 |
3067 					 SKB_GSO_UDP_TUNNEL |
3068 					 SKB_GSO_UDP_TUNNEL_CSUM)) {
3069 		if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3070 		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
3071 			l4.udp->len = 0;
3072 
3073 			/* determine offset of outer transport header */
3074 			l4_offset = l4.hdr - skb->data;
3075 
3076 			/* remove payload length from outer checksum */
3077 			paylen = skb->len - l4_offset;
3078 			csum_replace_by_diff(&l4.udp->check,
3079 					     (__force __wsum)htonl(paylen));
3080 		}
3081 
3082 		/* reset pointers to inner headers */
3083 		ip.hdr = skb_inner_network_header(skb);
3084 		l4.hdr = skb_inner_transport_header(skb);
3085 
3086 		/* initialize inner IP header fields */
3087 		if (ip.v4->version == 4) {
3088 			ip.v4->tot_len = 0;
3089 			ip.v4->check = 0;
3090 		} else {
3091 			ip.v6->payload_len = 0;
3092 		}
3093 	}
3094 
3095 	/* determine offset of inner transport header */
3096 	l4_offset = l4.hdr - skb->data;
3097 
3098 	/* remove payload length from inner checksum */
3099 	paylen = skb->len - l4_offset;
3100 
3101 	if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3102 		csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
3103 		/* compute length of segmentation header */
3104 		*hdr_len = sizeof(*l4.udp) + l4_offset;
3105 	} else {
3106 		csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
3107 		/* compute length of segmentation header */
3108 		*hdr_len = (l4.tcp->doff * 4) + l4_offset;
3109 	}
3110 
3111 	/* pull values out of skb_shinfo */
3112 	gso_size = skb_shinfo(skb)->gso_size;
3113 
3114 	/* update GSO size and bytecount with header size */
3115 	first->gso_segs = skb_shinfo(skb)->gso_segs;
3116 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
3117 
3118 	/* find the field values */
3119 	cd_cmd = I40E_TX_CTX_DESC_TSO;
3120 	cd_tso_len = skb->len - *hdr_len;
3121 	cd_mss = gso_size;
3122 	*cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
3123 				(cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
3124 				(cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
3125 	return 1;
3126 }
3127 
3128 /**
3129  * i40e_tsyn - set up the tsyn context descriptor
3130  * @tx_ring:  ptr to the ring to send
3131  * @skb:      ptr to the skb we're sending
3132  * @tx_flags: the collected send information
3133  * @cd_type_cmd_tso_mss: Quad Word 1
3134  *
3135  * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3136  **/
i40e_tsyn(struct i40e_ring * tx_ring,struct sk_buff * skb,u32 tx_flags,u64 * cd_type_cmd_tso_mss)3137 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3138 		     u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3139 {
3140 	struct i40e_pf *pf;
3141 
3142 	if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3143 		return 0;
3144 
3145 	/* Tx timestamps cannot be sampled when doing TSO */
3146 	if (tx_flags & I40E_TX_FLAGS_TSO)
3147 		return 0;
3148 
3149 	/* only timestamp the outbound packet if the user has requested it and
3150 	 * we are not already transmitting a packet to be timestamped
3151 	 */
3152 	pf = i40e_netdev_to_pf(tx_ring->netdev);
3153 	if (!(pf->flags & I40E_FLAG_PTP))
3154 		return 0;
3155 
3156 	if (pf->ptp_tx &&
3157 	    !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3158 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3159 		pf->ptp_tx_start = jiffies;
3160 		pf->ptp_tx_skb = skb_get(skb);
3161 	} else {
3162 		pf->tx_hwtstamp_skipped++;
3163 		return 0;
3164 	}
3165 
3166 	*cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3167 				I40E_TXD_CTX_QW1_CMD_SHIFT;
3168 
3169 	return 1;
3170 }
3171 
3172 /**
3173  * i40e_tx_enable_csum - Enable Tx checksum offloads
3174  * @skb: send buffer
3175  * @tx_flags: pointer to Tx flags currently set
3176  * @td_cmd: Tx descriptor command bits to set
3177  * @td_offset: Tx descriptor header offsets to set
3178  * @tx_ring: Tx descriptor ring
3179  * @cd_tunneling: ptr to context desc bits
3180  **/
i40e_tx_enable_csum(struct sk_buff * skb,u32 * tx_flags,u32 * td_cmd,u32 * td_offset,struct i40e_ring * tx_ring,u32 * cd_tunneling)3181 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3182 			       u32 *td_cmd, u32 *td_offset,
3183 			       struct i40e_ring *tx_ring,
3184 			       u32 *cd_tunneling)
3185 {
3186 	union {
3187 		struct iphdr *v4;
3188 		struct ipv6hdr *v6;
3189 		unsigned char *hdr;
3190 	} ip;
3191 	union {
3192 		struct tcphdr *tcp;
3193 		struct udphdr *udp;
3194 		unsigned char *hdr;
3195 	} l4;
3196 	unsigned char *exthdr;
3197 	u32 offset, cmd = 0;
3198 	__be16 frag_off;
3199 	__be16 protocol;
3200 	u8 l4_proto = 0;
3201 
3202 	if (skb->ip_summed != CHECKSUM_PARTIAL)
3203 		return 0;
3204 
3205 	protocol = vlan_get_protocol(skb);
3206 
3207 	if (eth_p_mpls(protocol)) {
3208 		ip.hdr = skb_inner_network_header(skb);
3209 		l4.hdr = skb_checksum_start(skb);
3210 	} else {
3211 		ip.hdr = skb_network_header(skb);
3212 		l4.hdr = skb_transport_header(skb);
3213 	}
3214 
3215 	/* set the tx_flags to indicate the IP protocol type. this is
3216 	 * required so that checksum header computation below is accurate.
3217 	 */
3218 	if (ip.v4->version == 4)
3219 		*tx_flags |= I40E_TX_FLAGS_IPV4;
3220 	else
3221 		*tx_flags |= I40E_TX_FLAGS_IPV6;
3222 
3223 	/* compute outer L2 header size */
3224 	offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3225 
3226 	if (skb->encapsulation) {
3227 		u32 tunnel = 0;
3228 		/* define outer network header type */
3229 		if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3230 			tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3231 				  I40E_TX_CTX_EXT_IP_IPV4 :
3232 				  I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3233 
3234 			l4_proto = ip.v4->protocol;
3235 		} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3236 			int ret;
3237 
3238 			tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3239 
3240 			exthdr = ip.hdr + sizeof(*ip.v6);
3241 			l4_proto = ip.v6->nexthdr;
3242 			ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
3243 					       &l4_proto, &frag_off);
3244 			if (ret < 0)
3245 				return -1;
3246 		}
3247 
3248 		/* define outer transport */
3249 		switch (l4_proto) {
3250 		case IPPROTO_UDP:
3251 			tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3252 			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3253 			break;
3254 		case IPPROTO_GRE:
3255 			tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3256 			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3257 			break;
3258 		case IPPROTO_IPIP:
3259 		case IPPROTO_IPV6:
3260 			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3261 			l4.hdr = skb_inner_network_header(skb);
3262 			break;
3263 		default:
3264 			if (*tx_flags & I40E_TX_FLAGS_TSO)
3265 				return -1;
3266 
3267 			skb_checksum_help(skb);
3268 			return 0;
3269 		}
3270 
3271 		/* compute outer L3 header size */
3272 		tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3273 			  I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3274 
3275 		/* switch IP header pointer from outer to inner header */
3276 		ip.hdr = skb_inner_network_header(skb);
3277 
3278 		/* compute tunnel header size */
3279 		tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3280 			  I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3281 
3282 		/* indicate if we need to offload outer UDP header */
3283 		if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3284 		    !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3285 		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3286 			tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3287 
3288 		/* record tunnel offload values */
3289 		*cd_tunneling |= tunnel;
3290 
3291 		/* switch L4 header pointer from outer to inner */
3292 		l4.hdr = skb_inner_transport_header(skb);
3293 		l4_proto = 0;
3294 
3295 		/* reset type as we transition from outer to inner headers */
3296 		*tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3297 		if (ip.v4->version == 4)
3298 			*tx_flags |= I40E_TX_FLAGS_IPV4;
3299 		if (ip.v6->version == 6)
3300 			*tx_flags |= I40E_TX_FLAGS_IPV6;
3301 	}
3302 
3303 	/* Enable IP checksum offloads */
3304 	if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3305 		l4_proto = ip.v4->protocol;
3306 		/* the stack computes the IP header already, the only time we
3307 		 * need the hardware to recompute it is in the case of TSO.
3308 		 */
3309 		cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3310 		       I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3311 		       I40E_TX_DESC_CMD_IIPT_IPV4;
3312 	} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3313 		cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3314 
3315 		exthdr = ip.hdr + sizeof(*ip.v6);
3316 		l4_proto = ip.v6->nexthdr;
3317 		if (l4.hdr != exthdr)
3318 			ipv6_skip_exthdr(skb, exthdr - skb->data,
3319 					 &l4_proto, &frag_off);
3320 	}
3321 
3322 	/* compute inner L3 header size */
3323 	offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3324 
3325 	/* Enable L4 checksum offloads */
3326 	switch (l4_proto) {
3327 	case IPPROTO_TCP:
3328 		/* enable checksum offloads */
3329 		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3330 		offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3331 		break;
3332 	case IPPROTO_SCTP:
3333 		/* enable SCTP checksum offload */
3334 		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3335 		offset |= (sizeof(struct sctphdr) >> 2) <<
3336 			  I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3337 		break;
3338 	case IPPROTO_UDP:
3339 		/* enable UDP checksum offload */
3340 		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3341 		offset |= (sizeof(struct udphdr) >> 2) <<
3342 			  I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3343 		break;
3344 	default:
3345 		if (*tx_flags & I40E_TX_FLAGS_TSO)
3346 			return -1;
3347 		skb_checksum_help(skb);
3348 		return 0;
3349 	}
3350 
3351 	*td_cmd |= cmd;
3352 	*td_offset |= offset;
3353 
3354 	return 1;
3355 }
3356 
3357 /**
3358  * i40e_create_tx_ctx - Build the Tx context descriptor
3359  * @tx_ring:  ring to create the descriptor on
3360  * @cd_type_cmd_tso_mss: Quad Word 1
3361  * @cd_tunneling: Quad Word 0 - bits 0-31
3362  * @cd_l2tag2: Quad Word 0 - bits 32-63
3363  **/
i40e_create_tx_ctx(struct i40e_ring * tx_ring,const u64 cd_type_cmd_tso_mss,const u32 cd_tunneling,const u32 cd_l2tag2)3364 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3365 			       const u64 cd_type_cmd_tso_mss,
3366 			       const u32 cd_tunneling, const u32 cd_l2tag2)
3367 {
3368 	struct i40e_tx_context_desc *context_desc;
3369 	int i = tx_ring->next_to_use;
3370 
3371 	if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3372 	    !cd_tunneling && !cd_l2tag2)
3373 		return;
3374 
3375 	/* grab the next descriptor */
3376 	context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3377 
3378 	i++;
3379 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3380 
3381 	/* cpu_to_le32 and assign to struct fields */
3382 	context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3383 	context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3384 	context_desc->rsvd = cpu_to_le16(0);
3385 	context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3386 }
3387 
3388 /**
3389  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3390  * @tx_ring: the ring to be checked
3391  * @size:    the size buffer we want to assure is available
3392  *
3393  * Returns -EBUSY if a stop is needed, else 0
3394  **/
__i40e_maybe_stop_tx(struct i40e_ring * tx_ring,int size)3395 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3396 {
3397 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3398 	/* Memory barrier before checking head and tail */
3399 	smp_mb();
3400 
3401 	++tx_ring->tx_stats.tx_stopped;
3402 
3403 	/* Check again in a case another CPU has just made room available. */
3404 	if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3405 		return -EBUSY;
3406 
3407 	/* A reprieve! - use start_queue because it doesn't call schedule */
3408 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3409 	++tx_ring->tx_stats.restart_queue;
3410 	return 0;
3411 }
3412 
3413 /**
3414  * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3415  * @skb:      send buffer
3416  *
3417  * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3418  * and so we need to figure out the cases where we need to linearize the skb.
3419  *
3420  * For TSO we need to count the TSO header and segment payload separately.
3421  * As such we need to check cases where we have 7 fragments or more as we
3422  * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3423  * the segment payload in the first descriptor, and another 7 for the
3424  * fragments.
3425  **/
__i40e_chk_linearize(struct sk_buff * skb)3426 bool __i40e_chk_linearize(struct sk_buff *skb)
3427 {
3428 	const skb_frag_t *frag, *stale;
3429 	int nr_frags, sum;
3430 
3431 	/* no need to check if number of frags is less than 7 */
3432 	nr_frags = skb_shinfo(skb)->nr_frags;
3433 	if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3434 		return false;
3435 
3436 	/* We need to walk through the list and validate that each group
3437 	 * of 6 fragments totals at least gso_size.
3438 	 */
3439 	nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3440 	frag = &skb_shinfo(skb)->frags[0];
3441 
3442 	/* Initialize size to the negative value of gso_size minus 1.  We
3443 	 * use this as the worst case scenerio in which the frag ahead
3444 	 * of us only provides one byte which is why we are limited to 6
3445 	 * descriptors for a single transmit as the header and previous
3446 	 * fragment are already consuming 2 descriptors.
3447 	 */
3448 	sum = 1 - skb_shinfo(skb)->gso_size;
3449 
3450 	/* Add size of frags 0 through 4 to create our initial sum */
3451 	sum += skb_frag_size(frag++);
3452 	sum += skb_frag_size(frag++);
3453 	sum += skb_frag_size(frag++);
3454 	sum += skb_frag_size(frag++);
3455 	sum += skb_frag_size(frag++);
3456 
3457 	/* Walk through fragments adding latest fragment, testing it, and
3458 	 * then removing stale fragments from the sum.
3459 	 */
3460 	for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3461 		int stale_size = skb_frag_size(stale);
3462 
3463 		sum += skb_frag_size(frag++);
3464 
3465 		/* The stale fragment may present us with a smaller
3466 		 * descriptor than the actual fragment size. To account
3467 		 * for that we need to remove all the data on the front and
3468 		 * figure out what the remainder would be in the last
3469 		 * descriptor associated with the fragment.
3470 		 */
3471 		if (stale_size > I40E_MAX_DATA_PER_TXD) {
3472 			int align_pad = -(skb_frag_off(stale)) &
3473 					(I40E_MAX_READ_REQ_SIZE - 1);
3474 
3475 			sum -= align_pad;
3476 			stale_size -= align_pad;
3477 
3478 			do {
3479 				sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3480 				stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3481 			} while (stale_size > I40E_MAX_DATA_PER_TXD);
3482 		}
3483 
3484 		/* if sum is negative we failed to make sufficient progress */
3485 		if (sum < 0)
3486 			return true;
3487 
3488 		if (!nr_frags--)
3489 			break;
3490 
3491 		sum -= stale_size;
3492 	}
3493 
3494 	return false;
3495 }
3496 
3497 /**
3498  * i40e_tx_map - Build the Tx descriptor
3499  * @tx_ring:  ring to send buffer on
3500  * @skb:      send buffer
3501  * @first:    first buffer info buffer to use
3502  * @tx_flags: collected send information
3503  * @hdr_len:  size of the packet header
3504  * @td_cmd:   the command field in the descriptor
3505  * @td_offset: offset for checksum or crc
3506  *
3507  * Returns 0 on success, -1 on failure to DMA
3508  **/
i40e_tx_map(struct i40e_ring * tx_ring,struct sk_buff * skb,struct i40e_tx_buffer * first,u32 tx_flags,const u8 hdr_len,u32 td_cmd,u32 td_offset)3509 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3510 			      struct i40e_tx_buffer *first, u32 tx_flags,
3511 			      const u8 hdr_len, u32 td_cmd, u32 td_offset)
3512 {
3513 	unsigned int data_len = skb->data_len;
3514 	unsigned int size = skb_headlen(skb);
3515 	skb_frag_t *frag;
3516 	struct i40e_tx_buffer *tx_bi;
3517 	struct i40e_tx_desc *tx_desc;
3518 	u16 i = tx_ring->next_to_use;
3519 	u32 td_tag = 0;
3520 	dma_addr_t dma;
3521 	u16 desc_count = 1;
3522 
3523 	if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3524 		td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3525 		td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3526 			 I40E_TX_FLAGS_VLAN_SHIFT;
3527 	}
3528 
3529 	first->tx_flags = tx_flags;
3530 
3531 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3532 
3533 	tx_desc = I40E_TX_DESC(tx_ring, i);
3534 	tx_bi = first;
3535 
3536 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3537 		unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3538 
3539 		if (dma_mapping_error(tx_ring->dev, dma))
3540 			goto dma_error;
3541 
3542 		/* record length, and DMA address */
3543 		dma_unmap_len_set(tx_bi, len, size);
3544 		dma_unmap_addr_set(tx_bi, dma, dma);
3545 
3546 		/* align size to end of page */
3547 		max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3548 		tx_desc->buffer_addr = cpu_to_le64(dma);
3549 
3550 		while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3551 			tx_desc->cmd_type_offset_bsz =
3552 				build_ctob(td_cmd, td_offset,
3553 					   max_data, td_tag);
3554 
3555 			tx_desc++;
3556 			i++;
3557 			desc_count++;
3558 
3559 			if (i == tx_ring->count) {
3560 				tx_desc = I40E_TX_DESC(tx_ring, 0);
3561 				i = 0;
3562 			}
3563 
3564 			dma += max_data;
3565 			size -= max_data;
3566 
3567 			max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3568 			tx_desc->buffer_addr = cpu_to_le64(dma);
3569 		}
3570 
3571 		if (likely(!data_len))
3572 			break;
3573 
3574 		tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3575 							  size, td_tag);
3576 
3577 		tx_desc++;
3578 		i++;
3579 		desc_count++;
3580 
3581 		if (i == tx_ring->count) {
3582 			tx_desc = I40E_TX_DESC(tx_ring, 0);
3583 			i = 0;
3584 		}
3585 
3586 		size = skb_frag_size(frag);
3587 		data_len -= size;
3588 
3589 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3590 				       DMA_TO_DEVICE);
3591 
3592 		tx_bi = &tx_ring->tx_bi[i];
3593 	}
3594 
3595 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3596 
3597 	i++;
3598 	if (i == tx_ring->count)
3599 		i = 0;
3600 
3601 	tx_ring->next_to_use = i;
3602 
3603 	i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3604 
3605 	/* write last descriptor with EOP bit */
3606 	td_cmd |= I40E_TX_DESC_CMD_EOP;
3607 
3608 	/* We OR these values together to check both against 4 (WB_STRIDE)
3609 	 * below. This is safe since we don't re-use desc_count afterwards.
3610 	 */
3611 	desc_count |= ++tx_ring->packet_stride;
3612 
3613 	if (desc_count >= WB_STRIDE) {
3614 		/* write last descriptor with RS bit set */
3615 		td_cmd |= I40E_TX_DESC_CMD_RS;
3616 		tx_ring->packet_stride = 0;
3617 	}
3618 
3619 	tx_desc->cmd_type_offset_bsz =
3620 			build_ctob(td_cmd, td_offset, size, td_tag);
3621 
3622 	skb_tx_timestamp(skb);
3623 
3624 	/* Force memory writes to complete before letting h/w know there
3625 	 * are new descriptors to fetch.
3626 	 *
3627 	 * We also use this memory barrier to make certain all of the
3628 	 * status bits have been updated before next_to_watch is written.
3629 	 */
3630 	wmb();
3631 
3632 	/* set next_to_watch value indicating a packet is present */
3633 	first->next_to_watch = tx_desc;
3634 
3635 	/* notify HW of packet */
3636 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3637 		writel(i, tx_ring->tail);
3638 	}
3639 
3640 	return 0;
3641 
3642 dma_error:
3643 	dev_info(tx_ring->dev, "TX DMA map failed\n");
3644 
3645 	/* clear dma mappings for failed tx_bi map */
3646 	for (;;) {
3647 		tx_bi = &tx_ring->tx_bi[i];
3648 		i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3649 		if (tx_bi == first)
3650 			break;
3651 		if (i == 0)
3652 			i = tx_ring->count;
3653 		i--;
3654 	}
3655 
3656 	tx_ring->next_to_use = i;
3657 
3658 	return -1;
3659 }
3660 
i40e_swdcb_skb_tx_hash(struct net_device * dev,const struct sk_buff * skb,u16 num_tx_queues)3661 static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev,
3662 				  const struct sk_buff *skb,
3663 				  u16 num_tx_queues)
3664 {
3665 	u32 jhash_initval_salt = 0xd631614b;
3666 	u32 hash;
3667 
3668 	if (skb->sk && skb->sk->sk_hash)
3669 		hash = skb->sk->sk_hash;
3670 	else
3671 		hash = (__force u16)skb->protocol ^ skb->hash;
3672 
3673 	hash = jhash_1word(hash, jhash_initval_salt);
3674 
3675 	return (u16)(((u64)hash * num_tx_queues) >> 32);
3676 }
3677 
i40e_lan_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device __always_unused * sb_dev)3678 u16 i40e_lan_select_queue(struct net_device *netdev,
3679 			  struct sk_buff *skb,
3680 			  struct net_device __always_unused *sb_dev)
3681 {
3682 	struct i40e_netdev_priv *np = netdev_priv(netdev);
3683 	struct i40e_vsi *vsi = np->vsi;
3684 	struct i40e_hw *hw;
3685 	u16 qoffset;
3686 	u16 qcount;
3687 	u8 tclass;
3688 	u16 hash;
3689 	u8 prio;
3690 
3691 	/* is DCB enabled at all? */
3692 	if (vsi->tc_config.numtc == 1 ||
3693 	    i40e_is_tc_mqprio_enabled(vsi->back))
3694 		return netdev_pick_tx(netdev, skb, sb_dev);
3695 
3696 	prio = skb->priority;
3697 	hw = &vsi->back->hw;
3698 	tclass = hw->local_dcbx_config.etscfg.prioritytable[prio];
3699 	/* sanity check */
3700 	if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass))))
3701 		tclass = 0;
3702 
3703 	/* select a queue assigned for the given TC */
3704 	qcount = vsi->tc_config.tc_info[tclass].qcount;
3705 	hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount);
3706 
3707 	qoffset = vsi->tc_config.tc_info[tclass].qoffset;
3708 	return qoffset + hash;
3709 }
3710 
3711 /**
3712  * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3713  * @xdpf: data to transmit
3714  * @xdp_ring: XDP Tx ring
3715  **/
i40e_xmit_xdp_ring(struct xdp_frame * xdpf,struct i40e_ring * xdp_ring)3716 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3717 			      struct i40e_ring *xdp_ring)
3718 {
3719 	u16 i = xdp_ring->next_to_use;
3720 	struct i40e_tx_buffer *tx_bi;
3721 	struct i40e_tx_desc *tx_desc;
3722 	void *data = xdpf->data;
3723 	u32 size = xdpf->len;
3724 	dma_addr_t dma;
3725 
3726 	if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3727 		xdp_ring->tx_stats.tx_busy++;
3728 		return I40E_XDP_CONSUMED;
3729 	}
3730 	dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3731 	if (dma_mapping_error(xdp_ring->dev, dma))
3732 		return I40E_XDP_CONSUMED;
3733 
3734 	tx_bi = &xdp_ring->tx_bi[i];
3735 	tx_bi->bytecount = size;
3736 	tx_bi->gso_segs = 1;
3737 	tx_bi->xdpf = xdpf;
3738 
3739 	/* record length, and DMA address */
3740 	dma_unmap_len_set(tx_bi, len, size);
3741 	dma_unmap_addr_set(tx_bi, dma, dma);
3742 
3743 	tx_desc = I40E_TX_DESC(xdp_ring, i);
3744 	tx_desc->buffer_addr = cpu_to_le64(dma);
3745 	tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3746 						  | I40E_TXD_CMD,
3747 						  0, size, 0);
3748 
3749 	/* Make certain all of the status bits have been updated
3750 	 * before next_to_watch is written.
3751 	 */
3752 	smp_wmb();
3753 
3754 	xdp_ring->xdp_tx_active++;
3755 	i++;
3756 	if (i == xdp_ring->count)
3757 		i = 0;
3758 
3759 	tx_bi->next_to_watch = tx_desc;
3760 	xdp_ring->next_to_use = i;
3761 
3762 	return I40E_XDP_TX;
3763 }
3764 
3765 /**
3766  * i40e_xmit_frame_ring - Sends buffer on Tx ring
3767  * @skb:     send buffer
3768  * @tx_ring: ring to send buffer on
3769  *
3770  * Returns NETDEV_TX_OK if sent, else an error code
3771  **/
i40e_xmit_frame_ring(struct sk_buff * skb,struct i40e_ring * tx_ring)3772 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3773 					struct i40e_ring *tx_ring)
3774 {
3775 	u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3776 	u32 cd_tunneling = 0, cd_l2tag2 = 0;
3777 	struct i40e_tx_buffer *first;
3778 	u32 td_offset = 0;
3779 	u32 tx_flags = 0;
3780 	u32 td_cmd = 0;
3781 	u8 hdr_len = 0;
3782 	int tso, count;
3783 	int tsyn;
3784 
3785 	/* prefetch the data, we'll need it later */
3786 	prefetch(skb->data);
3787 
3788 	i40e_trace(xmit_frame_ring, skb, tx_ring);
3789 
3790 	count = i40e_xmit_descriptor_count(skb);
3791 	if (i40e_chk_linearize(skb, count)) {
3792 		if (__skb_linearize(skb)) {
3793 			dev_kfree_skb_any(skb);
3794 			return NETDEV_TX_OK;
3795 		}
3796 		count = i40e_txd_use_count(skb->len);
3797 		tx_ring->tx_stats.tx_linearize++;
3798 	}
3799 
3800 	/* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3801 	 *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3802 	 *       + 4 desc gap to avoid the cache line where head is,
3803 	 *       + 1 desc for context descriptor,
3804 	 * otherwise try next time
3805 	 */
3806 	if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3807 		tx_ring->tx_stats.tx_busy++;
3808 		return NETDEV_TX_BUSY;
3809 	}
3810 
3811 	/* record the location of the first descriptor for this packet */
3812 	first = &tx_ring->tx_bi[tx_ring->next_to_use];
3813 	first->skb = skb;
3814 	first->bytecount = skb->len;
3815 	first->gso_segs = 1;
3816 
3817 	/* prepare the xmit flags */
3818 	if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3819 		goto out_drop;
3820 
3821 	tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3822 
3823 	if (tso < 0)
3824 		goto out_drop;
3825 	else if (tso)
3826 		tx_flags |= I40E_TX_FLAGS_TSO;
3827 
3828 	/* Always offload the checksum, since it's in the data descriptor */
3829 	tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3830 				  tx_ring, &cd_tunneling);
3831 	if (tso < 0)
3832 		goto out_drop;
3833 
3834 	tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3835 
3836 	if (tsyn)
3837 		tx_flags |= I40E_TX_FLAGS_TSYN;
3838 
3839 	/* always enable CRC insertion offload */
3840 	td_cmd |= I40E_TX_DESC_CMD_ICRC;
3841 
3842 	i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3843 			   cd_tunneling, cd_l2tag2);
3844 
3845 	/* Add Flow Director ATR if it's enabled.
3846 	 *
3847 	 * NOTE: this must always be directly before the data descriptor.
3848 	 */
3849 	i40e_atr(tx_ring, skb, tx_flags);
3850 
3851 	if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3852 			td_cmd, td_offset))
3853 		goto cleanup_tx_tstamp;
3854 
3855 	return NETDEV_TX_OK;
3856 
3857 out_drop:
3858 	i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3859 	dev_kfree_skb_any(first->skb);
3860 	first->skb = NULL;
3861 cleanup_tx_tstamp:
3862 	if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3863 		struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3864 
3865 		dev_kfree_skb_any(pf->ptp_tx_skb);
3866 		pf->ptp_tx_skb = NULL;
3867 		clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3868 	}
3869 
3870 	return NETDEV_TX_OK;
3871 }
3872 
3873 /**
3874  * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3875  * @skb:    send buffer
3876  * @netdev: network interface device structure
3877  *
3878  * Returns NETDEV_TX_OK if sent, else an error code
3879  **/
i40e_lan_xmit_frame(struct sk_buff * skb,struct net_device * netdev)3880 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3881 {
3882 	struct i40e_netdev_priv *np = netdev_priv(netdev);
3883 	struct i40e_vsi *vsi = np->vsi;
3884 	struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3885 
3886 	/* hardware can't handle really short frames, hardware padding works
3887 	 * beyond this point
3888 	 */
3889 	if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3890 		return NETDEV_TX_OK;
3891 
3892 	return i40e_xmit_frame_ring(skb, tx_ring);
3893 }
3894 
3895 /**
3896  * i40e_xdp_xmit - Implements ndo_xdp_xmit
3897  * @dev: netdev
3898  * @n: number of frames
3899  * @frames: array of XDP buffer pointers
3900  * @flags: XDP extra info
3901  *
3902  * Returns number of frames successfully sent. Failed frames
3903  * will be free'ed by XDP core.
3904  *
3905  * For error cases, a negative errno code is returned and no-frames
3906  * are transmitted (caller must handle freeing frames).
3907  **/
i40e_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)3908 int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
3909 		  u32 flags)
3910 {
3911 	struct i40e_netdev_priv *np = netdev_priv(dev);
3912 	unsigned int queue_index = smp_processor_id();
3913 	struct i40e_vsi *vsi = np->vsi;
3914 	struct i40e_pf *pf = vsi->back;
3915 	struct i40e_ring *xdp_ring;
3916 	int nxmit = 0;
3917 	int i;
3918 
3919 	if (test_bit(__I40E_VSI_DOWN, vsi->state))
3920 		return -ENETDOWN;
3921 
3922 	if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
3923 	    test_bit(__I40E_CONFIG_BUSY, pf->state))
3924 		return -ENXIO;
3925 
3926 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3927 		return -EINVAL;
3928 
3929 	xdp_ring = vsi->xdp_rings[queue_index];
3930 
3931 	for (i = 0; i < n; i++) {
3932 		struct xdp_frame *xdpf = frames[i];
3933 		int err;
3934 
3935 		err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3936 		if (err != I40E_XDP_TX)
3937 			break;
3938 		nxmit++;
3939 	}
3940 
3941 	if (unlikely(flags & XDP_XMIT_FLUSH))
3942 		i40e_xdp_ring_update_tail(xdp_ring);
3943 
3944 	return nxmit;
3945 }
3946