1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #ifndef _I40E_ADMINQ_H_
5 #define _I40E_ADMINQ_H_
6
7 #include "i40e_osdep.h"
8 #include "i40e_adminq_cmd.h"
9
10 #define I40E_ADMINQ_DESC(R, i) \
11 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
12
13 #define I40E_ADMINQ_DESC_ALIGNMENT 4096
14
15 struct i40e_adminq_ring {
16 struct i40e_virt_mem dma_head; /* space for dma structures */
17 struct i40e_dma_mem desc_buf; /* descriptor ring memory */
18 struct i40e_virt_mem cmd_buf; /* command buffer memory */
19
20 union {
21 struct i40e_dma_mem *asq_bi;
22 struct i40e_dma_mem *arq_bi;
23 } r;
24
25 u16 count; /* Number of descriptors */
26 u16 rx_buf_len; /* Admin Receive Queue buffer length */
27
28 /* used for interrupt processing */
29 u16 next_to_use;
30 u16 next_to_clean;
31
32 /* used for queue tracking */
33 u32 head;
34 u32 tail;
35 u32 len;
36 u32 bah;
37 u32 bal;
38 };
39
40 /* ASQ transaction details */
41 struct i40e_asq_cmd_details {
42 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
43 u64 cookie;
44 u16 flags_ena;
45 u16 flags_dis;
46 bool async;
47 bool postpone;
48 struct i40e_aq_desc *wb_desc;
49 };
50
51 #define I40E_ADMINQ_DETAILS(R, i) \
52 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
53
54 /* ARQ event information */
55 struct i40e_arq_event_info {
56 struct i40e_aq_desc desc;
57 u16 msg_len;
58 u16 buf_len;
59 u8 *msg_buf;
60 };
61
62 /* Admin Queue information */
63 struct i40e_adminq_info {
64 struct i40e_adminq_ring arq; /* receive queue */
65 struct i40e_adminq_ring asq; /* send queue */
66 u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
67 u16 num_arq_entries; /* receive queue depth */
68 u16 num_asq_entries; /* send queue depth */
69 u16 arq_buf_size; /* receive queue buffer size */
70 u16 asq_buf_size; /* send queue buffer size */
71 u16 fw_maj_ver; /* firmware major version */
72 u16 fw_min_ver; /* firmware minor version */
73 u32 fw_build; /* firmware build number */
74 u16 api_maj_ver; /* api major version */
75 u16 api_min_ver; /* api minor version */
76
77 struct mutex asq_mutex; /* Send queue lock */
78 struct mutex arq_mutex; /* Receive queue lock */
79
80 /* last status values on send and receive queues */
81 enum i40e_admin_queue_err asq_last_status;
82 enum i40e_admin_queue_err arq_last_status;
83 };
84
85 /**
86 * i40e_aq_rc_to_posix - convert errors to user-land codes
87 * @aq_ret: AdminQ handler error code can override aq_rc
88 * @aq_rc: AdminQ firmware error code to convert
89 **/
i40e_aq_rc_to_posix(int aq_ret,int aq_rc)90 static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)
91 {
92 int aq_to_posix[] = {
93 0, /* I40E_AQ_RC_OK */
94 -EPERM, /* I40E_AQ_RC_EPERM */
95 -ENOENT, /* I40E_AQ_RC_ENOENT */
96 -ESRCH, /* I40E_AQ_RC_ESRCH */
97 -EINTR, /* I40E_AQ_RC_EINTR */
98 -EIO, /* I40E_AQ_RC_EIO */
99 -ENXIO, /* I40E_AQ_RC_ENXIO */
100 -E2BIG, /* I40E_AQ_RC_E2BIG */
101 -EAGAIN, /* I40E_AQ_RC_EAGAIN */
102 -ENOMEM, /* I40E_AQ_RC_ENOMEM */
103 -EACCES, /* I40E_AQ_RC_EACCES */
104 -EFAULT, /* I40E_AQ_RC_EFAULT */
105 -EBUSY, /* I40E_AQ_RC_EBUSY */
106 -EEXIST, /* I40E_AQ_RC_EEXIST */
107 -EINVAL, /* I40E_AQ_RC_EINVAL */
108 -ENOTTY, /* I40E_AQ_RC_ENOTTY */
109 -ENOSPC, /* I40E_AQ_RC_ENOSPC */
110 -ENOSYS, /* I40E_AQ_RC_ENOSYS */
111 -ERANGE, /* I40E_AQ_RC_ERANGE */
112 -EPIPE, /* I40E_AQ_RC_EFLUSHED */
113 -ESPIPE, /* I40E_AQ_RC_BAD_ADDR */
114 -EROFS, /* I40E_AQ_RC_EMODE */
115 -EFBIG, /* I40E_AQ_RC_EFBIG */
116 };
117
118 /* aq_rc is invalid if AQ timed out */
119 if (aq_ret == -EIO)
120 return -EAGAIN;
121
122 if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0]))))
123 return -ERANGE;
124
125 return aq_to_posix[aq_rc];
126 }
127
128 /* general information */
129 #define I40E_AQ_LARGE_BUF 512
130 #define I40E_ASQ_CMD_TIMEOUT 250000 /* usecs */
131
132 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
133 u16 opcode);
134
135 #endif /* _I40E_ADMINQ_H_ */
136