1 /*
2  * ross.h: Ross module specific definitions and defines.
3  *
4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5  */
6 
7 #ifndef _SPARC_ROSS_H
8 #define _SPARC_ROSS_H
9 
10 #include <asm/asi.h>
11 #include <asm/page.h>
12 
13 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
14  * field has '1111'.
15  */
16 
17 /* The MMU control register fields on the HyperSparc.
18  *
19  * -----------------------------------------------------------------
20  * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
21  * -----------------------------------------------------------------
22  *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
23  *
24  * Phew, lots of fields there ;-)
25  *
26  * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
27  * SE: Snoop Enable, turns on bus snooping for cache activity if one.
28  * WBE: Write Buffer Enable, one turns it on.
29  * MID: The ModuleID of the chip for MBus transactions.
30  * BM: Boot-Mode. One indicates the MMU is in boot mode.
31  * C: Indicates whether accesses are cachable while the MMU is
32  *    disabled.
33  * CS: Cache Size -- 0 = 128k, 1 = 256k
34  * MR: Memory Reflection, one indicates that the memory bus connected
35  *     to the MBus supports memory reflection.
36  * CM: Cache Mode -- 0 = write-through, 1 = copy-back
37  * CE: Cache Enable -- 0 = no caching, 1 = cache is on
38  * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
39  *                 1 = faults from supervisor mode do not generate traps
40  * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
41  */
42 
43 #define HYPERSPARC_CWENABLE   0x00200000
44 #define HYPERSPARC_SBENABLE   0x00100000
45 #define HYPERSPARC_WBENABLE   0x00080000
46 #define HYPERSPARC_MIDMASK    0x00078000
47 #define HYPERSPARC_BMODE      0x00004000
48 #define HYPERSPARC_ACENABLE   0x00002000
49 #define HYPERSPARC_CSIZE      0x00001000
50 #define HYPERSPARC_MRFLCT     0x00000800
51 #define HYPERSPARC_CMODE      0x00000400
52 #define HYPERSPARC_CENABLE    0x00000100
53 #define HYPERSPARC_NFAULT     0x00000002
54 #define HYPERSPARC_MENABLE    0x00000001
55 
56 
57 /* The ICCR instruction cache register on the HyperSparc.
58  *
59  * -----------------------------------------------
60  * |                                 | FTD | ICE |
61  * -----------------------------------------------
62  *  31                                  1     0
63  *
64  * This register is accessed using the V8 'wrasr' and 'rdasr'
65  * opcodes, since not all assemblers understand them and those
66  * that do use different semantics I will just hard code the
67  * instruction with a '.word' statement.
68  *
69  * FTD:  If set to one flush instructions executed during an
70  *       instruction cache hit occurs, the corresponding line
71  *       for said cache-hit is invalidated.  If FTD is zero,
72  *       an unimplemented 'flush' trap will occur when any
73  *       flush is executed by the processor.
74  *
75  * ICE:  If set to one, the instruction cache is enabled.  If
76  *       zero, the cache will not be used for instruction fetches.
77  *
78  * All other bits are read as zeros, and writes to them have no
79  * effect.
80  *
81  * Wheee, not many assemblers understand the %iccr register nor
82  * the generic asr r/w instructions.
83  *
84  *  1000 0011 0100 0111 1100 0000 0000 0000   ! rd %iccr, %g1
85  *
86  * 0x  8    3    4    7    c    0    0    0   ! 0x8347c000
87  *
88  *  1011 1111 1000 0000 0110 0000 0000 0000   ! wr %g1, 0x0, %iccr
89  *
90  * 0x  b    f    8    0    6    0    0    0   ! 0xbf806000
91  *
92  */
93 
94 #define HYPERSPARC_ICCR_FTD     0x00000002
95 #define HYPERSPARC_ICCR_ICE     0x00000001
96 
97 #ifndef __ASSEMBLY__
98 
get_ross_icr(void)99 static inline unsigned int get_ross_icr(void)
100 {
101 	unsigned int icreg;
102 
103 	__asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
104 			     "mov %%g1, %0\n\t"
105 			     : "=r" (icreg)
106 			     : /* no inputs */
107 			     : "g1", "memory");
108 
109 	return icreg;
110 }
111 
put_ross_icr(unsigned int icreg)112 static inline void put_ross_icr(unsigned int icreg)
113 {
114 	__asm__ __volatile__("or %%g0, %0, %%g1\n\t"
115 			     ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
116 			     "nop\n\t"
117 			     "nop\n\t"
118 			     "nop\n\t"
119 			     : /* no outputs */
120 			     : "r" (icreg)
121 			     : "g1", "memory");
122 
123 	return;
124 }
125 
126 /* HyperSparc specific cache flushing. */
127 
128 /* This is for the on-chip instruction cache. */
hyper_flush_whole_icache(void)129 static inline void hyper_flush_whole_icache(void)
130 {
131 	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
132 			     : /* no outputs */
133 			     : "i" (ASI_M_FLUSH_IWHOLE)
134 			     : "memory");
135 	return;
136 }
137 
138 extern int vac_cache_size;
139 extern int vac_line_size;
140 
hyper_clear_all_tags(void)141 static inline void hyper_clear_all_tags(void)
142 {
143 	unsigned long addr;
144 
145 	for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
146 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
147 				     : /* no outputs */
148 				     : "r" (addr), "i" (ASI_M_DATAC_TAG)
149 				     : "memory");
150 }
151 
hyper_flush_unconditional_combined(void)152 static inline void hyper_flush_unconditional_combined(void)
153 {
154 	unsigned long addr;
155 
156 	for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
157 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
158 				     : /* no outputs */
159 				     : "r" (addr), "i" (ASI_M_FLUSH_CTX)
160 				     : "memory");
161 }
162 
hyper_flush_cache_user(void)163 static inline void hyper_flush_cache_user(void)
164 {
165 	unsigned long addr;
166 
167 	for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
168 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
169 				     : /* no outputs */
170 				     : "r" (addr), "i" (ASI_M_FLUSH_USER)
171 				     : "memory");
172 }
173 
hyper_flush_cache_page(unsigned long page)174 static inline void hyper_flush_cache_page(unsigned long page)
175 {
176 	unsigned long end;
177 
178 	page &= PAGE_MASK;
179 	end = page + PAGE_SIZE;
180 	while (page < end) {
181 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
182 				     : /* no outputs */
183 				     : "r" (page), "i" (ASI_M_FLUSH_PAGE)
184 				     : "memory");
185 		page += vac_line_size;
186 	}
187 }
188 
189 #endif /* !(__ASSEMBLY__) */
190 
191 #endif /* !(_SPARC_ROSS_H) */
192