1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 41 #define MAX_CLOCK_SOURCES 7 42 #define MAX_SVP_PHANTOM_STREAMS 2 43 #define MAX_SVP_PHANTOM_PLANES 2 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 #include "link_hwss.h" 58 59 /************ link *****************/ 60 struct link_init_data { 61 const struct dc *dc; 62 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 63 uint32_t connector_index; /* this will be mapped to the HPD pins */ 64 uint32_t link_index; /* this is mapped to DAL display_index 65 TODO: remove it when DC is complete. */ 66 bool is_dpia_link; 67 }; 68 69 struct dc_link *link_create(const struct link_init_data *init_params); 70 void link_destroy(struct dc_link **link); 71 72 enum dc_status dc_link_validate_mode_timing( 73 const struct dc_stream_state *stream, 74 struct dc_link *link, 75 const struct dc_crtc_timing *timing); 76 77 void core_link_resume(struct dc_link *link); 78 79 void core_link_enable_stream( 80 struct dc_state *state, 81 struct pipe_ctx *pipe_ctx); 82 83 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 84 85 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 86 /********** DAL Core*********************/ 87 #include "transform.h" 88 #include "dpp.h" 89 90 struct resource_pool; 91 struct dc_state; 92 struct resource_context; 93 struct clk_bw_params; 94 95 struct resource_funcs { 96 void (*destroy)(struct resource_pool **pool); 97 void (*link_init)(struct dc_link *link); 98 struct panel_cntl*(*panel_cntl_create)( 99 const struct panel_cntl_init_data *panel_cntl_init_data); 100 struct link_encoder *(*link_enc_create)( 101 struct dc_context *ctx, 102 const struct encoder_init_data *init); 103 /* Create a minimal link encoder object with no dc_link object 104 * associated with it. */ 105 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 106 107 bool (*validate_bandwidth)( 108 struct dc *dc, 109 struct dc_state *context, 110 bool fast_validate); 111 void (*calculate_wm_and_dlg)( 112 struct dc *dc, struct dc_state *context, 113 display_e2e_pipe_params_st *pipes, 114 int pipe_cnt, 115 int vlevel); 116 void (*update_soc_for_wm_a)( 117 struct dc *dc, struct dc_state *context); 118 int (*populate_dml_pipes)( 119 struct dc *dc, 120 struct dc_state *context, 121 display_e2e_pipe_params_st *pipes, 122 bool fast_validate); 123 124 /* 125 * Algorithm for assigning available link encoders to links. 126 * 127 * Update link_enc_assignments table and link_enc_avail list accordingly in 128 * struct resource_context. 129 */ 130 void (*link_encs_assign)( 131 struct dc *dc, 132 struct dc_state *state, 133 struct dc_stream_state *streams[], 134 uint8_t stream_count); 135 /* 136 * Unassign a link encoder from a stream. 137 * 138 * Update link_enc_assignments table and link_enc_avail list accordingly in 139 * struct resource_context. 140 */ 141 void (*link_enc_unassign)( 142 struct dc_state *state, 143 struct dc_stream_state *stream); 144 145 enum dc_status (*validate_global)( 146 struct dc *dc, 147 struct dc_state *context); 148 149 /* 150 * Acquires a free pipe for the head pipe. 151 * The head pipe is first pipe in the current context that matches the stream 152 * and does not have a top pipe or prev_odm_pipe. 153 */ 154 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 155 struct dc_state *context, 156 const struct resource_pool *pool, 157 struct dc_stream_state *stream); 158 159 /* 160 * Acquires a free pipe for the head pipe with some additional checks for odm. 161 * The head pipe is passed in as an argument unlike acquire_idle_pipe_for_layer 162 * where it is read from the context. So this allows us look for different 163 * idle_pipe if the head_pipes are different ( ex. in odm 2:1 when we have 164 * a left and right pipe ). 165 * 166 * It also checks the old context to see if: 167 * 168 * 1. a pipe has already been allocated for the head pipe. If so, it will 169 * try to select that pipe as the idle pipe if it is available in the current 170 * context. 171 * 2. if the head_pipe is on the left, it will check if the right pipe has 172 * a pipe already allocated. If so, it will not use that pipe if it is 173 * selected as the idle pipe. 174 */ 175 struct pipe_ctx *(*acquire_idle_pipe_for_head_pipe_in_layer)( 176 struct dc_state *context, 177 const struct resource_pool *pool, 178 struct dc_stream_state *stream, 179 struct pipe_ctx *head_pipe); 180 181 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 182 183 enum dc_status (*add_stream_to_ctx)( 184 struct dc *dc, 185 struct dc_state *new_ctx, 186 struct dc_stream_state *dc_stream); 187 188 enum dc_status (*remove_stream_from_ctx)( 189 struct dc *dc, 190 struct dc_state *new_ctx, 191 struct dc_stream_state *stream); 192 enum dc_status (*patch_unknown_plane_state)( 193 struct dc_plane_state *plane_state); 194 195 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 196 struct resource_context *res_ctx, 197 const struct resource_pool *pool, 198 struct dc_stream_state *stream); 199 void (*populate_dml_writeback_from_context)( 200 struct dc *dc, 201 struct resource_context *res_ctx, 202 display_e2e_pipe_params_st *pipes); 203 204 void (*set_mcif_arb_params)( 205 struct dc *dc, 206 struct dc_state *context, 207 display_e2e_pipe_params_st *pipes, 208 int pipe_cnt); 209 void (*update_bw_bounding_box)( 210 struct dc *dc, 211 struct clk_bw_params *bw_params); 212 bool (*acquire_post_bldn_3dlut)( 213 struct resource_context *res_ctx, 214 const struct resource_pool *pool, 215 int mpcc_id, 216 struct dc_3dlut **lut, 217 struct dc_transfer_func **shaper); 218 219 bool (*release_post_bldn_3dlut)( 220 struct resource_context *res_ctx, 221 const struct resource_pool *pool, 222 struct dc_3dlut **lut, 223 struct dc_transfer_func **shaper); 224 225 enum dc_status (*add_dsc_to_stream_resource)( 226 struct dc *dc, struct dc_state *state, 227 struct dc_stream_state *stream); 228 229 void (*add_phantom_pipes)( 230 struct dc *dc, 231 struct dc_state *context, 232 display_e2e_pipe_params_st *pipes, 233 unsigned int pipe_cnt, 234 unsigned int index); 235 236 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context); 237 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 238 }; 239 240 struct audio_support{ 241 bool dp_audio; 242 bool hdmi_audio_on_dongle; 243 bool hdmi_audio_native; 244 }; 245 246 #define NO_UNDERLAY_PIPE -1 247 248 struct resource_pool { 249 struct mem_input *mis[MAX_PIPES]; 250 struct hubp *hubps[MAX_PIPES]; 251 struct input_pixel_processor *ipps[MAX_PIPES]; 252 struct transform *transforms[MAX_PIPES]; 253 struct dpp *dpps[MAX_PIPES]; 254 struct output_pixel_processor *opps[MAX_PIPES]; 255 struct timing_generator *timing_generators[MAX_PIPES]; 256 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 257 struct hubbub *hubbub; 258 struct mpc *mpc; 259 struct pp_smu_funcs *pp_smu; 260 struct dce_aux *engines[MAX_PIPES]; 261 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 262 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 263 bool i2c_hw_buffer_in_use; 264 265 struct dwbc *dwbc[MAX_DWB_PIPES]; 266 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 267 struct { 268 unsigned int gsl_0:1; 269 unsigned int gsl_1:1; 270 unsigned int gsl_2:1; 271 } gsl_groups; 272 273 struct display_stream_compressor *dscs[MAX_PIPES]; 274 275 unsigned int pipe_count; 276 unsigned int underlay_pipe_index; 277 unsigned int stream_enc_count; 278 279 /* An array for accessing the link encoder objects that have been created. 280 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 281 */ 282 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 283 /* Number of DIG link encoder objects created - i.e. number of valid 284 * entries in link_encoders array. 285 */ 286 unsigned int dig_link_enc_count; 287 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 288 unsigned int usb4_dpia_count; 289 290 unsigned int hpo_dp_stream_enc_count; 291 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 292 unsigned int hpo_dp_link_enc_count; 293 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 294 struct dc_3dlut *mpc_lut[MAX_PIPES]; 295 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 296 297 struct { 298 unsigned int xtalin_clock_inKhz; 299 unsigned int dccg_ref_clock_inKhz; 300 unsigned int dchub_ref_clock_inKhz; 301 } ref_clocks; 302 unsigned int timing_generator_count; 303 unsigned int mpcc_count; 304 305 unsigned int writeback_pipe_count; 306 /* 307 * reserved clock source for DP 308 */ 309 struct clock_source *dp_clock_source; 310 311 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 312 unsigned int clk_src_count; 313 314 struct audio *audios[MAX_AUDIOS]; 315 unsigned int audio_count; 316 struct audio_support audio_support; 317 318 struct dccg *dccg; 319 struct irq_service *irqs; 320 321 struct abm *abm; 322 struct dmcu *dmcu; 323 struct dmub_psr *psr; 324 325 struct abm *multiple_abms[MAX_PIPES]; 326 327 const struct resource_funcs *funcs; 328 const struct resource_caps *res_cap; 329 330 struct ddc_service *oem_device; 331 }; 332 333 struct dcn_fe_bandwidth { 334 int dppclk_khz; 335 336 }; 337 338 struct stream_resource { 339 struct output_pixel_processor *opp; 340 struct display_stream_compressor *dsc; 341 struct timing_generator *tg; 342 struct stream_encoder *stream_enc; 343 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 344 struct audio *audio; 345 346 struct pixel_clk_params pix_clk_params; 347 struct encoder_info_frame encoder_info_frame; 348 349 struct abm *abm; 350 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 351 * otherwise it's using group number 'gsl_group-1' 352 */ 353 uint8_t gsl_group; 354 }; 355 356 struct plane_resource { 357 struct scaler_data scl_data; 358 struct hubp *hubp; 359 struct mem_input *mi; 360 struct input_pixel_processor *ipp; 361 struct transform *xfm; 362 struct dpp *dpp; 363 uint8_t mpcc_inst; 364 365 struct dcn_fe_bandwidth bw; 366 }; 367 368 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 369 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 370 371 /* all mappable hardware resources used to enable a link */ 372 struct link_resource { 373 struct hpo_dp_link_encoder *hpo_dp_link_enc; 374 }; 375 376 struct link_config { 377 struct dc_link_settings dp_link_settings; 378 }; 379 union pipe_update_flags { 380 struct { 381 uint32_t enable : 1; 382 uint32_t disable : 1; 383 uint32_t odm : 1; 384 uint32_t global_sync : 1; 385 uint32_t opp_changed : 1; 386 uint32_t tg_changed : 1; 387 uint32_t mpcc : 1; 388 uint32_t dppclk : 1; 389 uint32_t hubp_interdependent : 1; 390 uint32_t hubp_rq_dlg_ttu : 1; 391 uint32_t gamut_remap : 1; 392 uint32_t scaler : 1; 393 uint32_t viewport : 1; 394 uint32_t plane_changed : 1; 395 uint32_t det_size : 1; 396 } bits; 397 uint32_t raw; 398 }; 399 400 struct pipe_ctx { 401 struct dc_plane_state *plane_state; 402 struct dc_stream_state *stream; 403 404 struct plane_resource plane_res; 405 406 /** 407 * @stream_res: Reference to DCN resource components such OPP and DSC. 408 */ 409 struct stream_resource stream_res; 410 struct link_resource link_res; 411 412 struct clock_source *clock_source; 413 414 struct pll_settings pll_settings; 415 416 /* link config records software decision for what link config should be 417 * enabled given current link capability and stream during hw resource 418 * mapping. This is to decouple the dependency on link capability during 419 * dc commit or update. 420 */ 421 struct link_config link_config; 422 423 uint8_t pipe_idx; 424 uint8_t pipe_idx_syncd; 425 426 struct pipe_ctx *top_pipe; 427 struct pipe_ctx *bottom_pipe; 428 struct pipe_ctx *next_odm_pipe; 429 struct pipe_ctx *prev_odm_pipe; 430 431 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 432 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 433 struct _vcs_dpi_display_rq_regs_st rq_regs; 434 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 435 struct _vcs_dpi_display_rq_params_st dml_rq_param; 436 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 437 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 438 int det_buffer_size_kb; 439 bool unbounded_req; 440 441 union pipe_update_flags update_flags; 442 struct dwbc *dwbc; 443 struct mcif_wb *mcif_wb; 444 }; 445 446 /* Data used for dynamic link encoder assignment. 447 * Tracks current and future assignments; available link encoders; 448 * and mode of operation (whether to use current or future assignments). 449 */ 450 struct link_enc_cfg_context { 451 enum link_enc_cfg_mode mode; 452 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 453 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 454 struct link_enc_assignment transient_assignments[MAX_PIPES]; 455 }; 456 457 struct resource_context { 458 struct pipe_ctx pipe_ctx[MAX_PIPES]; 459 bool is_stream_enc_acquired[MAX_PIPES * 2]; 460 bool is_audio_acquired[MAX_PIPES]; 461 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 462 uint8_t dp_clock_source_ref_count; 463 bool is_dsc_acquired[MAX_PIPES]; 464 struct link_enc_cfg_context link_enc_cfg_ctx; 465 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 466 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 467 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 468 bool is_mpc_3dlut_acquired[MAX_PIPES]; 469 }; 470 471 struct dce_bw_output { 472 bool cpuc_state_change_enable; 473 bool cpup_state_change_enable; 474 bool stutter_mode_enable; 475 bool nbp_state_change_enable; 476 bool all_displays_in_sync; 477 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 478 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 479 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 480 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 481 int sclk_khz; 482 int sclk_deep_sleep_khz; 483 int yclk_khz; 484 int dispclk_khz; 485 int blackout_recovery_time_us; 486 }; 487 488 struct dcn_bw_writeback { 489 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 490 }; 491 492 struct dcn_bw_output { 493 struct dc_clocks clk; 494 struct dcn_watermark_set watermarks; 495 struct dcn_bw_writeback bw_writeback; 496 int compbuf_size_kb; 497 unsigned int legacy_svp_drr_stream_index; 498 bool legacy_svp_drr_stream_index_valid; 499 }; 500 501 union bw_output { 502 struct dcn_bw_output dcn; 503 struct dce_bw_output dce; 504 }; 505 506 struct bw_context { 507 union bw_output bw; 508 struct display_mode_lib dml; 509 }; 510 /** 511 * struct dc_state - The full description of a state requested by a user 512 * 513 * @streams: Stream properties 514 * @stream_status: The planes on a given stream 515 * @res_ctx: Persistent state of resources 516 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 517 * @pp_display_cfg: PowerPlay clocks and settings 518 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 519 * 520 */ 521 struct dc_state { 522 struct dc_stream_state *streams[MAX_PIPES]; 523 struct dc_stream_status stream_status[MAX_PIPES]; 524 uint8_t stream_count; 525 uint8_t stream_mask; 526 527 struct resource_context res_ctx; 528 529 struct bw_context bw_ctx; 530 531 /* Note: these are big structures, do *not* put on stack! */ 532 struct dm_pp_display_configuration pp_display_cfg; 533 struct dcn_bw_internal_vars dcn_bw_vars; 534 535 struct clk_mgr *clk_mgr; 536 537 struct kref refcount; 538 539 struct { 540 unsigned int stutter_period_us; 541 } perf_params; 542 }; 543 544 struct dc_bounding_box_max_clk { 545 int max_dcfclk_mhz; 546 int max_dispclk_mhz; 547 int max_dppclk_mhz; 548 int max_phyclk_mhz; 549 }; 550 551 #endif /* _CORE_TYPES_H_ */ 552