1 #ifndef HPT366_H 2 #define HPT366_H 3 4 #include <linux/config.h> 5 #include <linux/pci.h> 6 #include <linux/ide.h> 7 8 #define DISPLAY_HPT366_TIMINGS 9 10 /* various tuning parameters */ 11 #define HPT_RESET_STATE_ENGINE 12 #undef HPT_DELAY_INTERRUPT 13 #undef HPT_SERIALIZE_IO 14 15 const char *quirk_drives[] = { 16 "QUANTUM FIREBALLlct08 08", 17 "QUANTUM FIREBALLP KA6.4", 18 "QUANTUM FIREBALLP LM20.4", 19 "QUANTUM FIREBALLP LM20.5", 20 NULL 21 }; 22 23 const char *bad_ata100_5[] = { 24 "IBM-DTLA-307075", 25 "IBM-DTLA-307060", 26 "IBM-DTLA-307045", 27 "IBM-DTLA-307030", 28 "IBM-DTLA-307020", 29 "IBM-DTLA-307015", 30 "IBM-DTLA-305040", 31 "IBM-DTLA-305030", 32 "IBM-DTLA-305020", 33 "IC35L010AVER07-0", 34 "IC35L020AVER07-0", 35 "IC35L030AVER07-0", 36 "IC35L040AVER07-0", 37 "IC35L060AVER07-0", 38 "WDC AC310200R", 39 NULL 40 }; 41 42 const char *bad_ata66_4[] = { 43 "IBM-DTLA-307075", 44 "IBM-DTLA-307060", 45 "IBM-DTLA-307045", 46 "IBM-DTLA-307030", 47 "IBM-DTLA-307020", 48 "IBM-DTLA-307015", 49 "IBM-DTLA-305040", 50 "IBM-DTLA-305030", 51 "IBM-DTLA-305020", 52 "IC35L010AVER07-0", 53 "IC35L020AVER07-0", 54 "IC35L030AVER07-0", 55 "IC35L040AVER07-0", 56 "IC35L060AVER07-0", 57 "WDC AC310200R", 58 NULL 59 }; 60 61 const char *bad_ata66_3[] = { 62 "WDC AC310200R", 63 NULL 64 }; 65 66 const char *bad_ata33[] = { 67 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 68 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 69 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 70 "Maxtor 90510D4", 71 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 72 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 73 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 74 NULL 75 }; 76 77 struct chipset_bus_clock_list_entry { 78 byte xfer_speed; 79 unsigned int chipset_settings; 80 }; 81 82 /* key for bus clock timings 83 * bit 84 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW 85 * DMA. cycles = value + 1 86 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW 87 * DMA. cycles = value + 1 88 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file 89 * register access. 90 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file 91 * register access. 92 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. 93 * during task file register access. 94 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA 95 * xfer. 96 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task 97 * register access. 98 * 28 UDMA enable 99 * 29 DMA enable 100 * 30 PIO_MST enable. if set, the chip is in bus master mode during 101 * PIO. 102 * 31 FIFO enable. 103 */ 104 struct chipset_bus_clock_list_entry forty_base_hpt366[] = { 105 { XFER_UDMA_4, 0x900fd943 }, 106 { XFER_UDMA_3, 0x900ad943 }, 107 { XFER_UDMA_2, 0x900bd943 }, 108 { XFER_UDMA_1, 0x9008d943 }, 109 { XFER_UDMA_0, 0x9008d943 }, 110 111 { XFER_MW_DMA_2, 0xa008d943 }, 112 { XFER_MW_DMA_1, 0xa010d955 }, 113 { XFER_MW_DMA_0, 0xa010d9fc }, 114 115 { XFER_PIO_4, 0xc008d963 }, 116 { XFER_PIO_3, 0xc010d974 }, 117 { XFER_PIO_2, 0xc010d997 }, 118 { XFER_PIO_1, 0xc010d9c7 }, 119 { XFER_PIO_0, 0xc018d9d9 }, 120 { 0, 0x0120d9d9 } 121 }; 122 123 struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = { 124 { XFER_UDMA_4, 0x90c9a731 }, 125 { XFER_UDMA_3, 0x90cfa731 }, 126 { XFER_UDMA_2, 0x90caa731 }, 127 { XFER_UDMA_1, 0x90cba731 }, 128 { XFER_UDMA_0, 0x90c8a731 }, 129 130 { XFER_MW_DMA_2, 0xa0c8a731 }, 131 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */ 132 { XFER_MW_DMA_0, 0xa0c8a797 }, 133 134 { XFER_PIO_4, 0xc0c8a731 }, 135 { XFER_PIO_3, 0xc0c8a742 }, 136 { XFER_PIO_2, 0xc0d0a753 }, 137 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */ 138 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */ 139 { 0, 0x0120a7a7 } 140 }; 141 142 struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = { 143 144 { XFER_UDMA_4, 0x90c98521 }, 145 { XFER_UDMA_3, 0x90cf8521 }, 146 { XFER_UDMA_2, 0x90cf8521 }, 147 { XFER_UDMA_1, 0x90cb8521 }, 148 { XFER_UDMA_0, 0x90cb8521 }, 149 150 { XFER_MW_DMA_2, 0xa0ca8521 }, 151 { XFER_MW_DMA_1, 0xa0ca8532 }, 152 { XFER_MW_DMA_0, 0xa0ca8575 }, 153 154 { XFER_PIO_4, 0xc0ca8521 }, 155 { XFER_PIO_3, 0xc0ca8532 }, 156 { XFER_PIO_2, 0xc0ca8542 }, 157 { XFER_PIO_1, 0xc0d08572 }, 158 { XFER_PIO_0, 0xc0d08585 }, 159 { 0, 0x01208585 } 160 }; 161 162 /* from highpoint documentation. these are old values */ 163 struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = { 164 /* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */ 165 { XFER_UDMA_5, 0x16454e31 }, 166 { XFER_UDMA_4, 0x16454e31 }, 167 { XFER_UDMA_3, 0x166d4e31 }, 168 { XFER_UDMA_2, 0x16494e31 }, 169 { XFER_UDMA_1, 0x164d4e31 }, 170 { XFER_UDMA_0, 0x16514e31 }, 171 172 { XFER_MW_DMA_2, 0x26514e21 }, 173 { XFER_MW_DMA_1, 0x26514e33 }, 174 { XFER_MW_DMA_0, 0x26514e97 }, 175 176 { XFER_PIO_4, 0x06514e21 }, 177 { XFER_PIO_3, 0x06514e22 }, 178 { XFER_PIO_2, 0x06514e33 }, 179 { XFER_PIO_1, 0x06914e43 }, 180 { XFER_PIO_0, 0x06914e57 }, 181 { 0, 0x06514e57 } 182 }; 183 184 struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = { 185 { XFER_UDMA_5, 0x14846231 }, 186 { XFER_UDMA_4, 0x14886231 }, 187 { XFER_UDMA_3, 0x148c6231 }, 188 { XFER_UDMA_2, 0x148c6231 }, 189 { XFER_UDMA_1, 0x14906231 }, 190 { XFER_UDMA_0, 0x14986231 }, 191 192 { XFER_MW_DMA_2, 0x26514e21 }, 193 { XFER_MW_DMA_1, 0x26514e33 }, 194 { XFER_MW_DMA_0, 0x26514e97 }, 195 196 { XFER_PIO_4, 0x06514e21 }, 197 { XFER_PIO_3, 0x06514e22 }, 198 { XFER_PIO_2, 0x06514e33 }, 199 { XFER_PIO_1, 0x06914e43 }, 200 { XFER_PIO_0, 0x06914e57 }, 201 { 0, 0x06514e57 } 202 }; 203 204 /* these are the current (4 sep 2001) timings from highpoint */ 205 struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = { 206 { XFER_UDMA_5, 0x12446231 }, 207 { XFER_UDMA_4, 0x12446231 }, 208 { XFER_UDMA_3, 0x126c6231 }, 209 { XFER_UDMA_2, 0x12486231 }, 210 { XFER_UDMA_1, 0x124c6233 }, 211 { XFER_UDMA_0, 0x12506297 }, 212 213 { XFER_MW_DMA_2, 0x22406c31 }, 214 { XFER_MW_DMA_1, 0x22406c33 }, 215 { XFER_MW_DMA_0, 0x22406c97 }, 216 217 { XFER_PIO_4, 0x06414e31 }, 218 { XFER_PIO_3, 0x06414e42 }, 219 { XFER_PIO_2, 0x06414e53 }, 220 { XFER_PIO_1, 0x06814e93 }, 221 { XFER_PIO_0, 0x06814ea7 }, 222 { 0, 0x06814ea7 } 223 }; 224 225 /* 2x 33MHz timings */ 226 struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = { 227 { XFER_UDMA_5, 0x1488e673 }, 228 { XFER_UDMA_4, 0x1488e673 }, 229 { XFER_UDMA_3, 0x1498e673 }, 230 { XFER_UDMA_2, 0x1490e673 }, 231 { XFER_UDMA_1, 0x1498e677 }, 232 { XFER_UDMA_0, 0x14a0e73f }, 233 234 { XFER_MW_DMA_2, 0x2480fa73 }, 235 { XFER_MW_DMA_1, 0x2480fa77 }, 236 { XFER_MW_DMA_0, 0x2480fb3f }, 237 238 { XFER_PIO_4, 0x0c82be73 }, 239 { XFER_PIO_3, 0x0c82be95 }, 240 { XFER_PIO_2, 0x0c82beb7 }, 241 { XFER_PIO_1, 0x0d02bf37 }, 242 { XFER_PIO_0, 0x0d02bf5f }, 243 { 0, 0x0d02bf5f } 244 }; 245 246 struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = { 247 { XFER_UDMA_5, 0x12848242 }, 248 { XFER_UDMA_4, 0x12ac8242 }, 249 { XFER_UDMA_3, 0x128c8242 }, 250 { XFER_UDMA_2, 0x120c8242 }, 251 { XFER_UDMA_1, 0x12148254 }, 252 { XFER_UDMA_0, 0x121882ea }, 253 254 { XFER_MW_DMA_2, 0x22808242 }, 255 { XFER_MW_DMA_1, 0x22808254 }, 256 { XFER_MW_DMA_0, 0x228082ea }, 257 258 { XFER_PIO_4, 0x0a81f442 }, 259 { XFER_PIO_3, 0x0a81f443 }, 260 { XFER_PIO_2, 0x0a81f454 }, 261 { XFER_PIO_1, 0x0ac1f465 }, 262 { XFER_PIO_0, 0x0ac1f48a }, 263 { 0, 0x0ac1f48a } 264 }; 265 266 struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = { 267 { XFER_UDMA_6, 0x1c81dc62 }, 268 { XFER_UDMA_5, 0x1c6ddc62 }, 269 { XFER_UDMA_4, 0x1c8ddc62 }, 270 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */ 271 { XFER_UDMA_2, 0x1c91dc62 }, 272 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */ 273 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */ 274 275 { XFER_MW_DMA_2, 0x2c829262 }, 276 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */ 277 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */ 278 279 { XFER_PIO_4, 0x0c829c62 }, 280 { XFER_PIO_3, 0x0c829c84 }, 281 { XFER_PIO_2, 0x0c829ca6 }, 282 { XFER_PIO_1, 0x0d029d26 }, 283 { XFER_PIO_0, 0x0d029d5e }, 284 { 0, 0x0d029d5e } 285 }; 286 287 struct chipset_bus_clock_list_entry fifty_base_hpt372[] = { 288 { XFER_UDMA_5, 0x12848242 }, 289 { XFER_UDMA_4, 0x12ac8242 }, 290 { XFER_UDMA_3, 0x128c8242 }, 291 { XFER_UDMA_2, 0x120c8242 }, 292 { XFER_UDMA_1, 0x12148254 }, 293 { XFER_UDMA_0, 0x121882ea }, 294 295 { XFER_MW_DMA_2, 0x22808242 }, 296 { XFER_MW_DMA_1, 0x22808254 }, 297 { XFER_MW_DMA_0, 0x228082ea }, 298 299 { XFER_PIO_4, 0x0a81f442 }, 300 { XFER_PIO_3, 0x0a81f443 }, 301 { XFER_PIO_2, 0x0a81f454 }, 302 { XFER_PIO_1, 0x0ac1f465 }, 303 { XFER_PIO_0, 0x0ac1f48a }, 304 { 0, 0x0a81f443 } 305 }; 306 307 struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = { 308 { XFER_UDMA_6, 0x1c869c62 }, 309 { XFER_UDMA_5, 0x1cae9c62 }, 310 { XFER_UDMA_4, 0x1c8a9c62 }, 311 { XFER_UDMA_3, 0x1c8e9c62 }, 312 { XFER_UDMA_2, 0x1c929c62 }, 313 { XFER_UDMA_1, 0x1c9a9c62 }, 314 { XFER_UDMA_0, 0x1c829c62 }, 315 316 { XFER_MW_DMA_2, 0x2c829c62 }, 317 { XFER_MW_DMA_1, 0x2c829c66 }, 318 { XFER_MW_DMA_0, 0x2c829d2e }, 319 320 { XFER_PIO_4, 0x0c829c62 }, 321 { XFER_PIO_3, 0x0c829c84 }, 322 { XFER_PIO_2, 0x0c829ca6 }, 323 { XFER_PIO_1, 0x0d029d26 }, 324 { XFER_PIO_0, 0x0d029d5e }, 325 { 0, 0x0d029d26 } 326 }; 327 328 struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = { 329 { XFER_UDMA_6, 0x12808242 }, 330 { XFER_UDMA_5, 0x12848242 }, 331 { XFER_UDMA_4, 0x12ac8242 }, 332 { XFER_UDMA_3, 0x128c8242 }, 333 { XFER_UDMA_2, 0x120c8242 }, 334 { XFER_UDMA_1, 0x12148254 }, 335 { XFER_UDMA_0, 0x121882ea }, 336 337 { XFER_MW_DMA_2, 0x22808242 }, 338 { XFER_MW_DMA_1, 0x22808254 }, 339 { XFER_MW_DMA_0, 0x228082ea }, 340 341 { XFER_PIO_4, 0x0a81f442 }, 342 { XFER_PIO_3, 0x0a81f443 }, 343 { XFER_PIO_2, 0x0a81f454 }, 344 { XFER_PIO_1, 0x0ac1f465 }, 345 { XFER_PIO_0, 0x0ac1f48a }, 346 { 0, 0x06814e93 } 347 }; 348 349 #if 0 350 struct chipset_bus_clock_list_entry fifty_base_hpt374[] = { 351 { XFER_UDMA_6, }, 352 { XFER_UDMA_5, }, 353 { XFER_UDMA_4, }, 354 { XFER_UDMA_3, }, 355 { XFER_UDMA_2, }, 356 { XFER_UDMA_1, }, 357 { XFER_UDMA_0, }, 358 { XFER_MW_DMA_2, }, 359 { XFER_MW_DMA_1, }, 360 { XFER_MW_DMA_0, }, 361 { XFER_PIO_4, }, 362 { XFER_PIO_3, }, 363 { XFER_PIO_2, }, 364 { XFER_PIO_1, }, 365 { XFER_PIO_0, }, 366 { 0, } 367 }; 368 #endif 369 #if 0 370 struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = { 371 { XFER_UDMA_6, 0x12406231 }, /* checkme */ 372 { XFER_UDMA_5, 0x12446231 }, 373 0x14846231 374 { XFER_UDMA_4, 0x16814ea7 }, 375 0x14886231 376 { XFER_UDMA_3, 0x16814ea7 }, 377 0x148c6231 378 { XFER_UDMA_2, 0x16814ea7 }, 379 0x148c6231 380 { XFER_UDMA_1, 0x16814ea7 }, 381 0x14906231 382 { XFER_UDMA_0, 0x16814ea7 }, 383 0x14986231 384 { XFER_MW_DMA_2, 0x16814ea7 }, 385 0x26514e21 386 { XFER_MW_DMA_1, 0x16814ea7 }, 387 0x26514e97 388 { XFER_MW_DMA_0, 0x16814ea7 }, 389 0x26514e97 390 { XFER_PIO_4, 0x06814ea7 }, 391 0x06514e21 392 { XFER_PIO_3, 0x06814ea7 }, 393 0x06514e22 394 { XFER_PIO_2, 0x06814ea7 }, 395 0x06514e33 396 { XFER_PIO_1, 0x06814ea7 }, 397 0x06914e43 398 { XFER_PIO_0, 0x06814ea7 }, 399 0x06914e57 400 { 0, 0x06814ea7 } 401 }; 402 #endif 403 404 #define HPT366_DEBUG_DRIVE_INFO 0 405 #define HPT374_ALLOW_ATA133_6 0 406 #define HPT371_ALLOW_ATA133_6 0 407 #define HPT302_ALLOW_ATA133_6 0 408 #define HPT372_ALLOW_ATA133_6 1 409 #define HPT370_ALLOW_ATA100_5 1 410 #define HPT366_ALLOW_ATA66_4 1 411 #define HPT366_ALLOW_ATA66_3 1 412 #define HPT366_MAX_DEVS 8 413 414 #define F_LOW_PCI_33 0x23 415 #define F_LOW_PCI_40 0x29 416 #define F_LOW_PCI_50 0x2d 417 #define F_LOW_PCI_66 0x42 418 419 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) 420 #include <linux/stat.h> 421 #include <linux/proc_fs.h> 422 423 static u8 hpt366_proc; 424 425 static int hpt366_get_info(char *, char **, off_t, int); 426 427 static ide_pci_host_proc_t hpt366_procs[] __initdata = { 428 { 429 .name = "hpt366", 430 .set = 1, 431 .get_info = hpt366_get_info, 432 .parent = NULL, 433 }, 434 }; 435 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */ 436 437 static void init_setup_hpt366(struct pci_dev *, ide_pci_device_t *); 438 static void init_setup_hpt37x(struct pci_dev *, ide_pci_device_t *); 439 static void init_setup_hpt374(struct pci_dev *, ide_pci_device_t *); 440 static unsigned int init_chipset_hpt366(struct pci_dev *, const char *); 441 static void init_hwif_hpt366(ide_hwif_t *); 442 static void init_dma_hpt366(ide_hwif_t *, unsigned long); 443 444 static ide_pci_device_t hpt366_chipsets[] __devinitdata = { 445 { /* 0 */ 446 .vendor = PCI_VENDOR_ID_TTI, 447 .device = PCI_DEVICE_ID_TTI_HPT366, 448 .name = "HPT366", 449 .init_setup = init_setup_hpt366, 450 .init_chipset = init_chipset_hpt366, 451 .init_iops = NULL, 452 .init_hwif = init_hwif_hpt366, 453 .init_dma = init_dma_hpt366, 454 .channels = 2, 455 .autodma = AUTODMA, 456 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 457 .bootable = OFF_BOARD, 458 .extra = 240 459 },{ /* 1 */ 460 .vendor = PCI_VENDOR_ID_TTI, 461 .device = PCI_DEVICE_ID_TTI_HPT372, 462 .name = "HPT372A", 463 .init_setup = init_setup_hpt37x, 464 .init_chipset = init_chipset_hpt366, 465 .init_iops = NULL, 466 .init_hwif = init_hwif_hpt366, 467 .init_dma = init_dma_hpt366, 468 .channels = 2, 469 .autodma = AUTODMA, 470 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 471 .bootable = OFF_BOARD, 472 .extra = 0 473 },{ /* 2 */ 474 .vendor = PCI_VENDOR_ID_TTI, 475 .device = PCI_DEVICE_ID_TTI_HPT302, 476 .name = "HPT302", 477 .init_setup = init_setup_hpt37x, 478 .init_chipset = init_chipset_hpt366, 479 .init_iops = NULL, 480 .init_hwif = init_hwif_hpt366, 481 .init_dma = init_dma_hpt366, 482 .channels = 2, 483 .autodma = AUTODMA, 484 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 485 .bootable = OFF_BOARD, 486 .extra = 0 487 },{ /* 3 */ 488 .vendor = PCI_VENDOR_ID_TTI, 489 .device = PCI_DEVICE_ID_TTI_HPT371, 490 .name = "HPT371", 491 .init_setup = init_setup_hpt37x, 492 .init_chipset = init_chipset_hpt366, 493 .init_iops = NULL, 494 .init_hwif = init_hwif_hpt366, 495 .init_dma = init_dma_hpt366, 496 .channels = 2, 497 .autodma = AUTODMA, 498 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 499 .bootable = OFF_BOARD, 500 .extra = 0 501 },{ /* 4 */ 502 .vendor = PCI_VENDOR_ID_TTI, 503 .device = PCI_DEVICE_ID_TTI_HPT374, 504 .name = "HPT374", 505 .init_setup = init_setup_hpt374, 506 .init_chipset = init_chipset_hpt366, 507 .init_iops = NULL, 508 .init_hwif = init_hwif_hpt366, 509 .init_dma = init_dma_hpt366, 510 .channels = 2, /* 4 */ 511 .autodma = AUTODMA, 512 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 513 .bootable = OFF_BOARD, 514 .extra = 0 515 },{ /* 5 */ 516 .vendor = PCI_VENDOR_ID_TTI, 517 .device = PCI_DEVICE_ID_TTI_HPT372N, 518 .name = "HPT372N", 519 .init_setup = init_setup_hpt37x, 520 .init_chipset = init_chipset_hpt366, 521 .init_iops = NULL, 522 .init_hwif = init_hwif_hpt366, 523 .init_dma = init_dma_hpt366, 524 .channels = 2, /* 4 */ 525 .autodma = AUTODMA, 526 .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, 527 .bootable = OFF_BOARD, 528 .extra = 0 529 },{ 530 .vendor = 0, 531 .device = 0, 532 .channels = 0, 533 .bootable = EOL, 534 } 535 }; 536 537 #endif /* HPT366_H */ 538