1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.207" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 /** 122 * DOC: color-management-caps 123 * 124 * **Color management caps (DPP and MPC)** 125 * 126 * Modules/color calculates various color operations which are translated to 127 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 128 * DCN1, every new generation comes with fairly major differences in color 129 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 130 * decide mapping to HW block based on logical capabilities. 131 */ 132 133 /** 134 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 135 * @srgb: RGB color space transfer func 136 * @bt2020: BT.2020 transfer func 137 * @gamma2_2: standard gamma 138 * @pq: perceptual quantizer transfer function 139 * @hlg: hybrid log–gamma transfer function 140 */ 141 struct rom_curve_caps { 142 uint16_t srgb : 1; 143 uint16_t bt2020 : 1; 144 uint16_t gamma2_2 : 1; 145 uint16_t pq : 1; 146 uint16_t hlg : 1; 147 }; 148 149 /** 150 * struct dpp_color_caps - color pipeline capabilities for display pipe and 151 * plane blocks 152 * 153 * @dcn_arch: all DCE generations treated the same 154 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 155 * just plain 256-entry lookup 156 * @icsc: input color space conversion 157 * @dgam_ram: programmable degamma LUT 158 * @post_csc: post color space conversion, before gamut remap 159 * @gamma_corr: degamma correction 160 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 161 * with MPC by setting mpc:shared_3d_lut flag 162 * @ogam_ram: programmable out/blend gamma LUT 163 * @ocsc: output color space conversion 164 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 165 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 166 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 167 * 168 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 169 */ 170 struct dpp_color_caps { 171 uint16_t dcn_arch : 1; 172 uint16_t input_lut_shared : 1; 173 uint16_t icsc : 1; 174 uint16_t dgam_ram : 1; 175 uint16_t post_csc : 1; 176 uint16_t gamma_corr : 1; 177 uint16_t hw_3d_lut : 1; 178 uint16_t ogam_ram : 1; 179 uint16_t ocsc : 1; 180 uint16_t dgam_rom_for_yuv : 1; 181 struct rom_curve_caps dgam_rom_caps; 182 struct rom_curve_caps ogam_rom_caps; 183 }; 184 185 /** 186 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 187 * plane combined blocks 188 * 189 * @gamut_remap: color transformation matrix 190 * @ogam_ram: programmable out gamma LUT 191 * @ocsc: output color space conversion matrix 192 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 193 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 194 * instance 195 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 196 */ 197 struct mpc_color_caps { 198 uint16_t gamut_remap : 1; 199 uint16_t ogam_ram : 1; 200 uint16_t ocsc : 1; 201 uint16_t num_3dluts : 3; 202 uint16_t shared_3d_lut:1; 203 struct rom_curve_caps ogam_rom_caps; 204 }; 205 206 /** 207 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 208 * @dpp: color pipes caps for DPP 209 * @mpc: color pipes caps for MPC 210 */ 211 struct dc_color_caps { 212 struct dpp_color_caps dpp; 213 struct mpc_color_caps mpc; 214 }; 215 216 struct dc_dmub_caps { 217 bool psr; 218 bool mclk_sw; 219 }; 220 221 struct dc_caps { 222 uint32_t max_streams; 223 uint32_t max_links; 224 uint32_t max_audios; 225 uint32_t max_slave_planes; 226 uint32_t max_slave_yuv_planes; 227 uint32_t max_slave_rgb_planes; 228 uint32_t max_planes; 229 uint32_t max_downscale_ratio; 230 uint32_t i2c_speed_in_khz; 231 uint32_t i2c_speed_in_khz_hdcp; 232 uint32_t dmdata_alloc_size; 233 unsigned int max_cursor_size; 234 unsigned int max_video_width; 235 unsigned int min_horizontal_blanking_period; 236 int linear_pitch_alignment; 237 bool dcc_const_color; 238 bool dynamic_audio; 239 bool is_apu; 240 bool dual_link_dvi; 241 bool post_blend_color_processing; 242 bool force_dp_tps4_for_cp2520; 243 bool disable_dp_clk_share; 244 bool psp_setup_panel_mode; 245 bool extended_aux_timeout_support; 246 bool dmcub_support; 247 bool zstate_support; 248 uint32_t num_of_internal_disp; 249 enum dp_protocol_version max_dp_protocol_version; 250 unsigned int mall_size_per_mem_channel; 251 unsigned int mall_size_total; 252 unsigned int cursor_cache_size; 253 struct dc_plane_cap planes[MAX_PLANES]; 254 struct dc_color_caps color; 255 struct dc_dmub_caps dmub_caps; 256 bool dp_hpo; 257 bool dp_hdmi21_pcon_support; 258 bool edp_dsc_support; 259 bool vbios_lttpr_aware; 260 bool vbios_lttpr_enable; 261 uint32_t max_otg_num; 262 uint32_t max_cab_allocation_bytes; 263 uint32_t cache_line_size; 264 uint32_t cache_num_ways; 265 uint16_t subvp_fw_processing_delay_us; 266 uint16_t subvp_prefetch_end_to_mall_start_us; 267 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 268 uint16_t subvp_pstate_allow_width_us; 269 uint16_t subvp_vertical_int_margin_us; 270 bool seamless_odm; 271 }; 272 273 struct dc_bug_wa { 274 bool no_connect_phy_config; 275 bool dedcn20_305_wa; 276 bool skip_clock_update; 277 bool lt_early_cr_pattern; 278 }; 279 280 struct dc_dcc_surface_param { 281 struct dc_size surface_size; 282 enum surface_pixel_format format; 283 enum swizzle_mode_values swizzle_mode; 284 enum dc_scan_direction scan; 285 }; 286 287 struct dc_dcc_setting { 288 unsigned int max_compressed_blk_size; 289 unsigned int max_uncompressed_blk_size; 290 bool independent_64b_blks; 291 //These bitfields to be used starting with DCN 292 struct { 293 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 294 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 295 uint32_t dcc_256_128_128 : 1; //available starting with DCN 296 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 297 } dcc_controls; 298 }; 299 300 struct dc_surface_dcc_cap { 301 union { 302 struct { 303 struct dc_dcc_setting rgb; 304 } grph; 305 306 struct { 307 struct dc_dcc_setting luma; 308 struct dc_dcc_setting chroma; 309 } video; 310 }; 311 312 bool capable; 313 bool const_color_support; 314 }; 315 316 struct dc_static_screen_params { 317 struct { 318 bool force_trigger; 319 bool cursor_update; 320 bool surface_update; 321 bool overlay_update; 322 } triggers; 323 unsigned int num_frames; 324 }; 325 326 327 /* Surface update type is used by dc_update_surfaces_and_stream 328 * The update type is determined at the very beginning of the function based 329 * on parameters passed in and decides how much programming (or updating) is 330 * going to be done during the call. 331 * 332 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 333 * logical calculations or hardware register programming. This update MUST be 334 * ISR safe on windows. Currently fast update will only be used to flip surface 335 * address. 336 * 337 * UPDATE_TYPE_MED is used for slower updates which require significant hw 338 * re-programming however do not affect bandwidth consumption or clock 339 * requirements. At present, this is the level at which front end updates 340 * that do not require us to run bw_calcs happen. These are in/out transfer func 341 * updates, viewport offset changes, recout size changes and pixel depth changes. 342 * This update can be done at ISR, but we want to minimize how often this happens. 343 * 344 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 345 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 346 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 347 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 348 * a full update. This cannot be done at ISR level and should be a rare event. 349 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 350 * underscan we don't expect to see this call at all. 351 */ 352 353 enum surface_update_type { 354 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 355 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 356 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 357 }; 358 359 /* Forward declaration*/ 360 struct dc; 361 struct dc_plane_state; 362 struct dc_state; 363 364 365 struct dc_cap_funcs { 366 bool (*get_dcc_compression_cap)(const struct dc *dc, 367 const struct dc_dcc_surface_param *input, 368 struct dc_surface_dcc_cap *output); 369 }; 370 371 struct link_training_settings; 372 373 union allow_lttpr_non_transparent_mode { 374 struct { 375 bool DP1_4A : 1; 376 bool DP2_0 : 1; 377 } bits; 378 unsigned char raw; 379 }; 380 381 /* Structure to hold configuration flags set by dm at dc creation. */ 382 struct dc_config { 383 bool gpu_vm_support; 384 bool disable_disp_pll_sharing; 385 bool fbc_support; 386 bool disable_fractional_pwm; 387 bool allow_seamless_boot_optimization; 388 bool seamless_boot_edp_requested; 389 bool edp_not_connected; 390 bool edp_no_power_sequencing; 391 bool force_enum_edp; 392 bool forced_clocks; 393 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 394 bool multi_mon_pp_mclk_switch; 395 bool disable_dmcu; 396 bool enable_4to1MPC; 397 bool enable_windowed_mpo_odm; 398 uint32_t allow_edp_hotplug_detection; 399 bool clamp_min_dcfclk; 400 uint64_t vblank_alignment_dto_params; 401 uint8_t vblank_alignment_max_frame_time_diff; 402 bool is_asymmetric_memory; 403 bool is_single_rank_dimm; 404 bool is_vmin_only_asic; 405 bool use_pipe_ctx_sync_logic; 406 bool ignore_dpref_ss; 407 bool enable_mipi_converter_optimization; 408 bool use_default_clock_table; 409 bool force_bios_enable_lttpr; 410 uint8_t force_bios_fixed_vs; 411 412 }; 413 414 enum visual_confirm { 415 VISUAL_CONFIRM_DISABLE = 0, 416 VISUAL_CONFIRM_SURFACE = 1, 417 VISUAL_CONFIRM_HDR = 2, 418 VISUAL_CONFIRM_MPCTREE = 4, 419 VISUAL_CONFIRM_PSR = 5, 420 VISUAL_CONFIRM_SWAPCHAIN = 6, 421 VISUAL_CONFIRM_FAMS = 7, 422 VISUAL_CONFIRM_SWIZZLE = 9, 423 VISUAL_CONFIRM_SUBVP = 14, 424 }; 425 426 enum dc_psr_power_opts { 427 psr_power_opt_invalid = 0x0, 428 psr_power_opt_smu_opt_static_screen = 0x1, 429 psr_power_opt_z10_static_screen = 0x10, 430 psr_power_opt_ds_disable_allow = 0x100, 431 }; 432 433 enum dml_hostvm_override_opts { 434 DML_HOSTVM_NO_OVERRIDE = 0x0, 435 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 436 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 437 }; 438 439 enum dcc_option { 440 DCC_ENABLE = 0, 441 DCC_DISABLE = 1, 442 DCC_HALF_REQ_DISALBE = 2, 443 }; 444 445 /** 446 * enum pipe_split_policy - Pipe split strategy supported by DCN 447 * 448 * This enum is used to define the pipe split policy supported by DCN. By 449 * default, DC favors MPC_SPLIT_DYNAMIC. 450 */ 451 enum pipe_split_policy { 452 /** 453 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 454 * pipe in order to bring the best trade-off between performance and 455 * power consumption. This is the recommended option. 456 */ 457 MPC_SPLIT_DYNAMIC = 0, 458 459 /** 460 * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not 461 * try any sort of split optimization. 462 */ 463 MPC_SPLIT_AVOID = 1, 464 465 /** 466 * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize 467 * the pipe utilization when using a single display; if the user 468 * connects to a second display, DC will avoid pipe split. 469 */ 470 MPC_SPLIT_AVOID_MULT_DISP = 2, 471 }; 472 473 enum wm_report_mode { 474 WM_REPORT_DEFAULT = 0, 475 WM_REPORT_OVERRIDE = 1, 476 }; 477 enum dtm_pstate{ 478 dtm_level_p0 = 0,/*highest voltage*/ 479 dtm_level_p1, 480 dtm_level_p2, 481 dtm_level_p3, 482 dtm_level_p4,/*when active_display_count = 0*/ 483 }; 484 485 enum dcn_pwr_state { 486 DCN_PWR_STATE_UNKNOWN = -1, 487 DCN_PWR_STATE_MISSION_MODE = 0, 488 DCN_PWR_STATE_LOW_POWER = 3, 489 }; 490 491 enum dcn_zstate_support_state { 492 DCN_ZSTATE_SUPPORT_UNKNOWN, 493 DCN_ZSTATE_SUPPORT_ALLOW, 494 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 495 DCN_ZSTATE_SUPPORT_DISALLOW, 496 }; 497 /* 498 * For any clocks that may differ per pipe 499 * only the max is stored in this structure 500 */ 501 struct dc_clocks { 502 int dispclk_khz; 503 int actual_dispclk_khz; 504 int dppclk_khz; 505 int actual_dppclk_khz; 506 int disp_dpp_voltage_level_khz; 507 int dcfclk_khz; 508 int socclk_khz; 509 int dcfclk_deep_sleep_khz; 510 int fclk_khz; 511 int phyclk_khz; 512 int dramclk_khz; 513 bool p_state_change_support; 514 enum dcn_zstate_support_state zstate_support; 515 bool dtbclk_en; 516 int ref_dtbclk_khz; 517 bool fclk_p_state_change_support; 518 enum dcn_pwr_state pwr_state; 519 /* 520 * Elements below are not compared for the purposes of 521 * optimization required 522 */ 523 bool prev_p_state_change_support; 524 bool fclk_prev_p_state_change_support; 525 int num_ways; 526 bool fw_based_mclk_switching; 527 bool fw_based_mclk_switching_shut_down; 528 int prev_num_ways; 529 enum dtm_pstate dtm_level; 530 int max_supported_dppclk_khz; 531 int max_supported_dispclk_khz; 532 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 533 int bw_dispclk_khz; 534 }; 535 536 struct dc_bw_validation_profile { 537 bool enable; 538 539 unsigned long long total_ticks; 540 unsigned long long voltage_level_ticks; 541 unsigned long long watermark_ticks; 542 unsigned long long rq_dlg_ticks; 543 544 unsigned long long total_count; 545 unsigned long long skip_fast_count; 546 unsigned long long skip_pass_count; 547 unsigned long long skip_fail_count; 548 }; 549 550 #define BW_VAL_TRACE_SETUP() \ 551 unsigned long long end_tick = 0; \ 552 unsigned long long voltage_level_tick = 0; \ 553 unsigned long long watermark_tick = 0; \ 554 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 555 dm_get_timestamp(dc->ctx) : 0 556 557 #define BW_VAL_TRACE_COUNT() \ 558 if (dc->debug.bw_val_profile.enable) \ 559 dc->debug.bw_val_profile.total_count++ 560 561 #define BW_VAL_TRACE_SKIP(status) \ 562 if (dc->debug.bw_val_profile.enable) { \ 563 if (!voltage_level_tick) \ 564 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 565 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 566 } 567 568 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 569 if (dc->debug.bw_val_profile.enable) \ 570 voltage_level_tick = dm_get_timestamp(dc->ctx) 571 572 #define BW_VAL_TRACE_END_WATERMARKS() \ 573 if (dc->debug.bw_val_profile.enable) \ 574 watermark_tick = dm_get_timestamp(dc->ctx) 575 576 #define BW_VAL_TRACE_FINISH() \ 577 if (dc->debug.bw_val_profile.enable) { \ 578 end_tick = dm_get_timestamp(dc->ctx); \ 579 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 580 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 581 if (watermark_tick) { \ 582 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 583 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 584 } \ 585 } 586 587 union mem_low_power_enable_options { 588 struct { 589 bool vga: 1; 590 bool i2c: 1; 591 bool dmcu: 1; 592 bool dscl: 1; 593 bool cm: 1; 594 bool mpc: 1; 595 bool optc: 1; 596 bool vpg: 1; 597 bool afmt: 1; 598 } bits; 599 uint32_t u32All; 600 }; 601 602 union root_clock_optimization_options { 603 struct { 604 bool dpp: 1; 605 bool dsc: 1; 606 bool hdmistream: 1; 607 bool hdmichar: 1; 608 bool dpstream: 1; 609 bool symclk32_se: 1; 610 bool symclk32_le: 1; 611 bool symclk_fe: 1; 612 bool physymclk: 1; 613 bool dpiasymclk: 1; 614 uint32_t reserved: 22; 615 } bits; 616 uint32_t u32All; 617 }; 618 619 union dpia_debug_options { 620 struct { 621 uint32_t disable_dpia:1; /* bit 0 */ 622 uint32_t force_non_lttpr:1; /* bit 1 */ 623 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 624 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 625 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 626 uint32_t reserved:27; 627 } bits; 628 uint32_t raw; 629 }; 630 631 /* AUX wake work around options 632 * 0: enable/disable work around 633 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 634 * 15-2: reserved 635 * 31-16: timeout in ms 636 */ 637 union aux_wake_wa_options { 638 struct { 639 uint32_t enable_wa : 1; 640 uint32_t use_default_timeout : 1; 641 uint32_t rsvd: 14; 642 uint32_t timeout_ms : 16; 643 } bits; 644 uint32_t raw; 645 }; 646 647 struct dc_debug_data { 648 uint32_t ltFailCount; 649 uint32_t i2cErrorCount; 650 uint32_t auxErrorCount; 651 }; 652 653 struct dc_phy_addr_space_config { 654 struct { 655 uint64_t start_addr; 656 uint64_t end_addr; 657 uint64_t fb_top; 658 uint64_t fb_offset; 659 uint64_t fb_base; 660 uint64_t agp_top; 661 uint64_t agp_bot; 662 uint64_t agp_base; 663 } system_aperture; 664 665 struct { 666 uint64_t page_table_start_addr; 667 uint64_t page_table_end_addr; 668 uint64_t page_table_base_addr; 669 bool base_addr_is_mc_addr; 670 } gart_config; 671 672 bool valid; 673 bool is_hvm_enabled; 674 uint64_t page_table_default_page_addr; 675 }; 676 677 struct dc_virtual_addr_space_config { 678 uint64_t page_table_base_addr; 679 uint64_t page_table_start_addr; 680 uint64_t page_table_end_addr; 681 uint32_t page_table_block_size_in_bytes; 682 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 683 }; 684 685 struct dc_bounding_box_overrides { 686 int sr_exit_time_ns; 687 int sr_enter_plus_exit_time_ns; 688 int urgent_latency_ns; 689 int percent_of_ideal_drambw; 690 int dram_clock_change_latency_ns; 691 int dummy_clock_change_latency_ns; 692 int fclk_clock_change_latency_ns; 693 /* This forces a hard min on the DCFCLK we use 694 * for DML. Unlike the debug option for forcing 695 * DCFCLK, this override affects watermark calculations 696 */ 697 int min_dcfclk_mhz; 698 }; 699 700 struct dc_state; 701 struct resource_pool; 702 struct dce_hwseq; 703 704 /** 705 * struct dc_debug_options - DC debug struct 706 * 707 * This struct provides a simple mechanism for developers to change some 708 * configurations, enable/disable features, and activate extra debug options. 709 * This can be very handy to narrow down whether some specific feature is 710 * causing an issue or not. 711 */ 712 struct dc_debug_options { 713 bool native422_support; 714 bool disable_dsc; 715 enum visual_confirm visual_confirm; 716 int visual_confirm_rect_height; 717 718 bool sanity_checks; 719 bool max_disp_clk; 720 bool surface_trace; 721 bool timing_trace; 722 bool clock_trace; 723 bool validation_trace; 724 bool bandwidth_calcs_trace; 725 int max_downscale_src_width; 726 727 /* stutter efficiency related */ 728 bool disable_stutter; 729 bool use_max_lb; 730 enum dcc_option disable_dcc; 731 732 /** 733 * @pipe_split_policy: Define which pipe split policy is used by the 734 * display core. 735 */ 736 enum pipe_split_policy pipe_split_policy; 737 bool force_single_disp_pipe_split; 738 bool voltage_align_fclk; 739 bool disable_min_fclk; 740 741 bool disable_dfs_bypass; 742 bool disable_dpp_power_gate; 743 bool disable_hubp_power_gate; 744 bool disable_dsc_power_gate; 745 int dsc_min_slice_height_override; 746 int dsc_bpp_increment_div; 747 bool disable_pplib_wm_range; 748 enum wm_report_mode pplib_wm_report_mode; 749 unsigned int min_disp_clk_khz; 750 unsigned int min_dpp_clk_khz; 751 unsigned int min_dram_clk_khz; 752 int sr_exit_time_dpm0_ns; 753 int sr_enter_plus_exit_time_dpm0_ns; 754 int sr_exit_time_ns; 755 int sr_enter_plus_exit_time_ns; 756 int urgent_latency_ns; 757 uint32_t underflow_assert_delay_us; 758 int percent_of_ideal_drambw; 759 int dram_clock_change_latency_ns; 760 bool optimized_watermark; 761 int always_scale; 762 bool disable_pplib_clock_request; 763 bool disable_clock_gate; 764 bool disable_mem_low_power; 765 bool pstate_enabled; 766 bool disable_dmcu; 767 bool disable_psr; 768 bool force_abm_enable; 769 bool disable_stereo_support; 770 bool vsr_support; 771 bool performance_trace; 772 bool az_endpoint_mute_only; 773 bool always_use_regamma; 774 bool recovery_enabled; 775 bool avoid_vbios_exec_table; 776 bool scl_reset_length10; 777 bool hdmi20_disable; 778 bool skip_detection_link_training; 779 uint32_t edid_read_retry_times; 780 unsigned int force_odm_combine; //bit vector based on otg inst 781 unsigned int seamless_boot_odm_combine; 782 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 783 bool disable_z9_mpc; 784 unsigned int force_fclk_khz; 785 bool enable_tri_buf; 786 bool dmub_offload_enabled; 787 bool dmcub_emulation; 788 bool disable_idle_power_optimizations; 789 unsigned int mall_size_override; 790 unsigned int mall_additional_timer_percent; 791 bool mall_error_as_fatal; 792 bool dmub_command_table; /* for testing only */ 793 struct dc_bw_validation_profile bw_val_profile; 794 bool disable_fec; 795 bool disable_48mhz_pwrdwn; 796 /* This forces a hard min on the DCFCLK requested to SMU/PP 797 * watermarks are not affected. 798 */ 799 unsigned int force_min_dcfclk_mhz; 800 int dwb_fi_phase; 801 bool disable_timing_sync; 802 bool cm_in_bypass; 803 int force_clock_mode;/*every mode change.*/ 804 805 bool disable_dram_clock_change_vactive_support; 806 bool validate_dml_output; 807 bool enable_dmcub_surface_flip; 808 bool usbc_combo_phy_reset_wa; 809 bool enable_dram_clock_change_one_display_vactive; 810 /* TODO - remove once tested */ 811 bool legacy_dp2_lt; 812 bool set_mst_en_for_sst; 813 bool disable_uhbr; 814 bool force_dp2_lt_fallback_method; 815 bool ignore_cable_id; 816 union mem_low_power_enable_options enable_mem_low_power; 817 union root_clock_optimization_options root_clock_optimization; 818 bool hpo_optimization; 819 bool force_vblank_alignment; 820 821 /* Enable dmub aux for legacy ddc */ 822 bool enable_dmub_aux_for_legacy_ddc; 823 bool disable_fams; 824 /* FEC/PSR1 sequence enable delay in 100us */ 825 uint8_t fec_enable_delay_in100us; 826 bool enable_driver_sequence_debug; 827 enum det_size crb_alloc_policy; 828 int crb_alloc_policy_min_disp_count; 829 bool disable_z10; 830 bool enable_z9_disable_interface; 831 union dpia_debug_options dpia_debug; 832 bool disable_fixed_vs_aux_timeout_wa; 833 bool force_disable_subvp; 834 bool force_subvp_mclk_switch; 835 bool allow_sw_cursor_fallback; 836 unsigned int force_subvp_num_ways; 837 unsigned int force_mall_ss_num_ways; 838 bool alloc_extra_way_for_cursor; 839 bool force_usr_allow; 840 /* uses value at boot and disables switch */ 841 bool disable_dtb_ref_clk_switch; 842 uint32_t fixed_vs_aux_delay_config_wa; 843 bool extended_blank_optimization; 844 union aux_wake_wa_options aux_wake_wa; 845 uint32_t mst_start_top_delay; 846 uint8_t psr_power_use_phy_fsm; 847 enum dml_hostvm_override_opts dml_hostvm_override; 848 bool dml_disallow_alternate_prefetch_modes; 849 bool use_legacy_soc_bb_mechanism; 850 bool exit_idle_opt_for_cursor_updates; 851 bool enable_single_display_2to1_odm_policy; 852 bool enable_double_buffered_dsc_pg_support; 853 bool enable_dp_dig_pixel_rate_div_policy; 854 enum lttpr_mode lttpr_mode_override; 855 unsigned int dsc_delay_factor_wa_x1000; 856 unsigned int min_prefetch_in_strobe_ns; 857 }; 858 859 struct gpu_info_soc_bounding_box_v1_0; 860 struct dc { 861 struct dc_debug_options debug; 862 struct dc_versions versions; 863 struct dc_caps caps; 864 struct dc_cap_funcs cap_funcs; 865 struct dc_config config; 866 struct dc_bounding_box_overrides bb_overrides; 867 struct dc_bug_wa work_arounds; 868 struct dc_context *ctx; 869 struct dc_phy_addr_space_config vm_pa_config; 870 871 uint8_t link_count; 872 struct dc_link *links[MAX_PIPES * 2]; 873 874 struct dc_state *current_state; 875 struct resource_pool *res_pool; 876 877 struct clk_mgr *clk_mgr; 878 879 /* Display Engine Clock levels */ 880 struct dm_pp_clock_levels sclk_lvls; 881 882 /* Inputs into BW and WM calculations. */ 883 struct bw_calcs_dceip *bw_dceip; 884 struct bw_calcs_vbios *bw_vbios; 885 struct dcn_soc_bounding_box *dcn_soc; 886 struct dcn_ip_params *dcn_ip; 887 struct display_mode_lib dml; 888 889 /* HW functions */ 890 struct hw_sequencer_funcs hwss; 891 struct dce_hwseq *hwseq; 892 893 /* Require to optimize clocks and bandwidth for added/removed planes */ 894 bool optimized_required; 895 bool wm_optimized_required; 896 bool idle_optimizations_allowed; 897 bool enable_c20_dtm_b0; 898 899 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 900 901 /* FBC compressor */ 902 struct compressor *fbc_compressor; 903 904 struct dc_debug_data debug_data; 905 struct dpcd_vendor_signature vendor_signature; 906 907 const char *build_id; 908 struct vm_helper *vm_helper; 909 910 uint32_t *dcn_reg_offsets; 911 uint32_t *nbio_reg_offsets; 912 913 /* Scratch memory */ 914 struct { 915 struct { 916 /* 917 * For matching clock_limits table in driver with table 918 * from PMFW. 919 */ 920 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 921 } update_bw_bounding_box; 922 } scratch; 923 }; 924 925 enum frame_buffer_mode { 926 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 927 FRAME_BUFFER_MODE_ZFB_ONLY, 928 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 929 } ; 930 931 struct dchub_init_data { 932 int64_t zfb_phys_addr_base; 933 int64_t zfb_mc_base_addr; 934 uint64_t zfb_size_in_byte; 935 enum frame_buffer_mode fb_mode; 936 bool dchub_initialzied; 937 bool dchub_info_valid; 938 }; 939 940 struct dc_init_data { 941 struct hw_asic_id asic_id; 942 void *driver; /* ctx */ 943 struct cgs_device *cgs_device; 944 struct dc_bounding_box_overrides bb_overrides; 945 946 int num_virtual_links; 947 /* 948 * If 'vbios_override' not NULL, it will be called instead 949 * of the real VBIOS. Intended use is Diagnostics on FPGA. 950 */ 951 struct dc_bios *vbios_override; 952 enum dce_environment dce_environment; 953 954 struct dmub_offload_funcs *dmub_if; 955 struct dc_reg_helper_state *dmub_offload; 956 957 struct dc_config flags; 958 uint64_t log_mask; 959 960 struct dpcd_vendor_signature vendor_signature; 961 bool force_smu_not_present; 962 /* 963 * IP offset for run time initializaion of register addresses 964 * 965 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 966 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 967 * before them. 968 */ 969 uint32_t *dcn_reg_offsets; 970 uint32_t *nbio_reg_offsets; 971 }; 972 973 struct dc_callback_init { 974 #ifdef CONFIG_DRM_AMD_DC_HDCP 975 struct cp_psp cp_psp; 976 #else 977 uint8_t reserved; 978 #endif 979 }; 980 981 struct dc *dc_create(const struct dc_init_data *init_params); 982 void dc_hardware_init(struct dc *dc); 983 984 int dc_get_vmid_use_vector(struct dc *dc); 985 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 986 /* Returns the number of vmids supported */ 987 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 988 void dc_init_callbacks(struct dc *dc, 989 const struct dc_callback_init *init_params); 990 void dc_deinit_callbacks(struct dc *dc); 991 void dc_destroy(struct dc **dc); 992 993 /******************************************************************************* 994 * Surface Interfaces 995 ******************************************************************************/ 996 997 enum { 998 TRANSFER_FUNC_POINTS = 1025 999 }; 1000 1001 struct dc_hdr_static_metadata { 1002 /* display chromaticities and white point in units of 0.00001 */ 1003 unsigned int chromaticity_green_x; 1004 unsigned int chromaticity_green_y; 1005 unsigned int chromaticity_blue_x; 1006 unsigned int chromaticity_blue_y; 1007 unsigned int chromaticity_red_x; 1008 unsigned int chromaticity_red_y; 1009 unsigned int chromaticity_white_point_x; 1010 unsigned int chromaticity_white_point_y; 1011 1012 uint32_t min_luminance; 1013 uint32_t max_luminance; 1014 uint32_t maximum_content_light_level; 1015 uint32_t maximum_frame_average_light_level; 1016 }; 1017 1018 enum dc_transfer_func_type { 1019 TF_TYPE_PREDEFINED, 1020 TF_TYPE_DISTRIBUTED_POINTS, 1021 TF_TYPE_BYPASS, 1022 TF_TYPE_HWPWL 1023 }; 1024 1025 struct dc_transfer_func_distributed_points { 1026 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1027 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1028 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1029 1030 uint16_t end_exponent; 1031 uint16_t x_point_at_y1_red; 1032 uint16_t x_point_at_y1_green; 1033 uint16_t x_point_at_y1_blue; 1034 }; 1035 1036 enum dc_transfer_func_predefined { 1037 TRANSFER_FUNCTION_SRGB, 1038 TRANSFER_FUNCTION_BT709, 1039 TRANSFER_FUNCTION_PQ, 1040 TRANSFER_FUNCTION_LINEAR, 1041 TRANSFER_FUNCTION_UNITY, 1042 TRANSFER_FUNCTION_HLG, 1043 TRANSFER_FUNCTION_HLG12, 1044 TRANSFER_FUNCTION_GAMMA22, 1045 TRANSFER_FUNCTION_GAMMA24, 1046 TRANSFER_FUNCTION_GAMMA26 1047 }; 1048 1049 1050 struct dc_transfer_func { 1051 struct kref refcount; 1052 enum dc_transfer_func_type type; 1053 enum dc_transfer_func_predefined tf; 1054 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1055 uint32_t sdr_ref_white_level; 1056 union { 1057 struct pwl_params pwl; 1058 struct dc_transfer_func_distributed_points tf_pts; 1059 }; 1060 }; 1061 1062 1063 union dc_3dlut_state { 1064 struct { 1065 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1066 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1067 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1068 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1069 uint32_t mpc_rmu1_mux:4; 1070 uint32_t mpc_rmu2_mux:4; 1071 uint32_t reserved:15; 1072 } bits; 1073 uint32_t raw; 1074 }; 1075 1076 1077 struct dc_3dlut { 1078 struct kref refcount; 1079 struct tetrahedral_params lut_3d; 1080 struct fixed31_32 hdr_multiplier; 1081 union dc_3dlut_state state; 1082 }; 1083 /* 1084 * This structure is filled in by dc_surface_get_status and contains 1085 * the last requested address and the currently active address so the called 1086 * can determine if there are any outstanding flips 1087 */ 1088 struct dc_plane_status { 1089 struct dc_plane_address requested_address; 1090 struct dc_plane_address current_address; 1091 bool is_flip_pending; 1092 bool is_right_eye; 1093 }; 1094 1095 union surface_update_flags { 1096 1097 struct { 1098 uint32_t addr_update:1; 1099 /* Medium updates */ 1100 uint32_t dcc_change:1; 1101 uint32_t color_space_change:1; 1102 uint32_t horizontal_mirror_change:1; 1103 uint32_t per_pixel_alpha_change:1; 1104 uint32_t global_alpha_change:1; 1105 uint32_t hdr_mult:1; 1106 uint32_t rotation_change:1; 1107 uint32_t swizzle_change:1; 1108 uint32_t scaling_change:1; 1109 uint32_t position_change:1; 1110 uint32_t in_transfer_func_change:1; 1111 uint32_t input_csc_change:1; 1112 uint32_t coeff_reduction_change:1; 1113 uint32_t output_tf_change:1; 1114 uint32_t pixel_format_change:1; 1115 uint32_t plane_size_change:1; 1116 uint32_t gamut_remap_change:1; 1117 1118 /* Full updates */ 1119 uint32_t new_plane:1; 1120 uint32_t bpp_change:1; 1121 uint32_t gamma_change:1; 1122 uint32_t bandwidth_change:1; 1123 uint32_t clock_change:1; 1124 uint32_t stereo_format_change:1; 1125 uint32_t lut_3d:1; 1126 uint32_t tmz_changed:1; 1127 uint32_t full_update:1; 1128 } bits; 1129 1130 uint32_t raw; 1131 }; 1132 1133 struct dc_plane_state { 1134 struct dc_plane_address address; 1135 struct dc_plane_flip_time time; 1136 bool triplebuffer_flips; 1137 struct scaling_taps scaling_quality; 1138 struct rect src_rect; 1139 struct rect dst_rect; 1140 struct rect clip_rect; 1141 1142 struct plane_size plane_size; 1143 union dc_tiling_info tiling_info; 1144 1145 struct dc_plane_dcc_param dcc; 1146 1147 struct dc_gamma *gamma_correction; 1148 struct dc_transfer_func *in_transfer_func; 1149 struct dc_bias_and_scale *bias_and_scale; 1150 struct dc_csc_transform input_csc_color_matrix; 1151 struct fixed31_32 coeff_reduction_factor; 1152 struct fixed31_32 hdr_mult; 1153 struct colorspace_transform gamut_remap_matrix; 1154 1155 // TODO: No longer used, remove 1156 struct dc_hdr_static_metadata hdr_static_ctx; 1157 1158 enum dc_color_space color_space; 1159 1160 struct dc_3dlut *lut3d_func; 1161 struct dc_transfer_func *in_shaper_func; 1162 struct dc_transfer_func *blend_tf; 1163 1164 struct dc_transfer_func *gamcor_tf; 1165 enum surface_pixel_format format; 1166 enum dc_rotation_angle rotation; 1167 enum plane_stereo_format stereo_format; 1168 1169 bool is_tiling_rotated; 1170 bool per_pixel_alpha; 1171 bool pre_multiplied_alpha; 1172 bool global_alpha; 1173 int global_alpha_value; 1174 bool visible; 1175 bool flip_immediate; 1176 bool horizontal_mirror; 1177 int layer_index; 1178 1179 union surface_update_flags update_flags; 1180 bool flip_int_enabled; 1181 bool skip_manual_trigger; 1182 1183 /* private to DC core */ 1184 struct dc_plane_status status; 1185 struct dc_context *ctx; 1186 1187 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1188 bool force_full_update; 1189 1190 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1191 1192 /* private to dc_surface.c */ 1193 enum dc_irq_source irq_source; 1194 struct kref refcount; 1195 struct tg_color visual_confirm_color; 1196 1197 bool is_statically_allocated; 1198 }; 1199 1200 struct dc_plane_info { 1201 struct plane_size plane_size; 1202 union dc_tiling_info tiling_info; 1203 struct dc_plane_dcc_param dcc; 1204 enum surface_pixel_format format; 1205 enum dc_rotation_angle rotation; 1206 enum plane_stereo_format stereo_format; 1207 enum dc_color_space color_space; 1208 bool horizontal_mirror; 1209 bool visible; 1210 bool per_pixel_alpha; 1211 bool pre_multiplied_alpha; 1212 bool global_alpha; 1213 int global_alpha_value; 1214 bool input_csc_enabled; 1215 int layer_index; 1216 }; 1217 1218 struct dc_scaling_info { 1219 struct rect src_rect; 1220 struct rect dst_rect; 1221 struct rect clip_rect; 1222 struct scaling_taps scaling_quality; 1223 }; 1224 1225 struct dc_surface_update { 1226 struct dc_plane_state *surface; 1227 1228 /* isr safe update parameters. null means no updates */ 1229 const struct dc_flip_addrs *flip_addr; 1230 const struct dc_plane_info *plane_info; 1231 const struct dc_scaling_info *scaling_info; 1232 struct fixed31_32 hdr_mult; 1233 /* following updates require alloc/sleep/spin that is not isr safe, 1234 * null means no updates 1235 */ 1236 const struct dc_gamma *gamma; 1237 const struct dc_transfer_func *in_transfer_func; 1238 1239 const struct dc_csc_transform *input_csc_color_matrix; 1240 const struct fixed31_32 *coeff_reduction_factor; 1241 const struct dc_transfer_func *func_shaper; 1242 const struct dc_3dlut *lut3d_func; 1243 const struct dc_transfer_func *blend_tf; 1244 const struct colorspace_transform *gamut_remap_matrix; 1245 }; 1246 1247 /* 1248 * Create a new surface with default parameters; 1249 */ 1250 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1251 const struct dc_plane_status *dc_plane_get_status( 1252 const struct dc_plane_state *plane_state); 1253 1254 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1255 void dc_plane_state_release(struct dc_plane_state *plane_state); 1256 1257 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1258 void dc_gamma_release(struct dc_gamma **dc_gamma); 1259 struct dc_gamma *dc_create_gamma(void); 1260 1261 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1262 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1263 struct dc_transfer_func *dc_create_transfer_func(void); 1264 1265 struct dc_3dlut *dc_create_3dlut_func(void); 1266 void dc_3dlut_func_release(struct dc_3dlut *lut); 1267 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1268 1269 void dc_post_update_surfaces_to_stream( 1270 struct dc *dc); 1271 1272 #include "dc_stream.h" 1273 1274 /* 1275 * Structure to store surface/stream associations for validation 1276 */ 1277 struct dc_validation_set { 1278 struct dc_stream_state *stream; 1279 struct dc_plane_state *plane_states[MAX_SURFACES]; 1280 uint8_t plane_count; 1281 }; 1282 1283 bool dc_validate_boot_timing(const struct dc *dc, 1284 const struct dc_sink *sink, 1285 struct dc_crtc_timing *crtc_timing); 1286 1287 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1288 1289 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1290 1291 bool dc_set_generic_gpio_for_stereo(bool enable, 1292 struct gpio_service *gpio_service); 1293 1294 /* 1295 * fast_validate: we return after determining if we can support the new state, 1296 * but before we populate the programming info 1297 */ 1298 enum dc_status dc_validate_global_state( 1299 struct dc *dc, 1300 struct dc_state *new_ctx, 1301 bool fast_validate); 1302 1303 1304 void dc_resource_state_construct( 1305 const struct dc *dc, 1306 struct dc_state *dst_ctx); 1307 1308 bool dc_acquire_release_mpc_3dlut( 1309 struct dc *dc, bool acquire, 1310 struct dc_stream_state *stream, 1311 struct dc_3dlut **lut, 1312 struct dc_transfer_func **shaper); 1313 1314 void dc_resource_state_copy_construct( 1315 const struct dc_state *src_ctx, 1316 struct dc_state *dst_ctx); 1317 1318 void dc_resource_state_copy_construct_current( 1319 const struct dc *dc, 1320 struct dc_state *dst_ctx); 1321 1322 void dc_resource_state_destruct(struct dc_state *context); 1323 1324 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1325 1326 /* 1327 * TODO update to make it about validation sets 1328 * Set up streams and links associated to drive sinks 1329 * The streams parameter is an absolute set of all active streams. 1330 * 1331 * After this call: 1332 * Phy, Encoder, Timing Generator are programmed and enabled. 1333 * New streams are enabled with blank stream; no memory read. 1334 */ 1335 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1336 1337 struct dc_state *dc_create_state(struct dc *dc); 1338 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1339 void dc_retain_state(struct dc_state *context); 1340 void dc_release_state(struct dc_state *context); 1341 1342 /******************************************************************************* 1343 * Link Interfaces 1344 ******************************************************************************/ 1345 1346 struct dpcd_caps { 1347 union dpcd_rev dpcd_rev; 1348 union max_lane_count max_ln_count; 1349 union max_down_spread max_down_spread; 1350 union dprx_feature dprx_feature; 1351 1352 /* valid only for eDP v1.4 or higher*/ 1353 uint8_t edp_supported_link_rates_count; 1354 enum dc_link_rate edp_supported_link_rates[8]; 1355 1356 /* dongle type (DP converter, CV smart dongle) */ 1357 enum display_dongle_type dongle_type; 1358 bool is_dongle_type_one; 1359 /* branch device or sink device */ 1360 bool is_branch_dev; 1361 /* Dongle's downstream count. */ 1362 union sink_count sink_count; 1363 bool is_mst_capable; 1364 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1365 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1366 struct dc_dongle_caps dongle_caps; 1367 1368 uint32_t sink_dev_id; 1369 int8_t sink_dev_id_str[6]; 1370 int8_t sink_hw_revision; 1371 int8_t sink_fw_revision[2]; 1372 1373 uint32_t branch_dev_id; 1374 int8_t branch_dev_name[6]; 1375 int8_t branch_hw_revision; 1376 int8_t branch_fw_revision[2]; 1377 1378 bool allow_invalid_MSA_timing_param; 1379 bool panel_mode_edp; 1380 bool dpcd_display_control_capable; 1381 bool ext_receiver_cap_field_present; 1382 bool set_power_state_capable_edp; 1383 bool dynamic_backlight_capable_edp; 1384 union dpcd_fec_capability fec_cap; 1385 struct dpcd_dsc_capabilities dsc_caps; 1386 struct dc_lttpr_caps lttpr_caps; 1387 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1388 1389 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1390 union dp_main_line_channel_coding_cap channel_coding_cap; 1391 union dp_sink_video_fallback_formats fallback_formats; 1392 union dp_fec_capability1 fec_cap1; 1393 union dp_cable_id cable_id; 1394 uint8_t edp_rev; 1395 union edp_alpm_caps alpm_caps; 1396 struct edp_psr_info psr_info; 1397 }; 1398 1399 union dpcd_sink_ext_caps { 1400 struct { 1401 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1402 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1403 */ 1404 uint8_t sdr_aux_backlight_control : 1; 1405 uint8_t hdr_aux_backlight_control : 1; 1406 uint8_t reserved_1 : 2; 1407 uint8_t oled : 1; 1408 uint8_t reserved : 3; 1409 } bits; 1410 uint8_t raw; 1411 }; 1412 1413 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1414 union hdcp_rx_caps { 1415 struct { 1416 uint8_t version; 1417 uint8_t reserved; 1418 struct { 1419 uint8_t repeater : 1; 1420 uint8_t hdcp_capable : 1; 1421 uint8_t reserved : 6; 1422 } byte0; 1423 } fields; 1424 uint8_t raw[3]; 1425 }; 1426 1427 union hdcp_bcaps { 1428 struct { 1429 uint8_t HDCP_CAPABLE:1; 1430 uint8_t REPEATER:1; 1431 uint8_t RESERVED:6; 1432 } bits; 1433 uint8_t raw; 1434 }; 1435 1436 struct hdcp_caps { 1437 union hdcp_rx_caps rx_caps; 1438 union hdcp_bcaps bcaps; 1439 }; 1440 #endif 1441 1442 #include "dc_link.h" 1443 1444 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1445 1446 /******************************************************************************* 1447 * Sink Interfaces - A sink corresponds to a display output device 1448 ******************************************************************************/ 1449 1450 struct dc_container_id { 1451 // 128bit GUID in binary form 1452 unsigned char guid[16]; 1453 // 8 byte port ID -> ELD.PortID 1454 unsigned int portId[2]; 1455 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1456 unsigned short manufacturerName; 1457 // 2 byte product code -> ELD.ProductCode 1458 unsigned short productCode; 1459 }; 1460 1461 1462 struct dc_sink_dsc_caps { 1463 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1464 // 'false' if they are sink's DSC caps 1465 bool is_virtual_dpcd_dsc; 1466 #if defined(CONFIG_DRM_AMD_DC_DCN) 1467 // 'true' if MST topology supports DSC passthrough for sink 1468 // 'false' if MST topology does not support DSC passthrough 1469 bool is_dsc_passthrough_supported; 1470 #endif 1471 struct dsc_dec_dpcd_caps dsc_dec_caps; 1472 }; 1473 1474 struct dc_sink_fec_caps { 1475 bool is_rx_fec_supported; 1476 bool is_topology_fec_supported; 1477 }; 1478 1479 /* 1480 * The sink structure contains EDID and other display device properties 1481 */ 1482 struct dc_sink { 1483 enum signal_type sink_signal; 1484 struct dc_edid dc_edid; /* raw edid */ 1485 struct dc_edid_caps edid_caps; /* parse display caps */ 1486 struct dc_container_id *dc_container_id; 1487 uint32_t dongle_max_pix_clk; 1488 void *priv; 1489 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1490 bool converter_disable_audio; 1491 1492 struct dc_sink_dsc_caps dsc_caps; 1493 struct dc_sink_fec_caps fec_caps; 1494 1495 bool is_vsc_sdp_colorimetry_supported; 1496 1497 /* private to DC core */ 1498 struct dc_link *link; 1499 struct dc_context *ctx; 1500 1501 uint32_t sink_id; 1502 1503 /* private to dc_sink.c */ 1504 // refcount must be the last member in dc_sink, since we want the 1505 // sink structure to be logically cloneable up to (but not including) 1506 // refcount 1507 struct kref refcount; 1508 }; 1509 1510 void dc_sink_retain(struct dc_sink *sink); 1511 void dc_sink_release(struct dc_sink *sink); 1512 1513 struct dc_sink_init_data { 1514 enum signal_type sink_signal; 1515 struct dc_link *link; 1516 uint32_t dongle_max_pix_clk; 1517 bool converter_disable_audio; 1518 }; 1519 1520 bool dc_extended_blank_supported(struct dc *dc); 1521 1522 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1523 1524 /* Newer interfaces */ 1525 struct dc_cursor { 1526 struct dc_plane_address address; 1527 struct dc_cursor_attributes attributes; 1528 }; 1529 1530 1531 /******************************************************************************* 1532 * Interrupt interfaces 1533 ******************************************************************************/ 1534 enum dc_irq_source dc_interrupt_to_irq_source( 1535 struct dc *dc, 1536 uint32_t src_id, 1537 uint32_t ext_id); 1538 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1539 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1540 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1541 struct dc *dc, uint32_t link_index); 1542 1543 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1544 1545 /******************************************************************************* 1546 * Power Interfaces 1547 ******************************************************************************/ 1548 1549 void dc_set_power_state( 1550 struct dc *dc, 1551 enum dc_acpi_cm_power_state power_state); 1552 void dc_resume(struct dc *dc); 1553 1554 void dc_power_down_on_boot(struct dc *dc); 1555 1556 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1557 /* 1558 * HDCP Interfaces 1559 */ 1560 enum hdcp_message_status dc_process_hdcp_msg( 1561 enum signal_type signal, 1562 struct dc_link *link, 1563 struct hdcp_protection_message *message_info); 1564 #endif 1565 bool dc_is_dmcu_initialized(struct dc *dc); 1566 1567 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1568 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1569 1570 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1571 struct dc_cursor_attributes *cursor_attr); 1572 1573 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1574 1575 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1576 void dc_unlock_memory_clock_frequency(struct dc *dc); 1577 1578 /* set min memory clock to the min required for current mode, max to maxDPM */ 1579 void dc_lock_memory_clock_frequency(struct dc *dc); 1580 1581 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1582 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1583 1584 /* cleanup on driver unload */ 1585 void dc_hardware_release(struct dc *dc); 1586 1587 /* disables fw based mclk switch */ 1588 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1589 1590 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1591 void dc_z10_restore(const struct dc *dc); 1592 void dc_z10_save_init(struct dc *dc); 1593 1594 bool dc_is_dmub_outbox_supported(struct dc *dc); 1595 bool dc_enable_dmub_notifications(struct dc *dc); 1596 1597 void dc_enable_dmub_outbox(struct dc *dc); 1598 1599 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1600 uint32_t link_index, 1601 struct aux_payload *payload); 1602 1603 /* Get dc link index from dpia port index */ 1604 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1605 uint8_t dpia_port_index); 1606 1607 bool dc_process_dmub_set_config_async(struct dc *dc, 1608 uint32_t link_index, 1609 struct set_config_cmd_payload *payload, 1610 struct dmub_notification *notify); 1611 1612 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1613 uint32_t link_index, 1614 uint8_t mst_alloc_slots, 1615 uint8_t *mst_slots_in_use); 1616 1617 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 1618 uint32_t hpd_int_enable); 1619 1620 /******************************************************************************* 1621 * DSC Interfaces 1622 ******************************************************************************/ 1623 #include "dc_dsc.h" 1624 1625 /******************************************************************************* 1626 * Disable acc mode Interfaces 1627 ******************************************************************************/ 1628 void dc_disable_accelerated_mode(struct dc *dc); 1629 1630 #endif /* DC_INTERFACE_H_ */ 1631