1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
32
33 #define PT2PT_LocalID 1
34 #define PT2PT_RemoteID 2
35
36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
40
41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 0 */
43
44 #define FCELSSIZE 1024 /* maximum ELS transfer size */
45
46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93 };
94
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET 0x1
97 #define FC4_FEATURE_INIT 0x2
98 #define FC4_FEATURE_NVME_DISC 0x4
99
100 enum rft_word0 {
101 RFT_FCP_REG = (0x1 << 8),
102 };
103
104 enum rft_word1 {
105 RFT_NVME_REG = (0x1 << 8),
106 };
107
108 enum rft_word3 {
109 RFT_APP_SERV_REG = (0x1 << 0),
110 };
111
112 struct lpfc_sli_ct_request {
113 /* Structure is in Big Endian format */
114 union CtRevisionId RevisionId;
115 uint8_t FsType;
116 uint8_t FsSubType;
117 uint8_t Options;
118 uint8_t Rsrvd1;
119 union CtCommandResponse CommandResponse;
120 uint8_t Rsrvd2;
121 uint8_t ReasonCode;
122 uint8_t Explanation;
123 uint8_t VendorUnique;
124 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
125
126 union {
127 uint32_t PortID;
128 struct gid {
129 uint8_t PortType; /* for GID_PT requests */
130 #define GID_PT_N_PORT 1
131 uint8_t DomainScope;
132 uint8_t AreaScope;
133 uint8_t Fc4Type; /* for GID_FT requests */
134 } gid;
135 struct gid_ff {
136 uint8_t Flags;
137 uint8_t DomainScope;
138 uint8_t AreaScope;
139 uint8_t rsvd1;
140 uint8_t rsvd2;
141 uint8_t rsvd3;
142 uint8_t Fc4FBits;
143 uint8_t Fc4Type;
144 } gid_ff;
145 struct rft {
146 __be32 port_id; /* For RFT_ID requests */
147
148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */
149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */
150 __be32 word2;
151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */
152 __be32 word[4];
153 } rft;
154 struct rnn {
155 uint32_t PortId; /* For RNN_ID requests */
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn { /* For RSNN_ID requests */
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id { /* For DA_ID requests */
164 uint32_t port_id;
165 } da_id;
166 struct rspn { /* For RSPN_ID requests */
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct gff {
172 uint32_t PortId;
173 } gff;
174 struct gff_acc {
175 uint8_t fbits[128];
176 } gff_acc;
177 struct gft {
178 uint32_t PortId;
179 } gft;
180 struct gft_acc {
181 uint32_t fc4_types[8];
182 } gft_acc;
183 #define FCP_TYPE_FEATURE_OFFSET 7
184 struct rff {
185 uint32_t PortId;
186 uint8_t reserved[2];
187 uint8_t fbits;
188 uint8_t type_code; /* type=8 for FCP */
189 } rff;
190 } un;
191 };
192
193 #define LPFC_MAX_CT_SIZE (60 * 4096)
194
195 #define SLI_CT_REVISION 1
196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 sizeof(struct gid))
198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 sizeof(struct gid_ff))
200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 sizeof(struct gff))
202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 sizeof(struct gft))
204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 sizeof(struct rft))
206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 sizeof(struct rff))
208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 sizeof(struct rnn))
210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 sizeof(struct rsnn))
212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 sizeof(struct da_id))
214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
215 sizeof(struct rspn))
216
217 /*
218 * FsType Definitions
219 */
220
221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
222 #define SLI_CT_TIME_SERVICE 0xFB
223 #define SLI_CT_DIRECTORY_SERVICE 0xFC
224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225
226 /*
227 * Directory Service Subtypes
228 */
229
230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
231
232 /*
233 * Response Codes
234 */
235
236 #define SLI_CT_RESPONSE_FS_RJT 0x8001
237 #define SLI_CT_RESPONSE_FS_ACC 0x8002
238
239 /*
240 * Reason Codes
241 */
242
243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244 #define SLI_CT_INVALID_COMMAND 0x01
245 #define SLI_CT_INVALID_VERSION 0x02
246 #define SLI_CT_LOGICAL_ERROR 0x03
247 #define SLI_CT_INVALID_IU_SIZE 0x04
248 #define SLI_CT_LOGICAL_BUSY 0x05
249 #define SLI_CT_PROTOCOL_ERROR 0x07
250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259 #define SLI_CT_VENDOR_UNIQUE 0xff
260
261 /*
262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
263 */
264
265 #define SLI_CT_NO_PORT_ID 0x01
266 #define SLI_CT_NO_PORT_NAME 0x02
267 #define SLI_CT_NO_NODE_NAME 0x03
268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269 #define SLI_CT_NO_IP_ADDRESS 0x05
270 #define SLI_CT_NO_IPA 0x06
271 #define SLI_CT_NO_FC4_TYPES 0x07
272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274 #define SLI_CT_NO_PORT_TYPE 0x0A
275 #define SLI_CT_ACCESS_DENIED 0x10
276 #define SLI_CT_INVALID_PORT_ID 0x11
277 #define SLI_CT_DATABASE_EMPTY 0x12
278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40
279
280 /*
281 * Name Server Command Codes
282 */
283
284 #define SLI_CTNS_GA_NXT 0x0100
285 #define SLI_CTNS_GPN_ID 0x0112
286 #define SLI_CTNS_GNN_ID 0x0113
287 #define SLI_CTNS_GCS_ID 0x0114
288 #define SLI_CTNS_GFT_ID 0x0117
289 #define SLI_CTNS_GSPN_ID 0x0118
290 #define SLI_CTNS_GPT_ID 0x011A
291 #define SLI_CTNS_GFF_ID 0x011F
292 #define SLI_CTNS_GID_PN 0x0121
293 #define SLI_CTNS_GID_NN 0x0131
294 #define SLI_CTNS_GIP_NN 0x0135
295 #define SLI_CTNS_GIPA_NN 0x0136
296 #define SLI_CTNS_GSNN_NN 0x0139
297 #define SLI_CTNS_GNN_IP 0x0153
298 #define SLI_CTNS_GIPA_IP 0x0156
299 #define SLI_CTNS_GID_FT 0x0171
300 #define SLI_CTNS_GID_FF 0x01F1
301 #define SLI_CTNS_GID_PT 0x01A1
302 #define SLI_CTNS_RPN_ID 0x0212
303 #define SLI_CTNS_RNN_ID 0x0213
304 #define SLI_CTNS_RCS_ID 0x0214
305 #define SLI_CTNS_RFT_ID 0x0217
306 #define SLI_CTNS_RSPN_ID 0x0218
307 #define SLI_CTNS_RPT_ID 0x021A
308 #define SLI_CTNS_RFF_ID 0x021F
309 #define SLI_CTNS_RIP_NN 0x0235
310 #define SLI_CTNS_RIPA_NN 0x0236
311 #define SLI_CTNS_RSNN_NN 0x0239
312 #define SLI_CTNS_DA_ID 0x0300
313
314 /*
315 * Port Types
316 */
317
318 #define SLI_CTPT_N_PORT 0x01
319 #define SLI_CTPT_NL_PORT 0x02
320 #define SLI_CTPT_FNL_PORT 0x03
321 #define SLI_CTPT_IP 0x04
322 #define SLI_CTPT_FCP 0x08
323 #define SLI_CTPT_NVME 0x28
324 #define SLI_CTPT_NX_PORT 0x7F
325 #define SLI_CTPT_F_PORT 0x81
326 #define SLI_CTPT_FL_PORT 0x82
327 #define SLI_CTPT_E_PORT 0x84
328
329 #define SLI_CT_LAST_ENTRY 0x80000000
330
331 /* Fibre Channel Service Parameter definitions */
332
333 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
334 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
335 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
336 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
337
338 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
339 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
340 #define FC_PH3 0x20 /* FC-PH-3 version */
341
342 #define FF_FRAME_SIZE 2048
343
344 struct lpfc_name {
345 union {
346 struct {
347 #ifdef __BIG_ENDIAN_BITFIELD
348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
350 8:11 of IEEE ext */
351 #else /* __LITTLE_ENDIAN_BITFIELD */
352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
353 8:11 of IEEE ext */
354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
355 #endif
356
357 #define NAME_IEEE 0x1 /* IEEE name - nameType */
358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
359 #define NAME_FC_TYPE 0x3 /* FC native name type */
360 #define NAME_IP_TYPE 0x4 /* IP address */
361 #define NAME_CCITT_TYPE 0xC
362 #define NAME_CCITT_GR_TYPE 0xE
363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
364 extended Lsb */
365 uint8_t IEEE[6]; /* FC IEEE address */
366 } s;
367 uint8_t wwn[8];
368 uint64_t name;
369 } u;
370 };
371
372 struct csp {
373 uint8_t fcphHigh; /* FC Word 0, byte 0 */
374 uint8_t fcphLow;
375 uint8_t bbCreditMsb;
376 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
377
378 /*
379 * Word 1 Bit 31 in common service parameter is overloaded.
380 * Word 1 Bit 31 in FLOGI request is multiple NPort request
381 * Word 1 Bit 31 in FLOGI response is clean address bit
382 */
383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
384 /*
385 * Word 1 Bit 30 in common service parameter is overloaded.
386 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
387 * Word 1 Bit 30 in PLOGI request is random offset
388 */
389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
390 /*
391 * Word 1 Bit 29 in common service parameter is overloaded.
392 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
393 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
394 */
395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
396 #ifdef __BIG_ENDIAN_BITFIELD
397 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
398 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
399 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
400 uint16_t fPort:1; /* FC Word 1, bit 28 */
401 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
402 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
403 uint16_t multicast:1; /* FC Word 1, bit 25 */
404 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
405
406 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */
407 uint16_t simplex:1; /* FC Word 1, bit 22 */
408 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
409 uint16_t dhd:1; /* FC Word 1, bit 18 */
410 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
411 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
412 #else /* __LITTLE_ENDIAN_BITFIELD */
413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
414 uint16_t multicast:1; /* FC Word 1, bit 25 */
415 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
416 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
417 uint16_t fPort:1; /* FC Word 1, bit 28 */
418 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
419 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
420 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
421
422 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
423 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
424 uint16_t dhd:1; /* FC Word 1, bit 18 */
425 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
426 uint16_t simplex:1; /* FC Word 1, bit 22 */
427 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */
428 #endif
429
430 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
431 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
432 union {
433 struct {
434 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
435
436 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
437 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
438
439 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
440 } nPort;
441 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
442 } w2;
443
444 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
445 };
446
447 struct class_parms {
448 #ifdef __BIG_ENDIAN_BITFIELD
449 uint8_t classValid:1; /* FC Word 0, bit 31 */
450 uint8_t intermix:1; /* FC Word 0, bit 30 */
451 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
452 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
453 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
455 #else /* __LITTLE_ENDIAN_BITFIELD */
456 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
457 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
458 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
459 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
460 uint8_t intermix:1; /* FC Word 0, bit 30 */
461 uint8_t classValid:1; /* FC Word 0, bit 31 */
462
463 #endif
464
465 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
466
467 #ifdef __BIG_ENDIAN_BITFIELD
468 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
469 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
470 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
471 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
473 #else /* __LITTLE_ENDIAN_BITFIELD */
474 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
475 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
476 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
477 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
478 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
479 #endif
480
481 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
482
483 #ifdef __BIG_ENDIAN_BITFIELD
484 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
485 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
486 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
487 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
488 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
490 #else /* __LITTLE_ENDIAN_BITFIELD */
491 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
492 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
493 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
494 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
495 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
496 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
497 #endif
498
499 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
500 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
501 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
502
503 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
504 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
505 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
506 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
507
508 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
509 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
510 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
511 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
512 };
513
514 struct serv_parm { /* Structure is in Big Endian format */
515 struct csp cmn;
516 struct lpfc_name portName;
517 struct lpfc_name nodeName;
518 struct class_parms cls1;
519 struct class_parms cls2;
520 struct class_parms cls3;
521 struct class_parms cls4;
522 union {
523 uint8_t vendorVersion[16];
524 struct {
525 uint32_t vid;
526 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
527 uint32_t flags;
528 #define LPFC_VV_SUPPRESS_RSP 1
529 } vv;
530 } un;
531 };
532
533 /*
534 * Virtual Fabric Tagging Header
535 */
536 struct fc_vft_header {
537 uint32_t word0;
538 #define fc_vft_hdr_r_ctl_SHIFT 24
539 #define fc_vft_hdr_r_ctl_MASK 0xFF
540 #define fc_vft_hdr_r_ctl_WORD word0
541 #define fc_vft_hdr_ver_SHIFT 22
542 #define fc_vft_hdr_ver_MASK 0x3
543 #define fc_vft_hdr_ver_WORD word0
544 #define fc_vft_hdr_type_SHIFT 18
545 #define fc_vft_hdr_type_MASK 0xF
546 #define fc_vft_hdr_type_WORD word0
547 #define fc_vft_hdr_e_SHIFT 16
548 #define fc_vft_hdr_e_MASK 0x1
549 #define fc_vft_hdr_e_WORD word0
550 #define fc_vft_hdr_priority_SHIFT 13
551 #define fc_vft_hdr_priority_MASK 0x7
552 #define fc_vft_hdr_priority_WORD word0
553 #define fc_vft_hdr_vf_id_SHIFT 1
554 #define fc_vft_hdr_vf_id_MASK 0xFFF
555 #define fc_vft_hdr_vf_id_WORD word0
556 uint32_t word1;
557 #define fc_vft_hdr_hopct_SHIFT 24
558 #define fc_vft_hdr_hopct_MASK 0xFF
559 #define fc_vft_hdr_hopct_WORD word1
560 };
561
562 #include <uapi/scsi/fc/fc_els.h>
563
564 /*
565 * Extended Link Service LS_COMMAND codes (Payload Word 0)
566 */
567 #ifdef __BIG_ENDIAN_BITFIELD
568 #define ELS_CMD_MASK 0xffff0000
569 #define ELS_RSP_MASK 0xff000000
570 #define ELS_CMD_LS_RJT 0x01000000
571 #define ELS_CMD_ACC 0x02000000
572 #define ELS_CMD_PLOGI 0x03000000
573 #define ELS_CMD_FLOGI 0x04000000
574 #define ELS_CMD_LOGO 0x05000000
575 #define ELS_CMD_ABTX 0x06000000
576 #define ELS_CMD_RCS 0x07000000
577 #define ELS_CMD_RES 0x08000000
578 #define ELS_CMD_RSS 0x09000000
579 #define ELS_CMD_RSI 0x0A000000
580 #define ELS_CMD_ESTS 0x0B000000
581 #define ELS_CMD_ESTC 0x0C000000
582 #define ELS_CMD_ADVC 0x0D000000
583 #define ELS_CMD_RTV 0x0E000000
584 #define ELS_CMD_RLS 0x0F000000
585 #define ELS_CMD_ECHO 0x10000000
586 #define ELS_CMD_TEST 0x11000000
587 #define ELS_CMD_RRQ 0x12000000
588 #define ELS_CMD_REC 0x13000000
589 #define ELS_CMD_RDP 0x18000000
590 #define ELS_CMD_RDF 0x19000000
591 #define ELS_CMD_PRLI 0x20100014
592 #define ELS_CMD_NVMEPRLI 0x20140018
593 #define ELS_CMD_PRLO 0x21100014
594 #define ELS_CMD_PRLO_ACC 0x02100014
595 #define ELS_CMD_PDISC 0x50000000
596 #define ELS_CMD_FDISC 0x51000000
597 #define ELS_CMD_ADISC 0x52000000
598 #define ELS_CMD_FARP 0x54000000
599 #define ELS_CMD_FARPR 0x55000000
600 #define ELS_CMD_RPL 0x57000000
601 #define ELS_CMD_FAN 0x60000000
602 #define ELS_CMD_RSCN 0x61040000
603 #define ELS_CMD_RSCN_XMT 0x61040008
604 #define ELS_CMD_SCR 0x62000000
605 #define ELS_CMD_RNID 0x78000000
606 #define ELS_CMD_LIRR 0x7A000000
607 #define ELS_CMD_LCB 0x81000000
608 #define ELS_CMD_FPIN 0x16000000
609 #define ELS_CMD_EDC 0x17000000
610 #define ELS_CMD_QFPA 0xB0000000
611 #define ELS_CMD_UVEM 0xB1000000
612 #else /* __LITTLE_ENDIAN_BITFIELD */
613 #define ELS_CMD_MASK 0xffff
614 #define ELS_RSP_MASK 0xff
615 #define ELS_CMD_LS_RJT 0x01
616 #define ELS_CMD_ACC 0x02
617 #define ELS_CMD_PLOGI 0x03
618 #define ELS_CMD_FLOGI 0x04
619 #define ELS_CMD_LOGO 0x05
620 #define ELS_CMD_ABTX 0x06
621 #define ELS_CMD_RCS 0x07
622 #define ELS_CMD_RES 0x08
623 #define ELS_CMD_RSS 0x09
624 #define ELS_CMD_RSI 0x0A
625 #define ELS_CMD_ESTS 0x0B
626 #define ELS_CMD_ESTC 0x0C
627 #define ELS_CMD_ADVC 0x0D
628 #define ELS_CMD_RTV 0x0E
629 #define ELS_CMD_RLS 0x0F
630 #define ELS_CMD_ECHO 0x10
631 #define ELS_CMD_TEST 0x11
632 #define ELS_CMD_RRQ 0x12
633 #define ELS_CMD_REC 0x13
634 #define ELS_CMD_RDP 0x18
635 #define ELS_CMD_RDF 0x19
636 #define ELS_CMD_PRLI 0x14001020
637 #define ELS_CMD_NVMEPRLI 0x18001420
638 #define ELS_CMD_PRLO 0x14001021
639 #define ELS_CMD_PRLO_ACC 0x14001002
640 #define ELS_CMD_PDISC 0x50
641 #define ELS_CMD_FDISC 0x51
642 #define ELS_CMD_ADISC 0x52
643 #define ELS_CMD_FARP 0x54
644 #define ELS_CMD_FARPR 0x55
645 #define ELS_CMD_RPL 0x57
646 #define ELS_CMD_FAN 0x60
647 #define ELS_CMD_RSCN 0x0461
648 #define ELS_CMD_RSCN_XMT 0x08000461
649 #define ELS_CMD_SCR 0x62
650 #define ELS_CMD_RNID 0x78
651 #define ELS_CMD_LIRR 0x7A
652 #define ELS_CMD_LCB 0x81
653 #define ELS_CMD_FPIN ELS_FPIN
654 #define ELS_CMD_EDC ELS_EDC
655 #define ELS_CMD_QFPA 0xB0
656 #define ELS_CMD_UVEM 0xB1
657 #endif
658
659 /*
660 * LS_RJT Payload Definition
661 */
662
663 struct ls_rjt { /* Structure is in Big Endian format */
664 union {
665 __be32 ls_rjt_error_be;
666 uint32_t lsRjtError;
667 struct {
668 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
669
670 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
671 /* LS_RJT reason codes */
672 #define LSRJT_INVALID_CMD 0x01
673 #define LSRJT_LOGICAL_ERR 0x03
674 #define LSRJT_LOGICAL_BSY 0x05
675 #define LSRJT_PROTOCOL_ERR 0x07
676 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
677 #define LSRJT_CMD_UNSUPPORTED 0x0B
678 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
679
680 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
681 /* LS_RJT reason explanation */
682 #define LSEXP_NOTHING_MORE 0x00
683 #define LSEXP_SPARM_OPTIONS 0x01
684 #define LSEXP_SPARM_ICTL 0x03
685 #define LSEXP_SPARM_RCTL 0x05
686 #define LSEXP_SPARM_RCV_SIZE 0x07
687 #define LSEXP_SPARM_CONCUR_SEQ 0x09
688 #define LSEXP_SPARM_CREDIT 0x0B
689 #define LSEXP_INVALID_PNAME 0x0D
690 #define LSEXP_INVALID_NNAME 0x0E
691 #define LSEXP_INVALID_CSP 0x0F
692 #define LSEXP_INVALID_ASSOC_HDR 0x11
693 #define LSEXP_ASSOC_HDR_REQ 0x13
694 #define LSEXP_INVALID_O_SID 0x15
695 #define LSEXP_INVALID_OX_RX 0x17
696 #define LSEXP_CMD_IN_PROGRESS 0x19
697 #define LSEXP_PORT_LOGIN_REQ 0x1E
698 #define LSEXP_INVALID_NPORT_ID 0x1F
699 #define LSEXP_INVALID_SEQ_ID 0x21
700 #define LSEXP_INVALID_XCHG 0x23
701 #define LSEXP_INACTIVE_XCHG 0x25
702 #define LSEXP_RQ_REQUIRED 0x27
703 #define LSEXP_OUT_OF_RESOURCE 0x29
704 #define LSEXP_CANT_GIVE_DATA 0x2A
705 #define LSEXP_REQ_UNSUPPORTED 0x2C
706 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
707 } b;
708 } un;
709 };
710
711 /*
712 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
713 */
714
715 typedef struct _LOGO { /* Structure is in Big Endian format */
716 union {
717 uint32_t nPortId32; /* Access nPortId as a word */
718 struct {
719 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
720 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
721 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
722 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
723 } b;
724 } un;
725 struct lpfc_name portName; /* N_port name field */
726 } LOGO;
727
728 /*
729 * FCP Login (PRLI Request / ACC) Payload Definition
730 */
731
732 #define PRLX_PAGE_LEN 0x10
733 #define TPRLO_PAGE_LEN 0x14
734
735 typedef struct _PRLI { /* Structure is in Big Endian format */
736 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
737
738 #define PRLI_FCP_TYPE 0x08
739 #define PRLI_NVME_TYPE 0x28
740 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
741
742 #ifdef __BIG_ENDIAN_BITFIELD
743 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
744 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
745 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
746
747 /* ACC = imagePairEstablished */
748 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
749 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
750 #else /* __LITTLE_ENDIAN_BITFIELD */
751 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
752 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
753 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
754 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
755 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
756 /* ACC = imagePairEstablished */
757 #endif
758
759 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
760 #define PRLI_NO_RESOURCES 0x2
761 #define PRLI_INIT_INCOMPLETE 0x3
762 #define PRLI_NO_SUCH_PA 0x4
763 #define PRLI_PREDEF_CONFIG 0x5
764 #define PRLI_PARTIAL_SUCCESS 0x6
765 #define PRLI_INVALID_PAGE_CNT 0x7
766 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
767
768 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
769
770 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
771
772 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
773 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
774
775 #ifdef __BIG_ENDIAN_BITFIELD
776 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
777 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
778 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
779 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
780 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
781 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
782 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
783 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
784 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
785 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
786 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
787 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
788 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
789 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
790 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
791 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
792 #else /* __LITTLE_ENDIAN_BITFIELD */
793 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
794 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
795 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
796 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
797 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
798 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
799 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
800 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
801 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
802 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
803 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
804 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
805 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
806 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
807 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
808 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
809 #endif
810 } PRLI;
811
812 /*
813 * FCP Logout (PRLO Request / ACC) Payload Definition
814 */
815
816 typedef struct _PRLO { /* Structure is in Big Endian format */
817 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
818
819 #define PRLO_FCP_TYPE 0x08
820 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
821
822 #ifdef __BIG_ENDIAN_BITFIELD
823 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
824 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
825 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
826 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
827 #else /* __LITTLE_ENDIAN_BITFIELD */
828 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
829 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
830 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
831 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
832 #endif
833
834 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
835 #define PRLO_NO_SUCH_IMAGE 0x4
836 #define PRLO_INVALID_PAGE_CNT 0x7
837
838 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
839
840 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
841
842 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
843
844 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
845 } PRLO;
846
847 typedef struct _ADISC { /* Structure is in Big Endian format */
848 uint32_t hardAL_PA;
849 struct lpfc_name portName;
850 struct lpfc_name nodeName;
851 uint32_t DID;
852 } __packed ADISC;
853
854 typedef struct _FARP { /* Structure is in Big Endian format */
855 uint32_t Mflags:8;
856 uint32_t Odid:24;
857 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
858 action */
859 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
860 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
861 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
862 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
863 supported */
864 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
865 supported */
866 uint32_t Rflags:8;
867 uint32_t Rdid:24;
868 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
869 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
870 struct lpfc_name OportName;
871 struct lpfc_name OnodeName;
872 struct lpfc_name RportName;
873 struct lpfc_name RnodeName;
874 uint8_t Oipaddr[16];
875 uint8_t Ripaddr[16];
876 } FARP;
877
878 typedef struct _FAN { /* Structure is in Big Endian format */
879 uint32_t Fdid;
880 struct lpfc_name FportName;
881 struct lpfc_name FnodeName;
882 } __packed FAN;
883
884 typedef struct _SCR { /* Structure is in Big Endian format */
885 uint8_t resvd1;
886 uint8_t resvd2;
887 uint8_t resvd3;
888 uint8_t Function;
889 #define SCR_FUNC_FABRIC 0x01
890 #define SCR_FUNC_NPORT 0x02
891 #define SCR_FUNC_FULL 0x03
892 #define SCR_CLEAR 0xff
893 } SCR;
894
895 typedef struct _RNID_TOP_DISC {
896 struct lpfc_name portName;
897 uint8_t resvd[8];
898 uint32_t unitType;
899 #define RNID_HBA 0x7
900 #define RNID_HOST 0xa
901 #define RNID_DRIVER 0xd
902 uint32_t physPort;
903 uint32_t attachedNodes;
904 uint16_t ipVersion;
905 #define RNID_IPV4 0x1
906 #define RNID_IPV6 0x2
907 uint16_t UDPport;
908 uint8_t ipAddr[16];
909 uint16_t resvd1;
910 uint16_t flags;
911 #define RNID_TD_SUPPORT 0x1
912 #define RNID_LP_VALID 0x2
913 } RNID_TOP_DISC;
914
915 typedef struct _RNID { /* Structure is in Big Endian format */
916 uint8_t Format;
917 #define RNID_TOPOLOGY_DISC 0xdf
918 uint8_t CommonLen;
919 uint8_t resvd1;
920 uint8_t SpecificLen;
921 struct lpfc_name portName;
922 struct lpfc_name nodeName;
923 union {
924 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
925 } un;
926 } __packed RNID;
927
928 struct RLS { /* Structure is in Big Endian format */
929 uint32_t rls;
930 #define rls_rsvd_SHIFT 24
931 #define rls_rsvd_MASK 0x000000ff
932 #define rls_rsvd_WORD rls
933 #define rls_did_SHIFT 0
934 #define rls_did_MASK 0x00ffffff
935 #define rls_did_WORD rls
936 };
937
938 struct RLS_RSP { /* Structure is in Big Endian format */
939 uint32_t linkFailureCnt;
940 uint32_t lossSyncCnt;
941 uint32_t lossSignalCnt;
942 uint32_t primSeqErrCnt;
943 uint32_t invalidXmitWord;
944 uint32_t crcCnt;
945 };
946
947 struct RRQ { /* Structure is in Big Endian format */
948 uint32_t rrq;
949 #define rrq_rsvd_SHIFT 24
950 #define rrq_rsvd_MASK 0x000000ff
951 #define rrq_rsvd_WORD rrq
952 #define rrq_did_SHIFT 0
953 #define rrq_did_MASK 0x00ffffff
954 #define rrq_did_WORD rrq
955 uint32_t rrq_exchg;
956 #define rrq_oxid_SHIFT 16
957 #define rrq_oxid_MASK 0xffff
958 #define rrq_oxid_WORD rrq_exchg
959 #define rrq_rxid_SHIFT 0
960 #define rrq_rxid_MASK 0xffff
961 #define rrq_rxid_WORD rrq_exchg
962 };
963
964 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
965 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
966
967 struct RTV_RSP { /* Structure is in Big Endian format */
968 uint32_t ratov;
969 uint32_t edtov;
970 uint32_t qtov;
971 #define qtov_rsvd0_SHIFT 28
972 #define qtov_rsvd0_MASK 0x0000000f
973 #define qtov_rsvd0_WORD qtov /* reserved */
974 #define qtov_edtovres_SHIFT 27
975 #define qtov_edtovres_MASK 0x00000001
976 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
977 #define qtov__rsvd1_SHIFT 19
978 #define qtov_rsvd1_MASK 0x0000003f
979 #define qtov_rsvd1_WORD qtov /* reserved */
980 #define qtov_rttov_SHIFT 18
981 #define qtov_rttov_MASK 0x00000001
982 #define qtov_rttov_WORD qtov /* R_T_TOV value */
983 #define qtov_rsvd2_SHIFT 0
984 #define qtov_rsvd2_MASK 0x0003ffff
985 #define qtov_rsvd2_WORD qtov /* reserved */
986 };
987
988
989 typedef struct _RPL { /* Structure is in Big Endian format */
990 uint32_t maxsize;
991 uint32_t index;
992 } RPL;
993
994 typedef struct _PORT_NUM_BLK {
995 uint32_t portNum;
996 uint32_t portID;
997 struct lpfc_name portName;
998 } PORT_NUM_BLK;
999
1000 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
1001 uint32_t listLen;
1002 uint32_t index;
1003 PORT_NUM_BLK port_num_blk;
1004 } RPL_RSP;
1005
1006 /* This is used for RSCN command */
1007 typedef struct _D_ID { /* Structure is in Big Endian format */
1008 union {
1009 uint32_t word;
1010 struct {
1011 #ifdef __BIG_ENDIAN_BITFIELD
1012 uint8_t resv;
1013 uint8_t domain;
1014 uint8_t area;
1015 uint8_t id;
1016 #else /* __LITTLE_ENDIAN_BITFIELD */
1017 uint8_t id;
1018 uint8_t area;
1019 uint8_t domain;
1020 uint8_t resv;
1021 #endif
1022 } b;
1023 } un;
1024 } D_ID;
1025
1026 #define RSCN_ADDRESS_FORMAT_PORT 0x0
1027 #define RSCN_ADDRESS_FORMAT_AREA 0x1
1028 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1029 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1030 #define RSCN_ADDRESS_FORMAT_MASK 0x3
1031
1032 /*
1033 * Structure to define all ELS Payload types
1034 */
1035
1036 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1037 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1038 uint8_t elsByte1;
1039 uint8_t elsByte2;
1040 uint8_t elsByte3;
1041 union {
1042 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1043 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1044 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1045 PRLI prli; /* Payload for PRLI/ACC */
1046 PRLO prlo; /* Payload for PRLO/ACC */
1047 ADISC adisc; /* Payload for ADISC/ACC */
1048 FARP farp; /* Payload for FARP/ACC */
1049 FAN fan; /* Payload for FAN */
1050 SCR scr; /* Payload for SCR/ACC */
1051 RNID rnid; /* Payload for RNID */
1052 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1053 } un;
1054 } ELS_PKT;
1055
1056 /*
1057 * Link Cable Beacon (LCB) ELS Frame
1058 */
1059
1060 struct fc_lcb_request_frame {
1061 uint32_t lcb_command; /* ELS command opcode (0x81) */
1062 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1063 #define LPFC_LCB_ON 0x1
1064 #define LPFC_LCB_OFF 0x2
1065 uint8_t reserved[2];
1066 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1067 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1068 #define LPFC_LCB_GREEN 0x1
1069 #define LPFC_LCB_AMBER 0x2
1070 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1071 #define LCB_CAPABILITY_DURATION 1
1072 #define BEACON_VERSION_V1 1
1073 #define BEACON_VERSION_V0 0
1074 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1075 };
1076
1077 /*
1078 * Link Cable Beacon (LCB) ELS Response Frame
1079 */
1080 struct fc_lcb_res_frame {
1081 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1082 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1083 uint8_t reserved[2];
1084 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1085 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1086 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1087 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1088 };
1089
1090 /*
1091 * Read Diagnostic Parameters (RDP) ELS frame.
1092 */
1093 #define SFF_PG0_IDENT_SFP 0x3
1094
1095 #define SFP_FLAG_PT_OPTICAL 0x0
1096 #define SFP_FLAG_PT_SWLASER 0x01
1097 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1098 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1099 #define SFP_FLAG_PT_MASK 0x0F
1100 #define SFP_FLAG_PT_SHIFT 0
1101
1102 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1103 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1104 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1105
1106 #define SFP_FLAG_IS_DESC_VALID 0x01
1107 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1108 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1109
1110 #define SFP_FLAG_CT_UNKNOWN 0x0
1111 #define SFP_FLAG_CT_SFP_PLUS 0x01
1112 #define SFP_FLAG_CT_MASK 0x3C
1113 #define SFP_FLAG_CT_SHIFT 6
1114
1115 struct fc_rdp_port_name_info {
1116 uint8_t wwnn[8];
1117 uint8_t wwpn[8];
1118 };
1119
1120
1121 /*
1122 * Link Error Status Block Structure (FC-FS-3) for RDP
1123 * This similar to RPS ELS
1124 */
1125 struct fc_link_status {
1126 uint32_t link_failure_cnt;
1127 uint32_t loss_of_synch_cnt;
1128 uint32_t loss_of_signal_cnt;
1129 uint32_t primitive_seq_proto_err;
1130 uint32_t invalid_trans_word;
1131 uint32_t invalid_crc_cnt;
1132
1133 };
1134
1135 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1136 struct fc_rdp_port_name_desc {
1137 uint32_t tag; /* 0001 0003h */
1138 uint32_t length; /* set to size of payload struct */
1139 struct fc_rdp_port_name_info port_names;
1140 };
1141
1142
1143 struct fc_rdp_fec_info {
1144 uint32_t CorrectedBlocks;
1145 uint32_t UncorrectableBlocks;
1146 };
1147
1148 #define RDP_FEC_DESC_TAG 0x00010005
1149 struct fc_fec_rdp_desc {
1150 uint32_t tag;
1151 uint32_t length;
1152 struct fc_rdp_fec_info info;
1153 };
1154
1155 struct fc_rdp_link_error_status_payload_info {
1156 struct fc_link_status link_status; /* 24 bytes */
1157 uint32_t port_type; /* bits 31-30 only */
1158 };
1159
1160 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1161 struct fc_rdp_link_error_status_desc {
1162 uint32_t tag; /* 0001 0002h */
1163 uint32_t length; /* set to size of payload struct */
1164 struct fc_rdp_link_error_status_payload_info info;
1165 };
1166
1167 #define VN_PT_PHY_UNKNOWN 0x00
1168 #define VN_PT_PHY_PF_PORT 0x01
1169 #define VN_PT_PHY_ETH_MAC 0x10
1170 #define VN_PT_PHY_SHIFT 30
1171
1172 #define RDP_PS_1GB 0x8000
1173 #define RDP_PS_2GB 0x4000
1174 #define RDP_PS_4GB 0x2000
1175 #define RDP_PS_10GB 0x1000
1176 #define RDP_PS_8GB 0x0800
1177 #define RDP_PS_16GB 0x0400
1178 #define RDP_PS_32GB 0x0200
1179 #define RDP_PS_64GB 0x0100
1180 #define RDP_PS_128GB 0x0080
1181 #define RDP_PS_256GB 0x0040
1182
1183 #define RDP_CAP_USER_CONFIGURED 0x0002
1184 #define RDP_CAP_UNKNOWN 0x0001
1185 #define RDP_PS_UNKNOWN 0x0002
1186 #define RDP_PS_NOT_ESTABLISHED 0x0001
1187
1188 struct fc_rdp_port_speed {
1189 uint16_t capabilities;
1190 uint16_t speed;
1191 };
1192
1193 struct fc_rdp_port_speed_info {
1194 struct fc_rdp_port_speed port_speed;
1195 };
1196
1197 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1198 struct fc_rdp_port_speed_desc {
1199 uint32_t tag; /* 00010001h */
1200 uint32_t length; /* set to size of payload struct */
1201 struct fc_rdp_port_speed_info info;
1202 };
1203
1204 #define RDP_NPORT_ID_SIZE 4
1205 #define RDP_N_PORT_DESC_TAG 0x00000003
1206 struct fc_rdp_nport_desc {
1207 uint32_t tag; /* 0000 0003h, big endian */
1208 uint32_t length; /* size of RDP_N_PORT_ID struct */
1209 uint32_t nport_id : 12;
1210 uint32_t reserved : 8;
1211 };
1212
1213
1214 struct fc_rdp_link_service_info {
1215 uint32_t els_req; /* Request payload word 0 value.*/
1216 };
1217
1218 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1219 struct fc_rdp_link_service_desc {
1220 uint32_t tag; /* Descriptor tag 1 */
1221 uint32_t length; /* set to size of payload struct. */
1222 struct fc_rdp_link_service_info payload;
1223 /* must be ELS req Word 0(0x18) */
1224 };
1225
1226 struct fc_rdp_sfp_info {
1227 uint16_t temperature;
1228 uint16_t vcc;
1229 uint16_t tx_bias;
1230 uint16_t tx_power;
1231 uint16_t rx_power;
1232 uint16_t flags;
1233 };
1234
1235 #define RDP_SFP_DESC_TAG 0x00010000
1236 struct fc_rdp_sfp_desc {
1237 uint32_t tag;
1238 uint32_t length; /* set to size of sfp_info struct */
1239 struct fc_rdp_sfp_info sfp_info;
1240 };
1241
1242 /* Buffer Credit Descriptor */
1243 struct fc_rdp_bbc_info {
1244 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1245 uint32_t attached_port_bbc;
1246 uint32_t rtt; /* Round trip time */
1247 };
1248 #define RDP_BBC_DESC_TAG 0x00010006
1249 struct fc_rdp_bbc_desc {
1250 uint32_t tag;
1251 uint32_t length;
1252 struct fc_rdp_bbc_info bbc_info;
1253 };
1254
1255 /* Optical Element Type Transgression Flags */
1256 #define RDP_OET_LOW_WARNING 0x1
1257 #define RDP_OET_HIGH_WARNING 0x2
1258 #define RDP_OET_LOW_ALARM 0x4
1259 #define RDP_OET_HIGH_ALARM 0x8
1260
1261 #define RDP_OED_TEMPERATURE 0x1
1262 #define RDP_OED_VOLTAGE 0x2
1263 #define RDP_OED_TXBIAS 0x3
1264 #define RDP_OED_TXPOWER 0x4
1265 #define RDP_OED_RXPOWER 0x5
1266
1267 #define RDP_OED_TYPE_SHIFT 28
1268 /* Optical Element Data descriptor */
1269 struct fc_rdp_oed_info {
1270 uint16_t hi_alarm;
1271 uint16_t lo_alarm;
1272 uint16_t hi_warning;
1273 uint16_t lo_warning;
1274 uint32_t function_flags;
1275 };
1276 #define RDP_OED_DESC_TAG 0x00010007
1277 struct fc_rdp_oed_sfp_desc {
1278 uint32_t tag;
1279 uint32_t length;
1280 struct fc_rdp_oed_info oed_info;
1281 };
1282
1283 /* Optical Product Data descriptor */
1284 struct fc_rdp_opd_sfp_info {
1285 uint8_t vendor_name[16];
1286 uint8_t model_number[16];
1287 uint8_t serial_number[16];
1288 uint8_t revision[4];
1289 uint8_t date[8];
1290 };
1291
1292 #define RDP_OPD_DESC_TAG 0x00010008
1293 struct fc_rdp_opd_sfp_desc {
1294 uint32_t tag;
1295 uint32_t length;
1296 struct fc_rdp_opd_sfp_info opd_info;
1297 };
1298
1299 struct fc_rdp_req_frame {
1300 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1301 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1302 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1303 };
1304
1305
1306 struct fc_rdp_res_frame {
1307 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1308 uint32_t length; /* FC Word 1 */
1309 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1310 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1311 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1312 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1313 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1314 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1315 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1316 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1317 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1318 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1319 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1320 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1321 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1322 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1323 };
1324
1325
1326 /* UVEM */
1327
1328 #define LPFC_UVEM_SIZE 60
1329 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16
1330 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20
1331
1332 #define VEM_ID_DESC_TAG 0x0001000A
1333 struct lpfc_vem_id_desc {
1334 uint32_t tag;
1335 uint32_t length;
1336 uint8_t vem_id[16];
1337 };
1338
1339 #define LPFC_QFPA_SIZE 4
1340
1341 #define INSTANTIATED_VE_DESC_TAG 0x0001000B
1342 struct instantiated_ve_desc {
1343 uint32_t tag;
1344 uint32_t length;
1345 uint8_t global_vem_id[16];
1346 uint32_t word6;
1347 #define lpfc_instantiated_local_id_SHIFT 0
1348 #define lpfc_instantiated_local_id_MASK 0x000000ff
1349 #define lpfc_instantiated_local_id_WORD word6
1350 #define lpfc_instantiated_nport_id_SHIFT 8
1351 #define lpfc_instantiated_nport_id_MASK 0x00ffffff
1352 #define lpfc_instantiated_nport_id_WORD word6
1353 };
1354
1355 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C
1356 struct deinstantiated_ve_desc {
1357 uint32_t tag;
1358 uint32_t length;
1359 uint8_t global_vem_id[16];
1360 uint32_t word6;
1361 #define lpfc_deinstantiated_nport_id_SHIFT 0
1362 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff
1363 #define lpfc_deinstantiated_nport_id_WORD word6
1364 #define lpfc_deinstantiated_local_id_SHIFT 24
1365 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff
1366 #define lpfc_deinstantiated_local_id_WORD word6
1367 };
1368
1369 /* Query Fabric Priority Allocation Response */
1370 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12
1371
1372 struct priority_range_desc {
1373 uint32_t tag;
1374 uint32_t length;
1375 uint8_t lo_range;
1376 uint8_t hi_range;
1377 uint8_t qos_priority;
1378 uint8_t local_ve_id;
1379 };
1380
1381 struct fc_qfpa_res {
1382 uint32_t reply_sequence; /* LS_ACC or LS_RJT */
1383 uint32_t length; /* FC Word 1 */
1384 struct priority_range_desc desc[1];
1385 };
1386
1387 /* Application Server command code */
1388 /* VMID */
1389
1390 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */
1391
1392 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */
1393 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */
1394 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */
1395 /* for Nport */
1396 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */
1397 /* for Nport */
1398 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */
1399 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */
1400 /* Identifier */
1401 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */
1402 /* Identifier */
1403
1404 struct entity_id_object {
1405 uint8_t entity_id_len;
1406 uint8_t entity_id[255]; /* VM UUID */
1407 };
1408
1409 struct app_id_object {
1410 uint32_t port_id;
1411 uint32_t app_id;
1412 struct entity_id_object obj;
1413 };
1414
1415 struct lpfc_vmid_rapp_ident_list {
1416 uint32_t no_of_objects;
1417 struct entity_id_object obj[1];
1418 };
1419
1420 struct lpfc_vmid_dapp_ident_list {
1421 uint32_t no_of_objects;
1422 struct entity_id_object obj[1];
1423 };
1424
1425 #define GALLAPPIA_ID_LAST 0x80
1426 struct lpfc_vmid_gallapp_ident_list {
1427 uint8_t control;
1428 uint8_t reserved[3];
1429 struct app_id_object app_id;
1430 };
1431
1432 #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4)
1433 #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4)
1434 #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4)
1435 #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4)
1436
1437 /******** FDMI ********/
1438
1439 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1440 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1441
1442 /* Definitions for HBA / Port attribute entries */
1443
1444 /* Attribute Entry */
1445 struct lpfc_fdmi_attr_entry {
1446 union {
1447 uint32_t AttrInt;
1448 uint8_t AttrTypes[32];
1449 uint8_t AttrString[256];
1450 struct lpfc_name AttrWWN;
1451 } un;
1452 };
1453
1454 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1455 /* Structure is in Big Endian format */
1456 uint32_t AttrType:16;
1457 uint32_t AttrLen:16;
1458 /* Marks start of Value (ATTRIBUTE_ENTRY) */
1459 struct lpfc_fdmi_attr_entry AttrValue;
1460 } __packed;
1461
1462 /*
1463 * HBA Attribute Block
1464 */
1465 struct lpfc_fdmi_attr_block {
1466 uint32_t EntryCnt; /* Number of HBA attribute entries */
1467 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1468 };
1469
1470 /*
1471 * Port Entry
1472 */
1473 struct lpfc_fdmi_port_entry {
1474 struct lpfc_name PortName;
1475 };
1476
1477 /*
1478 * HBA Identifier
1479 */
1480 struct lpfc_fdmi_hba_ident {
1481 struct lpfc_name PortName;
1482 };
1483
1484 /*
1485 * Registered Port List Format
1486 */
1487 struct lpfc_fdmi_reg_port_list {
1488 uint32_t EntryCnt;
1489 struct lpfc_fdmi_port_entry pe;
1490 } __packed;
1491
1492 /*
1493 * Register HBA(RHBA)
1494 */
1495 struct lpfc_fdmi_reg_hba {
1496 struct lpfc_fdmi_hba_ident hi;
1497 struct lpfc_fdmi_reg_port_list rpl;
1498 };
1499
1500 /******** MI MIB ********/
1501 #define SLI_CT_MIB_Subtypes 0x11
1502
1503 /*
1504 * Register HBA Attributes (RHAT)
1505 */
1506 struct lpfc_fdmi_reg_hbaattr {
1507 struct lpfc_name HBA_PortName;
1508 struct lpfc_fdmi_attr_block ab;
1509 };
1510
1511 /*
1512 * Register Port Attributes (RPA)
1513 */
1514 struct lpfc_fdmi_reg_portattr {
1515 struct lpfc_name PortName;
1516 struct lpfc_fdmi_attr_block ab;
1517 };
1518
1519 /*
1520 * HBA MAnagement Operations Command Codes
1521 */
1522 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1523 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1524 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1525 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1526 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1527 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1528 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1529 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1530 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1531 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1532 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1533 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1534 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1535
1536 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1537
1538 /*
1539 * HBA Attribute Types
1540 */
1541 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1542 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1543 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1544 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1545 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1546 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1547 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1548 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1549 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1550 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1551 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1552 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1553 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1554 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1555 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1556 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1557 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1558 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1559
1560 /* Bit mask for all individual HBA attributes */
1561 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1562 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1563 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1564 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1565 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1566 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1567 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1568 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1569 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1570 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1571 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1572 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1573 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1574 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1575 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1576 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1577 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1578 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1579
1580 /* Bit mask for FDMI-1 defined HBA attributes */
1581 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1582
1583 /* Bit mask for FDMI-2 defined HBA attributes */
1584 /* Skip vendor_info and bios_state */
1585 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1586
1587 /*
1588 * Port Attribute Types
1589 */
1590 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1591 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1592 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1593 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1594 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1595 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1596 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1597 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1598 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1599 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1600 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1601 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1602 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1603 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1604 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1605 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1606 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */
1607 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1608 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1609 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1610 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1611 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1612 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1613 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1614
1615 /* Bit mask for all individual PORT attributes */
1616 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1617 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1618 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1619 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1620 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1621 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1622 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1623 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1624 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1625 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1626 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1627 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1628 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1629 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1630 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1631 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1632 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1633 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1634 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1635 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1636 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1637 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1638 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1639 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */
1640
1641 /* Bit mask for FDMI-1 defined PORT attributes */
1642 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1643
1644 /* Bit mask for FDMI-2 defined PORT attributes */
1645 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1646
1647 /* Bit mask for Smart SAN defined PORT attributes */
1648 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1649
1650 /* Defines for PORT port state attribute */
1651 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1652 #define LPFC_FDMI_PORTSTATE_ONLINE 2
1653
1654 /* Defines for PORT port type attribute */
1655 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1656 #define LPFC_FDMI_PORTTYPE_NPORT 1
1657 #define LPFC_FDMI_PORTTYPE_NLPORT 2
1658
1659 /*
1660 * Begin HBA configuration parameters.
1661 * The PCI configuration register BAR assignments are:
1662 * BAR0, offset 0x10 - SLIM base memory address
1663 * BAR1, offset 0x14 - SLIM base memory high address
1664 * BAR2, offset 0x18 - REGISTER base memory address
1665 * BAR3, offset 0x1c - REGISTER base memory high address
1666 * BAR4, offset 0x20 - BIU I/O registers
1667 * BAR5, offset 0x24 - REGISTER base io high address
1668 */
1669
1670 /* Number of rings currently used and available. */
1671 #define MAX_SLI3_CONFIGURED_RINGS 3
1672 #define MAX_SLI3_RINGS 4
1673
1674 /* IOCB / Mailbox is owned by FireFly */
1675 #define OWN_CHIP 1
1676
1677 /* IOCB / Mailbox is owned by Host */
1678 #define OWN_HOST 0
1679
1680 /* Number of 4-byte words in an IOCB. */
1681 #define IOCB_WORD_SZ 8
1682
1683 /* network headers for Dfctl field */
1684 #define FC_NET_HDR 0x20
1685
1686 /* Start FireFly Register definitions */
1687 #define PCI_VENDOR_ID_EMULEX 0x10df
1688 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1689 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1690 #define PCI_DEVICE_ID_BALIUS 0xe131
1691 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1692 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1693 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1694 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1695 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1696 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1697 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1698 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500
1699 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1700 #define PCI_DEVICE_ID_SAT_MID 0xf015
1701 #define PCI_DEVICE_ID_RFLY 0xf095
1702 #define PCI_DEVICE_ID_PFLY 0xf098
1703 #define PCI_DEVICE_ID_LP101 0xf0a1
1704 #define PCI_DEVICE_ID_TFLY 0xf0a5
1705 #define PCI_DEVICE_ID_BSMB 0xf0d1
1706 #define PCI_DEVICE_ID_BMID 0xf0d5
1707 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1708 #define PCI_DEVICE_ID_ZMID 0xf0e5
1709 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1710 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1711 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1712 #define PCI_DEVICE_ID_SAT 0xf100
1713 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1714 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1715 #define PCI_DEVICE_ID_FALCON 0xf180
1716 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1717 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1718 #define PCI_DEVICE_ID_CENTAUR 0xf900
1719 #define PCI_DEVICE_ID_PEGASUS 0xf980
1720 #define PCI_DEVICE_ID_THOR 0xfa00
1721 #define PCI_DEVICE_ID_VIPER 0xfb00
1722 #define PCI_DEVICE_ID_LP10000S 0xfc00
1723 #define PCI_DEVICE_ID_LP11000S 0xfc10
1724 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1725 #define PCI_DEVICE_ID_SAT_S 0xfc40
1726 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1727 #define PCI_DEVICE_ID_HELIOS 0xfd00
1728 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1729 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1730 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1731 #define PCI_DEVICE_ID_HORNET 0xfe05
1732 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1733 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1734 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1735 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1736 #define PCI_DEVICE_ID_TOMCAT 0x0714
1737 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1738 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1739 #define PCI_VENDOR_ID_ATTO 0x117c
1740 #define PCI_DEVICE_ID_CLRY_16XE 0x0064
1741 #define PCI_DEVICE_ID_CLRY_161E 0x0063
1742 #define PCI_DEVICE_ID_CLRY_162E 0x0064
1743 #define PCI_DEVICE_ID_CLRY_164E 0x0065
1744 #define PCI_DEVICE_ID_CLRY_16XP 0x0094
1745 #define PCI_DEVICE_ID_CLRY_161P 0x00a0
1746 #define PCI_DEVICE_ID_CLRY_162P 0x0094
1747 #define PCI_DEVICE_ID_CLRY_164P 0x00a1
1748 #define PCI_DEVICE_ID_CLRY_32XE 0x0094
1749 #define PCI_DEVICE_ID_CLRY_321E 0x00a2
1750 #define PCI_DEVICE_ID_CLRY_322E 0x00a3
1751 #define PCI_DEVICE_ID_CLRY_324E 0x00ac
1752 #define PCI_DEVICE_ID_CLRY_32XP 0x00bb
1753 #define PCI_DEVICE_ID_CLRY_321P 0x00bc
1754 #define PCI_DEVICE_ID_CLRY_322P 0x00bd
1755 #define PCI_DEVICE_ID_CLRY_324P 0x00be
1756 #define PCI_DEVICE_ID_TLFC_2 0x0064
1757 #define PCI_DEVICE_ID_TLFC_2XX2 0x4064
1758 #define PCI_DEVICE_ID_TLFC_3 0x0094
1759 #define PCI_DEVICE_ID_TLFC_3162 0x40a6
1760 #define PCI_DEVICE_ID_TLFC_3322 0x40a7
1761
1762 #define JEDEC_ID_ADDRESS 0x0080001c
1763 #define FIREFLY_JEDEC_ID 0x1ACC
1764 #define SUPERFLY_JEDEC_ID 0x0020
1765 #define DRAGONFLY_JEDEC_ID 0x0021
1766 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1767 #define CENTAUR_2G_JEDEC_ID 0x0026
1768 #define CENTAUR_1G_JEDEC_ID 0x0028
1769 #define PEGASUS_ORION_JEDEC_ID 0x0036
1770 #define PEGASUS_JEDEC_ID 0x0038
1771 #define THOR_JEDEC_ID 0x0012
1772 #define HELIOS_JEDEC_ID 0x0364
1773 #define ZEPHYR_JEDEC_ID 0x0577
1774 #define VIPER_JEDEC_ID 0x4838
1775 #define SATURN_JEDEC_ID 0x1004
1776 #define HORNET_JDEC_ID 0x2057706D
1777
1778 #define JEDEC_ID_MASK 0x0FFFF000
1779 #define JEDEC_ID_SHIFT 12
1780 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1781
1782 typedef struct { /* FireFly BIU registers */
1783 uint32_t hostAtt; /* See definitions for Host Attention
1784 register */
1785 uint32_t chipAtt; /* See definitions for Chip Attention
1786 register */
1787 uint32_t hostStatus; /* See definitions for Host Status register */
1788 uint32_t hostControl; /* See definitions for Host Control register */
1789 uint32_t buiConfig; /* See definitions for BIU configuration
1790 register */
1791 } FF_REGS;
1792
1793 /* IO Register size in bytes */
1794 #define FF_REG_AREA_SIZE 256
1795
1796 /* Host Attention Register */
1797
1798 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1799
1800 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1801 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1802 #define HA_R0ATT 0x00000008 /* Bit 3 */
1803 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1804 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1805 #define HA_R1ATT 0x00000080 /* Bit 7 */
1806 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1807 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1808 #define HA_R2ATT 0x00000800 /* Bit 11 */
1809 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1810 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1811 #define HA_R3ATT 0x00008000 /* Bit 15 */
1812 #define HA_LATT 0x20000000 /* Bit 29 */
1813 #define HA_MBATT 0x40000000 /* Bit 30 */
1814 #define HA_ERATT 0x80000000 /* Bit 31 */
1815
1816 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1817 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1818 #define HA_RXATT 0x00000008 /* Bit 3 */
1819 #define HA_RXMASK 0x0000000f
1820
1821 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1822 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1823 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1824 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1825
1826 #define HA_R0_POS 3
1827 #define HA_R1_POS 7
1828 #define HA_R2_POS 11
1829 #define HA_R3_POS 15
1830 #define HA_LE_POS 29
1831 #define HA_MB_POS 30
1832 #define HA_ER_POS 31
1833 /* Chip Attention Register */
1834
1835 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1836
1837 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1838 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1839 #define CA_R0ATT 0x00000008 /* Bit 3 */
1840 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1841 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1842 #define CA_R1ATT 0x00000080 /* Bit 7 */
1843 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1844 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1845 #define CA_R2ATT 0x00000800 /* Bit 11 */
1846 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1847 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1848 #define CA_R3ATT 0x00008000 /* Bit 15 */
1849 #define CA_MBATT 0x40000000 /* Bit 30 */
1850
1851 /* Host Status Register */
1852
1853 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1854
1855 #define HS_MBRDY 0x00400000 /* Bit 22 */
1856 #define HS_FFRDY 0x00800000 /* Bit 23 */
1857 #define HS_FFER8 0x01000000 /* Bit 24 */
1858 #define HS_FFER7 0x02000000 /* Bit 25 */
1859 #define HS_FFER6 0x04000000 /* Bit 26 */
1860 #define HS_FFER5 0x08000000 /* Bit 27 */
1861 #define HS_FFER4 0x10000000 /* Bit 28 */
1862 #define HS_FFER3 0x20000000 /* Bit 29 */
1863 #define HS_FFER2 0x40000000 /* Bit 30 */
1864 #define HS_FFER1 0x80000000 /* Bit 31 */
1865 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1866 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1867 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1868 /* Host Control Register */
1869
1870 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1871
1872 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1873 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1874 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1875 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1876 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1877 #define HC_INITHBI 0x02000000 /* Bit 25 */
1878 #define HC_INITMB 0x04000000 /* Bit 26 */
1879 #define HC_INITFF 0x08000000 /* Bit 27 */
1880 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1881 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1882
1883 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1884 #define MSIX_DFLT_ID 0
1885 #define MSIX_RNG0_ID 0
1886 #define MSIX_RNG1_ID 1
1887 #define MSIX_RNG2_ID 2
1888 #define MSIX_RNG3_ID 3
1889
1890 #define MSIX_LINK_ID 4
1891 #define MSIX_MBOX_ID 5
1892
1893 #define MSIX_SPARE0_ID 6
1894 #define MSIX_SPARE1_ID 7
1895
1896 /* Mailbox Commands */
1897 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1898 #define MBX_LOAD_SM 0x01
1899 #define MBX_READ_NV 0x02
1900 #define MBX_WRITE_NV 0x03
1901 #define MBX_RUN_BIU_DIAG 0x04
1902 #define MBX_INIT_LINK 0x05
1903 #define MBX_DOWN_LINK 0x06
1904 #define MBX_CONFIG_LINK 0x07
1905 #define MBX_CONFIG_RING 0x09
1906 #define MBX_RESET_RING 0x0A
1907 #define MBX_READ_CONFIG 0x0B
1908 #define MBX_READ_RCONFIG 0x0C
1909 #define MBX_READ_SPARM 0x0D
1910 #define MBX_READ_STATUS 0x0E
1911 #define MBX_READ_RPI 0x0F
1912 #define MBX_READ_XRI 0x10
1913 #define MBX_READ_REV 0x11
1914 #define MBX_READ_LNK_STAT 0x12
1915 #define MBX_REG_LOGIN 0x13
1916 #define MBX_UNREG_LOGIN 0x14
1917 #define MBX_CLEAR_LA 0x16
1918 #define MBX_DUMP_MEMORY 0x17
1919 #define MBX_DUMP_CONTEXT 0x18
1920 #define MBX_RUN_DIAGS 0x19
1921 #define MBX_RESTART 0x1A
1922 #define MBX_UPDATE_CFG 0x1B
1923 #define MBX_DOWN_LOAD 0x1C
1924 #define MBX_DEL_LD_ENTRY 0x1D
1925 #define MBX_RUN_PROGRAM 0x1E
1926 #define MBX_SET_MASK 0x20
1927 #define MBX_SET_VARIABLE 0x21
1928 #define MBX_UNREG_D_ID 0x23
1929 #define MBX_KILL_BOARD 0x24
1930 #define MBX_CONFIG_FARP 0x25
1931 #define MBX_BEACON 0x2A
1932 #define MBX_CONFIG_MSI 0x30
1933 #define MBX_HEARTBEAT 0x31
1934 #define MBX_WRITE_VPARMS 0x32
1935 #define MBX_ASYNCEVT_ENABLE 0x33
1936 #define MBX_READ_EVENT_LOG_STATUS 0x37
1937 #define MBX_READ_EVENT_LOG 0x38
1938 #define MBX_WRITE_EVENT_LOG 0x39
1939
1940 #define MBX_PORT_CAPABILITIES 0x3B
1941 #define MBX_PORT_IOV_CONTROL 0x3C
1942
1943 #define MBX_CONFIG_HBQ 0x7C
1944 #define MBX_LOAD_AREA 0x81
1945 #define MBX_RUN_BIU_DIAG64 0x84
1946 #define MBX_CONFIG_PORT 0x88
1947 #define MBX_READ_SPARM64 0x8D
1948 #define MBX_READ_RPI64 0x8F
1949 #define MBX_REG_LOGIN64 0x93
1950 #define MBX_READ_TOPOLOGY 0x95
1951 #define MBX_REG_VPI 0x96
1952 #define MBX_UNREG_VPI 0x97
1953
1954 #define MBX_WRITE_WWN 0x98
1955 #define MBX_SET_DEBUG 0x99
1956 #define MBX_LOAD_EXP_ROM 0x9C
1957 #define MBX_SLI4_CONFIG 0x9B
1958 #define MBX_SLI4_REQ_FTRS 0x9D
1959 #define MBX_MAX_CMDS 0x9E
1960 #define MBX_RESUME_RPI 0x9E
1961 #define MBX_SLI2_CMD_MASK 0x80
1962 #define MBX_REG_VFI 0x9F
1963 #define MBX_REG_FCFI 0xA0
1964 #define MBX_UNREG_VFI 0xA1
1965 #define MBX_UNREG_FCFI 0xA2
1966 #define MBX_INIT_VFI 0xA3
1967 #define MBX_INIT_VPI 0xA4
1968 #define MBX_ACCESS_VDATA 0xA5
1969 #define MBX_REG_FCFI_MRQ 0xAF
1970
1971 #define MBX_AUTH_PORT 0xF8
1972 #define MBX_SECURITY_MGMT 0xF9
1973
1974 /* IOCB Commands */
1975
1976 #define CMD_RCV_SEQUENCE_CX 0x01
1977 #define CMD_XMIT_SEQUENCE_CR 0x02
1978 #define CMD_XMIT_SEQUENCE_CX 0x03
1979 #define CMD_XMIT_BCAST_CN 0x04
1980 #define CMD_XMIT_BCAST_CX 0x05
1981 #define CMD_QUE_RING_BUF_CN 0x06
1982 #define CMD_QUE_XRI_BUF_CX 0x07
1983 #define CMD_IOCB_CONTINUE_CN 0x08
1984 #define CMD_RET_XRI_BUF_CX 0x09
1985 #define CMD_ELS_REQUEST_CR 0x0A
1986 #define CMD_ELS_REQUEST_CX 0x0B
1987 #define CMD_RCV_ELS_REQ_CX 0x0D
1988 #define CMD_ABORT_XRI_CN 0x0E
1989 #define CMD_ABORT_XRI_CX 0x0F
1990 #define CMD_CLOSE_XRI_CN 0x10
1991 #define CMD_CLOSE_XRI_CX 0x11
1992 #define CMD_CREATE_XRI_CR 0x12
1993 #define CMD_CREATE_XRI_CX 0x13
1994 #define CMD_GET_RPI_CN 0x14
1995 #define CMD_XMIT_ELS_RSP_CX 0x15
1996 #define CMD_GET_RPI_CR 0x16
1997 #define CMD_XRI_ABORTED_CX 0x17
1998 #define CMD_FCP_IWRITE_CR 0x18
1999 #define CMD_FCP_IWRITE_CX 0x19
2000 #define CMD_FCP_IREAD_CR 0x1A
2001 #define CMD_FCP_IREAD_CX 0x1B
2002 #define CMD_FCP_ICMND_CR 0x1C
2003 #define CMD_FCP_ICMND_CX 0x1D
2004 #define CMD_FCP_TSEND_CX 0x1F
2005 #define CMD_FCP_TRECEIVE_CX 0x21
2006 #define CMD_FCP_TRSP_CX 0x23
2007 #define CMD_FCP_AUTO_TRSP_CX 0x29
2008
2009 #define CMD_ADAPTER_MSG 0x20
2010 #define CMD_ADAPTER_DUMP 0x22
2011
2012 /* SLI_2 IOCB Command Set */
2013
2014 #define CMD_ASYNC_STATUS 0x7C
2015 #define CMD_RCV_SEQUENCE64_CX 0x81
2016 #define CMD_XMIT_SEQUENCE64_CR 0x82
2017 #define CMD_XMIT_SEQUENCE64_CX 0x83
2018 #define CMD_XMIT_BCAST64_CN 0x84
2019 #define CMD_XMIT_BCAST64_CX 0x85
2020 #define CMD_QUE_RING_BUF64_CN 0x86
2021 #define CMD_QUE_XRI_BUF64_CX 0x87
2022 #define CMD_IOCB_CONTINUE64_CN 0x88
2023 #define CMD_RET_XRI_BUF64_CX 0x89
2024 #define CMD_ELS_REQUEST64_CR 0x8A
2025 #define CMD_ELS_REQUEST64_CX 0x8B
2026 #define CMD_ABORT_MXRI64_CN 0x8C
2027 #define CMD_RCV_ELS_REQ64_CX 0x8D
2028 #define CMD_XMIT_ELS_RSP64_CX 0x95
2029 #define CMD_XMIT_BLS_RSP64_CX 0x97
2030 #define CMD_FCP_IWRITE64_CR 0x98
2031 #define CMD_FCP_IWRITE64_CX 0x99
2032 #define CMD_FCP_IREAD64_CR 0x9A
2033 #define CMD_FCP_IREAD64_CX 0x9B
2034 #define CMD_FCP_ICMND64_CR 0x9C
2035 #define CMD_FCP_ICMND64_CX 0x9D
2036 #define CMD_FCP_TSEND64_CX 0x9F
2037 #define CMD_FCP_TRECEIVE64_CX 0xA1
2038 #define CMD_FCP_TRSP64_CX 0xA3
2039
2040 #define CMD_QUE_XRI64_CX 0xB3
2041 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
2042 #define CMD_IOCB_RCV_ELS64_CX 0xB7
2043 #define CMD_IOCB_RET_XRI64_CX 0xB9
2044 #define CMD_IOCB_RCV_CONT64_CX 0xBB
2045
2046 #define CMD_GEN_REQUEST64_CR 0xC2
2047 #define CMD_GEN_REQUEST64_CX 0xC3
2048
2049 /* Unhandled SLI-3 Commands */
2050 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
2051 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
2052 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
2053 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
2054 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
2055 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
2056 #define CMD_IOCB_RET_HBQE64_CN 0xCA
2057 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
2058 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
2059 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
2060 #define CMD_IOCB_LOGENTRY_CN 0x94
2061 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
2062
2063 /* Data Security SLI Commands */
2064 #define DSSCMD_IWRITE64_CR 0xF8
2065 #define DSSCMD_IWRITE64_CX 0xF9
2066 #define DSSCMD_IREAD64_CR 0xFA
2067 #define DSSCMD_IREAD64_CX 0xFB
2068
2069 #define CMD_MAX_IOCB_CMD 0xFB
2070 #define CMD_IOCB_MASK 0xff
2071
2072 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
2073 iocb */
2074 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
2075 /*
2076 * Define Status
2077 */
2078 #define MBX_SUCCESS 0
2079 #define MBXERR_NUM_RINGS 1
2080 #define MBXERR_NUM_IOCBS 2
2081 #define MBXERR_IOCBS_EXCEEDED 3
2082 #define MBXERR_BAD_RING_NUMBER 4
2083 #define MBXERR_MASK_ENTRIES_RANGE 5
2084 #define MBXERR_MASKS_EXCEEDED 6
2085 #define MBXERR_BAD_PROFILE 7
2086 #define MBXERR_BAD_DEF_CLASS 8
2087 #define MBXERR_BAD_MAX_RESPONDER 9
2088 #define MBXERR_BAD_MAX_ORIGINATOR 10
2089 #define MBXERR_RPI_REGISTERED 11
2090 #define MBXERR_RPI_FULL 12
2091 #define MBXERR_NO_RESOURCES 13
2092 #define MBXERR_BAD_RCV_LENGTH 14
2093 #define MBXERR_DMA_ERROR 15
2094 #define MBXERR_ERROR 16
2095 #define MBXERR_LINK_DOWN 0x33
2096 #define MBXERR_SEC_NO_PERMISSION 0xF02
2097 #define MBX_NOT_FINISHED 255
2098
2099 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
2100 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
2101
2102 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
2103
2104 /*
2105 * return code Fail
2106 */
2107 #define FAILURE 1
2108
2109 /*
2110 * Begin Structure Definitions for Mailbox Commands
2111 */
2112
2113 typedef struct {
2114 #ifdef __BIG_ENDIAN_BITFIELD
2115 uint8_t tval;
2116 uint8_t tmask;
2117 uint8_t rval;
2118 uint8_t rmask;
2119 #else /* __LITTLE_ENDIAN_BITFIELD */
2120 uint8_t rmask;
2121 uint8_t rval;
2122 uint8_t tmask;
2123 uint8_t tval;
2124 #endif
2125 } RR_REG;
2126
2127 struct ulp_bde {
2128 uint32_t bdeAddress;
2129 #ifdef __BIG_ENDIAN_BITFIELD
2130 uint32_t bdeReserved:4;
2131 uint32_t bdeAddrHigh:4;
2132 uint32_t bdeSize:24;
2133 #else /* __LITTLE_ENDIAN_BITFIELD */
2134 uint32_t bdeSize:24;
2135 uint32_t bdeAddrHigh:4;
2136 uint32_t bdeReserved:4;
2137 #endif
2138 };
2139
2140 typedef struct ULP_BDL { /* SLI-2 */
2141 #ifdef __BIG_ENDIAN_BITFIELD
2142 uint32_t bdeFlags:8; /* BDL Flags */
2143 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2144 #else /* __LITTLE_ENDIAN_BITFIELD */
2145 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2146 uint32_t bdeFlags:8; /* BDL Flags */
2147 #endif
2148
2149 uint32_t addrLow; /* Address 0:31 */
2150 uint32_t addrHigh; /* Address 32:63 */
2151 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2152 } ULP_BDL;
2153
2154 /*
2155 * BlockGuard Definitions
2156 */
2157
2158 enum lpfc_protgrp_type {
2159 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2160 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2161 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2162 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2163 };
2164
2165 /* PDE Descriptors */
2166 #define LPFC_PDE5_DESCRIPTOR 0x85
2167 #define LPFC_PDE6_DESCRIPTOR 0x86
2168 #define LPFC_PDE7_DESCRIPTOR 0x87
2169
2170 /* BlockGuard Opcodes */
2171 #define BG_OP_IN_NODIF_OUT_CRC 0x0
2172 #define BG_OP_IN_CRC_OUT_NODIF 0x1
2173 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
2174 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
2175 #define BG_OP_IN_CRC_OUT_CRC 0x4
2176 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
2177 #define BG_OP_IN_CRC_OUT_CSUM 0x6
2178 #define BG_OP_IN_CSUM_OUT_CRC 0x7
2179 #define BG_OP_RAW_MODE 0x8
2180
2181 struct lpfc_pde5 {
2182 uint32_t word0;
2183 #define pde5_type_SHIFT 24
2184 #define pde5_type_MASK 0x000000ff
2185 #define pde5_type_WORD word0
2186 #define pde5_rsvd0_SHIFT 0
2187 #define pde5_rsvd0_MASK 0x00ffffff
2188 #define pde5_rsvd0_WORD word0
2189 uint32_t reftag; /* Reference Tag Value */
2190 uint32_t reftagtr; /* Reference Tag Translation Value */
2191 };
2192
2193 struct lpfc_pde6 {
2194 uint32_t word0;
2195 #define pde6_type_SHIFT 24
2196 #define pde6_type_MASK 0x000000ff
2197 #define pde6_type_WORD word0
2198 #define pde6_rsvd0_SHIFT 0
2199 #define pde6_rsvd0_MASK 0x00ffffff
2200 #define pde6_rsvd0_WORD word0
2201 uint32_t word1;
2202 #define pde6_rsvd1_SHIFT 26
2203 #define pde6_rsvd1_MASK 0x0000003f
2204 #define pde6_rsvd1_WORD word1
2205 #define pde6_na_SHIFT 25
2206 #define pde6_na_MASK 0x00000001
2207 #define pde6_na_WORD word1
2208 #define pde6_rsvd2_SHIFT 16
2209 #define pde6_rsvd2_MASK 0x000001FF
2210 #define pde6_rsvd2_WORD word1
2211 #define pde6_apptagtr_SHIFT 0
2212 #define pde6_apptagtr_MASK 0x0000ffff
2213 #define pde6_apptagtr_WORD word1
2214 uint32_t word2;
2215 #define pde6_optx_SHIFT 28
2216 #define pde6_optx_MASK 0x0000000f
2217 #define pde6_optx_WORD word2
2218 #define pde6_oprx_SHIFT 24
2219 #define pde6_oprx_MASK 0x0000000f
2220 #define pde6_oprx_WORD word2
2221 #define pde6_nr_SHIFT 23
2222 #define pde6_nr_MASK 0x00000001
2223 #define pde6_nr_WORD word2
2224 #define pde6_ce_SHIFT 22
2225 #define pde6_ce_MASK 0x00000001
2226 #define pde6_ce_WORD word2
2227 #define pde6_re_SHIFT 21
2228 #define pde6_re_MASK 0x00000001
2229 #define pde6_re_WORD word2
2230 #define pde6_ae_SHIFT 20
2231 #define pde6_ae_MASK 0x00000001
2232 #define pde6_ae_WORD word2
2233 #define pde6_ai_SHIFT 19
2234 #define pde6_ai_MASK 0x00000001
2235 #define pde6_ai_WORD word2
2236 #define pde6_bs_SHIFT 16
2237 #define pde6_bs_MASK 0x00000007
2238 #define pde6_bs_WORD word2
2239 #define pde6_apptagval_SHIFT 0
2240 #define pde6_apptagval_MASK 0x0000ffff
2241 #define pde6_apptagval_WORD word2
2242 };
2243
2244 struct lpfc_pde7 {
2245 uint32_t word0;
2246 #define pde7_type_SHIFT 24
2247 #define pde7_type_MASK 0x000000ff
2248 #define pde7_type_WORD word0
2249 #define pde7_rsvd0_SHIFT 0
2250 #define pde7_rsvd0_MASK 0x00ffffff
2251 #define pde7_rsvd0_WORD word0
2252 uint32_t addrHigh;
2253 uint32_t addrLow;
2254 };
2255
2256 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2257
2258 typedef struct {
2259 #ifdef __BIG_ENDIAN_BITFIELD
2260 uint32_t rsvd2:25;
2261 uint32_t acknowledgment:1;
2262 uint32_t version:1;
2263 uint32_t erase_or_prog:1;
2264 uint32_t update_flash:1;
2265 uint32_t update_ram:1;
2266 uint32_t method:1;
2267 uint32_t load_cmplt:1;
2268 #else /* __LITTLE_ENDIAN_BITFIELD */
2269 uint32_t load_cmplt:1;
2270 uint32_t method:1;
2271 uint32_t update_ram:1;
2272 uint32_t update_flash:1;
2273 uint32_t erase_or_prog:1;
2274 uint32_t version:1;
2275 uint32_t acknowledgment:1;
2276 uint32_t rsvd2:25;
2277 #endif
2278
2279 uint32_t dl_to_adr_low;
2280 uint32_t dl_to_adr_high;
2281 uint32_t dl_len;
2282 union {
2283 uint32_t dl_from_mbx_offset;
2284 struct ulp_bde dl_from_bde;
2285 struct ulp_bde64 dl_from_bde64;
2286 } un;
2287
2288 } LOAD_SM_VAR;
2289
2290 /* Structure for MB Command READ_NVPARM (02) */
2291
2292 typedef struct {
2293 uint32_t rsvd1[3]; /* Read as all one's */
2294 uint32_t rsvd2; /* Read as all zero's */
2295 uint32_t portname[2]; /* N_PORT name */
2296 uint32_t nodename[2]; /* NODE name */
2297
2298 #ifdef __BIG_ENDIAN_BITFIELD
2299 uint32_t pref_DID:24;
2300 uint32_t hardAL_PA:8;
2301 #else /* __LITTLE_ENDIAN_BITFIELD */
2302 uint32_t hardAL_PA:8;
2303 uint32_t pref_DID:24;
2304 #endif
2305
2306 uint32_t rsvd3[21]; /* Read as all one's */
2307 } READ_NV_VAR;
2308
2309 /* Structure for MB Command WRITE_NVPARMS (03) */
2310
2311 typedef struct {
2312 uint32_t rsvd1[3]; /* Must be all one's */
2313 uint32_t rsvd2; /* Must be all zero's */
2314 uint32_t portname[2]; /* N_PORT name */
2315 uint32_t nodename[2]; /* NODE name */
2316
2317 #ifdef __BIG_ENDIAN_BITFIELD
2318 uint32_t pref_DID:24;
2319 uint32_t hardAL_PA:8;
2320 #else /* __LITTLE_ENDIAN_BITFIELD */
2321 uint32_t hardAL_PA:8;
2322 uint32_t pref_DID:24;
2323 #endif
2324
2325 uint32_t rsvd3[21]; /* Must be all one's */
2326 } WRITE_NV_VAR;
2327
2328 /* Structure for MB Command RUN_BIU_DIAG (04) */
2329 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2330
2331 typedef struct {
2332 uint32_t rsvd1;
2333 union {
2334 struct {
2335 struct ulp_bde xmit_bde;
2336 struct ulp_bde rcv_bde;
2337 } s1;
2338 struct {
2339 struct ulp_bde64 xmit_bde64;
2340 struct ulp_bde64 rcv_bde64;
2341 } s2;
2342 } un;
2343 } BIU_DIAG_VAR;
2344
2345 /* Structure for MB command READ_EVENT_LOG (0x38) */
2346 struct READ_EVENT_LOG_VAR {
2347 uint32_t word1;
2348 #define lpfc_event_log_SHIFT 29
2349 #define lpfc_event_log_MASK 0x00000001
2350 #define lpfc_event_log_WORD word1
2351 #define USE_MAILBOX_RESPONSE 1
2352 uint32_t offset;
2353 struct ulp_bde64 rcv_bde64;
2354 };
2355
2356 /* Structure for MB Command INIT_LINK (05) */
2357
2358 typedef struct {
2359 #ifdef __BIG_ENDIAN_BITFIELD
2360 uint32_t rsvd1:24;
2361 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2362 #else /* __LITTLE_ENDIAN_BITFIELD */
2363 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2364 uint32_t rsvd1:24;
2365 #endif
2366
2367 #ifdef __BIG_ENDIAN_BITFIELD
2368 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2369 uint8_t rsvd2;
2370 uint16_t link_flags;
2371 #else /* __LITTLE_ENDIAN_BITFIELD */
2372 uint16_t link_flags;
2373 uint8_t rsvd2;
2374 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2375 #endif
2376
2377 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2378 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2379 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2380 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2381 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2382 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2383 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2384
2385 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2386 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2387 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2388
2389 uint32_t link_speed;
2390 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2391 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2392 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2393 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2394 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2395 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2396 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2397 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2398 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
2399 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
2400 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
2401
2402 } INIT_LINK_VAR;
2403
2404 /* Structure for MB Command DOWN_LINK (06) */
2405
2406 typedef struct {
2407 uint32_t rsvd1;
2408 } DOWN_LINK_VAR;
2409
2410 /* Structure for MB Command CONFIG_LINK (07) */
2411
2412 typedef struct {
2413 #ifdef __BIG_ENDIAN_BITFIELD
2414 uint32_t cr:1;
2415 uint32_t ci:1;
2416 uint32_t cr_delay:6;
2417 uint32_t cr_count:8;
2418 uint32_t rsvd1:8;
2419 uint32_t MaxBBC:8;
2420 #else /* __LITTLE_ENDIAN_BITFIELD */
2421 uint32_t MaxBBC:8;
2422 uint32_t rsvd1:8;
2423 uint32_t cr_count:8;
2424 uint32_t cr_delay:6;
2425 uint32_t ci:1;
2426 uint32_t cr:1;
2427 #endif
2428
2429 uint32_t myId;
2430 uint32_t rsvd2;
2431 uint32_t edtov;
2432 uint32_t arbtov;
2433 uint32_t ratov;
2434 uint32_t rttov;
2435 uint32_t altov;
2436 uint32_t crtov;
2437
2438 #ifdef __BIG_ENDIAN_BITFIELD
2439 uint32_t rsvd4:19;
2440 uint32_t cscn:1;
2441 uint32_t bbscn:4;
2442 uint32_t rsvd3:8;
2443 #else /* __LITTLE_ENDIAN_BITFIELD */
2444 uint32_t rsvd3:8;
2445 uint32_t bbscn:4;
2446 uint32_t cscn:1;
2447 uint32_t rsvd4:19;
2448 #endif
2449
2450 #ifdef __BIG_ENDIAN_BITFIELD
2451 uint32_t rrq_enable:1;
2452 uint32_t rrq_immed:1;
2453 uint32_t rsvd5:29;
2454 uint32_t ack0_enable:1;
2455 #else /* __LITTLE_ENDIAN_BITFIELD */
2456 uint32_t ack0_enable:1;
2457 uint32_t rsvd5:29;
2458 uint32_t rrq_immed:1;
2459 uint32_t rrq_enable:1;
2460 #endif
2461 } CONFIG_LINK;
2462
2463 /* Structure for MB Command PART_SLIM (08)
2464 * will be removed since SLI1 is no longer supported!
2465 */
2466 typedef struct {
2467 #ifdef __BIG_ENDIAN_BITFIELD
2468 uint16_t offCiocb;
2469 uint16_t numCiocb;
2470 uint16_t offRiocb;
2471 uint16_t numRiocb;
2472 #else /* __LITTLE_ENDIAN_BITFIELD */
2473 uint16_t numCiocb;
2474 uint16_t offCiocb;
2475 uint16_t numRiocb;
2476 uint16_t offRiocb;
2477 #endif
2478 } RING_DEF;
2479
2480 typedef struct {
2481 #ifdef __BIG_ENDIAN_BITFIELD
2482 uint32_t unused1:24;
2483 uint32_t numRing:8;
2484 #else /* __LITTLE_ENDIAN_BITFIELD */
2485 uint32_t numRing:8;
2486 uint32_t unused1:24;
2487 #endif
2488
2489 RING_DEF ringdef[4];
2490 uint32_t hbainit;
2491 } PART_SLIM_VAR;
2492
2493 /* Structure for MB Command CONFIG_RING (09) */
2494
2495 typedef struct {
2496 #ifdef __BIG_ENDIAN_BITFIELD
2497 uint32_t unused2:6;
2498 uint32_t recvSeq:1;
2499 uint32_t recvNotify:1;
2500 uint32_t numMask:8;
2501 uint32_t profile:8;
2502 uint32_t unused1:4;
2503 uint32_t ring:4;
2504 #else /* __LITTLE_ENDIAN_BITFIELD */
2505 uint32_t ring:4;
2506 uint32_t unused1:4;
2507 uint32_t profile:8;
2508 uint32_t numMask:8;
2509 uint32_t recvNotify:1;
2510 uint32_t recvSeq:1;
2511 uint32_t unused2:6;
2512 #endif
2513
2514 #ifdef __BIG_ENDIAN_BITFIELD
2515 uint16_t maxRespXchg;
2516 uint16_t maxOrigXchg;
2517 #else /* __LITTLE_ENDIAN_BITFIELD */
2518 uint16_t maxOrigXchg;
2519 uint16_t maxRespXchg;
2520 #endif
2521
2522 RR_REG rrRegs[6];
2523 } CONFIG_RING_VAR;
2524
2525 /* Structure for MB Command RESET_RING (10) */
2526
2527 typedef struct {
2528 uint32_t ring_no;
2529 } RESET_RING_VAR;
2530
2531 /* Structure for MB Command READ_CONFIG (11) */
2532
2533 typedef struct {
2534 #ifdef __BIG_ENDIAN_BITFIELD
2535 uint32_t cr:1;
2536 uint32_t ci:1;
2537 uint32_t cr_delay:6;
2538 uint32_t cr_count:8;
2539 uint32_t InitBBC:8;
2540 uint32_t MaxBBC:8;
2541 #else /* __LITTLE_ENDIAN_BITFIELD */
2542 uint32_t MaxBBC:8;
2543 uint32_t InitBBC:8;
2544 uint32_t cr_count:8;
2545 uint32_t cr_delay:6;
2546 uint32_t ci:1;
2547 uint32_t cr:1;
2548 #endif
2549
2550 #ifdef __BIG_ENDIAN_BITFIELD
2551 uint32_t topology:8;
2552 uint32_t myDid:24;
2553 #else /* __LITTLE_ENDIAN_BITFIELD */
2554 uint32_t myDid:24;
2555 uint32_t topology:8;
2556 #endif
2557
2558 /* Defines for topology (defined previously) */
2559 #ifdef __BIG_ENDIAN_BITFIELD
2560 uint32_t AR:1;
2561 uint32_t IR:1;
2562 uint32_t rsvd1:29;
2563 uint32_t ack0:1;
2564 #else /* __LITTLE_ENDIAN_BITFIELD */
2565 uint32_t ack0:1;
2566 uint32_t rsvd1:29;
2567 uint32_t IR:1;
2568 uint32_t AR:1;
2569 #endif
2570
2571 uint32_t edtov;
2572 uint32_t arbtov;
2573 uint32_t ratov;
2574 uint32_t rttov;
2575 uint32_t altov;
2576 uint32_t lmt;
2577 #define LMT_RESERVED 0x000 /* Not used */
2578 #define LMT_1Gb 0x004
2579 #define LMT_2Gb 0x008
2580 #define LMT_4Gb 0x040
2581 #define LMT_8Gb 0x080
2582 #define LMT_10Gb 0x100
2583 #define LMT_16Gb 0x200
2584 #define LMT_32Gb 0x400
2585 #define LMT_64Gb 0x800
2586 #define LMT_128Gb 0x1000
2587 #define LMT_256Gb 0x2000
2588 uint32_t rsvd2;
2589 uint32_t rsvd3;
2590 uint32_t max_xri;
2591 uint32_t max_iocb;
2592 uint32_t max_rpi;
2593 uint32_t avail_xri;
2594 uint32_t avail_iocb;
2595 uint32_t avail_rpi;
2596 uint32_t max_vpi;
2597 uint32_t rsvd4;
2598 uint32_t rsvd5;
2599 uint32_t avail_vpi;
2600 } READ_CONFIG_VAR;
2601
2602 /* Structure for MB Command READ_RCONFIG (12) */
2603
2604 typedef struct {
2605 #ifdef __BIG_ENDIAN_BITFIELD
2606 uint32_t rsvd2:7;
2607 uint32_t recvNotify:1;
2608 uint32_t numMask:8;
2609 uint32_t profile:8;
2610 uint32_t rsvd1:4;
2611 uint32_t ring:4;
2612 #else /* __LITTLE_ENDIAN_BITFIELD */
2613 uint32_t ring:4;
2614 uint32_t rsvd1:4;
2615 uint32_t profile:8;
2616 uint32_t numMask:8;
2617 uint32_t recvNotify:1;
2618 uint32_t rsvd2:7;
2619 #endif
2620
2621 #ifdef __BIG_ENDIAN_BITFIELD
2622 uint16_t maxResp;
2623 uint16_t maxOrig;
2624 #else /* __LITTLE_ENDIAN_BITFIELD */
2625 uint16_t maxOrig;
2626 uint16_t maxResp;
2627 #endif
2628
2629 RR_REG rrRegs[6];
2630
2631 #ifdef __BIG_ENDIAN_BITFIELD
2632 uint16_t cmdRingOffset;
2633 uint16_t cmdEntryCnt;
2634 uint16_t rspRingOffset;
2635 uint16_t rspEntryCnt;
2636 uint16_t nextCmdOffset;
2637 uint16_t rsvd3;
2638 uint16_t nextRspOffset;
2639 uint16_t rsvd4;
2640 #else /* __LITTLE_ENDIAN_BITFIELD */
2641 uint16_t cmdEntryCnt;
2642 uint16_t cmdRingOffset;
2643 uint16_t rspEntryCnt;
2644 uint16_t rspRingOffset;
2645 uint16_t rsvd3;
2646 uint16_t nextCmdOffset;
2647 uint16_t rsvd4;
2648 uint16_t nextRspOffset;
2649 #endif
2650 } READ_RCONF_VAR;
2651
2652 /* Structure for MB Command READ_SPARM (13) */
2653 /* Structure for MB Command READ_SPARM64 (0x8D) */
2654
2655 typedef struct {
2656 uint32_t rsvd1;
2657 uint32_t rsvd2;
2658 union {
2659 struct ulp_bde sp; /* This BDE points to struct serv_parm
2660 structure */
2661 struct ulp_bde64 sp64;
2662 } un;
2663 #ifdef __BIG_ENDIAN_BITFIELD
2664 uint16_t rsvd3;
2665 uint16_t vpi;
2666 #else /* __LITTLE_ENDIAN_BITFIELD */
2667 uint16_t vpi;
2668 uint16_t rsvd3;
2669 #endif
2670 } READ_SPARM_VAR;
2671
2672 /* Structure for MB Command READ_STATUS (14) */
2673 enum read_status_word1 {
2674 RD_ST_CC = 0x01,
2675 RD_ST_XKB = 0x80,
2676 };
2677
2678 enum read_status_word17 {
2679 RD_ST_XMIT_XKB_MASK = 0x3fffff,
2680 };
2681
2682 enum read_status_word18 {
2683 RD_ST_RCV_XKB_MASK = 0x3fffff,
2684 };
2685
2686 typedef struct {
2687 u8 clear_counters; /* rsvd 7:1, cc 0 */
2688 u8 rsvd5;
2689 u8 rsvd6;
2690 u8 xkb; /* xkb 7, rsvd 6:0 */
2691
2692 u32 rsvd8;
2693
2694 uint32_t xmitByteCnt;
2695 uint32_t rcvByteCnt;
2696 uint32_t xmitFrameCnt;
2697 uint32_t rcvFrameCnt;
2698 uint32_t xmitSeqCnt;
2699 uint32_t rcvSeqCnt;
2700 uint32_t totalOrigExchanges;
2701 uint32_t totalRespExchanges;
2702 uint32_t rcvPbsyCnt;
2703 uint32_t rcvFbsyCnt;
2704
2705 u32 drop_frame_no_rq;
2706 u32 empty_rq;
2707 u32 drop_frame_no_xri;
2708 u32 empty_xri;
2709
2710 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */
2711 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */
2712 } READ_STATUS_VAR;
2713
2714 /* Structure for MB Command READ_RPI (15) */
2715 /* Structure for MB Command READ_RPI64 (0x8F) */
2716
2717 typedef struct {
2718 #ifdef __BIG_ENDIAN_BITFIELD
2719 uint16_t nextRpi;
2720 uint16_t reqRpi;
2721 uint32_t rsvd2:8;
2722 uint32_t DID:24;
2723 #else /* __LITTLE_ENDIAN_BITFIELD */
2724 uint16_t reqRpi;
2725 uint16_t nextRpi;
2726 uint32_t DID:24;
2727 uint32_t rsvd2:8;
2728 #endif
2729
2730 union {
2731 struct ulp_bde sp;
2732 struct ulp_bde64 sp64;
2733 } un;
2734
2735 } READ_RPI_VAR;
2736
2737 /* Structure for MB Command READ_XRI (16) */
2738
2739 typedef struct {
2740 #ifdef __BIG_ENDIAN_BITFIELD
2741 uint16_t nextXri;
2742 uint16_t reqXri;
2743 uint16_t rsvd1;
2744 uint16_t rpi;
2745 uint32_t rsvd2:8;
2746 uint32_t DID:24;
2747 uint32_t rsvd3:8;
2748 uint32_t SID:24;
2749 uint32_t rsvd4;
2750 uint8_t seqId;
2751 uint8_t rsvd5;
2752 uint16_t seqCount;
2753 uint16_t oxId;
2754 uint16_t rxId;
2755 uint32_t rsvd6:30;
2756 uint32_t si:1;
2757 uint32_t exchOrig:1;
2758 #else /* __LITTLE_ENDIAN_BITFIELD */
2759 uint16_t reqXri;
2760 uint16_t nextXri;
2761 uint16_t rpi;
2762 uint16_t rsvd1;
2763 uint32_t DID:24;
2764 uint32_t rsvd2:8;
2765 uint32_t SID:24;
2766 uint32_t rsvd3:8;
2767 uint32_t rsvd4;
2768 uint16_t seqCount;
2769 uint8_t rsvd5;
2770 uint8_t seqId;
2771 uint16_t rxId;
2772 uint16_t oxId;
2773 uint32_t exchOrig:1;
2774 uint32_t si:1;
2775 uint32_t rsvd6:30;
2776 #endif
2777 } READ_XRI_VAR;
2778
2779 /* Structure for MB Command READ_REV (17) */
2780
2781 typedef struct {
2782 #ifdef __BIG_ENDIAN_BITFIELD
2783 uint32_t cv:1;
2784 uint32_t rr:1;
2785 uint32_t rsvd2:2;
2786 uint32_t v3req:1;
2787 uint32_t v3rsp:1;
2788 uint32_t rsvd1:25;
2789 uint32_t rv:1;
2790 #else /* __LITTLE_ENDIAN_BITFIELD */
2791 uint32_t rv:1;
2792 uint32_t rsvd1:25;
2793 uint32_t v3rsp:1;
2794 uint32_t v3req:1;
2795 uint32_t rsvd2:2;
2796 uint32_t rr:1;
2797 uint32_t cv:1;
2798 #endif
2799
2800 uint32_t biuRev;
2801 uint32_t smRev;
2802 union {
2803 uint32_t smFwRev;
2804 struct {
2805 #ifdef __BIG_ENDIAN_BITFIELD
2806 uint8_t ProgType;
2807 uint8_t ProgId;
2808 uint16_t ProgVer:4;
2809 uint16_t ProgRev:4;
2810 uint16_t ProgFixLvl:2;
2811 uint16_t ProgDistType:2;
2812 uint16_t DistCnt:4;
2813 #else /* __LITTLE_ENDIAN_BITFIELD */
2814 uint16_t DistCnt:4;
2815 uint16_t ProgDistType:2;
2816 uint16_t ProgFixLvl:2;
2817 uint16_t ProgRev:4;
2818 uint16_t ProgVer:4;
2819 uint8_t ProgId;
2820 uint8_t ProgType;
2821 #endif
2822
2823 } b;
2824 } un;
2825 uint32_t endecRev;
2826 #ifdef __BIG_ENDIAN_BITFIELD
2827 uint8_t feaLevelHigh;
2828 uint8_t feaLevelLow;
2829 uint8_t fcphHigh;
2830 uint8_t fcphLow;
2831 #else /* __LITTLE_ENDIAN_BITFIELD */
2832 uint8_t fcphLow;
2833 uint8_t fcphHigh;
2834 uint8_t feaLevelLow;
2835 uint8_t feaLevelHigh;
2836 #endif
2837
2838 uint32_t postKernRev;
2839 uint32_t opFwRev;
2840 uint8_t opFwName[16];
2841 uint32_t sli1FwRev;
2842 uint8_t sli1FwName[16];
2843 uint32_t sli2FwRev;
2844 uint8_t sli2FwName[16];
2845 uint32_t sli3Feat;
2846 uint32_t RandomData[6];
2847 } READ_REV_VAR;
2848
2849 /* Structure for MB Command READ_LINK_STAT (18) */
2850
2851 typedef struct {
2852 uint32_t word0;
2853
2854 #define lpfc_read_link_stat_rec_SHIFT 0
2855 #define lpfc_read_link_stat_rec_MASK 0x1
2856 #define lpfc_read_link_stat_rec_WORD word0
2857
2858 #define lpfc_read_link_stat_gec_SHIFT 1
2859 #define lpfc_read_link_stat_gec_MASK 0x1
2860 #define lpfc_read_link_stat_gec_WORD word0
2861
2862 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2863 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2864 #define lpfc_read_link_stat_w02oftow23of_WORD word0
2865
2866 #define lpfc_read_link_stat_rsvd_SHIFT 24
2867 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2868 #define lpfc_read_link_stat_rsvd_WORD word0
2869
2870 #define lpfc_read_link_stat_gec2_SHIFT 29
2871 #define lpfc_read_link_stat_gec2_MASK 0x1
2872 #define lpfc_read_link_stat_gec2_WORD word0
2873
2874 #define lpfc_read_link_stat_clrc_SHIFT 30
2875 #define lpfc_read_link_stat_clrc_MASK 0x1
2876 #define lpfc_read_link_stat_clrc_WORD word0
2877
2878 #define lpfc_read_link_stat_clof_SHIFT 31
2879 #define lpfc_read_link_stat_clof_MASK 0x1
2880 #define lpfc_read_link_stat_clof_WORD word0
2881
2882 uint32_t linkFailureCnt;
2883 uint32_t lossSyncCnt;
2884 uint32_t lossSignalCnt;
2885 uint32_t primSeqErrCnt;
2886 uint32_t invalidXmitWord;
2887 uint32_t crcCnt;
2888 uint32_t primSeqTimeout;
2889 uint32_t elasticOverrun;
2890 uint32_t arbTimeout;
2891 uint32_t advRecBufCredit;
2892 uint32_t curRecBufCredit;
2893 uint32_t advTransBufCredit;
2894 uint32_t curTransBufCredit;
2895 uint32_t recEofCount;
2896 uint32_t recEofdtiCount;
2897 uint32_t recEofniCount;
2898 uint32_t recSofcount;
2899 uint32_t rsvd1;
2900 uint32_t rsvd2;
2901 uint32_t recDrpXriCount;
2902 uint32_t fecCorrBlkCount;
2903 uint32_t fecUncorrBlkCount;
2904 } READ_LNK_VAR;
2905
2906 /* Structure for MB Command REG_LOGIN (19) */
2907 /* Structure for MB Command REG_LOGIN64 (0x93) */
2908
2909 typedef struct {
2910 #ifdef __BIG_ENDIAN_BITFIELD
2911 uint16_t rsvd1;
2912 uint16_t rpi;
2913 uint32_t rsvd2:8;
2914 uint32_t did:24;
2915 #else /* __LITTLE_ENDIAN_BITFIELD */
2916 uint16_t rpi;
2917 uint16_t rsvd1;
2918 uint32_t did:24;
2919 uint32_t rsvd2:8;
2920 #endif
2921
2922 union {
2923 struct ulp_bde sp;
2924 struct ulp_bde64 sp64;
2925 } un;
2926
2927 #ifdef __BIG_ENDIAN_BITFIELD
2928 uint16_t rsvd6;
2929 uint16_t vpi;
2930 #else /* __LITTLE_ENDIAN_BITFIELD */
2931 uint16_t vpi;
2932 uint16_t rsvd6;
2933 #endif
2934
2935 } REG_LOGIN_VAR;
2936
2937 /* Word 30 contents for REG_LOGIN */
2938 typedef union {
2939 struct {
2940 #ifdef __BIG_ENDIAN_BITFIELD
2941 uint16_t rsvd1:12;
2942 uint16_t wd30_class:4;
2943 uint16_t xri;
2944 #else /* __LITTLE_ENDIAN_BITFIELD */
2945 uint16_t xri;
2946 uint16_t wd30_class:4;
2947 uint16_t rsvd1:12;
2948 #endif
2949 } f;
2950 uint32_t word;
2951 } REG_WD30;
2952
2953 /* Structure for MB Command UNREG_LOGIN (20) */
2954
2955 typedef struct {
2956 #ifdef __BIG_ENDIAN_BITFIELD
2957 uint16_t rsvd1;
2958 uint16_t rpi;
2959 uint32_t rsvd2;
2960 uint32_t rsvd3;
2961 uint32_t rsvd4;
2962 uint32_t rsvd5;
2963 uint16_t rsvd6;
2964 uint16_t vpi;
2965 #else /* __LITTLE_ENDIAN_BITFIELD */
2966 uint16_t rpi;
2967 uint16_t rsvd1;
2968 uint32_t rsvd2;
2969 uint32_t rsvd3;
2970 uint32_t rsvd4;
2971 uint32_t rsvd5;
2972 uint16_t vpi;
2973 uint16_t rsvd6;
2974 #endif
2975 } UNREG_LOGIN_VAR;
2976
2977 /* Structure for MB Command REG_VPI (0x96) */
2978 typedef struct {
2979 #ifdef __BIG_ENDIAN_BITFIELD
2980 uint32_t rsvd1;
2981 uint32_t rsvd2:7;
2982 uint32_t upd:1;
2983 uint32_t sid:24;
2984 uint32_t wwn[2];
2985 uint32_t rsvd5;
2986 uint16_t vfi;
2987 uint16_t vpi;
2988 #else /* __LITTLE_ENDIAN */
2989 uint32_t rsvd1;
2990 uint32_t sid:24;
2991 uint32_t upd:1;
2992 uint32_t rsvd2:7;
2993 uint32_t wwn[2];
2994 uint32_t rsvd5;
2995 uint16_t vpi;
2996 uint16_t vfi;
2997 #endif
2998 } REG_VPI_VAR;
2999
3000 /* Structure for MB Command UNREG_VPI (0x97) */
3001 typedef struct {
3002 uint32_t rsvd1;
3003 #ifdef __BIG_ENDIAN_BITFIELD
3004 uint16_t rsvd2;
3005 uint16_t sli4_vpi;
3006 #else /* __LITTLE_ENDIAN */
3007 uint16_t sli4_vpi;
3008 uint16_t rsvd2;
3009 #endif
3010 uint32_t rsvd3;
3011 uint32_t rsvd4;
3012 uint32_t rsvd5;
3013 #ifdef __BIG_ENDIAN_BITFIELD
3014 uint16_t rsvd6;
3015 uint16_t vpi;
3016 #else /* __LITTLE_ENDIAN */
3017 uint16_t vpi;
3018 uint16_t rsvd6;
3019 #endif
3020 } UNREG_VPI_VAR;
3021
3022 /* Structure for MB Command UNREG_D_ID (0x23) */
3023
3024 typedef struct {
3025 uint32_t did;
3026 uint32_t rsvd2;
3027 uint32_t rsvd3;
3028 uint32_t rsvd4;
3029 uint32_t rsvd5;
3030 #ifdef __BIG_ENDIAN_BITFIELD
3031 uint16_t rsvd6;
3032 uint16_t vpi;
3033 #else
3034 uint16_t vpi;
3035 uint16_t rsvd6;
3036 #endif
3037 } UNREG_D_ID_VAR;
3038
3039 /* Structure for MB Command READ_TOPOLOGY (0x95) */
3040 struct lpfc_mbx_read_top {
3041 uint32_t eventTag; /* Event tag */
3042 uint32_t word2;
3043 #define lpfc_mbx_read_top_fa_SHIFT 12
3044 #define lpfc_mbx_read_top_fa_MASK 0x00000001
3045 #define lpfc_mbx_read_top_fa_WORD word2
3046 #define lpfc_mbx_read_top_mm_SHIFT 11
3047 #define lpfc_mbx_read_top_mm_MASK 0x00000001
3048 #define lpfc_mbx_read_top_mm_WORD word2
3049 #define lpfc_mbx_read_top_pb_SHIFT 9
3050 #define lpfc_mbx_read_top_pb_MASK 0X00000001
3051 #define lpfc_mbx_read_top_pb_WORD word2
3052 #define lpfc_mbx_read_top_il_SHIFT 8
3053 #define lpfc_mbx_read_top_il_MASK 0x00000001
3054 #define lpfc_mbx_read_top_il_WORD word2
3055 #define lpfc_mbx_read_top_att_type_SHIFT 0
3056 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
3057 #define lpfc_mbx_read_top_att_type_WORD word2
3058 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
3059 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
3060 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
3061 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
3062 uint32_t word3;
3063 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
3064 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
3065 #define lpfc_mbx_read_top_alpa_granted_WORD word3
3066 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
3067 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
3068 #define lpfc_mbx_read_top_lip_alps_WORD word3
3069 #define lpfc_mbx_read_top_lip_type_SHIFT 8
3070 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
3071 #define lpfc_mbx_read_top_lip_type_WORD word3
3072 #define lpfc_mbx_read_top_topology_SHIFT 0
3073 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
3074 #define lpfc_mbx_read_top_topology_WORD word3
3075 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
3076 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
3077 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
3078 /* store the LILP AL_PA position map into */
3079 struct ulp_bde64 lilpBde64;
3080 #define LPFC_ALPA_MAP_SIZE 128
3081 uint32_t word7;
3082 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
3083 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
3084 #define lpfc_mbx_read_top_ld_lu_WORD word7
3085 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
3086 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
3087 #define lpfc_mbx_read_top_ld_tf_WORD word7
3088 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
3089 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
3090 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
3091 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
3092 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
3093 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
3094 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
3095 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
3096 #define lpfc_mbx_read_top_ld_tx_WORD word7
3097 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
3098 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
3099 #define lpfc_mbx_read_top_ld_rx_WORD word7
3100 uint32_t word8;
3101 #define lpfc_mbx_read_top_lu_SHIFT 31
3102 #define lpfc_mbx_read_top_lu_MASK 0x00000001
3103 #define lpfc_mbx_read_top_lu_WORD word8
3104 #define lpfc_mbx_read_top_tf_SHIFT 30
3105 #define lpfc_mbx_read_top_tf_MASK 0x00000001
3106 #define lpfc_mbx_read_top_tf_WORD word8
3107 #define lpfc_mbx_read_top_link_spd_SHIFT 8
3108 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
3109 #define lpfc_mbx_read_top_link_spd_WORD word8
3110 #define lpfc_mbx_read_top_nl_port_SHIFT 4
3111 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
3112 #define lpfc_mbx_read_top_nl_port_WORD word8
3113 #define lpfc_mbx_read_top_tx_SHIFT 2
3114 #define lpfc_mbx_read_top_tx_MASK 0x00000003
3115 #define lpfc_mbx_read_top_tx_WORD word8
3116 #define lpfc_mbx_read_top_rx_SHIFT 0
3117 #define lpfc_mbx_read_top_rx_MASK 0x00000003
3118 #define lpfc_mbx_read_top_rx_WORD word8
3119 #define LPFC_LINK_SPEED_UNKNOWN 0x0
3120 #define LPFC_LINK_SPEED_1GHZ 0x04
3121 #define LPFC_LINK_SPEED_2GHZ 0x08
3122 #define LPFC_LINK_SPEED_4GHZ 0x10
3123 #define LPFC_LINK_SPEED_8GHZ 0x20
3124 #define LPFC_LINK_SPEED_10GHZ 0x40
3125 #define LPFC_LINK_SPEED_16GHZ 0x80
3126 #define LPFC_LINK_SPEED_32GHZ 0x90
3127 #define LPFC_LINK_SPEED_64GHZ 0xA0
3128 #define LPFC_LINK_SPEED_128GHZ 0xB0
3129 #define LPFC_LINK_SPEED_256GHZ 0xC0
3130 };
3131
3132 /* Structure for MB Command CLEAR_LA (22) */
3133
3134 typedef struct {
3135 uint32_t eventTag; /* Event tag */
3136 uint32_t rsvd1;
3137 } CLEAR_LA_VAR;
3138
3139 /* Structure for MB Command DUMP */
3140
3141 typedef struct {
3142 #ifdef __BIG_ENDIAN_BITFIELD
3143 uint32_t rsvd:25;
3144 uint32_t ra:1;
3145 uint32_t co:1;
3146 uint32_t cv:1;
3147 uint32_t type:4;
3148 uint32_t entry_index:16;
3149 uint32_t region_id:16;
3150 #else /* __LITTLE_ENDIAN_BITFIELD */
3151 uint32_t type:4;
3152 uint32_t cv:1;
3153 uint32_t co:1;
3154 uint32_t ra:1;
3155 uint32_t rsvd:25;
3156 uint32_t region_id:16;
3157 uint32_t entry_index:16;
3158 #endif
3159
3160 uint32_t sli4_length;
3161 uint32_t word_cnt;
3162 uint32_t resp_offset;
3163 } DUMP_VAR;
3164
3165 #define DMP_MEM_REG 0x1
3166 #define DMP_NV_PARAMS 0x2
3167 #define DMP_LMSD 0x3 /* Link Module Serial Data */
3168 #define DMP_WELL_KNOWN 0x4
3169
3170 #define DMP_REGION_VPD 0xe
3171 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3172 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3173 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3174
3175 #define DMP_REGION_VPORT 0x16 /* VPort info region */
3176 #define DMP_VPORT_REGION_SIZE 0x200
3177 #define DMP_MBOX_OFFSET_WORD 0x5
3178
3179 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
3180 #define DMP_RGN23_SIZE 0x400
3181
3182 #define WAKE_UP_PARMS_REGION_ID 4
3183 #define WAKE_UP_PARMS_WORD_SIZE 15
3184
3185 struct vport_rec {
3186 uint8_t wwpn[8];
3187 uint8_t wwnn[8];
3188 };
3189
3190 #define VPORT_INFO_SIG 0x32324752
3191 #define VPORT_INFO_REV_MASK 0xff
3192 #define VPORT_INFO_REV 0x1
3193 #define MAX_STATIC_VPORT_COUNT 16
3194 struct static_vport_info {
3195 uint32_t signature;
3196 uint32_t rev;
3197 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3198 uint32_t resvd[66];
3199 };
3200
3201 /* Option rom version structure */
3202 struct prog_id {
3203 #ifdef __BIG_ENDIAN_BITFIELD
3204 uint8_t type;
3205 uint8_t id;
3206 uint32_t ver:4; /* Major Version */
3207 uint32_t rev:4; /* Revision */
3208 uint32_t lev:2; /* Level */
3209 uint32_t dist:2; /* Dist Type */
3210 uint32_t num:4; /* number after dist type */
3211 #else /* __LITTLE_ENDIAN_BITFIELD */
3212 uint32_t num:4; /* number after dist type */
3213 uint32_t dist:2; /* Dist Type */
3214 uint32_t lev:2; /* Level */
3215 uint32_t rev:4; /* Revision */
3216 uint32_t ver:4; /* Major Version */
3217 uint8_t id;
3218 uint8_t type;
3219 #endif
3220 };
3221
3222 /* Structure for MB Command UPDATE_CFG (0x1B) */
3223
3224 struct update_cfg_var {
3225 #ifdef __BIG_ENDIAN_BITFIELD
3226 uint32_t rsvd2:16;
3227 uint32_t type:8;
3228 uint32_t rsvd:1;
3229 uint32_t ra:1;
3230 uint32_t co:1;
3231 uint32_t cv:1;
3232 uint32_t req:4;
3233 uint32_t entry_length:16;
3234 uint32_t region_id:16;
3235 #else /* __LITTLE_ENDIAN_BITFIELD */
3236 uint32_t req:4;
3237 uint32_t cv:1;
3238 uint32_t co:1;
3239 uint32_t ra:1;
3240 uint32_t rsvd:1;
3241 uint32_t type:8;
3242 uint32_t rsvd2:16;
3243 uint32_t region_id:16;
3244 uint32_t entry_length:16;
3245 #endif
3246
3247 uint32_t resp_info;
3248 uint32_t byte_cnt;
3249 uint32_t data_offset;
3250 };
3251
3252 struct hbq_mask {
3253 #ifdef __BIG_ENDIAN_BITFIELD
3254 uint8_t tmatch;
3255 uint8_t tmask;
3256 uint8_t rctlmatch;
3257 uint8_t rctlmask;
3258 #else /* __LITTLE_ENDIAN */
3259 uint8_t rctlmask;
3260 uint8_t rctlmatch;
3261 uint8_t tmask;
3262 uint8_t tmatch;
3263 #endif
3264 };
3265
3266
3267 /* Structure for MB Command CONFIG_HBQ (7c) */
3268
3269 struct config_hbq_var {
3270 #ifdef __BIG_ENDIAN_BITFIELD
3271 uint32_t rsvd1 :7;
3272 uint32_t recvNotify :1; /* Receive Notification */
3273 uint32_t numMask :8; /* # Mask Entries */
3274 uint32_t profile :8; /* Selection Profile */
3275 uint32_t rsvd2 :8;
3276 #else /* __LITTLE_ENDIAN */
3277 uint32_t rsvd2 :8;
3278 uint32_t profile :8; /* Selection Profile */
3279 uint32_t numMask :8; /* # Mask Entries */
3280 uint32_t recvNotify :1; /* Receive Notification */
3281 uint32_t rsvd1 :7;
3282 #endif
3283
3284 #ifdef __BIG_ENDIAN_BITFIELD
3285 uint32_t hbqId :16;
3286 uint32_t rsvd3 :12;
3287 uint32_t ringMask :4;
3288 #else /* __LITTLE_ENDIAN */
3289 uint32_t ringMask :4;
3290 uint32_t rsvd3 :12;
3291 uint32_t hbqId :16;
3292 #endif
3293
3294 #ifdef __BIG_ENDIAN_BITFIELD
3295 uint32_t entry_count :16;
3296 uint32_t rsvd4 :8;
3297 uint32_t headerLen :8;
3298 #else /* __LITTLE_ENDIAN */
3299 uint32_t headerLen :8;
3300 uint32_t rsvd4 :8;
3301 uint32_t entry_count :16;
3302 #endif
3303
3304 uint32_t hbqaddrLow;
3305 uint32_t hbqaddrHigh;
3306
3307 #ifdef __BIG_ENDIAN_BITFIELD
3308 uint32_t rsvd5 :31;
3309 uint32_t logEntry :1;
3310 #else /* __LITTLE_ENDIAN */
3311 uint32_t logEntry :1;
3312 uint32_t rsvd5 :31;
3313 #endif
3314
3315 uint32_t rsvd6; /* w7 */
3316 uint32_t rsvd7; /* w8 */
3317 uint32_t rsvd8; /* w9 */
3318
3319 struct hbq_mask hbqMasks[6];
3320
3321
3322 union {
3323 uint32_t allprofiles[12];
3324
3325 struct {
3326 #ifdef __BIG_ENDIAN_BITFIELD
3327 uint32_t seqlenoff :16;
3328 uint32_t maxlen :16;
3329 #else /* __LITTLE_ENDIAN */
3330 uint32_t maxlen :16;
3331 uint32_t seqlenoff :16;
3332 #endif
3333 #ifdef __BIG_ENDIAN_BITFIELD
3334 uint32_t rsvd1 :28;
3335 uint32_t seqlenbcnt :4;
3336 #else /* __LITTLE_ENDIAN */
3337 uint32_t seqlenbcnt :4;
3338 uint32_t rsvd1 :28;
3339 #endif
3340 uint32_t rsvd[10];
3341 } profile2;
3342
3343 struct {
3344 #ifdef __BIG_ENDIAN_BITFIELD
3345 uint32_t seqlenoff :16;
3346 uint32_t maxlen :16;
3347 #else /* __LITTLE_ENDIAN */
3348 uint32_t maxlen :16;
3349 uint32_t seqlenoff :16;
3350 #endif
3351 #ifdef __BIG_ENDIAN_BITFIELD
3352 uint32_t cmdcodeoff :28;
3353 uint32_t rsvd1 :12;
3354 uint32_t seqlenbcnt :4;
3355 #else /* __LITTLE_ENDIAN */
3356 uint32_t seqlenbcnt :4;
3357 uint32_t rsvd1 :12;
3358 uint32_t cmdcodeoff :28;
3359 #endif
3360 uint32_t cmdmatch[8];
3361
3362 uint32_t rsvd[2];
3363 } profile3;
3364
3365 struct {
3366 #ifdef __BIG_ENDIAN_BITFIELD
3367 uint32_t seqlenoff :16;
3368 uint32_t maxlen :16;
3369 #else /* __LITTLE_ENDIAN */
3370 uint32_t maxlen :16;
3371 uint32_t seqlenoff :16;
3372 #endif
3373 #ifdef __BIG_ENDIAN_BITFIELD
3374 uint32_t cmdcodeoff :28;
3375 uint32_t rsvd1 :12;
3376 uint32_t seqlenbcnt :4;
3377 #else /* __LITTLE_ENDIAN */
3378 uint32_t seqlenbcnt :4;
3379 uint32_t rsvd1 :12;
3380 uint32_t cmdcodeoff :28;
3381 #endif
3382 uint32_t cmdmatch[8];
3383
3384 uint32_t rsvd[2];
3385 } profile5;
3386
3387 } profiles;
3388
3389 };
3390
3391
3392
3393 /* Structure for MB Command CONFIG_PORT (0x88) */
3394 typedef struct {
3395 #ifdef __BIG_ENDIAN_BITFIELD
3396 uint32_t cBE : 1;
3397 uint32_t cET : 1;
3398 uint32_t cHpcb : 1;
3399 uint32_t cMA : 1;
3400 uint32_t sli_mode : 4;
3401 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3402 * config block */
3403 #else /* __LITTLE_ENDIAN */
3404 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3405 * config block */
3406 uint32_t sli_mode : 4;
3407 uint32_t cMA : 1;
3408 uint32_t cHpcb : 1;
3409 uint32_t cET : 1;
3410 uint32_t cBE : 1;
3411 #endif
3412
3413 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3414 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3415 uint32_t hbainit[5];
3416 #ifdef __BIG_ENDIAN_BITFIELD
3417 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3418 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3419 #else /* __LITTLE_ENDIAN */
3420 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3421 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3422 #endif
3423
3424 #ifdef __BIG_ENDIAN_BITFIELD
3425 uint32_t rsvd1 : 20; /* Reserved */
3426 uint32_t casabt : 1; /* Configure async abts status notice */
3427 uint32_t rsvd2 : 2; /* Reserved */
3428 uint32_t cbg : 1; /* Configure BlockGuard */
3429 uint32_t cmv : 1; /* Configure Max VPIs */
3430 uint32_t ccrp : 1; /* Config Command Ring Polling */
3431 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3432 uint32_t chbs : 1; /* Cofigure Host Backing store */
3433 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3434 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3435 uint32_t cmx : 1; /* Configure Max XRIs */
3436 uint32_t cmr : 1; /* Configure Max RPIs */
3437 #else /* __LITTLE_ENDIAN */
3438 uint32_t cmr : 1; /* Configure Max RPIs */
3439 uint32_t cmx : 1; /* Configure Max XRIs */
3440 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3441 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3442 uint32_t chbs : 1; /* Cofigure Host Backing store */
3443 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3444 uint32_t ccrp : 1; /* Config Command Ring Polling */
3445 uint32_t cmv : 1; /* Configure Max VPIs */
3446 uint32_t cbg : 1; /* Configure BlockGuard */
3447 uint32_t rsvd2 : 2; /* Reserved */
3448 uint32_t casabt : 1; /* Configure async abts status notice */
3449 uint32_t rsvd1 : 20; /* Reserved */
3450 #endif
3451 #ifdef __BIG_ENDIAN_BITFIELD
3452 uint32_t rsvd3 : 20; /* Reserved */
3453 uint32_t gasabt : 1; /* Grant async abts status notice */
3454 uint32_t rsvd4 : 2; /* Reserved */
3455 uint32_t gbg : 1; /* Grant BlockGuard */
3456 uint32_t gmv : 1; /* Grant Max VPIs */
3457 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3458 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3459 uint32_t ghbs : 1; /* Grant Host Backing Store */
3460 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3461 uint32_t gerbm : 1; /* Grant ERBM Request */
3462 uint32_t gmx : 1; /* Grant Max XRIs */
3463 uint32_t gmr : 1; /* Grant Max RPIs */
3464 #else /* __LITTLE_ENDIAN */
3465 uint32_t gmr : 1; /* Grant Max RPIs */
3466 uint32_t gmx : 1; /* Grant Max XRIs */
3467 uint32_t gerbm : 1; /* Grant ERBM Request */
3468 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3469 uint32_t ghbs : 1; /* Grant Host Backing Store */
3470 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3471 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3472 uint32_t gmv : 1; /* Grant Max VPIs */
3473 uint32_t gbg : 1; /* Grant BlockGuard */
3474 uint32_t rsvd4 : 2; /* Reserved */
3475 uint32_t gasabt : 1; /* Grant async abts status notice */
3476 uint32_t rsvd3 : 20; /* Reserved */
3477 #endif
3478
3479 #ifdef __BIG_ENDIAN_BITFIELD
3480 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3481 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3482 #else /* __LITTLE_ENDIAN */
3483 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3484 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3485 #endif
3486
3487 #ifdef __BIG_ENDIAN_BITFIELD
3488 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3489 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3490 #else /* __LITTLE_ENDIAN */
3491 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3492 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3493 #endif
3494
3495 uint32_t rsvd6; /* Reserved */
3496
3497 #ifdef __BIG_ENDIAN_BITFIELD
3498 uint32_t rsvd7 : 16;
3499 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3500 #else /* __LITTLE_ENDIAN */
3501 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3502 uint32_t rsvd7 : 16;
3503 #endif
3504
3505 } CONFIG_PORT_VAR;
3506
3507 /* Structure for MB Command CONFIG_MSI (0x30) */
3508 struct config_msi_var {
3509 #ifdef __BIG_ENDIAN_BITFIELD
3510 uint32_t dfltMsgNum:8; /* Default message number */
3511 uint32_t rsvd1:11; /* Reserved */
3512 uint32_t NID:5; /* Number of secondary attention IDs */
3513 uint32_t rsvd2:5; /* Reserved */
3514 uint32_t dfltPresent:1; /* Default message number present */
3515 uint32_t addFlag:1; /* Add association flag */
3516 uint32_t reportFlag:1; /* Report association flag */
3517 #else /* __LITTLE_ENDIAN_BITFIELD */
3518 uint32_t reportFlag:1; /* Report association flag */
3519 uint32_t addFlag:1; /* Add association flag */
3520 uint32_t dfltPresent:1; /* Default message number present */
3521 uint32_t rsvd2:5; /* Reserved */
3522 uint32_t NID:5; /* Number of secondary attention IDs */
3523 uint32_t rsvd1:11; /* Reserved */
3524 uint32_t dfltMsgNum:8; /* Default message number */
3525 #endif
3526 uint32_t attentionConditions[2];
3527 uint8_t attentionId[16];
3528 uint8_t messageNumberByHA[64];
3529 uint8_t messageNumberByID[16];
3530 uint32_t autoClearHA[2];
3531 #ifdef __BIG_ENDIAN_BITFIELD
3532 uint32_t rsvd3:16;
3533 uint32_t autoClearID:16;
3534 #else /* __LITTLE_ENDIAN_BITFIELD */
3535 uint32_t autoClearID:16;
3536 uint32_t rsvd3:16;
3537 #endif
3538 uint32_t rsvd4;
3539 };
3540
3541 /* SLI-2 Port Control Block */
3542
3543 /* SLIM POINTER */
3544 #define SLIMOFF 0x30 /* WORD */
3545
3546 typedef struct _SLI2_RDSC {
3547 uint32_t cmdEntries;
3548 uint32_t cmdAddrLow;
3549 uint32_t cmdAddrHigh;
3550
3551 uint32_t rspEntries;
3552 uint32_t rspAddrLow;
3553 uint32_t rspAddrHigh;
3554 } SLI2_RDSC;
3555
3556 typedef struct _PCB {
3557 #ifdef __BIG_ENDIAN_BITFIELD
3558 uint32_t type:8;
3559 #define TYPE_NATIVE_SLI2 0x01
3560 uint32_t feature:8;
3561 #define FEATURE_INITIAL_SLI2 0x01
3562 uint32_t rsvd:12;
3563 uint32_t maxRing:4;
3564 #else /* __LITTLE_ENDIAN_BITFIELD */
3565 uint32_t maxRing:4;
3566 uint32_t rsvd:12;
3567 uint32_t feature:8;
3568 #define FEATURE_INITIAL_SLI2 0x01
3569 uint32_t type:8;
3570 #define TYPE_NATIVE_SLI2 0x01
3571 #endif
3572
3573 uint32_t mailBoxSize;
3574 uint32_t mbAddrLow;
3575 uint32_t mbAddrHigh;
3576
3577 uint32_t hgpAddrLow;
3578 uint32_t hgpAddrHigh;
3579
3580 uint32_t pgpAddrLow;
3581 uint32_t pgpAddrHigh;
3582 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3583 } PCB_t;
3584
3585 /* NEW_FEATURE */
3586 typedef struct {
3587 #ifdef __BIG_ENDIAN_BITFIELD
3588 uint32_t rsvd0:27;
3589 uint32_t discardFarp:1;
3590 uint32_t IPEnable:1;
3591 uint32_t nodeName:1;
3592 uint32_t portName:1;
3593 uint32_t filterEnable:1;
3594 #else /* __LITTLE_ENDIAN_BITFIELD */
3595 uint32_t filterEnable:1;
3596 uint32_t portName:1;
3597 uint32_t nodeName:1;
3598 uint32_t IPEnable:1;
3599 uint32_t discardFarp:1;
3600 uint32_t rsvd:27;
3601 #endif
3602
3603 uint8_t portname[8]; /* Used to be struct lpfc_name */
3604 uint8_t nodename[8];
3605 uint32_t rsvd1;
3606 uint32_t rsvd2;
3607 uint32_t rsvd3;
3608 uint32_t IPAddress;
3609 } CONFIG_FARP_VAR;
3610
3611 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3612
3613 typedef struct {
3614 #ifdef __BIG_ENDIAN_BITFIELD
3615 uint32_t rsvd:30;
3616 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3617 #else /* __LITTLE_ENDIAN */
3618 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3619 uint32_t rsvd:30;
3620 #endif
3621 } ASYNCEVT_ENABLE_VAR;
3622
3623 /* Union of all Mailbox Command types */
3624 #define MAILBOX_CMD_WSIZE 32
3625 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3626 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3627 #define MAILBOX_EXT_WSIZE 512
3628 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3629 #define MAILBOX_HBA_EXT_OFFSET 0x100
3630 /* max mbox xmit size is a page size for sysfs IO operations */
3631 #define MAILBOX_SYSFS_MAX 4096
3632
3633 typedef union {
3634 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3635 * feature/max ring number
3636 */
3637 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3638 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3639 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3640 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3641 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3642 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3643 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3644 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3645 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3646 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3647 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3648 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3649 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3650 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3651 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3652 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3653 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3654 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3655 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3656 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3657 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3658 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3659 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3660 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3661 * NEW_FEATURE
3662 */
3663 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3664 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3665 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3666 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3667 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3668 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3669 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3670 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3671 * (READ_EVENT_LOG)
3672 */
3673 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3674 } MAILVARIANTS;
3675
3676 /*
3677 * SLI-2 specific structures
3678 */
3679
3680 struct lpfc_hgp {
3681 __le32 cmdPutInx;
3682 __le32 rspGetInx;
3683 };
3684
3685 struct lpfc_pgp {
3686 __le32 cmdGetInx;
3687 __le32 rspPutInx;
3688 };
3689
3690 struct sli2_desc {
3691 uint32_t unused1[16];
3692 struct lpfc_hgp host[MAX_SLI3_RINGS];
3693 struct lpfc_pgp port[MAX_SLI3_RINGS];
3694 };
3695
3696 struct sli3_desc {
3697 struct lpfc_hgp host[MAX_SLI3_RINGS];
3698 uint32_t reserved[8];
3699 uint32_t hbq_put[16];
3700 };
3701
3702 struct sli3_pgp {
3703 struct lpfc_pgp port[MAX_SLI3_RINGS];
3704 uint32_t hbq_get[16];
3705 };
3706
3707 union sli_var {
3708 struct sli2_desc s2;
3709 struct sli3_desc s3;
3710 struct sli3_pgp s3_pgp;
3711 };
3712
3713 typedef struct {
3714 struct_group_tagged(MAILBOX_word0, bits,
3715 union {
3716 struct {
3717 #ifdef __BIG_ENDIAN_BITFIELD
3718 uint16_t mbxStatus;
3719 uint8_t mbxCommand;
3720 uint8_t mbxReserved:6;
3721 uint8_t mbxHc:1;
3722 uint8_t mbxOwner:1; /* Low order bit first word */
3723 #else /* __LITTLE_ENDIAN_BITFIELD */
3724 uint8_t mbxOwner:1; /* Low order bit first word */
3725 uint8_t mbxHc:1;
3726 uint8_t mbxReserved:6;
3727 uint8_t mbxCommand;
3728 uint16_t mbxStatus;
3729 #endif
3730 };
3731 u32 word0;
3732 };
3733 );
3734
3735 MAILVARIANTS un;
3736 union sli_var us;
3737 } MAILBOX_t;
3738
3739 /*
3740 * Begin Structure Definitions for IOCB Commands
3741 */
3742
3743 typedef struct {
3744 #ifdef __BIG_ENDIAN_BITFIELD
3745 uint8_t statAction;
3746 uint8_t statRsn;
3747 uint8_t statBaExp;
3748 uint8_t statLocalError;
3749 #else /* __LITTLE_ENDIAN_BITFIELD */
3750 uint8_t statLocalError;
3751 uint8_t statBaExp;
3752 uint8_t statRsn;
3753 uint8_t statAction;
3754 #endif
3755 /* statRsn P/F_RJT reason codes */
3756 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3757 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3758 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3759 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3760 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3761 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3762 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3763 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3764 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3765 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3766 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3767 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3768 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3769 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3770 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3771 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3772 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3773 #define RJT_PROT_ERR 0x12 /* Protocol error */
3774 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3775 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3776 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3777 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3778 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3779 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3780 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3781 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3782
3783 #define IOERR_SUCCESS 0x00 /* statLocalError */
3784 #define IOERR_MISSING_CONTINUE 0x01
3785 #define IOERR_SEQUENCE_TIMEOUT 0x02
3786 #define IOERR_INTERNAL_ERROR 0x03
3787 #define IOERR_INVALID_RPI 0x04
3788 #define IOERR_NO_XRI 0x05
3789 #define IOERR_ILLEGAL_COMMAND 0x06
3790 #define IOERR_XCHG_DROPPED 0x07
3791 #define IOERR_ILLEGAL_FIELD 0x08
3792 #define IOERR_RPI_SUSPENDED 0x09
3793 #define IOERR_TOO_MANY_BUFFERS 0x0A
3794 #define IOERR_RCV_BUFFER_WAITING 0x0B
3795 #define IOERR_NO_CONNECTION 0x0C
3796 #define IOERR_TX_DMA_FAILED 0x0D
3797 #define IOERR_RX_DMA_FAILED 0x0E
3798 #define IOERR_ILLEGAL_FRAME 0x0F
3799 #define IOERR_EXTRA_DATA 0x10
3800 #define IOERR_NO_RESOURCES 0x11
3801 #define IOERR_RESERVED 0x12
3802 #define IOERR_ILLEGAL_LENGTH 0x13
3803 #define IOERR_UNSUPPORTED_FEATURE 0x14
3804 #define IOERR_ABORT_IN_PROGRESS 0x15
3805 #define IOERR_ABORT_REQUESTED 0x16
3806 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3807 #define IOERR_LOOP_OPEN_FAILURE 0x18
3808 #define IOERR_RING_RESET 0x19
3809 #define IOERR_LINK_DOWN 0x1A
3810 #define IOERR_CORRUPTED_DATA 0x1B
3811 #define IOERR_CORRUPTED_RPI 0x1C
3812 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3813 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3814 #define IOERR_DUP_FRAME 0x1F
3815 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3816 #define IOERR_BAD_HOST_ADDRESS 0x21
3817 #define IOERR_RCV_HDRBUF_WAITING 0x22
3818 #define IOERR_MISSING_HDR_BUFFER 0x23
3819 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3820 #define IOERR_ABORTMULT_REQUESTED 0x25
3821 #define IOERR_BUFFER_SHORTAGE 0x28
3822 #define IOERR_DEFAULT 0x29
3823 #define IOERR_CNT 0x2A
3824 #define IOERR_SLER_FAILURE 0x46
3825 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3826 #define IOERR_SLER_REC_RJT_ERR 0x48
3827 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3828 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3829 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3830 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3831 #define IOERR_SLER_ABTS_ERR 0x4E
3832 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3833 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3834 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3835 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3836 #define IOERR_DRVR_MASK 0x100
3837 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3838 #define IOERR_SLI_BRESET 0x102
3839 #define IOERR_SLI_ABORTED 0x103
3840 #define IOERR_PARAM_MASK 0x1ff
3841 } PARM_ERR;
3842
3843 typedef union {
3844 struct {
3845 #ifdef __BIG_ENDIAN_BITFIELD
3846 uint8_t Rctl; /* R_CTL field */
3847 uint8_t Type; /* TYPE field */
3848 uint8_t Dfctl; /* DF_CTL field */
3849 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3850 #else /* __LITTLE_ENDIAN_BITFIELD */
3851 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3852 uint8_t Dfctl; /* DF_CTL field */
3853 uint8_t Type; /* TYPE field */
3854 uint8_t Rctl; /* R_CTL field */
3855 #endif
3856
3857 #define BC 0x02 /* Broadcast Received - Fctl */
3858 #define SI 0x04 /* Sequence Initiative */
3859 #define LA 0x08 /* Ignore Link Attention state */
3860 #define LS 0x80 /* Last Sequence */
3861 } hcsw;
3862 uint32_t reserved;
3863 } WORD5;
3864
3865 /* IOCB Command template for a generic response */
3866 typedef struct {
3867 uint32_t reserved[4];
3868 PARM_ERR perr;
3869 } GENERIC_RSP;
3870
3871 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3872 typedef struct {
3873 struct ulp_bde xrsqbde[2];
3874 uint32_t xrsqRo; /* Starting Relative Offset */
3875 WORD5 w5; /* Header control/status word */
3876 } XR_SEQ_FIELDS;
3877
3878 /* IOCB Command template for ELS_REQUEST */
3879 typedef struct {
3880 struct ulp_bde elsReq;
3881 struct ulp_bde elsRsp;
3882
3883 #ifdef __BIG_ENDIAN_BITFIELD
3884 uint32_t word4Rsvd:7;
3885 uint32_t fl:1;
3886 uint32_t myID:24;
3887 uint32_t word5Rsvd:8;
3888 uint32_t remoteID:24;
3889 #else /* __LITTLE_ENDIAN_BITFIELD */
3890 uint32_t myID:24;
3891 uint32_t fl:1;
3892 uint32_t word4Rsvd:7;
3893 uint32_t remoteID:24;
3894 uint32_t word5Rsvd:8;
3895 #endif
3896 } ELS_REQUEST;
3897
3898 /* IOCB Command template for RCV_ELS_REQ */
3899 typedef struct {
3900 struct ulp_bde elsReq[2];
3901 uint32_t parmRo;
3902
3903 #ifdef __BIG_ENDIAN_BITFIELD
3904 uint32_t word5Rsvd:8;
3905 uint32_t remoteID:24;
3906 #else /* __LITTLE_ENDIAN_BITFIELD */
3907 uint32_t remoteID:24;
3908 uint32_t word5Rsvd:8;
3909 #endif
3910 } RCV_ELS_REQ;
3911
3912 /* IOCB Command template for ABORT / CLOSE_XRI */
3913 typedef struct {
3914 uint32_t rsvd[3];
3915 uint32_t abortType;
3916 #define ABORT_TYPE_ABTX 0x00000000
3917 #define ABORT_TYPE_ABTS 0x00000001
3918 uint32_t parm;
3919 #ifdef __BIG_ENDIAN_BITFIELD
3920 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3921 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3922 #else /* __LITTLE_ENDIAN_BITFIELD */
3923 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3924 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3925 #endif
3926 } AC_XRI;
3927
3928 /* IOCB Command template for ABORT_MXRI64 */
3929 typedef struct {
3930 uint32_t rsvd[3];
3931 uint32_t abortType;
3932 uint32_t parm;
3933 uint32_t iotag32;
3934 } A_MXRI64;
3935
3936 /* IOCB Command template for GET_RPI */
3937 typedef struct {
3938 uint32_t rsvd[4];
3939 uint32_t parmRo;
3940 #ifdef __BIG_ENDIAN_BITFIELD
3941 uint32_t word5Rsvd:8;
3942 uint32_t remoteID:24;
3943 #else /* __LITTLE_ENDIAN_BITFIELD */
3944 uint32_t remoteID:24;
3945 uint32_t word5Rsvd:8;
3946 #endif
3947 } GET_RPI;
3948
3949 /* IOCB Command template for all FCP Initiator commands */
3950 typedef struct {
3951 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3952 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3953 uint32_t fcpi_parm;
3954 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3955 } FCPI_FIELDS;
3956
3957 /* IOCB Command template for all FCP Target commands */
3958 typedef struct {
3959 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3960 uint32_t fcpt_Offset;
3961 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3962 } FCPT_FIELDS;
3963
3964 /* SLI-2 IOCB structure definitions */
3965
3966 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3967 typedef struct {
3968 ULP_BDL bdl;
3969 uint32_t xrsqRo; /* Starting Relative Offset */
3970 WORD5 w5; /* Header control/status word */
3971 } XMT_SEQ_FIELDS64;
3972
3973 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3974 #define xmit_els_remoteID xrsqRo
3975
3976 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3977 typedef struct {
3978 struct ulp_bde64 rcvBde;
3979 uint32_t rsvd1;
3980 uint32_t xrsqRo; /* Starting Relative Offset */
3981 WORD5 w5; /* Header control/status word */
3982 } RCV_SEQ_FIELDS64;
3983
3984 /* IOCB Command template for ELS_REQUEST64 */
3985 typedef struct {
3986 ULP_BDL bdl;
3987 #ifdef __BIG_ENDIAN_BITFIELD
3988 uint32_t word4Rsvd:7;
3989 uint32_t fl:1;
3990 uint32_t myID:24;
3991 uint32_t word5Rsvd:8;
3992 uint32_t remoteID:24;
3993 #else /* __LITTLE_ENDIAN_BITFIELD */
3994 uint32_t myID:24;
3995 uint32_t fl:1;
3996 uint32_t word4Rsvd:7;
3997 uint32_t remoteID:24;
3998 uint32_t word5Rsvd:8;
3999 #endif
4000 } ELS_REQUEST64;
4001
4002 /* IOCB Command template for GEN_REQUEST64 */
4003 typedef struct {
4004 ULP_BDL bdl;
4005 uint32_t xrsqRo; /* Starting Relative Offset */
4006 WORD5 w5; /* Header control/status word */
4007 } GEN_REQUEST64;
4008
4009 /* IOCB Command template for RCV_ELS_REQ64 */
4010 typedef struct {
4011 struct ulp_bde64 elsReq;
4012 uint32_t rcvd1;
4013 uint32_t parmRo;
4014
4015 #ifdef __BIG_ENDIAN_BITFIELD
4016 uint32_t word5Rsvd:8;
4017 uint32_t remoteID:24;
4018 #else /* __LITTLE_ENDIAN_BITFIELD */
4019 uint32_t remoteID:24;
4020 uint32_t word5Rsvd:8;
4021 #endif
4022 } RCV_ELS_REQ64;
4023
4024 /* IOCB Command template for RCV_SEQ64 */
4025 struct rcv_seq64 {
4026 struct ulp_bde64 elsReq;
4027 uint32_t hbq_1;
4028 uint32_t parmRo;
4029 #ifdef __BIG_ENDIAN_BITFIELD
4030 uint32_t rctl:8;
4031 uint32_t type:8;
4032 uint32_t dfctl:8;
4033 uint32_t ls:1;
4034 uint32_t fs:1;
4035 uint32_t rsvd2:3;
4036 uint32_t si:1;
4037 uint32_t bc:1;
4038 uint32_t rsvd3:1;
4039 #else /* __LITTLE_ENDIAN_BITFIELD */
4040 uint32_t rsvd3:1;
4041 uint32_t bc:1;
4042 uint32_t si:1;
4043 uint32_t rsvd2:3;
4044 uint32_t fs:1;
4045 uint32_t ls:1;
4046 uint32_t dfctl:8;
4047 uint32_t type:8;
4048 uint32_t rctl:8;
4049 #endif
4050 };
4051
4052 /* IOCB Command template for all 64 bit FCP Initiator commands */
4053 typedef struct {
4054 ULP_BDL bdl;
4055 uint32_t fcpi_parm;
4056 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
4057 } FCPI_FIELDS64;
4058
4059 /* IOCB Command template for all 64 bit FCP Target commands */
4060 typedef struct {
4061 ULP_BDL bdl;
4062 uint32_t fcpt_Offset;
4063 uint32_t fcpt_Length; /* transfer ready for IWRITE */
4064 } FCPT_FIELDS64;
4065
4066 /* IOCB Command template for Async Status iocb commands */
4067 typedef struct {
4068 uint32_t rsvd[4];
4069 uint32_t param;
4070 #ifdef __BIG_ENDIAN_BITFIELD
4071 uint16_t evt_code; /* High order bits word 5 */
4072 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
4073 #else /* __LITTLE_ENDIAN_BITFIELD */
4074 uint16_t sub_ctxt_tag; /* High order bits word 5 */
4075 uint16_t evt_code; /* Low order bits word 5 */
4076 #endif
4077 } ASYNCSTAT_FIELDS;
4078 #define ASYNC_TEMP_WARN 0x100
4079 #define ASYNC_TEMP_SAFE 0x101
4080 #define ASYNC_STATUS_CN 0x102
4081
4082 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4083 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4084
4085 struct rcv_sli3 {
4086 #ifdef __BIG_ENDIAN_BITFIELD
4087 uint16_t ox_id;
4088 uint16_t seq_cnt;
4089
4090 uint16_t vpi;
4091 uint16_t word9Rsvd;
4092 #else /* __LITTLE_ENDIAN */
4093 uint16_t seq_cnt;
4094 uint16_t ox_id;
4095
4096 uint16_t word9Rsvd;
4097 uint16_t vpi;
4098 #endif
4099 uint32_t word10Rsvd;
4100 uint32_t acc_len; /* accumulated length */
4101 struct ulp_bde64 bde2;
4102 };
4103
4104 /* Structure used for a single HBQ entry */
4105 struct lpfc_hbq_entry {
4106 struct ulp_bde64 bde;
4107 uint32_t buffer_tag;
4108 };
4109
4110 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4111 typedef struct {
4112 struct lpfc_hbq_entry buff;
4113 uint32_t rsvd;
4114 uint32_t rsvd1;
4115 } QUE_XRI64_CX_FIELDS;
4116
4117 struct que_xri64cx_ext_fields {
4118 uint32_t iotag64_low;
4119 uint32_t iotag64_high;
4120 uint32_t ebde_count;
4121 uint32_t rsvd;
4122 struct lpfc_hbq_entry buff[5];
4123 };
4124
4125 struct sli3_bg_fields {
4126 uint32_t filler[6]; /* word 8-13 in IOCB */
4127 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
4128 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
4129 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
4130 #define BGS_BIDIR_BG_PROF_SHIFT 24
4131 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
4132 #define BGS_BIDIR_ERR_COND_SHIFT 16
4133 #define BGS_BG_PROFILE_MASK 0x0000ff00
4134 #define BGS_BG_PROFILE_SHIFT 8
4135 #define BGS_INVALID_PROF_MASK 0x00000020
4136 #define BGS_INVALID_PROF_SHIFT 5
4137 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
4138 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
4139 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
4140 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4141 #define BGS_REFTAG_ERR_MASK 0x00000004
4142 #define BGS_REFTAG_ERR_SHIFT 2
4143 #define BGS_APPTAG_ERR_MASK 0x00000002
4144 #define BGS_APPTAG_ERR_SHIFT 1
4145 #define BGS_GUARD_ERR_MASK 0x00000001
4146 #define BGS_GUARD_ERR_SHIFT 0
4147 uint32_t bgstat; /* word 15 - BlockGuard Status */
4148 };
4149
4150 static inline uint32_t
lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)4151 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4152 {
4153 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4154 BGS_BIDIR_BG_PROF_SHIFT;
4155 }
4156
4157 static inline uint32_t
lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)4158 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4159 {
4160 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4161 BGS_BIDIR_ERR_COND_SHIFT;
4162 }
4163
4164 static inline uint32_t
lpfc_bgs_get_bg_prof(uint32_t bgstat)4165 lpfc_bgs_get_bg_prof(uint32_t bgstat)
4166 {
4167 return (bgstat & BGS_BG_PROFILE_MASK) >>
4168 BGS_BG_PROFILE_SHIFT;
4169 }
4170
4171 static inline uint32_t
lpfc_bgs_get_invalid_prof(uint32_t bgstat)4172 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4173 {
4174 return (bgstat & BGS_INVALID_PROF_MASK) >>
4175 BGS_INVALID_PROF_SHIFT;
4176 }
4177
4178 static inline uint32_t
lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)4179 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4180 {
4181 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4182 BGS_UNINIT_DIF_BLOCK_SHIFT;
4183 }
4184
4185 static inline uint32_t
lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)4186 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4187 {
4188 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4189 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4190 }
4191
4192 static inline uint32_t
lpfc_bgs_get_reftag_err(uint32_t bgstat)4193 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4194 {
4195 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4196 BGS_REFTAG_ERR_SHIFT;
4197 }
4198
4199 static inline uint32_t
lpfc_bgs_get_apptag_err(uint32_t bgstat)4200 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4201 {
4202 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4203 BGS_APPTAG_ERR_SHIFT;
4204 }
4205
4206 static inline uint32_t
lpfc_bgs_get_guard_err(uint32_t bgstat)4207 lpfc_bgs_get_guard_err(uint32_t bgstat)
4208 {
4209 return (bgstat & BGS_GUARD_ERR_MASK) >>
4210 BGS_GUARD_ERR_SHIFT;
4211 }
4212
4213 #define LPFC_EXT_DATA_BDE_COUNT 3
4214 struct fcp_irw_ext {
4215 uint32_t io_tag64_low;
4216 uint32_t io_tag64_high;
4217 #ifdef __BIG_ENDIAN_BITFIELD
4218 uint8_t reserved1;
4219 uint8_t reserved2;
4220 uint8_t reserved3;
4221 uint8_t ebde_count;
4222 #else /* __LITTLE_ENDIAN */
4223 uint8_t ebde_count;
4224 uint8_t reserved3;
4225 uint8_t reserved2;
4226 uint8_t reserved1;
4227 #endif
4228 uint32_t reserved4;
4229 struct ulp_bde64 rbde; /* response bde */
4230 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4231 uint8_t icd[32]; /* immediate command data (32 bytes) */
4232 };
4233
4234 typedef struct _IOCB { /* IOCB structure */
4235 union {
4236 GENERIC_RSP grsp; /* Generic response */
4237 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4238 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4239 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4240 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4241 A_MXRI64 amxri; /* abort multiple xri command overlay */
4242 GET_RPI getrpi; /* GET_RPI template */
4243 FCPI_FIELDS fcpi; /* FCP Initiator template */
4244 FCPT_FIELDS fcpt; /* FCP target template */
4245
4246 /* SLI-2 structures */
4247
4248 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4249 * bde_64s */
4250 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4251 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4252 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4253 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4254 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4255 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4256 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4257 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4258 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4259 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4260 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4261 } un;
4262 union {
4263 struct {
4264 #ifdef __BIG_ENDIAN_BITFIELD
4265 uint16_t ulpContext; /* High order bits word 6 */
4266 uint16_t ulpIoTag; /* Low order bits word 6 */
4267 #else /* __LITTLE_ENDIAN_BITFIELD */
4268 uint16_t ulpIoTag; /* Low order bits word 6 */
4269 uint16_t ulpContext; /* High order bits word 6 */
4270 #endif
4271 } t1;
4272 struct {
4273 #ifdef __BIG_ENDIAN_BITFIELD
4274 uint16_t ulpContext; /* High order bits word 6 */
4275 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4276 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4277 #else /* __LITTLE_ENDIAN_BITFIELD */
4278 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4279 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4280 uint16_t ulpContext; /* High order bits word 6 */
4281 #endif
4282 } t2;
4283 } un1;
4284 #define ulpContext un1.t1.ulpContext
4285 #define ulpIoTag un1.t1.ulpIoTag
4286 #define ulpIoTag0 un1.t2.ulpIoTag0
4287
4288 #ifdef __BIG_ENDIAN_BITFIELD
4289 uint32_t ulpTimeout:8;
4290 uint32_t ulpXS:1;
4291 uint32_t ulpFCP2Rcvy:1;
4292 uint32_t ulpPU:2;
4293 uint32_t ulpIr:1;
4294 uint32_t ulpClass:3;
4295 uint32_t ulpCommand:8;
4296 uint32_t ulpStatus:4;
4297 uint32_t ulpBdeCount:2;
4298 uint32_t ulpLe:1;
4299 uint32_t ulpOwner:1; /* Low order bit word 7 */
4300 #else /* __LITTLE_ENDIAN_BITFIELD */
4301 uint32_t ulpOwner:1; /* Low order bit word 7 */
4302 uint32_t ulpLe:1;
4303 uint32_t ulpBdeCount:2;
4304 uint32_t ulpStatus:4;
4305 uint32_t ulpCommand:8;
4306 uint32_t ulpClass:3;
4307 uint32_t ulpIr:1;
4308 uint32_t ulpPU:2;
4309 uint32_t ulpFCP2Rcvy:1;
4310 uint32_t ulpXS:1;
4311 uint32_t ulpTimeout:8;
4312 #endif
4313
4314 union {
4315 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4316
4317 /* words 8-31 used for que_xri_cx iocb */
4318 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4319 struct fcp_irw_ext fcp_ext;
4320 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4321
4322 /* words 8-15 for BlockGuard */
4323 struct sli3_bg_fields sli3_bg;
4324 } unsli3;
4325
4326 #define ulpCt_h ulpXS
4327 #define ulpCt_l ulpFCP2Rcvy
4328
4329 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4330 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4331 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4332 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4333 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4334 #define PARM_NPIV_DID 3
4335 #define CLASS1 0 /* Class 1 */
4336 #define CLASS2 1 /* Class 2 */
4337 #define CLASS3 2 /* Class 3 */
4338 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4339
4340 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4341 #define IOSTAT_FCP_RSP_ERROR 0x1
4342 #define IOSTAT_REMOTE_STOP 0x2
4343 #define IOSTAT_LOCAL_REJECT 0x3
4344 #define IOSTAT_NPORT_RJT 0x4
4345 #define IOSTAT_FABRIC_RJT 0x5
4346 #define IOSTAT_NPORT_BSY 0x6
4347 #define IOSTAT_FABRIC_BSY 0x7
4348 #define IOSTAT_INTERMED_RSP 0x8
4349 #define IOSTAT_LS_RJT 0x9
4350 #define IOSTAT_BA_RJT 0xA
4351 #define IOSTAT_RSVD1 0xB
4352 #define IOSTAT_RSVD2 0xC
4353 #define IOSTAT_RSVD3 0xD
4354 #define IOSTAT_RSVD4 0xE
4355 #define IOSTAT_NEED_BUFFER 0xF
4356 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4357 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4358 #define IOSTAT_CNT 0x11
4359
4360 } IOCB_t;
4361
4362
4363 #define SLI1_SLIM_SIZE (4 * 1024)
4364
4365 /* Up to 498 IOCBs will fit into 16k
4366 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4367 */
4368 #define SLI2_SLIM_SIZE (64 * 1024)
4369
4370 /* Maximum IOCBs that will fit in SLI2 slim */
4371 #define MAX_SLI2_IOCB 498
4372 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4373 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4374 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4375
4376 /* HBQ entries are 4 words each = 4k */
4377 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4378 lpfc_sli_hbq_count())
4379
4380 struct lpfc_sli2_slim {
4381 MAILBOX_t mbx;
4382 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4383 PCB_t pcb;
4384 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4385 };
4386
4387 /*
4388 * This function checks PCI device to allow special handling for LC HBAs.
4389 *
4390 * Parameters:
4391 * device : struct pci_dev 's device field
4392 *
4393 * return 1 => TRUE
4394 * 0 => FALSE
4395 */
4396 static inline int
lpfc_is_LC_HBA(unsigned short device)4397 lpfc_is_LC_HBA(unsigned short device)
4398 {
4399 if ((device == PCI_DEVICE_ID_TFLY) ||
4400 (device == PCI_DEVICE_ID_PFLY) ||
4401 (device == PCI_DEVICE_ID_LP101) ||
4402 (device == PCI_DEVICE_ID_BMID) ||
4403 (device == PCI_DEVICE_ID_BSMB) ||
4404 (device == PCI_DEVICE_ID_ZMID) ||
4405 (device == PCI_DEVICE_ID_ZSMB) ||
4406 (device == PCI_DEVICE_ID_SAT_MID) ||
4407 (device == PCI_DEVICE_ID_SAT_SMB) ||
4408 (device == PCI_DEVICE_ID_RFLY))
4409 return 1;
4410 else
4411 return 0;
4412 }
4413
4414 /*
4415 * Determine if failed because of a link event or firmware reset.
4416 */
4417 static inline int
lpfc_error_lost_link(u32 ulp_status,u32 ulp_word4)4418 lpfc_error_lost_link(u32 ulp_status, u32 ulp_word4)
4419 {
4420 return (ulp_status == IOSTAT_LOCAL_REJECT &&
4421 (ulp_word4 == IOERR_SLI_ABORTED ||
4422 ulp_word4 == IOERR_LINK_DOWN ||
4423 ulp_word4 == IOERR_SLI_DOWN));
4424 }
4425
4426 #define MENLO_TRANSPORT_TYPE 0xfe
4427 #define MENLO_CONTEXT 0
4428 #define MENLO_PU 3
4429 #define MENLO_TIMEOUT 30
4430 #define SETVAR_MLOMNT 0x103107
4431 #define SETVAR_MLORST 0x103007
4432
4433 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4434