1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license.  When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 //	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 //	    Rander Wang <rander.wang@intel.com>
11 //          Keyon Jie <yang.jie@linux.intel.com>
12 //
13 
14 /*
15  * Hardware interface for HDA DSP code loader
16  */
17 
18 #include <linux/firmware.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include <sound/sof.h>
22 #include "ext_manifest.h"
23 #include "../ops.h"
24 #include "../sof-priv.h"
25 #include "hda.h"
26 
hda_ssp_set_cbp_cfp(struct snd_sof_dev * sdev)27 static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev)
28 {
29 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
30 	const struct sof_intel_dsp_desc *chip = hda->desc;
31 	int i;
32 
33 	/* DSP is powered up, set all SSPs to clock consumer/codec provider mode */
34 	for (i = 0; i < chip->ssp_count; i++) {
35 		snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
36 						 chip->ssp_base_offset
37 						 + i * SSP_DEV_MEM_SIZE
38 						 + SSP_SSC1_OFFSET,
39 						 SSP_SET_CBP_CFP,
40 						 SSP_SET_CBP_CFP);
41 	}
42 }
43 
hda_cl_stream_prepare(struct snd_sof_dev * sdev,unsigned int format,unsigned int size,struct snd_dma_buffer * dmab,int direction)44 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
45 					      unsigned int size, struct snd_dma_buffer *dmab,
46 					      int direction)
47 {
48 	struct hdac_ext_stream *hext_stream;
49 	struct hdac_stream *hstream;
50 	struct pci_dev *pci = to_pci_dev(sdev->dev);
51 	int ret;
52 
53 	hext_stream = hda_dsp_stream_get(sdev, direction, 0);
54 
55 	if (!hext_stream) {
56 		dev_err(sdev->dev, "error: no stream available\n");
57 		return ERR_PTR(-ENODEV);
58 	}
59 	hstream = &hext_stream->hstream;
60 	hstream->substream = NULL;
61 
62 	/* allocate DMA buffer */
63 	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
64 	if (ret < 0) {
65 		dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret);
66 		goto out_put;
67 	}
68 
69 	hstream->period_bytes = 0;/* initialize period_bytes */
70 	hstream->format_val = format;
71 	hstream->bufsize = size;
72 
73 	if (direction == SNDRV_PCM_STREAM_CAPTURE) {
74 		ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL);
75 		if (ret < 0) {
76 			dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret);
77 			goto out_free;
78 		}
79 	} else {
80 		ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL);
81 		if (ret < 0) {
82 			dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret);
83 			goto out_free;
84 		}
85 		hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size);
86 	}
87 
88 	return hext_stream;
89 
90 out_free:
91 	snd_dma_free_pages(dmab);
92 out_put:
93 	hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
94 	return ERR_PTR(ret);
95 }
96 
97 /*
98  * first boot sequence has some extra steps.
99  * power on all host managed cores and only unstall/run the boot core to boot the
100  * DSP then turn off all non boot cores (if any) is powered on.
101  */
cl_dsp_init(struct snd_sof_dev * sdev,int stream_tag,bool imr_boot)102 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
103 {
104 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
105 	const struct sof_intel_dsp_desc *chip = hda->desc;
106 	unsigned int status, target_status;
107 	u32 flags, ipc_hdr, j;
108 	unsigned long mask;
109 	char *dump_msg;
110 	int ret;
111 
112 	/* step 1: power up corex */
113 	ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
114 	if (ret < 0) {
115 		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
116 			dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
117 		goto err;
118 	}
119 
120 	hda_ssp_set_cbp_cfp(sdev);
121 
122 	/* step 2: Send ROM_CONTROL command (stream_tag is ignored for IMR boot) */
123 	ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
124 	if (!imr_boot)
125 		ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
126 
127 	snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
128 
129 	/* step 3: unset core 0 reset state & unstall/run core 0 */
130 	ret = hda_dsp_core_run(sdev, chip->init_core_mask);
131 	if (ret < 0) {
132 		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
133 			dev_err(sdev->dev,
134 				"error: dsp core start failed %d\n", ret);
135 		ret = -EIO;
136 		goto err;
137 	}
138 
139 	/* step 4: wait for IPC DONE bit from ROM */
140 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
141 					    chip->ipc_ack, status,
142 					    ((status & chip->ipc_ack_mask)
143 						    == chip->ipc_ack_mask),
144 					    HDA_DSP_REG_POLL_INTERVAL_US,
145 					    HDA_DSP_INIT_TIMEOUT_US);
146 
147 	if (ret < 0) {
148 		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
149 			dev_err(sdev->dev,
150 				"error: %s: timeout for HIPCIE done\n",
151 				__func__);
152 		goto err;
153 	}
154 
155 	/* set DONE bit to clear the reply IPC message */
156 	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
157 				       chip->ipc_ack,
158 				       chip->ipc_ack_mask,
159 				       chip->ipc_ack_mask);
160 
161 	/* step 5: power down cores that are no longer needed */
162 	ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask &
163 					   ~(chip->init_core_mask));
164 	if (ret < 0) {
165 		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
166 			dev_err(sdev->dev,
167 				"error: dsp core x power down failed\n");
168 		goto err;
169 	}
170 
171 	/* step 6: enable IPC interrupts */
172 	hda_dsp_ipc_int_enable(sdev);
173 
174 	/*
175 	 * step 7:
176 	 * - Cold/Full boot: wait for ROM init to proceed to download the firmware
177 	 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
178 	 */
179 	if (imr_boot)
180 		target_status = FSR_STATE_FW_ENTERED;
181 	else
182 		target_status = FSR_STATE_INIT_DONE;
183 
184 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
185 					chip->rom_status_reg, status,
186 					(FSR_TO_STATE_CODE(status) == target_status),
187 					HDA_DSP_REG_POLL_INTERVAL_US,
188 					chip->rom_init_timeout *
189 					USEC_PER_MSEC);
190 	if (!ret) {
191 		/* set enabled cores mask and increment ref count for cores in init_core_mask */
192 		sdev->enabled_cores_mask |= chip->init_core_mask;
193 		mask = sdev->enabled_cores_mask;
194 		for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES)
195 			sdev->dsp_core_ref_count[j]++;
196 		return 0;
197 	}
198 
199 	if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
200 		dev_err(sdev->dev,
201 			"%s: timeout with rom_status_reg (%#x) read\n",
202 			__func__, chip->rom_status_reg);
203 
204 err:
205 	flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
206 
207 	/* after max boot attempts make sure that the dump is printed */
208 	if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
209 		flags &= ~SOF_DBG_DUMP_OPTIONAL;
210 
211 	dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
212 			     hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
213 	snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
214 	hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
215 
216 	kfree(dump_msg);
217 	return ret;
218 }
219 
cl_trigger(struct snd_sof_dev * sdev,struct hdac_ext_stream * hext_stream,int cmd)220 static int cl_trigger(struct snd_sof_dev *sdev,
221 		      struct hdac_ext_stream *hext_stream, int cmd)
222 {
223 	struct hdac_stream *hstream = &hext_stream->hstream;
224 	int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
225 
226 	/* code loader is special case that reuses stream ops */
227 	switch (cmd) {
228 	case SNDRV_PCM_TRIGGER_START:
229 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
230 					1 << hstream->index,
231 					1 << hstream->index);
232 
233 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
234 					sd_offset,
235 					SOF_HDA_SD_CTL_DMA_START |
236 					SOF_HDA_CL_DMA_SD_INT_MASK,
237 					SOF_HDA_SD_CTL_DMA_START |
238 					SOF_HDA_CL_DMA_SD_INT_MASK);
239 
240 		hstream->running = true;
241 		return 0;
242 	default:
243 		return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
244 	}
245 }
246 
hda_cl_cleanup(struct snd_sof_dev * sdev,struct snd_dma_buffer * dmab,struct hdac_ext_stream * hext_stream)247 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
248 		   struct hdac_ext_stream *hext_stream)
249 {
250 	struct hdac_stream *hstream = &hext_stream->hstream;
251 	int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
252 	int ret = 0;
253 
254 	if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
255 		ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
256 	else
257 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
258 					SOF_HDA_SD_CTL_DMA_START, 0);
259 
260 	hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
261 	hstream->running = 0;
262 	hstream->substream = NULL;
263 
264 	/* reset BDL address */
265 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
266 			  sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
267 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
268 			  sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
269 
270 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
271 	snd_dma_free_pages(dmab);
272 	dmab->area = NULL;
273 	hstream->bufsize = 0;
274 	hstream->format_val = 0;
275 
276 	return ret;
277 }
278 
hda_cl_copy_fw(struct snd_sof_dev * sdev,struct hdac_ext_stream * hext_stream)279 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream)
280 {
281 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
282 	const struct sof_intel_dsp_desc *chip = hda->desc;
283 	unsigned int reg;
284 	int ret, status;
285 
286 	ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START);
287 	if (ret < 0) {
288 		dev_err(sdev->dev, "error: DMA trigger start failed\n");
289 		return ret;
290 	}
291 
292 	status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
293 					chip->rom_status_reg, reg,
294 					(FSR_TO_STATE_CODE(reg) == FSR_STATE_FW_ENTERED),
295 					HDA_DSP_REG_POLL_INTERVAL_US,
296 					HDA_DSP_BASEFW_TIMEOUT_US);
297 
298 	/*
299 	 * even in case of errors we still need to stop the DMAs,
300 	 * but we return the initial error should the DMA stop also fail
301 	 */
302 
303 	if (status < 0) {
304 		dev_err(sdev->dev,
305 			"%s: timeout with rom_status_reg (%#x) read\n",
306 			__func__, chip->rom_status_reg);
307 	}
308 
309 	ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
310 	if (ret < 0) {
311 		dev_err(sdev->dev, "error: DMA trigger stop failed\n");
312 		if (!status)
313 			status = ret;
314 	}
315 
316 	return status;
317 }
318 
hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev * sdev)319 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
320 {
321 	struct snd_sof_pdata *plat_data = sdev->pdata;
322 	struct hdac_ext_stream *iccmax_stream;
323 	struct hdac_bus *bus = sof_to_bus(sdev);
324 	struct firmware stripped_firmware;
325 	struct snd_dma_buffer dmab_bdl;
326 	int ret, ret1;
327 	u8 original_gb;
328 
329 	/* save the original LTRP guardband value */
330 	original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
331 
332 	if (plat_data->fw->size <= plat_data->fw_offset) {
333 		dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
334 		return -EINVAL;
335 	}
336 
337 	stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
338 
339 	/* prepare capture stream for ICCMAX */
340 	iccmax_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
341 					      &dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
342 	if (IS_ERR(iccmax_stream)) {
343 		dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
344 		return PTR_ERR(iccmax_stream);
345 	}
346 
347 	ret = hda_dsp_cl_boot_firmware(sdev);
348 
349 	/*
350 	 * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
351 	 * If the cleanup also fails, we return the initial error
352 	 */
353 	ret1 = hda_cl_cleanup(sdev, &dmab_bdl, iccmax_stream);
354 	if (ret1 < 0) {
355 		dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
356 
357 		/* set return value to indicate cleanup failure */
358 		if (!ret)
359 			ret = ret1;
360 	}
361 
362 	/* restore the original guardband value after FW boot */
363 	snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
364 
365 	return ret;
366 }
367 
hda_dsp_boot_imr(struct snd_sof_dev * sdev)368 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
369 {
370 	const struct sof_intel_dsp_desc *chip_info;
371 	int ret;
372 
373 	chip_info = get_chip_info(sdev->pdata);
374 	if (chip_info->cl_init)
375 		ret = chip_info->cl_init(sdev, 0, true);
376 	else
377 		ret = -EINVAL;
378 
379 	if (!ret)
380 		hda_sdw_process_wakeen(sdev);
381 
382 	return ret;
383 }
384 
hda_dsp_cl_boot_firmware(struct snd_sof_dev * sdev)385 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
386 {
387 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
388 	struct snd_sof_pdata *plat_data = sdev->pdata;
389 	const struct sof_dev_desc *desc = plat_data->desc;
390 	const struct sof_intel_dsp_desc *chip_info;
391 	struct hdac_ext_stream *hext_stream;
392 	struct firmware stripped_firmware;
393 	struct snd_dma_buffer dmab;
394 	int ret, ret1, i;
395 
396 	if (hda->imrboot_supported && !sdev->first_boot && !hda->skip_imr_boot) {
397 		dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
398 		hda->boot_iteration = 0;
399 		ret = hda_dsp_boot_imr(sdev);
400 		if (!ret)
401 			return 0;
402 
403 		dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n");
404 	}
405 
406 	chip_info = desc->chip_info;
407 
408 	if (plat_data->fw->size <= plat_data->fw_offset) {
409 		dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
410 		return -EINVAL;
411 	}
412 
413 	stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
414 	stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
415 
416 	/* init for booting wait */
417 	init_waitqueue_head(&sdev->boot_wait);
418 
419 	/* prepare DMA for code loader stream */
420 	hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT,
421 					    stripped_firmware.size,
422 					    &dmab, SNDRV_PCM_STREAM_PLAYBACK);
423 	if (IS_ERR(hext_stream)) {
424 		dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
425 		return PTR_ERR(hext_stream);
426 	}
427 
428 	memcpy(dmab.area, stripped_firmware.data,
429 	       stripped_firmware.size);
430 
431 	/* try ROM init a few times before giving up */
432 	for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
433 		dev_dbg(sdev->dev,
434 			"Attempting iteration %d of Core En/ROM load...\n", i);
435 
436 		hda->boot_iteration = i + 1;
437 		if (chip_info->cl_init)
438 			ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
439 		else
440 			ret = -EINVAL;
441 
442 		/* don't retry anymore if successful */
443 		if (!ret)
444 			break;
445 	}
446 
447 	if (i == HDA_FW_BOOT_ATTEMPTS) {
448 		dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
449 			i, ret);
450 		goto cleanup;
451 	}
452 
453 	/*
454 	 * When a SoundWire link is in clock stop state, a Slave
455 	 * device may trigger in-band wakes for events such as jack
456 	 * insertion or acoustic event detection. This event will lead
457 	 * to a WAKEEN interrupt, handled by the PCI device and routed
458 	 * to PME if the PCI device is in D3. The resume function in
459 	 * audio PCI driver will be invoked by ACPI for PME event and
460 	 * initialize the device and process WAKEEN interrupt.
461 	 *
462 	 * The WAKEEN interrupt should be processed ASAP to prevent an
463 	 * interrupt flood, otherwise other interrupts, such IPC,
464 	 * cannot work normally.  The WAKEEN is handled after the ROM
465 	 * is initialized successfully, which ensures power rails are
466 	 * enabled before accessing the SoundWire SHIM registers
467 	 */
468 	if (!sdev->first_boot)
469 		hda_sdw_process_wakeen(sdev);
470 
471 	/*
472 	 * Set the boot_iteration to the last attempt, indicating that the
473 	 * DSP ROM has been initialized and from this point there will be no
474 	 * retry done to boot.
475 	 *
476 	 * Continue with code loading and firmware boot
477 	 */
478 	hda->boot_iteration = HDA_FW_BOOT_ATTEMPTS;
479 	ret = hda_cl_copy_fw(sdev, hext_stream);
480 	if (!ret) {
481 		dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
482 		hda->skip_imr_boot = false;
483 	} else {
484 		snd_sof_dsp_dbg_dump(sdev, "Firmware download failed",
485 				     SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX);
486 		hda->skip_imr_boot = true;
487 	}
488 
489 cleanup:
490 	/*
491 	 * Perform codeloader stream cleanup.
492 	 * This should be done even if firmware loading fails.
493 	 * If the cleanup also fails, we return the initial error
494 	 */
495 	ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream);
496 	if (ret1 < 0) {
497 		dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
498 
499 		/* set return value to indicate cleanup failure */
500 		if (!ret)
501 			ret = ret1;
502 	}
503 
504 	/*
505 	 * return primary core id if both fw copy
506 	 * and stream clean up are successful
507 	 */
508 	if (!ret)
509 		return chip_info->init_core_mask;
510 
511 	/* disable DSP */
512 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
513 				SOF_HDA_REG_PP_PPCTL,
514 				SOF_HDA_PPCTL_GPROCEN, 0);
515 	return ret;
516 }
517 
518 /* pre fw run operations */
hda_dsp_pre_fw_run(struct snd_sof_dev * sdev)519 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
520 {
521 	/* disable clock gating and power gating */
522 	return hda_dsp_ctrl_clock_power_gating(sdev, false);
523 }
524 
525 /* post fw run operations */
hda_dsp_post_fw_run(struct snd_sof_dev * sdev)526 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
527 {
528 	int ret;
529 
530 	if (sdev->first_boot) {
531 		struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
532 
533 		ret = hda_sdw_startup(sdev);
534 		if (ret < 0) {
535 			dev_err(sdev->dev,
536 				"error: could not startup SoundWire links\n");
537 			return ret;
538 		}
539 
540 		/* Check if IMR boot is usable */
541 		if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
542 		    (sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
543 		     sdev->pdata->ipc_type == SOF_INTEL_IPC4))
544 			hdev->imrboot_supported = true;
545 	}
546 
547 	hda_sdw_int_enable(sdev, true);
548 
549 	/* re-enable clock gating and power gating */
550 	return hda_dsp_ctrl_clock_power_gating(sdev, true);
551 }
552 
hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev * sdev,const struct sof_ext_man_elem_header * hdr)553 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
554 					 const struct sof_ext_man_elem_header *hdr)
555 {
556 	const struct sof_ext_man_cavs_config_data *config_data =
557 		container_of(hdr, struct sof_ext_man_cavs_config_data, hdr);
558 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
559 	int i, elem_num;
560 
561 	/* calculate total number of config data elements */
562 	elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header))
563 		   / sizeof(struct sof_config_elem);
564 	if (elem_num <= 0) {
565 		dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num);
566 		return -EINVAL;
567 	}
568 
569 	for (i = 0; i < elem_num; i++)
570 		switch (config_data->elems[i].token) {
571 		case SOF_EXT_MAN_CAVS_CONFIG_EMPTY:
572 			/* skip empty token */
573 			break;
574 		case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO:
575 			hda->clk_config_lpro = config_data->elems[i].value;
576 			dev_dbg(sdev->dev, "FW clock config: %s\n",
577 				hda->clk_config_lpro ? "LPRO" : "HPRO");
578 			break;
579 		case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE:
580 		case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE:
581 			/* These elements are defined but not being used yet. No warn is required */
582 			break;
583 		default:
584 			dev_info(sdev->dev, "unsupported token type: %d\n",
585 				 config_data->elems[i].token);
586 		}
587 
588 	return 0;
589 }
590