1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Synopsys DesignWare I2C adapter driver (master only).
4  *
5  * Based on the TI DAVINCI I2C adapter driver.
6  *
7  * Copyright (C) 2006 Texas Instruments.
8  * Copyright (C) 2007 MontaVista Software Inc.
9  * Copyright (C) 2009 Provigent Ltd.
10  * Copyright (C) 2011, 2015, 2016 Intel Corporation.
11  */
12 #include <linux/acpi.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 
26 #include "i2c-designware-core.h"
27 #include "i2c-ccgx-ucsi.h"
28 
29 #define DRIVER_NAME "i2c-designware-pci"
30 #define AMD_CLK_RATE_HZ	100000
31 
32 enum dw_pci_ctl_id_t {
33 	medfield,
34 	merrifield,
35 	baytrail,
36 	cherrytrail,
37 	haswell,
38 	elkhartlake,
39 	navi_amd,
40 };
41 
42 /*
43  * This is a legacy structure to describe the hardware counters
44  * to configure signal timings on the bus. For Device Tree platforms
45  * one should use the respective properties and for ACPI there is
46  * a set of ACPI methods that provide these counters. No new
47  * platform should use this structure.
48  */
49 struct dw_scl_sda_cfg {
50 	u16 ss_hcnt;
51 	u16 fs_hcnt;
52 	u16 ss_lcnt;
53 	u16 fs_lcnt;
54 	u32 sda_hold;
55 };
56 
57 struct dw_pci_controller {
58 	u32 bus_num;
59 	u32 flags;
60 	struct dw_scl_sda_cfg *scl_sda_cfg;
61 	int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
62 	u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
63 };
64 
65 /* Merrifield HCNT/LCNT/SDA hold time */
66 static struct dw_scl_sda_cfg mrfld_config = {
67 	.ss_hcnt = 0x2f8,
68 	.fs_hcnt = 0x87,
69 	.ss_lcnt = 0x37b,
70 	.fs_lcnt = 0x10a,
71 };
72 
73 /* BayTrail HCNT/LCNT/SDA hold time */
74 static struct dw_scl_sda_cfg byt_config = {
75 	.ss_hcnt = 0x200,
76 	.fs_hcnt = 0x55,
77 	.ss_lcnt = 0x200,
78 	.fs_lcnt = 0x99,
79 	.sda_hold = 0x6,
80 };
81 
82 /* Haswell HCNT/LCNT/SDA hold time */
83 static struct dw_scl_sda_cfg hsw_config = {
84 	.ss_hcnt = 0x01b0,
85 	.fs_hcnt = 0x48,
86 	.ss_lcnt = 0x01fb,
87 	.fs_lcnt = 0xa0,
88 	.sda_hold = 0x9,
89 };
90 
91 /* NAVI-AMD HCNT/LCNT/SDA hold time */
92 static struct dw_scl_sda_cfg navi_amd_config = {
93 	.ss_hcnt = 0x1ae,
94 	.ss_lcnt = 0x23a,
95 	.sda_hold = 0x9,
96 };
97 
mfld_get_clk_rate_khz(struct dw_i2c_dev * dev)98 static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
99 {
100 	return 25000;
101 }
102 
navi_amd_get_clk_rate_khz(struct dw_i2c_dev * dev)103 static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev)
104 {
105 	return AMD_CLK_RATE_HZ;
106 }
107 
mfld_setup(struct pci_dev * pdev,struct dw_pci_controller * c)108 static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
109 {
110 	struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
111 
112 	switch (pdev->device) {
113 	case 0x0817:
114 		dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
115 		fallthrough;
116 	case 0x0818:
117 	case 0x0819:
118 		c->bus_num = pdev->device - 0x817 + 3;
119 		return 0;
120 	case 0x082C:
121 	case 0x082D:
122 	case 0x082E:
123 		c->bus_num = pdev->device - 0x82C + 0;
124 		return 0;
125 	}
126 	return -ENODEV;
127 }
128 
navi_amd_setup(struct pci_dev * pdev,struct dw_pci_controller * c)129 static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
130 {
131 	struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
132 
133 	dev->flags |= MODEL_AMD_NAVI_GPU;
134 	dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
135 	return 0;
136 }
137 
mrfld_setup(struct pci_dev * pdev,struct dw_pci_controller * c)138 static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
139 {
140 	/*
141 	 * On Intel Merrifield the user visible i2c buses are enumerated
142 	 * [1..7]. So, we add 1 to shift the default range. Besides that the
143 	 * first PCI slot provides 4 functions, that's why we have to add 0 to
144 	 * the first slot and 4 to the next one.
145 	 */
146 	switch (PCI_SLOT(pdev->devfn)) {
147 	case 8:
148 		c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
149 		return 0;
150 	case 9:
151 		c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
152 		return 0;
153 	}
154 	return -ENODEV;
155 }
156 
ehl_get_clk_rate_khz(struct dw_i2c_dev * dev)157 static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
158 {
159 	return 100000;
160 }
161 
162 static struct dw_pci_controller dw_pci_controllers[] = {
163 	[medfield] = {
164 		.bus_num = -1,
165 		.setup = mfld_setup,
166 		.get_clk_rate_khz = mfld_get_clk_rate_khz,
167 	},
168 	[merrifield] = {
169 		.bus_num = -1,
170 		.scl_sda_cfg = &mrfld_config,
171 		.setup = mrfld_setup,
172 	},
173 	[baytrail] = {
174 		.bus_num = -1,
175 		.scl_sda_cfg = &byt_config,
176 	},
177 	[haswell] = {
178 		.bus_num = -1,
179 		.scl_sda_cfg = &hsw_config,
180 	},
181 	[cherrytrail] = {
182 		.bus_num = -1,
183 		.scl_sda_cfg = &byt_config,
184 	},
185 	[elkhartlake] = {
186 		.bus_num = -1,
187 		.get_clk_rate_khz = ehl_get_clk_rate_khz,
188 	},
189 	[navi_amd] = {
190 		.bus_num = -1,
191 		.scl_sda_cfg = &navi_amd_config,
192 		.setup =  navi_amd_setup,
193 		.get_clk_rate_khz = navi_amd_get_clk_rate_khz,
194 	},
195 };
196 
i2c_dw_pci_runtime_suspend(struct device * dev)197 static int __maybe_unused i2c_dw_pci_runtime_suspend(struct device *dev)
198 {
199 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
200 
201 	i_dev->disable(i_dev);
202 	return 0;
203 }
204 
i2c_dw_pci_suspend(struct device * dev)205 static int __maybe_unused i2c_dw_pci_suspend(struct device *dev)
206 {
207 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
208 
209 	i2c_mark_adapter_suspended(&i_dev->adapter);
210 
211 	return i2c_dw_pci_runtime_suspend(dev);
212 }
213 
i2c_dw_pci_runtime_resume(struct device * dev)214 static int __maybe_unused i2c_dw_pci_runtime_resume(struct device *dev)
215 {
216 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
217 
218 	return i_dev->init(i_dev);
219 }
220 
i2c_dw_pci_resume(struct device * dev)221 static int __maybe_unused i2c_dw_pci_resume(struct device *dev)
222 {
223 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
224 	int ret;
225 
226 	ret = i2c_dw_pci_runtime_resume(dev);
227 
228 	i2c_mark_adapter_resumed(&i_dev->adapter);
229 
230 	return ret;
231 }
232 
233 static const struct dev_pm_ops i2c_dw_pm_ops = {
234 	SET_SYSTEM_SLEEP_PM_OPS(i2c_dw_pci_suspend, i2c_dw_pci_resume)
235 	SET_RUNTIME_PM_OPS(i2c_dw_pci_runtime_suspend, i2c_dw_pci_runtime_resume, NULL)
236 };
237 
i2c_dw_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)238 static int i2c_dw_pci_probe(struct pci_dev *pdev,
239 			    const struct pci_device_id *id)
240 {
241 	struct dw_i2c_dev *dev;
242 	struct i2c_adapter *adap;
243 	int r;
244 	struct dw_pci_controller *controller;
245 	struct dw_scl_sda_cfg *cfg;
246 
247 	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers))
248 		return dev_err_probe(&pdev->dev, -EINVAL,
249 				     "Invalid driver data %ld\n",
250 				     id->driver_data);
251 
252 	controller = &dw_pci_controllers[id->driver_data];
253 
254 	r = pcim_enable_device(pdev);
255 	if (r)
256 		return dev_err_probe(&pdev->dev, r,
257 				     "Failed to enable I2C PCI device\n");
258 
259 	pci_set_master(pdev);
260 
261 	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
262 	if (r)
263 		return dev_err_probe(&pdev->dev, r,
264 				     "I/O memory remapping failed\n");
265 
266 	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
267 	if (!dev)
268 		return -ENOMEM;
269 
270 	r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
271 	if (r < 0)
272 		return r;
273 
274 	dev->get_clk_rate_khz = controller->get_clk_rate_khz;
275 	dev->timings.bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
276 	dev->base = pcim_iomap_table(pdev)[0];
277 	dev->dev = &pdev->dev;
278 	dev->irq = pci_irq_vector(pdev, 0);
279 	dev->flags |= controller->flags;
280 
281 	pci_set_drvdata(pdev, dev);
282 
283 	if (controller->setup) {
284 		r = controller->setup(pdev, controller);
285 		if (r) {
286 			pci_free_irq_vectors(pdev);
287 			return r;
288 		}
289 	}
290 
291 	i2c_dw_adjust_bus_speed(dev);
292 
293 	if (has_acpi_companion(&pdev->dev))
294 		i2c_dw_acpi_configure(&pdev->dev);
295 
296 	r = i2c_dw_validate_speed(dev);
297 	if (r) {
298 		pci_free_irq_vectors(pdev);
299 		return r;
300 	}
301 
302 	i2c_dw_configure(dev);
303 
304 	if (controller->scl_sda_cfg) {
305 		cfg = controller->scl_sda_cfg;
306 		dev->ss_hcnt = cfg->ss_hcnt;
307 		dev->fs_hcnt = cfg->fs_hcnt;
308 		dev->ss_lcnt = cfg->ss_lcnt;
309 		dev->fs_lcnt = cfg->fs_lcnt;
310 		dev->sda_hold_time = cfg->sda_hold;
311 	}
312 
313 	adap = &dev->adapter;
314 	adap->owner = THIS_MODULE;
315 	adap->class = 0;
316 	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
317 	adap->nr = controller->bus_num;
318 
319 	r = i2c_dw_probe(dev);
320 	if (r) {
321 		pci_free_irq_vectors(pdev);
322 		return r;
323 	}
324 
325 	if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
326 		dev->slave = i2c_new_ccgx_ucsi(&dev->adapter, dev->irq, NULL);
327 		if (IS_ERR(dev->slave))
328 			return dev_err_probe(dev->dev, PTR_ERR(dev->slave),
329 					     "register UCSI failed\n");
330 	}
331 
332 	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
333 	pm_runtime_use_autosuspend(&pdev->dev);
334 	pm_runtime_put_autosuspend(&pdev->dev);
335 	pm_runtime_allow(&pdev->dev);
336 
337 	return 0;
338 }
339 
i2c_dw_pci_remove(struct pci_dev * pdev)340 static void i2c_dw_pci_remove(struct pci_dev *pdev)
341 {
342 	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
343 
344 	dev->disable(dev);
345 	pm_runtime_forbid(&pdev->dev);
346 	pm_runtime_get_noresume(&pdev->dev);
347 
348 	i2c_del_adapter(&dev->adapter);
349 	devm_free_irq(&pdev->dev, dev->irq, dev);
350 	pci_free_irq_vectors(pdev);
351 }
352 
353 static const struct pci_device_id i2_designware_pci_ids[] = {
354 	/* Medfield */
355 	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
356 	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
357 	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
358 	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
359 	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
360 	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
361 	/* Merrifield */
362 	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
363 	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
364 	/* Baytrail */
365 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
366 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
367 	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
368 	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
369 	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
370 	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
371 	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
372 	/* Haswell */
373 	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
374 	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
375 	/* Braswell / Cherrytrail */
376 	{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
377 	{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
378 	{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
379 	{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
380 	{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
381 	{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
382 	{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
383 	/* Elkhart Lake (PSE I2C) */
384 	{ PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
385 	{ PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
386 	{ PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
387 	{ PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
388 	{ PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
389 	{ PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
390 	{ PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
391 	{ PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
392 	{ PCI_VDEVICE(ATI,  0x7314), navi_amd },
393 	{ PCI_VDEVICE(ATI,  0x73a4), navi_amd },
394 	{ PCI_VDEVICE(ATI,  0x73e4), navi_amd },
395 	{ PCI_VDEVICE(ATI,  0x73c4), navi_amd },
396 	{ 0,}
397 };
398 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
399 
400 static struct pci_driver dw_i2c_driver = {
401 	.name		= DRIVER_NAME,
402 	.id_table	= i2_designware_pci_ids,
403 	.probe		= i2c_dw_pci_probe,
404 	.remove		= i2c_dw_pci_remove,
405 	.driver         = {
406 		.pm     = &i2c_dw_pm_ops,
407 	},
408 };
409 module_pci_driver(dw_i2c_driver);
410 
411 /* Work with hotplug and coldplug */
412 MODULE_ALIAS("i2c_designware-pci");
413 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
414 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
415 MODULE_LICENSE("GPL");
416