1 /*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
21
22 /* definitions used for the EHCI driver */
23
24 /*
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
28 *
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
31 */
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
35 #else
36 #define __hc32 __le32
37 #define __hc16 __le16
38 #endif
39
40 /* statistics can be kept for tuning/monitoring */
41 struct ehci_stats {
42 /* irq usage */
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
47
48 /* termination of urbs from core */
49 unsigned long complete;
50 unsigned long unlink;
51 };
52
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
57 * ehci_qtd: qtd_list
58 *
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
61 */
62
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
64
65 struct ehci_hcd { /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
70
71 __u32 hcs_params; /* cached register copy */
72 spinlock_t lock;
73
74 /* async schedule support */
75 struct ehci_qh *async;
76 struct ehci_qh *dummy; /* For AMD quirk use */
77 struct ehci_qh *reclaim;
78 unsigned scanning : 1;
79
80 /* periodic schedule support */
81 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
82 unsigned periodic_size;
83 __hc32 *periodic; /* hw periodic table */
84 dma_addr_t periodic_dma;
85 unsigned i_thresh; /* uframes HC might cache */
86
87 union ehci_shadow *pshadow; /* mirror hw periodic table */
88 int next_uframe; /* scan periodic, start here */
89 unsigned periodic_sched; /* periodic activity count */
90
91 /* list of itds & sitds completed while clock_frame was still active */
92 struct list_head cached_itd_list;
93 struct list_head cached_sitd_list;
94 unsigned clock_frame;
95
96 /* per root hub port */
97 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
98
99 /* bit vectors (one bit per port) */
100 unsigned long bus_suspended; /* which ports were
101 already suspended at the start of a bus suspend */
102 unsigned long companion_ports; /* which ports are
103 dedicated to the companion controller */
104 unsigned long owned_ports; /* which ports are
105 owned by the companion during a bus suspend */
106 unsigned long port_c_suspend; /* which ports have
107 the change-suspend feature turned on */
108 unsigned long suspended_ports; /* which ports are
109 suspended */
110
111 /* per-HC memory pools (could be per-bus, but ...) */
112 struct dma_pool *qh_pool; /* qh per active urb */
113 struct dma_pool *qtd_pool; /* one or more per qh */
114 struct dma_pool *itd_pool; /* itd per iso urb */
115 struct dma_pool *sitd_pool; /* sitd per split iso urb */
116
117 struct timer_list iaa_watchdog;
118 struct timer_list watchdog;
119 unsigned long actions;
120 unsigned stamp;
121 unsigned random_frame;
122 unsigned long next_statechange;
123 ktime_t last_periodic_enable;
124 u32 command;
125
126 /* SILICON QUIRKS */
127 unsigned no_selective_suspend:1;
128 unsigned has_fsl_port_bug:1; /* FreeScale */
129 unsigned big_endian_mmio:1;
130 unsigned big_endian_desc:1;
131 unsigned has_amcc_usb23:1;
132 unsigned need_io_watchdog:1;
133 unsigned broken_periodic:1;
134 unsigned amd_pll_fix:1;
135 unsigned fs_i_thresh:1; /* Intel iso scheduling */
136 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
137
138 /* required for usb32 quirk */
139 #define OHCI_CTRL_HCFS (3 << 6)
140 #define OHCI_USB_OPER (2 << 6)
141 #define OHCI_USB_SUSPEND (3 << 6)
142
143 #define OHCI_HCCTRL_OFFSET 0x4
144 #define OHCI_HCCTRL_LEN 0x4
145 __hc32 *ohci_hcctrl_reg;
146 unsigned has_hostpc:1;
147 unsigned has_lpm:1; /* support link power management */
148 unsigned has_ppcd:1; /* support per-port change bits */
149 u8 sbrn; /* packed release number */
150
151 /* irq statistics */
152 #ifdef EHCI_STATS
153 struct ehci_stats stats;
154 # define COUNT(x) do { (x)++; } while (0)
155 #else
156 # define COUNT(x) do {} while (0)
157 #endif
158
159 /* debug files */
160 #ifdef DEBUG
161 struct dentry *debug_dir;
162 #endif
163 };
164
165 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_ehci(struct usb_hcd * hcd)166 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
167 {
168 return (struct ehci_hcd *) (hcd->hcd_priv);
169 }
ehci_to_hcd(struct ehci_hcd * ehci)170 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
171 {
172 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
173 }
174
175
176 static inline void
iaa_watchdog_start(struct ehci_hcd * ehci)177 iaa_watchdog_start(struct ehci_hcd *ehci)
178 {
179 WARN_ON(timer_pending(&ehci->iaa_watchdog));
180 mod_timer(&ehci->iaa_watchdog,
181 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
182 }
183
iaa_watchdog_done(struct ehci_hcd * ehci)184 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
185 {
186 del_timer(&ehci->iaa_watchdog);
187 }
188
189 enum ehci_timer_action {
190 TIMER_IO_WATCHDOG,
191 TIMER_ASYNC_SHRINK,
192 TIMER_ASYNC_OFF,
193 };
194
195 static inline void
timer_action_done(struct ehci_hcd * ehci,enum ehci_timer_action action)196 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
197 {
198 clear_bit (action, &ehci->actions);
199 }
200
201 static void free_cached_lists(struct ehci_hcd *ehci);
202
203 /*-------------------------------------------------------------------------*/
204
205 #include <linux/usb/ehci_def.h>
206
207 /*-------------------------------------------------------------------------*/
208
209 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
210
211 /*
212 * EHCI Specification 0.95 Section 3.5
213 * QTD: describe data transfer components (buffer, direction, ...)
214 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
215 *
216 * These are associated only with "QH" (Queue Head) structures,
217 * used with control, bulk, and interrupt transfers.
218 */
219 struct ehci_qtd {
220 /* first part defined by EHCI spec */
221 __hc32 hw_next; /* see EHCI 3.5.1 */
222 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
223 __hc32 hw_token; /* see EHCI 3.5.3 */
224 #define QTD_TOGGLE (1 << 31) /* data toggle */
225 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
226 #define QTD_IOC (1 << 15) /* interrupt on complete */
227 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
228 #define QTD_PID(tok) (((tok)>>8) & 0x3)
229 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
230 #define QTD_STS_HALT (1 << 6) /* halted on error */
231 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
232 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
233 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
234 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
235 #define QTD_STS_STS (1 << 1) /* split transaction state */
236 #define QTD_STS_PING (1 << 0) /* issue PING? */
237
238 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
239 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
240 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
241
242 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
243 __hc32 hw_buf_hi [5]; /* Appendix B */
244
245 /* the rest is HCD-private */
246 dma_addr_t qtd_dma; /* qtd address */
247 struct list_head qtd_list; /* sw qtd list */
248 struct urb *urb; /* qtd's urb */
249 size_t length; /* length of buffer */
250 } __attribute__ ((aligned (32)));
251
252 /* mask NakCnt+T in qh->hw_alt_next */
253 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
254
255 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
256
257 /*-------------------------------------------------------------------------*/
258
259 /* type tag from {qh,itd,sitd,fstn}->hw_next */
260 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
261
262 /*
263 * Now the following defines are not converted using the
264 * cpu_to_le32() macro anymore, since we have to support
265 * "dynamic" switching between be and le support, so that the driver
266 * can be used on one system with SoC EHCI controller using big-endian
267 * descriptors as well as a normal little-endian PCI EHCI controller.
268 */
269 /* values for that type tag */
270 #define Q_TYPE_ITD (0 << 1)
271 #define Q_TYPE_QH (1 << 1)
272 #define Q_TYPE_SITD (2 << 1)
273 #define Q_TYPE_FSTN (3 << 1)
274
275 /* next async queue entry, or pointer to interrupt/periodic QH */
276 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
277
278 /* for periodic/async schedules and qtd lists, mark end of list */
279 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
280
281 /*
282 * Entries in periodic shadow table are pointers to one of four kinds
283 * of data structure. That's dictated by the hardware; a type tag is
284 * encoded in the low bits of the hardware's periodic schedule. Use
285 * Q_NEXT_TYPE to get the tag.
286 *
287 * For entries in the async schedule, the type tag always says "qh".
288 */
289 union ehci_shadow {
290 struct ehci_qh *qh; /* Q_TYPE_QH */
291 struct ehci_itd *itd; /* Q_TYPE_ITD */
292 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
293 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
294 __hc32 *hw_next; /* (all types) */
295 void *ptr;
296 };
297
298 /*-------------------------------------------------------------------------*/
299
300 /*
301 * EHCI Specification 0.95 Section 3.6
302 * QH: describes control/bulk/interrupt endpoints
303 * See Fig 3-7 "Queue Head Structure Layout".
304 *
305 * These appear in both the async and (for interrupt) periodic schedules.
306 */
307
308 /* first part defined by EHCI spec */
309 struct ehci_qh_hw {
310 __hc32 hw_next; /* see EHCI 3.6.1 */
311 __hc32 hw_info1; /* see EHCI 3.6.2 */
312 #define QH_HEAD 0x00008000
313 __hc32 hw_info2; /* see EHCI 3.6.2 */
314 #define QH_SMASK 0x000000ff
315 #define QH_CMASK 0x0000ff00
316 #define QH_HUBADDR 0x007f0000
317 #define QH_HUBPORT 0x3f800000
318 #define QH_MULT 0xc0000000
319 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
320
321 /* qtd overlay (hardware parts of a struct ehci_qtd) */
322 __hc32 hw_qtd_next;
323 __hc32 hw_alt_next;
324 __hc32 hw_token;
325 __hc32 hw_buf [5];
326 __hc32 hw_buf_hi [5];
327 } __attribute__ ((aligned(32)));
328
329 struct ehci_qh {
330 struct ehci_qh_hw *hw;
331 /* the rest is HCD-private */
332 dma_addr_t qh_dma; /* address of qh */
333 union ehci_shadow qh_next; /* ptr to qh; or periodic */
334 struct list_head qtd_list; /* sw qtd list */
335 struct ehci_qtd *dummy;
336 struct ehci_qh *reclaim; /* next to reclaim */
337
338 struct ehci_hcd *ehci;
339
340 /*
341 * Do NOT use atomic operations for QH refcounting. On some CPUs
342 * (PPC7448 for example), atomic operations cannot be performed on
343 * memory that is cache-inhibited (i.e. being used for DMA).
344 * Spinlocks are used to protect all QH fields.
345 */
346 u32 refcount;
347 unsigned stamp;
348
349 u8 needs_rescan; /* Dequeue during giveback */
350 u8 qh_state;
351 #define QH_STATE_LINKED 1 /* HC sees this */
352 #define QH_STATE_UNLINK 2 /* HC may still see this */
353 #define QH_STATE_IDLE 3 /* HC doesn't see this */
354 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
355 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
356
357 u8 xacterrs; /* XactErr retry counter */
358 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
359
360 /* periodic schedule info */
361 u8 usecs; /* intr bandwidth */
362 u8 gap_uf; /* uframes split/csplit gap */
363 u8 c_usecs; /* ... split completion bw */
364 u16 tt_usecs; /* tt downstream bandwidth */
365 unsigned short period; /* polling interval */
366 unsigned short start; /* where polling starts */
367 #define NO_FRAME ((unsigned short)~0) /* pick new start */
368
369 struct usb_device *dev; /* access to TT */
370 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
371 };
372
373 /*-------------------------------------------------------------------------*/
374
375 /* description of one iso transaction (up to 3 KB data if highspeed) */
376 struct ehci_iso_packet {
377 /* These will be copied to iTD when scheduling */
378 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
379 __hc32 transaction; /* itd->hw_transaction[i] |= */
380 u8 cross; /* buf crosses pages */
381 /* for full speed OUT splits */
382 u32 buf1;
383 };
384
385 /* temporary schedule data for packets from iso urbs (both speeds)
386 * each packet is one logical usb transaction to the device (not TT),
387 * beginning at stream->next_uframe
388 */
389 struct ehci_iso_sched {
390 struct list_head td_list;
391 unsigned span;
392 struct ehci_iso_packet packet [0];
393 };
394
395 /*
396 * ehci_iso_stream - groups all (s)itds for this endpoint.
397 * acts like a qh would, if EHCI had them for ISO.
398 */
399 struct ehci_iso_stream {
400 /* first field matches ehci_hq, but is NULL */
401 struct ehci_qh_hw *hw;
402
403 u32 refcount;
404 u8 bEndpointAddress;
405 u8 highspeed;
406 struct list_head td_list; /* queued itds/sitds */
407 struct list_head free_list; /* list of unused itds/sitds */
408 struct usb_device *udev;
409 struct usb_host_endpoint *ep;
410
411 /* output of (re)scheduling */
412 int next_uframe;
413 __hc32 splits;
414
415 /* the rest is derived from the endpoint descriptor,
416 * trusting urb->interval == f(epdesc->bInterval) and
417 * including the extra info for hw_bufp[0..2]
418 */
419 u8 usecs, c_usecs;
420 u16 interval;
421 u16 tt_usecs;
422 u16 maxp;
423 u16 raw_mask;
424 unsigned bandwidth;
425
426 /* This is used to initialize iTD's hw_bufp fields */
427 __hc32 buf0;
428 __hc32 buf1;
429 __hc32 buf2;
430
431 /* this is used to initialize sITD's tt info */
432 __hc32 address;
433 };
434
435 /*-------------------------------------------------------------------------*/
436
437 /*
438 * EHCI Specification 0.95 Section 3.3
439 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
440 *
441 * Schedule records for high speed iso xfers
442 */
443 struct ehci_itd {
444 /* first part defined by EHCI spec */
445 __hc32 hw_next; /* see EHCI 3.3.1 */
446 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
447 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
448 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
449 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
450 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
451 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
452 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
453
454 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
455
456 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
457 __hc32 hw_bufp_hi [7]; /* Appendix B */
458
459 /* the rest is HCD-private */
460 dma_addr_t itd_dma; /* for this itd */
461 union ehci_shadow itd_next; /* ptr to periodic q entry */
462
463 struct urb *urb;
464 struct ehci_iso_stream *stream; /* endpoint's queue */
465 struct list_head itd_list; /* list of stream's itds */
466
467 /* any/all hw_transactions here may be used by that urb */
468 unsigned frame; /* where scheduled */
469 unsigned pg;
470 unsigned index[8]; /* in urb->iso_frame_desc */
471 } __attribute__ ((aligned (32)));
472
473 /*-------------------------------------------------------------------------*/
474
475 /*
476 * EHCI Specification 0.95 Section 3.4
477 * siTD, aka split-transaction isochronous Transfer Descriptor
478 * ... describe full speed iso xfers through TT in hubs
479 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
480 */
481 struct ehci_sitd {
482 /* first part defined by EHCI spec */
483 __hc32 hw_next;
484 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
485 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
486 __hc32 hw_uframe; /* EHCI table 3-10 */
487 __hc32 hw_results; /* EHCI table 3-11 */
488 #define SITD_IOC (1 << 31) /* interrupt on completion */
489 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
490 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
491 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
492 #define SITD_STS_ERR (1 << 6) /* error from TT */
493 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
494 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
495 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
496 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
497 #define SITD_STS_STS (1 << 1) /* split transaction state */
498
499 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
500
501 __hc32 hw_buf [2]; /* EHCI table 3-12 */
502 __hc32 hw_backpointer; /* EHCI table 3-13 */
503 __hc32 hw_buf_hi [2]; /* Appendix B */
504
505 /* the rest is HCD-private */
506 dma_addr_t sitd_dma;
507 union ehci_shadow sitd_next; /* ptr to periodic q entry */
508
509 struct urb *urb;
510 struct ehci_iso_stream *stream; /* endpoint's queue */
511 struct list_head sitd_list; /* list of stream's sitds */
512 unsigned frame;
513 unsigned index;
514 } __attribute__ ((aligned (32)));
515
516 /*-------------------------------------------------------------------------*/
517
518 /*
519 * EHCI Specification 0.96 Section 3.7
520 * Periodic Frame Span Traversal Node (FSTN)
521 *
522 * Manages split interrupt transactions (using TT) that span frame boundaries
523 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
524 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
525 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
526 */
527 struct ehci_fstn {
528 __hc32 hw_next; /* any periodic q entry */
529 __hc32 hw_prev; /* qh or EHCI_LIST_END */
530
531 /* the rest is HCD-private */
532 dma_addr_t fstn_dma;
533 union ehci_shadow fstn_next; /* ptr to periodic q entry */
534 } __attribute__ ((aligned (32)));
535
536 /*-------------------------------------------------------------------------*/
537
538 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
539
540 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
541 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
542
543 #define ehci_prepare_ports_for_controller_resume(ehci) \
544 ehci_adjust_port_wakeup_flags(ehci, false, false);
545
546 /*-------------------------------------------------------------------------*/
547
548 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
549
550 /*
551 * Some EHCI controllers have a Transaction Translator built into the
552 * root hub. This is a non-standard feature. Each controller will need
553 * to add code to the following inline functions, and call them as
554 * needed (mostly in root hub code).
555 */
556
557 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
558
559 /* Returns the speed of a device attached to a port on the root hub. */
560 static inline unsigned int
ehci_port_speed(struct ehci_hcd * ehci,unsigned int portsc)561 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
562 {
563 if (ehci_is_TDI(ehci)) {
564 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
565 case 0:
566 return 0;
567 case 1:
568 return USB_PORT_STAT_LOW_SPEED;
569 case 2:
570 default:
571 return USB_PORT_STAT_HIGH_SPEED;
572 }
573 }
574 return USB_PORT_STAT_HIGH_SPEED;
575 }
576
577 #else
578
579 #define ehci_is_TDI(e) (0)
580
581 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
582 #endif
583
584 /*-------------------------------------------------------------------------*/
585
586 #ifdef CONFIG_PPC_83xx
587 /* Some Freescale processors have an erratum in which the TT
588 * port number in the queue head was 0..N-1 instead of 1..N.
589 */
590 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
591 #else
592 #define ehci_has_fsl_portno_bug(e) (0)
593 #endif
594
595 /*
596 * While most USB host controllers implement their registers in
597 * little-endian format, a minority (celleb companion chip) implement
598 * them in big endian format.
599 *
600 * This attempts to support either format at compile time without a
601 * runtime penalty, or both formats with the additional overhead
602 * of checking a flag bit.
603 */
604
605 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
606 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
607 #else
608 #define ehci_big_endian_mmio(e) 0
609 #endif
610
611 /*
612 * Big-endian read/write functions are arch-specific.
613 * Other arches can be added if/when they're needed.
614 */
615 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
616 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
617 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
618 #endif
619
ehci_readl(const struct ehci_hcd * ehci,__u32 __iomem * regs)620 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
621 __u32 __iomem * regs)
622 {
623 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
624 return ehci_big_endian_mmio(ehci) ?
625 readl_be(regs) :
626 readl(regs);
627 #else
628 return readl(regs);
629 #endif
630 }
631
ehci_writel(const struct ehci_hcd * ehci,const unsigned int val,__u32 __iomem * regs)632 static inline void ehci_writel(const struct ehci_hcd *ehci,
633 const unsigned int val, __u32 __iomem *regs)
634 {
635 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
636 ehci_big_endian_mmio(ehci) ?
637 writel_be(val, regs) :
638 writel(val, regs);
639 #else
640 writel(val, regs);
641 #endif
642 }
643
644 /*
645 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
646 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
647 * Other common bits are dependent on has_amcc_usb23 quirk flag.
648 */
649 #ifdef CONFIG_44x
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)650 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
651 {
652 u32 hc_control;
653
654 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
655 if (operational)
656 hc_control |= OHCI_USB_OPER;
657 else
658 hc_control |= OHCI_USB_SUSPEND;
659
660 writel_be(hc_control, ehci->ohci_hcctrl_reg);
661 (void) readl_be(ehci->ohci_hcctrl_reg);
662 }
663 #else
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)664 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
665 { }
666 #endif
667
668 /*-------------------------------------------------------------------------*/
669
670 /*
671 * The AMCC 440EPx not only implements its EHCI registers in big-endian
672 * format, but also its DMA data structures (descriptors).
673 *
674 * EHCI controllers accessed through PCI work normally (little-endian
675 * everywhere), so we won't bother supporting a BE-only mode for now.
676 */
677 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
678 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
679
680 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)681 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
682 {
683 return ehci_big_endian_desc(ehci)
684 ? (__force __hc32)cpu_to_be32(x)
685 : (__force __hc32)cpu_to_le32(x);
686 }
687
688 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)689 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
690 {
691 return ehci_big_endian_desc(ehci)
692 ? be32_to_cpu((__force __be32)x)
693 : le32_to_cpu((__force __le32)x);
694 }
695
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)696 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
697 {
698 return ehci_big_endian_desc(ehci)
699 ? be32_to_cpup((__force __be32 *)x)
700 : le32_to_cpup((__force __le32 *)x);
701 }
702
703 #else
704
705 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)706 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
707 {
708 return cpu_to_le32(x);
709 }
710
711 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)712 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
713 {
714 return le32_to_cpu(x);
715 }
716
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)717 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
718 {
719 return le32_to_cpup(x);
720 }
721
722 #endif
723
724 /*-------------------------------------------------------------------------*/
725
726 #ifndef DEBUG
727 #define STUB_DEBUG_FILES
728 #endif /* DEBUG */
729
730 /*-------------------------------------------------------------------------*/
731
732 #endif /* __LINUX_EHCI_HCD_H */
733