1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2015 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7
8 #include "intel_engine.h"
9 #include "intel_gt.h"
10 #include "intel_gt_regs.h"
11 #include "intel_mocs.h"
12 #include "intel_ring.h"
13
14 /* structures required */
15 struct drm_i915_mocs_entry {
16 u32 control_value;
17 u16 l3cc_value;
18 u16 used;
19 };
20
21 struct drm_i915_mocs_table {
22 unsigned int size;
23 unsigned int n_entries;
24 const struct drm_i915_mocs_entry *table;
25 u8 uc_index;
26 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
27 u8 unused_entries_index;
28 };
29
30 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
31 #define _LE_CACHEABILITY(value) ((value) << 0)
32 #define _LE_TGT_CACHE(value) ((value) << 2)
33 #define LE_LRUM(value) ((value) << 4)
34 #define LE_AOM(value) ((value) << 6)
35 #define LE_RSC(value) ((value) << 7)
36 #define LE_SCC(value) ((value) << 8)
37 #define LE_PFM(value) ((value) << 11)
38 #define LE_SCF(value) ((value) << 14)
39 #define LE_COS(value) ((value) << 15)
40 #define LE_SSE(value) ((value) << 17)
41
42 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
43 #define L3_ESC(value) ((value) << 0)
44 #define L3_SCC(value) ((value) << 1)
45 #define _L3_CACHEABILITY(value) ((value) << 4)
46 #define L3_GLBGO(value) ((value) << 6)
47 #define L3_LKUP(value) ((value) << 7)
48
49 /* Helper defines */
50 #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
51 #define PVC_NUM_MOCS_ENTRIES 3
52
53 /* (e)LLC caching options */
54 /*
55 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
56 * the same as LE_UC
57 */
58 #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
59 #define LE_1_UC _LE_CACHEABILITY(1)
60 #define LE_2_WT _LE_CACHEABILITY(2)
61 #define LE_3_WB _LE_CACHEABILITY(3)
62
63 /* Target cache */
64 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
65 #define LE_TC_1_LLC _LE_TGT_CACHE(1)
66 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
67 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
68
69 /* L3 caching options */
70 #define L3_0_DIRECT _L3_CACHEABILITY(0)
71 #define L3_1_UC _L3_CACHEABILITY(1)
72 #define L3_2_RESERVED _L3_CACHEABILITY(2)
73 #define L3_3_WB _L3_CACHEABILITY(3)
74
75 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
76 [__idx] = { \
77 .control_value = __control_value, \
78 .l3cc_value = __l3cc_value, \
79 .used = 1, \
80 }
81
82 /*
83 * MOCS tables
84 *
85 * These are the MOCS tables that are programmed across all the rings.
86 * The control value is programmed to all the rings that support the
87 * MOCS registers. While the l3cc_values are only programmed to the
88 * LNCFCMOCS0 - LNCFCMOCS32 registers.
89 *
90 * These tables are intended to be kept reasonably consistent across
91 * HW platforms, and for ICL+, be identical across OSes. To achieve
92 * that, for Icelake and above, list of entries is published as part
93 * of bspec.
94 *
95 * Entries not part of the following tables are undefined as far as
96 * userspace is concerned and shouldn't be relied upon. For Gen < 12
97 * they will be initialized to PTE. Gen >= 12 don't have a setting for
98 * PTE and those platforms except TGL/RKL will be initialized L3 WB to
99 * catch accidental use of reserved and unused mocs indexes.
100 *
101 * The last few entries are reserved by the hardware. For ICL+ they
102 * should be initialized according to bspec and never used, for older
103 * platforms they should never be written to.
104 *
105 * NOTE1: These tables are part of bspec and defined as part of hardware
106 * interface for ICL+. For older platforms, they are part of kernel
107 * ABI. It is expected that, for specific hardware platform, existing
108 * entries will remain constant and the table will only be updated by
109 * adding new entries, filling unused positions.
110 *
111 * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
112 * indices have been set to L3 WB. These reserved entries should never
113 * be used, they may be changed to low performant variants with better
114 * coherency in the future if more entries are needed.
115 * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
116 */
117 #define GEN9_MOCS_ENTRIES \
118 MOCS_ENTRY(I915_MOCS_UNCACHED, \
119 LE_1_UC | LE_TC_2_LLC_ELLC, \
120 L3_1_UC), \
121 MOCS_ENTRY(I915_MOCS_PTE, \
122 LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
123 L3_3_WB)
124
125 static const struct drm_i915_mocs_entry skl_mocs_table[] = {
126 GEN9_MOCS_ENTRIES,
127 MOCS_ENTRY(I915_MOCS_CACHED,
128 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
129 L3_3_WB),
130
131 /*
132 * mocs:63
133 * - used by the L3 for all of its evictions.
134 * Thus it is expected to allow LLC cacheability to enable coherent
135 * flows to be maintained.
136 * - used to force L3 uncachable cycles.
137 * Thus it is expected to make the surface L3 uncacheable.
138 */
139 MOCS_ENTRY(63,
140 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
141 L3_1_UC)
142 };
143
144 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
145 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
146 GEN9_MOCS_ENTRIES,
147 MOCS_ENTRY(I915_MOCS_CACHED,
148 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
149 L3_3_WB)
150 };
151
152 #define GEN11_MOCS_ENTRIES \
153 /* Entries 0 and 1 are defined per-platform */ \
154 /* Base - L3 + LLC */ \
155 MOCS_ENTRY(2, \
156 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
157 L3_3_WB), \
158 /* Base - Uncached */ \
159 MOCS_ENTRY(3, \
160 LE_1_UC | LE_TC_1_LLC, \
161 L3_1_UC), \
162 /* Base - L3 */ \
163 MOCS_ENTRY(4, \
164 LE_1_UC | LE_TC_1_LLC, \
165 L3_3_WB), \
166 /* Base - LLC */ \
167 MOCS_ENTRY(5, \
168 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
169 L3_1_UC), \
170 /* Age 0 - LLC */ \
171 MOCS_ENTRY(6, \
172 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
173 L3_1_UC), \
174 /* Age 0 - L3 + LLC */ \
175 MOCS_ENTRY(7, \
176 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
177 L3_3_WB), \
178 /* Age: Don't Chg. - LLC */ \
179 MOCS_ENTRY(8, \
180 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
181 L3_1_UC), \
182 /* Age: Don't Chg. - L3 + LLC */ \
183 MOCS_ENTRY(9, \
184 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
185 L3_3_WB), \
186 /* No AOM - LLC */ \
187 MOCS_ENTRY(10, \
188 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
189 L3_1_UC), \
190 /* No AOM - L3 + LLC */ \
191 MOCS_ENTRY(11, \
192 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
193 L3_3_WB), \
194 /* No AOM; Age 0 - LLC */ \
195 MOCS_ENTRY(12, \
196 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
197 L3_1_UC), \
198 /* No AOM; Age 0 - L3 + LLC */ \
199 MOCS_ENTRY(13, \
200 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
201 L3_3_WB), \
202 /* No AOM; Age:DC - LLC */ \
203 MOCS_ENTRY(14, \
204 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
205 L3_1_UC), \
206 /* No AOM; Age:DC - L3 + LLC */ \
207 MOCS_ENTRY(15, \
208 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
209 L3_3_WB), \
210 /* Bypass LLC - Uncached (EHL+) */ \
211 MOCS_ENTRY(16, \
212 LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
213 L3_1_UC), \
214 /* Bypass LLC - L3 (Read-Only) (EHL+) */ \
215 MOCS_ENTRY(17, \
216 LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
217 L3_3_WB), \
218 /* Self-Snoop - L3 + LLC */ \
219 MOCS_ENTRY(18, \
220 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
221 L3_3_WB), \
222 /* Skip Caching - L3 + LLC(12.5%) */ \
223 MOCS_ENTRY(19, \
224 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
225 L3_3_WB), \
226 /* Skip Caching - L3 + LLC(25%) */ \
227 MOCS_ENTRY(20, \
228 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
229 L3_3_WB), \
230 /* Skip Caching - L3 + LLC(50%) */ \
231 MOCS_ENTRY(21, \
232 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
233 L3_3_WB), \
234 /* Skip Caching - L3 + LLC(75%) */ \
235 MOCS_ENTRY(22, \
236 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
237 L3_3_WB), \
238 /* Skip Caching - L3 + LLC(87.5%) */ \
239 MOCS_ENTRY(23, \
240 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
241 L3_3_WB), \
242 /* HW Reserved - SW program but never use */ \
243 MOCS_ENTRY(62, \
244 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
245 L3_1_UC), \
246 /* HW Reserved - SW program but never use */ \
247 MOCS_ENTRY(63, \
248 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
249 L3_1_UC)
250
251 static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
252 /*
253 * NOTE:
254 * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
255 * These reserved entries should never be used, they may be changed
256 * to low performant variants with better coherency in the future if
257 * more entries are needed. We are programming index I915_MOCS_PTE(1)
258 * only, __init_mocs_table() take care to program unused index with
259 * this entry.
260 */
261 MOCS_ENTRY(I915_MOCS_PTE,
262 LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
263 L3_1_UC),
264 GEN11_MOCS_ENTRIES,
265
266 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
267 MOCS_ENTRY(48,
268 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
269 L3_3_WB),
270 /* Implicitly enable L1 - HDC:L1 + L3 */
271 MOCS_ENTRY(49,
272 LE_1_UC | LE_TC_1_LLC,
273 L3_3_WB),
274 /* Implicitly enable L1 - HDC:L1 + LLC */
275 MOCS_ENTRY(50,
276 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
277 L3_1_UC),
278 /* Implicitly enable L1 - HDC:L1 */
279 MOCS_ENTRY(51,
280 LE_1_UC | LE_TC_1_LLC,
281 L3_1_UC),
282 /* HW Special Case (CCS) */
283 MOCS_ENTRY(60,
284 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
285 L3_1_UC),
286 /* HW Special Case (Displayable) */
287 MOCS_ENTRY(61,
288 LE_1_UC | LE_TC_1_LLC,
289 L3_3_WB),
290 };
291
292 static const struct drm_i915_mocs_entry icl_mocs_table[] = {
293 /* Base - Uncached (Deprecated) */
294 MOCS_ENTRY(I915_MOCS_UNCACHED,
295 LE_1_UC | LE_TC_1_LLC,
296 L3_1_UC),
297 /* Base - L3 + LeCC:PAT (Deprecated) */
298 MOCS_ENTRY(I915_MOCS_PTE,
299 LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
300 L3_3_WB),
301
302 GEN11_MOCS_ENTRIES
303 };
304
305 static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
306
307 /* UC */
308 MOCS_ENTRY(1, 0, L3_1_UC),
309 /* WB - L3 */
310 MOCS_ENTRY(5, 0, L3_3_WB),
311 /* WB - L3 50% */
312 MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
313 /* WB - L3 25% */
314 MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
315 /* WB - L3 12.5% */
316 MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
317
318 /* HDC:L1 + L3 */
319 MOCS_ENTRY(48, 0, L3_3_WB),
320 /* HDC:L1 */
321 MOCS_ENTRY(49, 0, L3_1_UC),
322
323 /* HW Reserved */
324 MOCS_ENTRY(60, 0, L3_1_UC),
325 MOCS_ENTRY(61, 0, L3_1_UC),
326 MOCS_ENTRY(62, 0, L3_1_UC),
327 MOCS_ENTRY(63, 0, L3_1_UC),
328 };
329
330 static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
331 GEN11_MOCS_ENTRIES,
332 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
333 MOCS_ENTRY(48,
334 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
335 L3_3_WB),
336 /* Implicitly enable L1 - HDC:L1 + L3 */
337 MOCS_ENTRY(49,
338 LE_1_UC | LE_TC_1_LLC,
339 L3_3_WB),
340 /* Implicitly enable L1 - HDC:L1 + LLC */
341 MOCS_ENTRY(50,
342 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
343 L3_1_UC),
344 /* Implicitly enable L1 - HDC:L1 */
345 MOCS_ENTRY(51,
346 LE_1_UC | LE_TC_1_LLC,
347 L3_1_UC),
348 /* HW Special Case (CCS) */
349 MOCS_ENTRY(60,
350 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
351 L3_1_UC),
352 /* HW Special Case (Displayable) */
353 MOCS_ENTRY(61,
354 LE_1_UC | LE_TC_1_LLC,
355 L3_3_WB),
356 };
357
358 static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
359 /* wa_1608975824 */
360 MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
361
362 /* UC - Coherent; GO:L3 */
363 MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
364 /* UC - Coherent; GO:Memory */
365 MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
366 /* UC - Non-Coherent; GO:Memory */
367 MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
368 /* UC - Non-Coherent; GO:L3 */
369 MOCS_ENTRY(4, 0, L3_1_UC),
370
371 /* WB */
372 MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
373
374 /* HW Reserved - SW program but never use. */
375 MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
376 MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
377 MOCS_ENTRY(60, 0, L3_1_UC),
378 MOCS_ENTRY(61, 0, L3_1_UC),
379 MOCS_ENTRY(62, 0, L3_1_UC),
380 MOCS_ENTRY(63, 0, L3_1_UC),
381 };
382
383 static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
384 /* UC - Coherent; GO:L3 */
385 MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
386 /* UC - Coherent; GO:Memory */
387 MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
388 /* UC - Non-Coherent; GO:Memory */
389 MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
390
391 /* WB - LC */
392 MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
393 };
394
395 static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
396 /* Wa_14011441408: Set Go to Memory for MOCS#0 */
397 MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
398 /* UC - Coherent; GO:Memory */
399 MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
400 /* UC - Non-Coherent; GO:Memory */
401 MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
402
403 /* WB - LC */
404 MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
405 };
406
407 static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
408 /* Error */
409 MOCS_ENTRY(0, 0, L3_3_WB),
410
411 /* UC */
412 MOCS_ENTRY(1, 0, L3_1_UC),
413
414 /* WB */
415 MOCS_ENTRY(2, 0, L3_3_WB),
416 };
417
418 enum {
419 HAS_GLOBAL_MOCS = BIT(0),
420 HAS_ENGINE_MOCS = BIT(1),
421 HAS_RENDER_L3CC = BIT(2),
422 };
423
has_l3cc(const struct drm_i915_private * i915)424 static bool has_l3cc(const struct drm_i915_private *i915)
425 {
426 return true;
427 }
428
has_global_mocs(const struct drm_i915_private * i915)429 static bool has_global_mocs(const struct drm_i915_private *i915)
430 {
431 return HAS_GLOBAL_MOCS_REGISTERS(i915);
432 }
433
has_mocs(const struct drm_i915_private * i915)434 static bool has_mocs(const struct drm_i915_private *i915)
435 {
436 return !IS_DGFX(i915);
437 }
438
get_mocs_settings(const struct drm_i915_private * i915,struct drm_i915_mocs_table * table)439 static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
440 struct drm_i915_mocs_table *table)
441 {
442 unsigned int flags;
443
444 memset(table, 0, sizeof(struct drm_i915_mocs_table));
445
446 table->unused_entries_index = I915_MOCS_PTE;
447 if (IS_PONTEVECCHIO(i915)) {
448 table->size = ARRAY_SIZE(pvc_mocs_table);
449 table->table = pvc_mocs_table;
450 table->n_entries = PVC_NUM_MOCS_ENTRIES;
451 table->uc_index = 1;
452 table->wb_index = 2;
453 table->unused_entries_index = 2;
454 } else if (IS_DG2(i915)) {
455 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
456 table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
457 table->table = dg2_mocs_table_g10_ax;
458 } else {
459 table->size = ARRAY_SIZE(dg2_mocs_table);
460 table->table = dg2_mocs_table;
461 }
462 table->uc_index = 1;
463 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
464 table->unused_entries_index = 3;
465 } else if (IS_XEHPSDV(i915)) {
466 table->size = ARRAY_SIZE(xehpsdv_mocs_table);
467 table->table = xehpsdv_mocs_table;
468 table->uc_index = 2;
469 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
470 table->unused_entries_index = 5;
471 } else if (IS_DG1(i915)) {
472 table->size = ARRAY_SIZE(dg1_mocs_table);
473 table->table = dg1_mocs_table;
474 table->uc_index = 1;
475 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
476 table->uc_index = 1;
477 table->unused_entries_index = 5;
478 } else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
479 /* For TGL/RKL, Can't be changed now for ABI reasons */
480 table->size = ARRAY_SIZE(tgl_mocs_table);
481 table->table = tgl_mocs_table;
482 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
483 table->uc_index = 3;
484 } else if (GRAPHICS_VER(i915) >= 12) {
485 table->size = ARRAY_SIZE(gen12_mocs_table);
486 table->table = gen12_mocs_table;
487 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
488 table->uc_index = 3;
489 table->unused_entries_index = 2;
490 } else if (GRAPHICS_VER(i915) == 11) {
491 table->size = ARRAY_SIZE(icl_mocs_table);
492 table->table = icl_mocs_table;
493 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
494 } else if (IS_GEN9_BC(i915)) {
495 table->size = ARRAY_SIZE(skl_mocs_table);
496 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
497 table->table = skl_mocs_table;
498 } else if (IS_GEN9_LP(i915)) {
499 table->size = ARRAY_SIZE(broxton_mocs_table);
500 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
501 table->table = broxton_mocs_table;
502 } else {
503 drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
504 "Platform that should have a MOCS table does not.\n");
505 return 0;
506 }
507
508 if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
509 return 0;
510
511 /* WaDisableSkipCaching:skl,bxt,kbl,glk */
512 if (GRAPHICS_VER(i915) == 9) {
513 int i;
514
515 for (i = 0; i < table->size; i++)
516 if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
517 (L3_ESC(1) | L3_SCC(0x7))))
518 return 0;
519 }
520
521 flags = 0;
522 if (has_mocs(i915)) {
523 if (has_global_mocs(i915))
524 flags |= HAS_GLOBAL_MOCS;
525 else
526 flags |= HAS_ENGINE_MOCS;
527 }
528 if (has_l3cc(i915))
529 flags |= HAS_RENDER_L3CC;
530
531 return flags;
532 }
533
534 /*
535 * Get control_value from MOCS entry taking into account when it's not used
536 * then if unused_entries_index is non-zero then its value will be returned
537 * otherwise I915_MOCS_PTE's value is returned in this case.
538 */
get_entry_control(const struct drm_i915_mocs_table * table,unsigned int index)539 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
540 unsigned int index)
541 {
542 if (index < table->size && table->table[index].used)
543 return table->table[index].control_value;
544 return table->table[table->unused_entries_index].control_value;
545 }
546
547 #define for_each_mocs(mocs, t, i) \
548 for (i = 0; \
549 i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
550 i++)
551
__init_mocs_table(struct intel_uncore * uncore,const struct drm_i915_mocs_table * table,u32 addr)552 static void __init_mocs_table(struct intel_uncore *uncore,
553 const struct drm_i915_mocs_table *table,
554 u32 addr)
555 {
556 unsigned int i;
557 u32 mocs;
558
559 drm_WARN_ONCE(&uncore->i915->drm, !table->unused_entries_index,
560 "Unused entries index should have been defined\n");
561 for_each_mocs(mocs, table, i)
562 intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
563 }
564
mocs_offset(const struct intel_engine_cs * engine)565 static u32 mocs_offset(const struct intel_engine_cs *engine)
566 {
567 static const u32 offset[] = {
568 [RCS0] = __GEN9_RCS0_MOCS0,
569 [VCS0] = __GEN9_VCS0_MOCS0,
570 [VCS1] = __GEN9_VCS1_MOCS0,
571 [VECS0] = __GEN9_VECS0_MOCS0,
572 [BCS0] = __GEN9_BCS0_MOCS0,
573 [VCS2] = __GEN11_VCS2_MOCS0,
574 };
575
576 GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
577 return offset[engine->id];
578 }
579
init_mocs_table(struct intel_engine_cs * engine,const struct drm_i915_mocs_table * table)580 static void init_mocs_table(struct intel_engine_cs *engine,
581 const struct drm_i915_mocs_table *table)
582 {
583 __init_mocs_table(engine->uncore, table, mocs_offset(engine));
584 }
585
586 /*
587 * Get l3cc_value from MOCS entry taking into account when it's not used
588 * then if unused_entries_index is not zero then its value will be returned
589 * otherwise I915_MOCS_PTE's value is returned in this case.
590 */
get_entry_l3cc(const struct drm_i915_mocs_table * table,unsigned int index)591 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
592 unsigned int index)
593 {
594 if (index < table->size && table->table[index].used)
595 return table->table[index].l3cc_value;
596 return table->table[table->unused_entries_index].l3cc_value;
597 }
598
l3cc_combine(u16 low,u16 high)599 static u32 l3cc_combine(u16 low, u16 high)
600 {
601 return low | (u32)high << 16;
602 }
603
604 #define for_each_l3cc(l3cc, t, i) \
605 for (i = 0; \
606 i < ((t)->n_entries + 1) / 2 ? \
607 (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
608 get_entry_l3cc((t), 2 * i + 1))), 1 : \
609 0; \
610 i++)
611
init_l3cc_table(struct intel_uncore * uncore,const struct drm_i915_mocs_table * table)612 static void init_l3cc_table(struct intel_uncore *uncore,
613 const struct drm_i915_mocs_table *table)
614 {
615 unsigned int i;
616 u32 l3cc;
617
618 for_each_l3cc(l3cc, table, i)
619 intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
620 }
621
intel_mocs_init_engine(struct intel_engine_cs * engine)622 void intel_mocs_init_engine(struct intel_engine_cs *engine)
623 {
624 struct drm_i915_mocs_table table;
625 unsigned int flags;
626
627 /* Called under a blanket forcewake */
628 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
629
630 flags = get_mocs_settings(engine->i915, &table);
631 if (!flags)
632 return;
633
634 /* Platforms with global MOCS do not need per-engine initialization. */
635 if (flags & HAS_ENGINE_MOCS)
636 init_mocs_table(engine, &table);
637
638 if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
639 init_l3cc_table(engine->uncore, &table);
640 }
641
global_mocs_offset(void)642 static u32 global_mocs_offset(void)
643 {
644 return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
645 }
646
intel_set_mocs_index(struct intel_gt * gt)647 void intel_set_mocs_index(struct intel_gt *gt)
648 {
649 struct drm_i915_mocs_table table;
650
651 get_mocs_settings(gt->i915, &table);
652 gt->mocs.uc_index = table.uc_index;
653 if (HAS_L3_CCS_READ(gt->i915))
654 gt->mocs.wb_index = table.wb_index;
655 }
656
intel_mocs_init(struct intel_gt * gt)657 void intel_mocs_init(struct intel_gt *gt)
658 {
659 struct drm_i915_mocs_table table;
660 unsigned int flags;
661
662 /*
663 * LLC and eDRAM control values are not applicable to dgfx
664 */
665 flags = get_mocs_settings(gt->i915, &table);
666 if (flags & HAS_GLOBAL_MOCS)
667 __init_mocs_table(gt->uncore, &table, global_mocs_offset());
668
669 /*
670 * Initialize the L3CC table as part of mocs initalization to make
671 * sure the LNCFCMOCSx registers are programmed for the subsequent
672 * memory transactions including guc transactions
673 */
674 if (flags & HAS_RENDER_L3CC)
675 init_l3cc_table(gt->uncore, &table);
676 }
677
678 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
679 #include "selftest_mocs.c"
680 #endif
681