1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2013, The Linux Foundation. All rights reserved. */
3 
4 #ifndef __QCOM_CLK_BRANCH_H__
5 #define __QCOM_CLK_BRANCH_H__
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk-provider.h>
9 
10 #include "clk-regmap.h"
11 
12 /**
13  * struct clk_branch - gating clock with status bit and dynamic hardware gating
14  *
15  * @hwcg_reg: dynamic hardware clock gating register
16  * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
17  * @halt_reg: halt register
18  * @halt_bit: ANDed with @halt_reg to test for clock halted
19  * @halt_check: type of halt checking to perform
20  * @clkr: handle between common and hardware-specific interfaces
21  *
22  * Clock which can gate its output.
23  */
24 struct clk_branch {
25 	u32	hwcg_reg;
26 	u32	halt_reg;
27 	u8	hwcg_bit;
28 	u8	halt_bit;
29 	u8	halt_check;
30 #define BRANCH_VOTED			BIT(7) /* Delay on disable */
31 #define BRANCH_HALT			0 /* pol: 1 = halt */
32 #define BRANCH_HALT_VOTED		(BRANCH_HALT | BRANCH_VOTED)
33 #define BRANCH_HALT_ENABLE		1 /* pol: 0 = halt */
34 #define BRANCH_HALT_ENABLE_VOTED	(BRANCH_HALT_ENABLE | BRANCH_VOTED)
35 #define BRANCH_HALT_DELAY		2 /* No bit to check; just delay */
36 #define BRANCH_HALT_SKIP		3 /* Don't check halt bit */
37 
38 	struct clk_regmap clkr;
39 };
40 
41 /* Branch clock common bits for HLOS-owned clocks */
42 #define CBCR_CLK_OFF			BIT(31)
43 #define CBCR_NOC_FSM_STATUS		GENMASK(30, 28)
44  #define FSM_STATUS_ON			BIT(1)
45 #define CBCR_FORCE_MEM_CORE_ON		BIT(14)
46 #define CBCR_FORCE_MEM_PERIPH_ON	BIT(13)
47 #define CBCR_FORCE_MEM_PERIPH_OFF	BIT(12)
48 #define CBCR_WAKEUP			GENMASK(11, 8)
49 #define CBCR_SLEEP			GENMASK(7, 4)
50 
qcom_branch_set_force_mem_core(struct regmap * regmap,struct clk_branch clk,bool on)51 static inline void qcom_branch_set_force_mem_core(struct regmap *regmap,
52 						  struct clk_branch clk, bool on)
53 {
54 	regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_CORE_ON,
55 			   on ? CBCR_FORCE_MEM_CORE_ON : 0);
56 }
57 
qcom_branch_set_force_periph_on(struct regmap * regmap,struct clk_branch clk,bool on)58 static inline void qcom_branch_set_force_periph_on(struct regmap *regmap,
59 						   struct clk_branch clk, bool on)
60 {
61 	regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_ON,
62 			   on ? CBCR_FORCE_MEM_PERIPH_ON : 0);
63 }
64 
qcom_branch_set_force_periph_off(struct regmap * regmap,struct clk_branch clk,bool on)65 static inline void qcom_branch_set_force_periph_off(struct regmap *regmap,
66 						    struct clk_branch clk, bool on)
67 {
68 	regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_OFF,
69 			   on ? CBCR_FORCE_MEM_PERIPH_OFF : 0);
70 }
71 
qcom_branch_set_wakeup(struct regmap * regmap,struct clk_branch clk,u32 val)72 static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val)
73 {
74 	regmap_update_bits(regmap, clk.halt_reg, CBCR_WAKEUP,
75 			   FIELD_PREP(CBCR_WAKEUP, val));
76 }
77 
qcom_branch_set_sleep(struct regmap * regmap,struct clk_branch clk,u32 val)78 static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val)
79 {
80 	regmap_update_bits(regmap, clk.halt_reg, CBCR_SLEEP,
81 			   FIELD_PREP(CBCR_SLEEP, val));
82 }
83 
84 extern const struct clk_ops clk_branch_ops;
85 extern const struct clk_ops clk_branch2_ops;
86 extern const struct clk_ops clk_branch_simple_ops;
87 extern const struct clk_ops clk_branch2_aon_ops;
88 
89 #define to_clk_branch(_hw) \
90 	container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
91 
92 #endif
93