1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HW_H
8 #define ATH12K_HW_H
9
10 #include <linux/mhi.h>
11
12 #include "wmi.h"
13 #include "hal.h"
14
15 /* Target configuration defines */
16
17 /* Num VDEVS per radio */
18 #define TARGET_NUM_VDEVS (16 + 1)
19
20 #define TARGET_NUM_PEERS_PDEV (512 + TARGET_NUM_VDEVS)
21
22 /* Num of peers for Single Radio mode */
23 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV)
24
25 /* Num of peers for DBS */
26 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV)
27
28 /* Num of peers for DBS_SBS */
29 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV)
30
31 /* Max num of stations (per radio) */
32 #define TARGET_NUM_STATIONS 512
33
34 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x
35 #define TARGET_NUM_PEER_KEYS 2
36 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \
37 4 * TARGET_NUM_VDEVS + 8)
38
39 #define TARGET_AST_SKID_LIMIT 16
40 #define TARGET_NUM_OFFLD_PEERS 4
41 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
42
43 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
44 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
45 #define TARGET_RX_TIMEOUT_LO_PRI 100
46 #define TARGET_RX_TIMEOUT_HI_PRI 40
47
48 #define TARGET_DECAP_MODE_RAW 0
49 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
50 #define TARGET_DECAP_MODE_ETH 2
51
52 #define TARGET_SCAN_MAX_PENDING_REQS 4
53 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
54 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
55 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
56 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
57 #define TARGET_NUM_MCAST_GROUPS 12
58 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
59 #define TARGET_MCAST2UCAST_MODE 2
60 #define TARGET_TX_DBG_LOG_SIZE 1024
61 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
62 #define TARGET_VOW_CONFIG 0
63 #define TARGET_NUM_MSDU_DESC (2500)
64 #define TARGET_MAX_FRAG_ENTRIES 6
65 #define TARGET_MAX_BCN_OFFLD 16
66 #define TARGET_NUM_WDS_ENTRIES 32
67 #define TARGET_DMA_BURST_SIZE 1
68 #define TARGET_RX_BATCHMODE 1
69
70 #define ATH12K_HW_MAX_QUEUES 4
71 #define ATH12K_QUEUE_LEN 4096
72
73 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
74
75 #define ATH12K_FW_DIR "ath12k"
76
77 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD"
78 #define ATH12K_BOARD_API2_FILE "board-2.bin"
79 #define ATH12K_DEFAULT_BOARD_FILE "board.bin"
80 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin"
81 #define ATH12K_AMSS_FILE "amss.bin"
82 #define ATH12K_M3_FILE "m3.bin"
83 #define ATH12K_REGDB_FILE_NAME "regdb.bin"
84
85 enum ath12k_hw_rate_cck {
86 ATH12K_HW_RATE_CCK_LP_11M = 0,
87 ATH12K_HW_RATE_CCK_LP_5_5M,
88 ATH12K_HW_RATE_CCK_LP_2M,
89 ATH12K_HW_RATE_CCK_LP_1M,
90 ATH12K_HW_RATE_CCK_SP_11M,
91 ATH12K_HW_RATE_CCK_SP_5_5M,
92 ATH12K_HW_RATE_CCK_SP_2M,
93 };
94
95 enum ath12k_hw_rate_ofdm {
96 ATH12K_HW_RATE_OFDM_48M = 0,
97 ATH12K_HW_RATE_OFDM_24M,
98 ATH12K_HW_RATE_OFDM_12M,
99 ATH12K_HW_RATE_OFDM_6M,
100 ATH12K_HW_RATE_OFDM_54M,
101 ATH12K_HW_RATE_OFDM_36M,
102 ATH12K_HW_RATE_OFDM_18M,
103 ATH12K_HW_RATE_OFDM_9M,
104 };
105
106 enum ath12k_bus {
107 ATH12K_BUS_PCI,
108 };
109
110 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11
111
112 struct hal_rx_desc;
113 struct hal_tcl_data_cmd;
114 struct htt_rx_ring_tlv_filter;
115 enum hal_encrypt_type;
116
117 struct ath12k_hw_ring_mask {
118 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
119 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
120 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
121 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX];
122 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX];
123 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX];
124 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX];
125 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
126 };
127
128 struct ath12k_hw_hal_params {
129 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
130 u32 wbm2sw_cc_enable;
131 };
132
133 struct ath12k_hw_params {
134 const char *name;
135 u16 hw_rev;
136
137 struct {
138 const char *dir;
139 size_t board_size;
140 size_t cal_offset;
141 } fw;
142
143 u8 max_radios;
144 bool single_pdev_only:1;
145 u32 qmi_service_ins_id;
146 bool internal_sleep_clock:1;
147
148 const struct ath12k_hw_ops *hw_ops;
149 const struct ath12k_hw_ring_mask *ring_mask;
150 const struct ath12k_hw_regs *regs;
151
152 const struct ce_attr *host_ce_config;
153 u32 ce_count;
154 const struct ce_pipe_config *target_ce_config;
155 u32 target_ce_count;
156 const struct service_to_pipe *svc_to_ce_map;
157 u32 svc_to_ce_map_len;
158
159 const struct ath12k_hw_hal_params *hal_params;
160
161 bool rxdma1_enable:1;
162 int num_rxmda_per_pdev;
163 int num_rxdma_dst_ring;
164 bool rx_mac_buf_ring:1;
165 bool vdev_start_delay:1;
166
167 u16 interface_modes;
168 bool supports_monitor:1;
169
170 bool idle_ps:1;
171 bool download_calib:1;
172 bool supports_suspend:1;
173 bool tcl_ring_retry:1;
174 bool reoq_lut_support:1;
175 bool supports_shadow_regs:1;
176
177 u32 hal_desc_sz;
178 u32 num_tcl_banks;
179 u32 max_tx_ring;
180
181 const struct mhi_controller_config *mhi_config;
182
183 void (*wmi_init)(struct ath12k_base *ab,
184 struct ath12k_wmi_resource_config_arg *config);
185
186 const struct hal_ops *hal_ops;
187
188 u64 qmi_cnss_feature_bitmap;
189 };
190
191 struct ath12k_hw_ops {
192 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
193 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id);
194 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id);
195 int (*rxdma_ring_sel_config)(struct ath12k_base *ab);
196 u8 (*get_ring_selector)(struct sk_buff *skb);
197 bool (*dp_srng_is_tx_comp_ring)(int ring_num);
198 };
199
200 static inline
ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params * hw,int pdev_idx)201 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw,
202 int pdev_idx)
203 {
204 if (hw->hw_ops->get_hw_mac_from_pdev_id)
205 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
206
207 return 0;
208 }
209
ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params * hw,int mac_id)210 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw,
211 int mac_id)
212 {
213 if (hw->hw_ops->mac_id_to_pdev_id)
214 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
215
216 return 0;
217 }
218
ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params * hw,int mac_id)219 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw,
220 int mac_id)
221 {
222 if (hw->hw_ops->mac_id_to_srng_id)
223 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
224
225 return 0;
226 }
227
228 struct ath12k_fw_ie {
229 __le32 id;
230 __le32 len;
231 u8 data[];
232 };
233
234 enum ath12k_bd_ie_board_type {
235 ATH12K_BD_IE_BOARD_NAME = 0,
236 ATH12K_BD_IE_BOARD_DATA = 1,
237 };
238
239 enum ath12k_bd_ie_type {
240 /* contains sub IEs of enum ath12k_bd_ie_board_type */
241 ATH12K_BD_IE_BOARD = 0,
242 ATH12K_BD_IE_BOARD_EXT = 1,
243 };
244
245 struct ath12k_hw_regs {
246 u32 hal_tcl1_ring_id;
247 u32 hal_tcl1_ring_misc;
248 u32 hal_tcl1_ring_tp_addr_lsb;
249 u32 hal_tcl1_ring_tp_addr_msb;
250 u32 hal_tcl1_ring_consumer_int_setup_ix0;
251 u32 hal_tcl1_ring_consumer_int_setup_ix1;
252 u32 hal_tcl1_ring_msi1_base_lsb;
253 u32 hal_tcl1_ring_msi1_base_msb;
254 u32 hal_tcl1_ring_msi1_data;
255 u32 hal_tcl_ring_base_lsb;
256
257 u32 hal_tcl_status_ring_base_lsb;
258
259 u32 hal_wbm_idle_ring_base_lsb;
260 u32 hal_wbm_idle_ring_misc_addr;
261 u32 hal_wbm_r0_idle_list_cntl_addr;
262 u32 hal_wbm_r0_idle_list_size_addr;
263 u32 hal_wbm_scattered_ring_base_lsb;
264 u32 hal_wbm_scattered_ring_base_msb;
265 u32 hal_wbm_scattered_desc_head_info_ix0;
266 u32 hal_wbm_scattered_desc_head_info_ix1;
267 u32 hal_wbm_scattered_desc_tail_info_ix0;
268 u32 hal_wbm_scattered_desc_tail_info_ix1;
269 u32 hal_wbm_scattered_desc_ptr_hp_addr;
270
271 u32 hal_wbm_sw_release_ring_base_lsb;
272 u32 hal_wbm_sw1_release_ring_base_lsb;
273 u32 hal_wbm0_release_ring_base_lsb;
274 u32 hal_wbm1_release_ring_base_lsb;
275
276 u32 pcie_qserdes_sysclk_en_sel;
277 u32 pcie_pcs_osc_dtct_config_base;
278
279 u32 hal_ppe_rel_ring_base;
280
281 u32 hal_reo2_ring_base;
282 u32 hal_reo1_misc_ctrl_addr;
283 u32 hal_reo1_sw_cookie_cfg0;
284 u32 hal_reo1_sw_cookie_cfg1;
285 u32 hal_reo1_qdesc_lut_base0;
286 u32 hal_reo1_qdesc_lut_base1;
287 u32 hal_reo1_ring_base_lsb;
288 u32 hal_reo1_ring_base_msb;
289 u32 hal_reo1_ring_id;
290 u32 hal_reo1_ring_misc;
291 u32 hal_reo1_ring_hp_addr_lsb;
292 u32 hal_reo1_ring_hp_addr_msb;
293 u32 hal_reo1_ring_producer_int_setup;
294 u32 hal_reo1_ring_msi1_base_lsb;
295 u32 hal_reo1_ring_msi1_base_msb;
296 u32 hal_reo1_ring_msi1_data;
297 u32 hal_reo1_aging_thres_ix0;
298 u32 hal_reo1_aging_thres_ix1;
299 u32 hal_reo1_aging_thres_ix2;
300 u32 hal_reo1_aging_thres_ix3;
301
302 u32 hal_reo2_sw0_ring_base;
303
304 u32 hal_sw2reo_ring_base;
305 u32 hal_sw2reo1_ring_base;
306
307 u32 hal_reo_cmd_ring_base;
308
309 u32 hal_reo_status_ring_base;
310 };
311
312 int ath12k_hw_init(struct ath12k_base *ab);
313
314 #endif
315