1 /*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "changk104.h"
23 #include "cgrp.h"
24
25 #include <core/client.h>
26 #include <core/gpuobj.h>
27
28 #include <nvif/clc36f.h>
29 #include <nvif/unpack.h>
30
31 static u32
gv100_fifo_gpfifo_submit_token(struct nvkm_fifo_chan * chan)32 gv100_fifo_gpfifo_submit_token(struct nvkm_fifo_chan *chan)
33 {
34 return chan->chid;
35 }
36
37 static int
gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan * chan,bool ce,bool valid)38 gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid)
39 {
40 struct nvkm_subdev *subdev = &chan->base.fifo->engine.subdev;
41 struct nvkm_device *device = subdev->device;
42 const u32 mask = ce ? 0x00020000 : 0x00010000;
43 const u32 data = valid ? mask : 0x00000000;
44 int ret;
45
46 /* Block runlist to prevent the channel from being rescheduled. */
47 mutex_lock(&chan->fifo->base.mutex);
48 nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl));
49
50 /* Preempt the channel. */
51 ret = gk104_fifo_gpfifo_kick_locked(chan);
52 if (ret == 0) {
53 /* Update engine context validity. */
54 nvkm_kmap(chan->base.inst);
55 nvkm_mo32(chan->base.inst, 0x0ac, mask, data);
56 nvkm_done(chan->base.inst);
57 }
58
59 /* Resume runlist. */
60 nvkm_mask(device, 0x002630, BIT(chan->runl), 0);
61 mutex_unlock(&chan->fifo->base.mutex);
62 return ret;
63 }
64
65 int
gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan * base,struct nvkm_engine * engine,bool suspend)66 gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
67 struct nvkm_engine *engine, bool suspend)
68 {
69 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
70 struct nvkm_gpuobj *inst = chan->base.inst;
71 int ret;
72
73 if (engine->subdev.type == NVKM_ENGINE_CE) {
74 ret = gv100_fifo_gpfifo_engine_valid(chan, true, false);
75 if (ret && suspend)
76 return ret;
77
78 nvkm_kmap(inst);
79 nvkm_wo32(chan->base.inst, 0x220, 0x00000000);
80 nvkm_wo32(chan->base.inst, 0x224, 0x00000000);
81 nvkm_done(inst);
82 return ret;
83 }
84
85 ret = gv100_fifo_gpfifo_engine_valid(chan, false, false);
86 if (ret && suspend)
87 return ret;
88
89 nvkm_kmap(inst);
90 nvkm_wo32(inst, 0x0210, 0x00000000);
91 nvkm_wo32(inst, 0x0214, 0x00000000);
92 nvkm_done(inst);
93 return ret;
94 }
95
96 int
gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan * base,struct nvkm_engine * engine)97 gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
98 struct nvkm_engine *engine)
99 {
100 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
101 struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
102 struct nvkm_gpuobj *inst = chan->base.inst;
103
104 if (engine->subdev.type == NVKM_ENGINE_CE) {
105 const u64 bar2 = nvkm_memory_bar2(engn->inst->memory);
106
107 nvkm_kmap(inst);
108 nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(bar2));
109 nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(bar2));
110 nvkm_done(inst);
111
112 return gv100_fifo_gpfifo_engine_valid(chan, true, true);
113 }
114
115 nvkm_kmap(inst);
116 nvkm_wo32(inst, 0x210, lower_32_bits(engn->vma->addr) | 0x00000004);
117 nvkm_wo32(inst, 0x214, upper_32_bits(engn->vma->addr));
118 nvkm_done(inst);
119
120 return gv100_fifo_gpfifo_engine_valid(chan, false, true);
121 }
122
123 static const struct nvkm_fifo_chan_func
124 gv100_fifo_gpfifo = {
125 .dtor = gk104_fifo_gpfifo_dtor,
126 .init = gk104_fifo_gpfifo_init,
127 .fini = gk104_fifo_gpfifo_fini,
128 .ntfy = gf100_fifo_chan_ntfy,
129 .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
130 .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
131 .engine_init = gv100_fifo_gpfifo_engine_init,
132 .engine_fini = gv100_fifo_gpfifo_engine_fini,
133 .submit_token = gv100_fifo_gpfifo_submit_token,
134 };
135
136 int
gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func * func,struct gk104_fifo * fifo,u64 * runlists,u16 * chid,u64 vmm,u64 ioffset,u64 ilength,u64 * inst,bool priv,u32 * token,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)137 gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
138 struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
139 u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv,
140 u32 *token, const struct nvkm_oclass *oclass,
141 struct nvkm_object **pobject)
142 {
143 struct gk104_fifo_chan *chan;
144 int runlist = ffs(*runlists) -1, ret, i;
145 u64 usermem;
146
147 if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
148 return -EINVAL;
149 *runlists = BIT_ULL(runlist);
150
151 /* Allocate the channel. */
152 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
153 return -ENOMEM;
154 *pobject = &chan->base.object;
155 chan->fifo = fifo;
156 chan->runl = runlist;
157 INIT_LIST_HEAD(&chan->head);
158
159 ret = nvkm_fifo_chan_ctor(func, &fifo->base, 0x1000, 0x1000, true, vmm,
160 0, fifo->runlist[runlist].engm, 1, fifo->user.bar->addr, 0x200,
161 oclass, &chan->base);
162 if (ret)
163 return ret;
164
165 *chid = chan->base.chid;
166 *inst = chan->base.inst->addr;
167 *token = chan->base.func->submit_token(&chan->base);
168
169 /* Hack to support GPUs where even individual channels should be
170 * part of a channel group.
171 */
172 if (fifo->func->cgrp_force) {
173 if (!(chan->cgrp = kmalloc(sizeof(*chan->cgrp), GFP_KERNEL)))
174 return -ENOMEM;
175 chan->cgrp->id = chan->base.chid;
176 INIT_LIST_HEAD(&chan->cgrp->head);
177 INIT_LIST_HEAD(&chan->cgrp->chan);
178 chan->cgrp->chan_nr = 0;
179 }
180
181 /* Clear channel control registers. */
182 usermem = chan->base.chid * 0x200;
183 ilength = order_base_2(ilength / 8);
184
185 nvkm_kmap(fifo->user.mem);
186 for (i = 0; i < 0x200; i += 4)
187 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
188 nvkm_done(fifo->user.mem);
189 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
190
191 /* RAMFC */
192 nvkm_kmap(chan->base.inst);
193 nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
194 nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
195 nvkm_wo32(chan->base.inst, 0x010, 0x0000face);
196 nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902);
197 nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset));
198 nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) |
199 (ilength << 16));
200 nvkm_wo32(chan->base.inst, 0x084, 0x20400000);
201 nvkm_wo32(chan->base.inst, 0x094, 0x30000001);
202 nvkm_wo32(chan->base.inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
203 nvkm_wo32(chan->base.inst, 0x0e8, chan->base.chid);
204 nvkm_wo32(chan->base.inst, 0x0f4, 0x00001000);
205 nvkm_wo32(chan->base.inst, 0x0f8, 0x10003080);
206 nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000);
207 nvkm_done(chan->base.inst);
208 return 0;
209 }
210
211 int
gv100_fifo_gpfifo_new(struct gk104_fifo * fifo,const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)212 gv100_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass,
213 void *data, u32 size, struct nvkm_object **pobject)
214 {
215 struct nvkm_object *parent = oclass->parent;
216 union {
217 struct volta_channel_gpfifo_a_v0 v0;
218 } *args = data;
219 int ret = -ENOSYS;
220
221 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
222 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
223 nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
224 "ioffset %016llx ilength %08x "
225 "runlist %016llx priv %d\n",
226 args->v0.version, args->v0.vmm, args->v0.ioffset,
227 args->v0.ilength, args->v0.runlist, args->v0.priv);
228 return gv100_fifo_gpfifo_new_(&gv100_fifo_gpfifo, fifo,
229 &args->v0.runlist,
230 &args->v0.chid,
231 args->v0.vmm,
232 args->v0.ioffset,
233 args->v0.ilength,
234 &args->v0.inst,
235 args->v0.priv,
236 &args->v0.token,
237 oclass, pobject);
238 }
239
240 return ret;
241 }
242