1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #ifndef __MSM_GPU_H__
8 #define __MSM_GPU_H__
9
10 #include <linux/adreno-smmu-priv.h>
11 #include <linux/clk.h>
12 #include <linux/devfreq.h>
13 #include <linux/interconnect.h>
14 #include <linux/pm_opp.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
17
18 #include "msm_drv.h"
19 #include "msm_fence.h"
20 #include "msm_ringbuffer.h"
21 #include "msm_gem.h"
22
23 struct msm_gem_submit;
24 struct msm_gpu_perfcntr;
25 struct msm_gpu_state;
26 struct msm_file_private;
27
28 struct msm_gpu_config {
29 const char *ioname;
30 unsigned int nr_rings;
31 };
32
33 /* So far, with hardware that I've seen to date, we can have:
34 * + zero, one, or two z180 2d cores
35 * + a3xx or a2xx 3d core, which share a common CP (the firmware
36 * for the CP seems to implement some different PM4 packet types
37 * but the basics of cmdstream submission are the same)
38 *
39 * Which means that the eventual complete "class" hierarchy, once
40 * support for all past and present hw is in place, becomes:
41 * + msm_gpu
42 * + adreno_gpu
43 * + a3xx_gpu
44 * + a2xx_gpu
45 * + z180_gpu
46 */
47 struct msm_gpu_funcs {
48 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
49 uint32_t param, uint64_t *value, uint32_t *len);
50 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
51 uint32_t param, uint64_t value, uint32_t len);
52 int (*hw_init)(struct msm_gpu *gpu);
53 int (*pm_suspend)(struct msm_gpu *gpu);
54 int (*pm_resume)(struct msm_gpu *gpu);
55 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
56 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
57 irqreturn_t (*irq)(struct msm_gpu *irq);
58 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
59 void (*recover)(struct msm_gpu *gpu);
60 void (*destroy)(struct msm_gpu *gpu);
61 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
62 /* show GPU status in debugfs: */
63 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
64 struct drm_printer *p);
65 /* for generation specific debugfs: */
66 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
67 #endif
68 /* note: gpu_busy() can assume that we have been pm_resumed */
69 u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
70 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
71 int (*gpu_state_put)(struct msm_gpu_state *state);
72 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
73 /* note: gpu_set_freq() can assume that we have been pm_resumed */
74 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
75 bool suspended);
76 struct msm_gem_address_space *(*create_address_space)
77 (struct msm_gpu *gpu, struct platform_device *pdev);
78 struct msm_gem_address_space *(*create_private_address_space)
79 (struct msm_gpu *gpu);
80 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
81 };
82
83 /* Additional state for iommu faults: */
84 struct msm_gpu_fault_info {
85 u64 ttbr0;
86 unsigned long iova;
87 int flags;
88 const char *type;
89 const char *block;
90 };
91
92 /**
93 * struct msm_gpu_devfreq - devfreq related state
94 */
95 struct msm_gpu_devfreq {
96 /** devfreq: devfreq instance */
97 struct devfreq *devfreq;
98
99 /** lock: lock for "suspended", "busy_cycles", and "time" */
100 struct mutex lock;
101
102 /**
103 * idle_constraint:
104 *
105 * A PM QoS constraint to limit max freq while the GPU is idle.
106 */
107 struct dev_pm_qos_request idle_freq;
108
109 /**
110 * boost_constraint:
111 *
112 * A PM QoS constraint to boost min freq for a period of time
113 * until the boost expires.
114 */
115 struct dev_pm_qos_request boost_freq;
116
117 /**
118 * busy_cycles: Last busy counter value, for calculating elapsed busy
119 * cycles since last sampling period.
120 */
121 u64 busy_cycles;
122
123 /** time: Time of last sampling period. */
124 ktime_t time;
125
126 /** idle_time: Time of last transition to idle: */
127 ktime_t idle_time;
128
129 struct devfreq_dev_status average_status;
130
131 /**
132 * idle_work:
133 *
134 * Used to delay clamping to idle freq on active->idle transition.
135 */
136 struct msm_hrtimer_work idle_work;
137
138 /**
139 * boost_work:
140 *
141 * Used to reset the boost_constraint after the boost period has
142 * elapsed
143 */
144 struct msm_hrtimer_work boost_work;
145
146 /** suspended: tracks if we're suspended */
147 bool suspended;
148 };
149
150 struct msm_gpu {
151 const char *name;
152 struct drm_device *dev;
153 struct platform_device *pdev;
154 const struct msm_gpu_funcs *funcs;
155
156 struct adreno_smmu_priv adreno_smmu;
157
158 /* performance counters (hw & sw): */
159 spinlock_t perf_lock;
160 bool perfcntr_active;
161 struct {
162 bool active;
163 ktime_t time;
164 } last_sample;
165 uint32_t totaltime, activetime; /* sw counters */
166 uint32_t last_cntrs[5]; /* hw counters */
167 const struct msm_gpu_perfcntr *perfcntrs;
168 uint32_t num_perfcntrs;
169
170 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
171 int nr_rings;
172
173 /**
174 * sysprof_active:
175 *
176 * The count of contexts that have enabled system profiling.
177 */
178 refcount_t sysprof_active;
179
180 /**
181 * cur_ctx_seqno:
182 *
183 * The ctx->seqno value of the last context to submit rendering,
184 * and the one with current pgtables installed (for generations
185 * that support per-context pgtables). Tracked by seqno rather
186 * than pointer value to avoid dangling pointers, and cases where
187 * a ctx can be freed and a new one created with the same address.
188 */
189 int cur_ctx_seqno;
190
191 /**
192 * lock:
193 *
194 * General lock for serializing all the gpu things.
195 *
196 * TODO move to per-ring locking where feasible (ie. submit/retire
197 * path, etc)
198 */
199 struct mutex lock;
200
201 /**
202 * active_submits:
203 *
204 * The number of submitted but not yet retired submits, used to
205 * determine transitions between active and idle.
206 *
207 * Protected by active_lock
208 */
209 int active_submits;
210
211 /** lock: protects active_submits and idle/active transitions */
212 struct mutex active_lock;
213
214 /* does gpu need hw_init? */
215 bool needs_hw_init;
216
217 /**
218 * global_faults: number of GPU hangs not attributed to a particular
219 * address space
220 */
221 int global_faults;
222
223 void __iomem *mmio;
224 int irq;
225
226 struct msm_gem_address_space *aspace;
227
228 /* Power Control: */
229 struct regulator *gpu_reg, *gpu_cx;
230 struct clk_bulk_data *grp_clks;
231 int nr_clocks;
232 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
233 uint32_t fast_rate;
234
235 /* Hang and Inactivity Detection:
236 */
237 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
238
239 #define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
240 struct timer_list hangcheck_timer;
241
242 /* Fault info for most recent iova fault: */
243 struct msm_gpu_fault_info fault_info;
244
245 /* work for handling GPU ioval faults: */
246 struct kthread_work fault_work;
247
248 /* work for handling GPU recovery: */
249 struct kthread_work recover_work;
250
251 /** retire_event: notified when submits are retired: */
252 wait_queue_head_t retire_event;
253
254 /* work for handling active-list retiring: */
255 struct kthread_work retire_work;
256
257 /* worker for retire/recover: */
258 struct kthread_worker *worker;
259
260 struct drm_gem_object *memptrs_bo;
261
262 struct msm_gpu_devfreq devfreq;
263
264 uint32_t suspend_count;
265
266 struct msm_gpu_state *crashstate;
267
268 /* Enable clamping to idle freq when inactive: */
269 bool clamp_to_idle;
270
271 /* True if the hardware supports expanded apriv (a650 and newer) */
272 bool hw_apriv;
273
274 struct thermal_cooling_device *cooling;
275
276 /* To poll for cx gdsc collapse during gpu recovery */
277 struct reset_control *cx_collapse;
278 };
279
dev_to_gpu(struct device * dev)280 static inline struct msm_gpu *dev_to_gpu(struct device *dev)
281 {
282 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
283
284 if (!adreno_smmu)
285 return NULL;
286
287 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
288 }
289
290 /* It turns out that all targets use the same ringbuffer size */
291 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
292 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
293
294 #define MSM_GPU_RB_CNTL_DEFAULT \
295 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
296 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
297
msm_gpu_active(struct msm_gpu * gpu)298 static inline bool msm_gpu_active(struct msm_gpu *gpu)
299 {
300 int i;
301
302 for (i = 0; i < gpu->nr_rings; i++) {
303 struct msm_ringbuffer *ring = gpu->rb[i];
304
305 if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))
306 return true;
307 }
308
309 return false;
310 }
311
312 /* Perf-Counters:
313 * The select_reg and select_val are just there for the benefit of the child
314 * class that actually enables the perf counter.. but msm_gpu base class
315 * will handle sampling/displaying the counters.
316 */
317
318 struct msm_gpu_perfcntr {
319 uint32_t select_reg;
320 uint32_t sample_reg;
321 uint32_t select_val;
322 const char *name;
323 };
324
325 /*
326 * The number of priority levels provided by drm gpu scheduler. The
327 * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some
328 * cases, so we don't use it (no need for kernel generated jobs).
329 */
330 #define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_HIGH - DRM_SCHED_PRIORITY_MIN)
331
332 /**
333 * struct msm_file_private - per-drm_file context
334 *
335 * @queuelock: synchronizes access to submitqueues list
336 * @submitqueues: list of &msm_gpu_submitqueue created by userspace
337 * @queueid: counter incremented each time a submitqueue is created,
338 * used to assign &msm_gpu_submitqueue.id
339 * @aspace: the per-process GPU address-space
340 * @ref: reference count
341 * @seqno: unique per process seqno
342 */
343 struct msm_file_private {
344 rwlock_t queuelock;
345 struct list_head submitqueues;
346 int queueid;
347 struct msm_gem_address_space *aspace;
348 struct kref ref;
349 int seqno;
350
351 /**
352 * sysprof:
353 *
354 * The value of MSM_PARAM_SYSPROF set by userspace. This is
355 * intended to be used by system profiling tools like Mesa's
356 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
357 *
358 * Setting a value of 1 will preserve performance counters across
359 * context switches. Setting a value of 2 will in addition
360 * suppress suspend. (Performance counters lose state across
361 * power collapse, which is undesirable for profiling in some
362 * cases.)
363 *
364 * The value automatically reverts to zero when the drm device
365 * file is closed.
366 */
367 int sysprof;
368
369 /**
370 * comm: Overridden task comm, see MSM_PARAM_COMM
371 *
372 * Accessed under msm_gpu::lock
373 */
374 char *comm;
375
376 /**
377 * cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE
378 *
379 * Accessed under msm_gpu::lock
380 */
381 char *cmdline;
382
383 /**
384 * elapsed:
385 *
386 * The total (cumulative) elapsed time GPU was busy with rendering
387 * from this context in ns.
388 */
389 uint64_t elapsed_ns;
390
391 /**
392 * cycles:
393 *
394 * The total (cumulative) GPU cycles elapsed attributed to this
395 * context.
396 */
397 uint64_t cycles;
398
399 /**
400 * entities:
401 *
402 * Table of per-priority-level sched entities used by submitqueues
403 * associated with this &drm_file. Because some userspace apps
404 * make assumptions about rendering from multiple gl contexts
405 * (of the same priority) within the process happening in FIFO
406 * order without requiring any fencing beyond MakeCurrent(), we
407 * create at most one &drm_sched_entity per-process per-priority-
408 * level.
409 */
410 struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS];
411 };
412
413 /**
414 * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
415 *
416 * @gpu: the gpu instance
417 * @prio: the userspace priority level
418 * @ring_nr: [out] the ringbuffer the userspace priority maps to
419 * @sched_prio: [out] the gpu scheduler priority level which the userspace
420 * priority maps to
421 *
422 * With drm/scheduler providing it's own level of prioritization, our total
423 * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES).
424 * Each ring is associated with it's own scheduler instance. However, our
425 * UABI is that lower numerical values are higher priority. So mapping the
426 * single userspace priority level into ring_nr and sched_prio takes some
427 * care. The userspace provided priority (when a submitqueue is created)
428 * is mapped to ring nr and scheduler priority as such:
429 *
430 * ring_nr = userspace_prio / NR_SCHED_PRIORITIES
431 * sched_prio = NR_SCHED_PRIORITIES -
432 * (userspace_prio % NR_SCHED_PRIORITIES) - 1
433 *
434 * This allows generations without preemption (nr_rings==1) to have some
435 * amount of prioritization, and provides more priority levels for gens
436 * that do have preemption.
437 */
msm_gpu_convert_priority(struct msm_gpu * gpu,int prio,unsigned * ring_nr,enum drm_sched_priority * sched_prio)438 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,
439 unsigned *ring_nr, enum drm_sched_priority *sched_prio)
440 {
441 unsigned rn, sp;
442
443 rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp);
444
445 /* invert sched priority to map to higher-numeric-is-higher-
446 * priority convention
447 */
448 sp = NR_SCHED_PRIORITIES - sp - 1;
449
450 if (rn >= gpu->nr_rings)
451 return -EINVAL;
452
453 *ring_nr = rn;
454 *sched_prio = sp;
455
456 return 0;
457 }
458
459 /**
460 * struct msm_gpu_submitqueues - Userspace created context.
461 *
462 * A submitqueue is associated with a gl context or vk queue (or equiv)
463 * in userspace.
464 *
465 * @id: userspace id for the submitqueue, unique within the drm_file
466 * @flags: userspace flags for the submitqueue, specified at creation
467 * (currently unusued)
468 * @ring_nr: the ringbuffer used by this submitqueue, which is determined
469 * by the submitqueue's priority
470 * @faults: the number of GPU hangs associated with this submitqueue
471 * @last_fence: the sequence number of the last allocated fence (for error
472 * checking)
473 * @ctx: the per-drm_file context associated with the submitqueue (ie.
474 * which set of pgtables do submits jobs associated with the
475 * submitqueue use)
476 * @node: node in the context's list of submitqueues
477 * @fence_idr: maps fence-id to dma_fence for userspace visible fence
478 * seqno, protected by submitqueue lock
479 * @idr_lock: for serializing access to fence_idr
480 * @lock: submitqueue lock for serializing submits on a queue
481 * @ref: reference count
482 * @entity: the submit job-queue
483 */
484 struct msm_gpu_submitqueue {
485 int id;
486 u32 flags;
487 u32 ring_nr;
488 int faults;
489 uint32_t last_fence;
490 struct msm_file_private *ctx;
491 struct list_head node;
492 struct idr fence_idr;
493 struct mutex idr_lock;
494 struct mutex lock;
495 struct kref ref;
496 struct drm_sched_entity *entity;
497 };
498
499 struct msm_gpu_state_bo {
500 u64 iova;
501 size_t size;
502 void *data;
503 bool encoded;
504 char name[32];
505 };
506
507 struct msm_gpu_state {
508 struct kref ref;
509 struct timespec64 time;
510
511 struct {
512 u64 iova;
513 u32 fence;
514 u32 seqno;
515 u32 rptr;
516 u32 wptr;
517 void *data;
518 int data_size;
519 bool encoded;
520 } ring[MSM_GPU_MAX_RINGS];
521
522 int nr_registers;
523 u32 *registers;
524
525 u32 rbbm_status;
526
527 char *comm;
528 char *cmd;
529
530 struct msm_gpu_fault_info fault_info;
531
532 int nr_bos;
533 struct msm_gpu_state_bo *bos;
534 };
535
gpu_write(struct msm_gpu * gpu,u32 reg,u32 data)536 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
537 {
538 msm_writel(data, gpu->mmio + (reg << 2));
539 }
540
gpu_read(struct msm_gpu * gpu,u32 reg)541 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
542 {
543 return msm_readl(gpu->mmio + (reg << 2));
544 }
545
gpu_rmw(struct msm_gpu * gpu,u32 reg,u32 mask,u32 or)546 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
547 {
548 msm_rmw(gpu->mmio + (reg << 2), mask, or);
549 }
550
gpu_read64(struct msm_gpu * gpu,u32 lo,u32 hi)551 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
552 {
553 u64 val;
554
555 /*
556 * Why not a readq here? Two reasons: 1) many of the LO registers are
557 * not quad word aligned and 2) the GPU hardware designers have a bit
558 * of a history of putting registers where they fit, especially in
559 * spins. The longer a GPU family goes the higher the chance that
560 * we'll get burned. We could do a series of validity checks if we
561 * wanted to, but really is a readq() that much better? Nah.
562 */
563
564 /*
565 * For some lo/hi registers (like perfcounters), the hi value is latched
566 * when the lo is read, so make sure to read the lo first to trigger
567 * that
568 */
569 val = (u64) msm_readl(gpu->mmio + (lo << 2));
570 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
571
572 return val;
573 }
574
gpu_write64(struct msm_gpu * gpu,u32 lo,u32 hi,u64 val)575 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
576 {
577 /* Why not a writeq here? Read the screed above */
578 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
579 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
580 }
581
582 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
583 int msm_gpu_pm_resume(struct msm_gpu *gpu);
584
585 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
586 struct drm_printer *p);
587
588 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
589 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
590 u32 id);
591 int msm_submitqueue_create(struct drm_device *drm,
592 struct msm_file_private *ctx,
593 u32 prio, u32 flags, u32 *id);
594 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
595 struct drm_msm_submitqueue_query *args);
596 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
597 void msm_submitqueue_close(struct msm_file_private *ctx);
598
599 void msm_submitqueue_destroy(struct kref *kref);
600
601 int msm_file_private_set_sysprof(struct msm_file_private *ctx,
602 struct msm_gpu *gpu, int sysprof);
603 void __msm_file_private_destroy(struct kref *kref);
604
msm_file_private_put(struct msm_file_private * ctx)605 static inline void msm_file_private_put(struct msm_file_private *ctx)
606 {
607 kref_put(&ctx->ref, __msm_file_private_destroy);
608 }
609
msm_file_private_get(struct msm_file_private * ctx)610 static inline struct msm_file_private *msm_file_private_get(
611 struct msm_file_private *ctx)
612 {
613 kref_get(&ctx->ref);
614 return ctx;
615 }
616
617 void msm_devfreq_init(struct msm_gpu *gpu);
618 void msm_devfreq_cleanup(struct msm_gpu *gpu);
619 void msm_devfreq_resume(struct msm_gpu *gpu);
620 void msm_devfreq_suspend(struct msm_gpu *gpu);
621 void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
622 void msm_devfreq_active(struct msm_gpu *gpu);
623 void msm_devfreq_idle(struct msm_gpu *gpu);
624
625 int msm_gpu_hw_init(struct msm_gpu *gpu);
626
627 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
628 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
629 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
630 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
631
632 void msm_gpu_retire(struct msm_gpu *gpu);
633 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
634
635 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
636 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
637 const char *name, struct msm_gpu_config *config);
638
639 struct msm_gem_address_space *
640 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
641
642 void msm_gpu_cleanup(struct msm_gpu *gpu);
643
644 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
645 void __init adreno_register(void);
646 void __exit adreno_unregister(void);
647
msm_submitqueue_put(struct msm_gpu_submitqueue * queue)648 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
649 {
650 if (queue)
651 kref_put(&queue->ref, msm_submitqueue_destroy);
652 }
653
msm_gpu_crashstate_get(struct msm_gpu * gpu)654 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
655 {
656 struct msm_gpu_state *state = NULL;
657
658 mutex_lock(&gpu->lock);
659
660 if (gpu->crashstate) {
661 kref_get(&gpu->crashstate->ref);
662 state = gpu->crashstate;
663 }
664
665 mutex_unlock(&gpu->lock);
666
667 return state;
668 }
669
msm_gpu_crashstate_put(struct msm_gpu * gpu)670 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
671 {
672 mutex_lock(&gpu->lock);
673
674 if (gpu->crashstate) {
675 if (gpu->funcs->gpu_state_put(gpu->crashstate))
676 gpu->crashstate = NULL;
677 }
678
679 mutex_unlock(&gpu->lock);
680 }
681
682 /*
683 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
684 * support expanded privileges
685 */
686 #define check_apriv(gpu, flags) \
687 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
688
689
690 #endif /* __MSM_GPU_H__ */
691